Capacitors having electrodes with portions of material removed and related semiconductor devices, systems, and methods

Abstract

This application relates to capacitors having electrodes with portions of material removed and related semiconductor devices, systems, and methods. A DRAM capacitor can include a first capacitor electrode, a capacitor dielectric adjacent to the first capacitor electrode, and a second capacitor electrode adjacent to the capacitor dielectric. The first capacitor electrode can include a lower portion, an upper portion, and a stepped transition between the lower portion and the upper portion, a width of the upper portion of the first capacitor electrode at the stepped transition being less than a width of the lower portion of the first capacitor electrode at the stepped transition. Semiconductor devices, systems, and methods are also disclosed.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 139,619, filed January 20, 2021, and U.S. Provisional Patent Application No. 17 / 647,902, filed January 13, 2022, pursuant to 35 U.S. SC § 119(e), the entire disclosure of each of which is hereby incorporated herein by reference. Technical Field

[0003] The embodiments disclosed herein relate to semiconductor manufacturing, including the fabrication of dynamic random access memory (DRAM). More specifically, embodiments of this disclosure relate to electrodes with partially removed material for DRAM capacitors, methods for forming DRAM capacitors, and related semiconductor devices and systems. Background Technology

[0004] A continuous goal in integrated circuit manufacturing is to increase integration density. Dynamic Random Access Memory (DRAM) uses DRAM capacitors to store the amount of charge representing the logic values ​​of the stored bits. To increase integration density, the lateral coverage area of ​​DRAM capacitors has been reduced by increasing the aspect ratio (i.e., the ratio of height to width or diameter) and decreasing the proximity of adjacent DRAM capacitors. Additionally, to increase the capacitance of a DRAM cell, the height of the DRAM cell can be increased to increase the surface area of ​​the capacitor. High aspect ratios and smaller lateral dimensions have increased the incidence of under-etching of the capacitor. Attempts have been made to reduce the incidence of under-etching by utilizing dry etching processes. While dry etching processes can reduce the incidence of under-etching, they significantly increase the risk of short circuits in the capacitor. Summary of the Invention

[0005] A DRAM capacitor includes: a first capacitor electrode comprising a lower portion, an upper portion, and a first stepped transition region between the lower portion and the upper portion, wherein the width of the upper portion of the first capacitor electrode at the first stepped transition region is smaller than the width of the lower portion of the first capacitor electrode at the first stepped transition region; a capacitor dielectric on the first capacitor electrode; and a second capacitor electrode on the capacitor dielectric.

[0006] A method of forming a DRAM capacitor includes forming a first capacitor electrode, which includes exposing an upper portion of the first capacitor electrode and removing a portion of the upper portion of the first capacitor electrode. The method further includes exposing a lower portion of the first capacitor electrode after removing a portion of the upper portion of the first capacitor electrode, forming a capacitor dielectric on the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric.

[0007] A semiconductor device includes a DRAM capacitor and an access means operatively coupled to the DRAM capacitor. At least one DRAM capacitor includes a first capacitor electrode comprising a lower portion and an upper portion, wherein the upper portion of the first capacitor electrode and the lower portion of the first capacitor electrode have a distance between approximately [missing information] at a stepped transition region. With the agreement The width difference between the two electrodes; the capacitor dielectric adjacent to the first capacitor electrode; and the second capacitor electrode adjacent to the capacitor dielectric.

[0008] A system includes a memory array comprising memory cells, each memory cell including a DRAM capacitor and an access means operatively coupled to the DRAM capacitor. At least one DRAM capacitor includes: a first capacitor electrode including a lower portion and an upper portion, the lower portion having a greater thickness than the upper portion; a capacitor dielectric adjacent to the first capacitor electrode; and a second capacitor electrode adjacent to the capacitor dielectric. Attached Figure Description

[0009] Figures 1 to 6 This is a schematic cross-sectional view of a portion of a semiconductor structure in a processing sequence for forming a DRAM capacitor according to some embodiments of the present disclosure;

[0010] Figure 7 A schematic cross-sectional view of a DRAM device according to some embodiments of the present disclosure;

[0011] Figure 8 A simplified block diagram of a DRAM device including a memory array according to some embodiments of the present disclosure; and

[0012] Figure 9 This is a simplified block diagram of a system implemented according to some embodiments of the present disclosure. Detailed Implementation

[0013] A DRAM capacitor includes a first capacitor electrode (e.g., a bottom capacitor electrode) comprising a lower portion, an upper portion with some material removed, and a stepped transition region between the lower and upper portions. Removing material from the upper portion provides increased space between the upper portions adjacent to the first capacitor electrode, allowing the first capacitor electrodes to be tightly positioned together while still providing increased space between them. This increased space reduces problems associated with compression of the capacitor dielectric material formed on the first capacitor electrodes. Additionally, the increased space reduces problems associated with compression and / or shorting of a second capacitor electrode (e.g., a top capacitor electrode) formed on the capacitor dielectric. DRAM devices incorporating DRAM capacitors are also disclosed, as well as methods for forming DRAM capacitors and systems for incorporating them into DRAM memory.

[0014] The following description provides specific details, such as material type, material thickness, and processing conditions, to provide a sufficient description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. Furthermore, the descriptions provided herein do not constitute a complete description of a semiconductor structure or a complete process flow for manufacturing a semiconductor device, and the structures described below do not form a complete semiconductor device. Only those processing actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions to form a complete semiconductor device can be performed using conventional techniques.

[0015] The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Shapes depicted in the drawings are expected to vary due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas illustrated, but should include, for example, shape variations caused by manufacturing processes. For example, an area illustrated or described as box-shaped may have rough and / or non-linear characteristics, and an area illustrated or described as circular may include some rough and / or linear characteristics. Furthermore, illustrated acute angles may be rounded, and vice versa. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims. The drawings are not necessarily to scale. Additionally, common elements between figures may retain the same numerical designations.

[0016] As used herein, the singular forms “a” and “the” are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0017] As used herein, the term “about” with respect to a given parameter, property, or condition means, and is included, the degree to which a given parameter, property, or condition satisfies variance (e.g., within acceptable manufacturing tolerances) as would be understood by one of ordinary skill in the art.

[0018] As used herein, the term "aspect ratio" means and includes the ratio of the height (e.g., length) of a structure, such as a DRAM capacitor, to the width (e.g., diameter) of the structure. The aspect ratio of a DRAM capacitor may be greater than about 20:1, greater than about 30:1, greater than about 40:1, greater than about 50:1, greater than about 60:1, greater than about 70:1, greater than about 80:1, greater than about 90:1, or greater than about 100:1. In some embodiments, the DRAM capacitor has an aspect ratio greater than about 50:1. In other embodiments, the DRAM capacitor has an aspect ratio greater than about 80:1. In still other embodiments, the DRAM capacitor has an aspect ratio greater than about 90:1. In yet still other embodiments, the DRAM capacitor has an aspect ratio greater than about 100:1.

[0019] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” and “right” are used to conveniently describe the relationship of one element or feature to another, as illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures is inverted, an element described as being “below,” “under,” “down,” or “on the bottom” of another element or feature would be oriented “above” or “on the top” of said other element or feature. Thus, the term “below” may cover both above and below orientations depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptors used herein will be interpreted accordingly.

[0020] As used herein, the term “configured as” refers to the size, shape, material composition, and arrangement of one or more of at least one structure and at least one device, which in a predetermined manner facilitates the operation of one or more of the structure and device.

[0021] As used herein, the term "generally" with respect to a given parameter, property, or condition means, and includes, the degree to which a given parameter, property, or condition satisfies variance (e.g., within acceptable manufacturing tolerances) as would be understood by one of ordinary skill in the art. As an example, depending on the specific parameter, property, or condition that is generally satisfied, it may be satisfied by at least 90.0%, at least 95.0%, at least 99.0%, or even at least 99.9%.

[0022] As used herein, the term "substrate" means and includes a base material or structure on which additional material is formed. A substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more materials, layers, structures, or regions formed thereon. Materials on a semiconductor substrate can include, but are not limited to, semiconductive materials, insulating materials, conductive materials, etc. The substrate can be a conventional silicon substrate or other bulk substrates including a layer of semiconductive material. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") and silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a base semiconductor, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. Substrates can be doped or undoped.

[0023] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is generally parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is generally perpendicular to the principal plane of the structure. The principal plane of the structure is defined by structural surfaces that have a relatively large area compared to the other surfaces of the structure.

[0024] As used herein, the term “semiconductor device” includes, but is not limited to, memory devices, and other semiconductor devices that can be incorporated into memory among other functions, such as a so-called “system-on-a-chip” (SoC) that includes a processor and memory, or a semiconductor device that includes logic and memory.

[0025] Figure 1 This diagram shows a cross-sectional view of a portion of a semiconductor structure 10 in an intermediate stage of a method for manufacturing a semiconductor device (e.g., a memory device) having a DRAM capacitor, according to embodiments of the present disclosure. The semiconductor structure may include a substrate 12, a first silicate material 14, a first lattice material 16, a second silicate material 18, and a second lattice material 20. One or more of the first silicate material 14, the first lattice material 16, the second silicate material 18, and the second lattice material 20 may be selected to be selectively etched relative to each other.

[0026] The substrate 12 may be a doped or undoped semiconductor material. For example, the substrate 12 may be composed of one or more of monocrystalline silicon (monosilicon), polycrystalline silicon (polysilicon), and amorphous silicon.

[0027] A first silicate material 14 may be formed (e.g., deposited) over the substrate 12. In some embodiments, the first silicate material 14 may be made of borosilicate glass (BPSG). However, other silicate materials may be used. A first lattice material 16 may be formed (deposited) over the first silicate material 14. The first lattice material 16 may be formed of a dielectric material, such as a dielectric nitride material or a dielectric oxide material. For example, the first lattice material 16 may be composed of one or more of silicon nitride, silicon oxide, and aluminum nitride.

[0028] A second silicate material 18 may be formed (e.g., deposited) over the first lattice material 16. In some embodiments, the second silicate material 18 may be composed of tetraethyl orthosilicate (TEOS). However, other silicate materials may be used. A second lattice material 20 may be formed (deposited) over the second silicate material 18. Similar to the first lattice material 16, the second lattice material 20 may be formed of a dielectric material, such as a dielectric nitride or dielectric oxide material. For example, the second lattice material 20 may be composed of one or more of silicon nitride and aluminum nitride.

[0029] The opening 22 can be formed in the semiconductor structure to extend from the second lattice material 20 to the substrate 12. For example, the initial opening can be generated using a dry etching process, followed by defining the opening 22 using a vapor-phase based etching process, such as by shaping the opening 22.

[0030] like Figure 2 As shown, a conductive material may be formed (e.g., deposited) within the opening to form a first capacitor electrode 30 (e.g., a bottom electrode). In some embodiments, each of the first capacitor electrodes 30 may be configured as a container, and a filler material 32 may be formed between the opposing surfaces of the first capacitor electrodes 30 to substantially fill the container defined by the first capacitor electrodes 30. The filler material 32 may be sacrificial because it is removed before additional material is added to form a capacitor, such as a DRAM capacitor. A portion of the first capacitor electrode 30 may be adjacent (e.g., laterally adjacent) to a stack of first silicate material 14, first lattice material 16, second silicate material 18, and second lattice material 20.

[0031] The first capacitor electrode 30 may be made of titanium nitride. In some embodiments, the titanium nitride may be doped with a metalloid element, a metallic element, carbon, or a combination thereof. By way of example only, the dopant may be silicon, boron, aluminum, zirconium, hafnium, phosphorus, carbon, gallium, germanium, antimony, tellurium, arsenic, tungsten, or a combination thereof. The dopant may be selected based on the resistivity or work function properties of the element. The doped TiN may include, but is not limited to, TiSiN, TiBN, TiAlN, TiPN, TiCN, TiGeN, TiAsN, TiWN, TiGaN, TiZrN, TiSbN, TiTeN, TiHfN, or TiN having two or more dopants. In some embodiments, the doped TiN is TiSiN. In other embodiments, the doped TiN is TiBN. The dopant can be present in doped TiN at a rate of about 0.1 atomic percent (at.%) to about 25 at.%, for example, about 0.1 at.% to about 15 at.%, about 0.1 at.% to about 10 at.%, or about 1 at.% to about 5 at.%.

[0032] The filler material 32 may be a conductive material, such as titanium nitride or doped titanium nitride, or it may be an insulating material, such as silicon nitride, doped silicon nitride, a high-k dielectric material, or an air gap. The filler material 32 may contain the same material as or a different material from the material of the first capacitor electrode 30. The filler material 32 may be adjacent to (e.g., laterally adjacent to) the first capacitor electrode 30, thereby extending along its length.

[0033] After the first capacitor electrode 30 has been formed, the upper portion 34 of the first capacitor electrode 30 can be exposed, such as... Figure 3 As shown in the diagram. To expose the upper portion 34 of the first capacitor electrode 30, at least a portion of the surrounding second silicate material 18 may be selectively removed. For example, the second silicate material 18 may be made of TEOS and may be removed (e.g., etched) by one or more of buffered hydrofluoric acid etching, diluted hydrofluoric acid etching, and vapor phase etching.

[0034] After exposing the upper portion 34 of the first capacitor electrode 30, a portion of the upper portion 34 of the first capacitor electrode 30 may be removed (e.g., thinned), such as... Figure 4 As shown in the figure. Thinning the exposed upper portion 34 of the first capacitor electrode 30 may include removing approximately 1 angstrom of the first capacitor electrode 30. With the agreement The material between. In some embodiments, thinning the exposed upper portion 34 of the first capacitor electrode 30 may include removing approximately With the agreement The material between. In other embodiments, thinning the exposed upper portion 34 of the first capacitor electrode 30 may include removing approximately With the agreement The material between. In yet another embodiment, thinning the exposed upper portion 34 of the first capacitor electrode 30 may include removing approximately With the agreement The materials between. Figure 4 As shown, the width of the upper portion 34 of the first capacitor electrode 30 may be smaller than the width of the lower portion 38 of the first capacitor electrode 30.

[0035] The upper portion 34 of the first capacitor electrode 30 may have some material removed by an etching process. In some embodiments, thinning the upper portion 34 of the first capacitor electrode 30 may include etching the upper portion 34 of the first capacitor electrode 30 with one or more of the following: hydrogen peroxide; a mixture of ammonia and hydrogen peroxide; a mixture of ammonium hydroxide, hydrogen peroxide, and water; and oxygen plasma. In an additional embodiment, thinning the upper portion 34 of the first capacitor electrode 30 may include performing vapor phase etching on the upper portion 34 of the first capacitor electrode 30.

[0036] Since the lower portion 38 of the first capacitor electrode 30 is not exposed to etching conditions due to the surrounding first silicate material 14 and any remaining second silicate material 18, the lower portion 38 of the first capacitor electrode 30 may not have any material removed during the removal of material from the upper portion 34 of the first capacitor electrode 30. In other words, the width of the lower portion 38 is approximately equal to the width of the initial forming material of the first capacitor electrode 30. Therefore, a stepped transition region 40 may be formed in the first capacitor electrode between the upper portion 34 and the lower portion 38. The stepped transition region 40 is a location where the thickness of the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 changes abruptly, for example, at the interface between the upper portion 34 and the lower portion 38. The difference in thickness between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may have a dimension D, which is approximately the same as the thickness of material removed from the upper portion 34 of the capacitor electrode 30 during the thinning process. In some embodiments, the width difference between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may be approximately With the agreement In an additional embodiment, the width difference between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may be between approximately With the agreement Between. In other embodiments, the width difference between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may be between approximately With the agreement Between. In another embodiment, the width difference between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may be between approximately With the agreement between.

[0037] After the upper portion 34 of the first capacitor electrode 30 has been removed, the remaining portions of the first silicate material 14 and the second silicate material 18 can be removed to expose the lower portion 38 of the first capacitor electrode 30, such as... Figure 5 As shown in the diagram. Exposing the lower portion 38 of the first capacitor electrode 30 may include removing (e.g., etching) the remaining portion of the second silicate material 18 (e.g., TEOS material) surrounding the lower portion 38 of the first capacitor electrode 30, and etching the first silicate material 14 (e.g., BPSG material) surrounding the lower portion 38 of the first capacitor electrode 30. For example, the remaining portion of the second silicate material 18 and the first silicate material 14 may be removed by one or more of buffered hydrofluoric acid etching, diluted hydrofluoric acid etching, and vapor phase etching. The second silicate material 18 and the first silicate material 14 may be selectively removed relative to the first lattice material 16, the second lattice material 20, and the substrate 12.

[0038] like Figure 6 As shown, after the lower portion 38 of the first capacitor electrode 30 has been exposed, a residual capacitor structure can be formed to provide a DRAM capacitor 50. A capacitor dielectric 52 can be formed adjacent to the first capacitor electrode 30 (e.g., formed on top of the electrode), and a second capacitor electrode 54 (e.g., a top electrode) can be formed adjacent to the first capacitor electrode 30 (e.g., formed on top of the electrode), wherein the capacitor dielectric 52 is between the first capacitor electrode 30 and the second capacitor electrode 54. A first lattice material 16 and a second lattice material 20 can provide additional support for the DRAM capacitor 50. Although two lattice materials are described, the DRAM capacitor 50 may contain more or fewer lattice materials. The capacitor dielectric 52 is formed on the sidewall of the first capacitor electrode 30, encompassing the sidewall and upper surface of the stepped transition region 40. Therefore, the width of the capacitor dielectric 52 adjacent to the upper portion 34 of the first capacitor electrode 30 may be greater than the width of the capacitor dielectric 52 adjacent to the lower portion 38 of the first capacitor electrode 30, such as... Figure 6 The width of the capacitor dielectric 52 may be substantially constant over the entire first capacitor electrode 30, as shown most clearly.

[0039] The capacitor dielectric 52 may be formed of an electrically insulating material, which includes, but is not limited to, electrically insulating oxides or electrically insulating nitrides. By way of example only, the capacitor dielectric 52 may include hafnium oxide, silicon dioxide, silicon nitride, zirconium oxide, or combinations thereof, and may be substantially composed of hafnium oxide, silicon dioxide, silicon nitride, zirconium oxide, or combinations thereof. In some embodiments, the capacitor dielectric 52 is zirconium oxide. The capacitor dielectric 52 may be formed by conventional techniques, such as physical vapor deposition (“PVD”), CVD, or ALD. PVD includes, but is not limited to, sputtering, evaporation, or ionization PVD. Such deposition techniques are known in this art and therefore will not be described in detail herein.

[0040] The second capacitor electrode 54 may be formed of a conductive material, which includes, but is not limited to, metals (e.g., platinum, titanium, tungsten, ruthenium, etc.), metal-containing compositions (e.g., metal nitrides, metal silicides, etc.), or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). The second capacitor electrode 54 may be formed using conventional techniques, such as PVD, CVD, or ALD. The width of the second capacitor electrode 54 may be substantially equal along its entire length.

[0041] The first lattice material 16 and the second lattice material 20 can be configured to provide additional structural support for the DRAM capacitor 50, thereby preventing or reducing the tipping, collapse, and wobbling of the DRAM capacitor 50. The first lattice material 16 and the second lattice material 20 can be formed of electrically insulating materials such as silicon nitride or silicon oxide. The first lattice material 16 and the second lattice material 20 can have any desired thickness, for example, approximately... to or about to The thickness. One or more of the first lattice material 16 and the second lattice material 20 may be present along the height of the first capacitor electrode 30, for example, at least one of the top portion, the middle portion, or the bottom portion of the first capacitor electrode 30. The number of lattice materials may depend on the height of the DRAM capacitor 50 and the mechanical support provided by the first capacitor electrode 30, as long as lateral movement of the DRAM capacitor 50 is appropriately reduced or prevented.

[0042] DRAM capacitor 50 may be a high aspect ratio (HAR) capacitor with an aspect ratio greater than about 20:1, greater than about 30:1, greater than about 40:1, greater than about 50:1, greater than about 60:1, greater than about 70:1, greater than about 80:1, greater than about 90:1, or greater than about 100:1. For example, the aspect ratio of DRAM capacitor 50 may be from about 20:1 to about 100:1, such as from about 20:1 to about 30:1, from about 50:1 to about 100:1, or from about 80:1 to about 100:1. In some embodiments, the aspect ratio of DRAM capacitor 50 is about 100:1. To achieve a high aspect ratio, the diameter (or width) and height of DRAM capacitor 50 may be appropriately sized. By way of example only, the diameter (or width) of DRAM capacitor 50 may be less than or equal to about 100:1. For example, less than or equal to approximately Less than or equal to approximately Less than or equal to approximately or less than or equal to approximately The height of the DRAM capacitor 50 may be greater than or equal to approximately For example, greater than or equal to approximately Greater than or equal to approximately or greater than or equal to approximately

[0043] An increased space is provided between the adjacent upper portion 34 of the first capacitor electrode 30 (see Figure 3 and 4 This design allows the first capacitor electrodes 30 to be positioned close together while providing increased space between the upper portions 34 of the first capacitor electrodes 30 for forming the capacitor dielectric 52 and the second capacitor electrode 54. The increased space reduces problems associated with compression of the capacitor dielectric 52 and compression and / or shorting of the second capacitor electrode 54.

[0044] After the first capacitor electrode 30 has been formed, the upper portion 34 of the first capacitor electrode 30 can be exposed, such as... Figure 3 As shown in the diagram. To expose the upper portion 34 of the first capacitor electrode 30, at least a portion of the surrounding second silicate material 18 may be selectively removed. For example, the second silicate material 18 may be made of TEOS and may be removed (e.g., etched) by one or more of buffered hydrofluoric acid etching, diluted hydrofluoric acid etching, and vapor phase etching.

[0045] After exposing the upper portion 34 of the first capacitor electrode 30, a portion of the upper portion 34 of the first capacitor electrode 30 may be removed (e.g., thinned), such as... Figure 4 As shown in the figure. Thinning the exposed upper portion 34 of the first capacitor electrode 30 may include removing approximately 1 angstrom of the first capacitor electrode 30. With the agreement The material between. In some embodiments, thinning the exposed upper portion 34 of the first capacitor electrode 30 may include removing approximately With the agreement The material between. In other embodiments, thinning the exposed upper portion 34 of the first capacitor electrode 30 may include removing approximately [a portion of] the first capacitor electrode 30. With the agreement The material between. In yet another embodiment, thinning the exposed upper portion 34 of the first capacitor electrode 30 may include removing approximately With the agreement The materials between. Figure 4 As shown, the width of the upper portion 34 of the first capacitor electrode 30 may be smaller than the width of the lower portion 38 of the first capacitor electrode 30.

[0046] The upper portion 34 of the first capacitor electrode 30 may have some material removed by an etching process. In some embodiments, thinning the upper portion 34 of the first capacitor electrode 30 may include etching the upper portion 34 of the first capacitor electrode 30 with one or more of the following: hydrogen peroxide; a mixture of ammonia and hydrogen peroxide; a mixture of ammonium hydroxide, hydrogen peroxide, and water; and oxygen plasma. In an additional embodiment, thinning the upper portion 34 of the first capacitor electrode 30 may include performing vapor phase etching on the upper portion 34 of the first capacitor electrode 30.

[0047] Since the lower portion 38 of the first capacitor electrode 30 is not exposed to etching conditions due to the surrounding first silicate material 14 and any remaining second silicate material 18, the lower portion 38 of the first capacitor electrode 30 may not have any material removed during the removal of material from the upper portion 34 of the first capacitor electrode 30. In other words, the width of the lower portion 38 is approximately equal to the width of the initial forming material of the first capacitor electrode 30. Therefore, a stepped transition region 40 may be formed in the first capacitor electrode between the upper portion 34 and the lower portion 38. The stepped transition region 40 is a location where the thickness of the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 changes abruptly, for example, at the interface between the upper portion 34 and the lower portion 38. The difference in thickness between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may have a dimension D, which is approximately the same as the thickness of material removed from the upper portion 34 of the capacitor electrode 30 during the thinning process. In some embodiments, the width difference between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may be approximately With the agreement In an additional embodiment, the width difference between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may be between approximately With the agreement Between. In other embodiments, the width difference between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may be between approximately With the agreement Between. In another embodiment, the width difference between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may be between approximately With the agreement between.

[0048] In an additional embodiment, it may be relative to a reference. Figure 3 The situation shown and described exposes a larger or smaller upper portion 34 of the first capacitor electrode 30. For example, as... Figure 4.1 As shown, when compared to Figure 3 At that time, the exposed upper portion 34 of the first capacitor electrode 30 can be relatively close to the second lattice material 20.

[0049] After exposing the upper portion 34 of the first capacitor electrode 30, a portion of the upper portion 34 of the first capacitor electrode 30 may be removed (e.g., thinned), such as... Figure 4.1 As shown, and as referenced Figure 4 As described. Figure 4.1 As shown, the width of the upper portion 34 of the first capacitor electrode 30 may be smaller than the width of the lower portion 38 of the first capacitor electrode 30. Therefore, a stepped transition region 40 may be formed in the first capacitor electrode between the upper portion 34 and the lower portion 38. The stepped transition region 40 is a location where the thickness of the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 changes abruptly, for example, at the interface between the upper portion 34 and the lower portion 38. The difference in thickness between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may have a dimension D, which is substantially the same as the thickness of material removed from the upper portion 34 of the capacitor electrode 30 during the thinning process. An additional transition region may optionally exist near the second lattice material 20.

[0050] In other embodiments, such as Figure 4.2 As shown, the exposed upper portion 34 of the first capacitor electrode 30 can extend to the first lattice material 16. Similar to reference... Figure 4As described, after exposing the upper portion 34 of the first capacitor electrode 30, a portion of the upper portion 34 of the first capacitor electrode 30 can be removed (e.g., thinned). Figure 4.2 As shown, the width of the upper portion 34 of the first capacitor electrode 30 may be smaller than the width of the lower portion 38 of the first capacitor electrode 30. Therefore, a stepped transition region 40 may be formed in the first capacitor electrode between the upper portion 34 and the lower portion 38. The difference in thickness between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may have a dimension D, which is substantially the same as the thickness of material removed from the upper portion 34 of the capacitor electrode 30 during the thinning process. An additional transition region may optionally exist near the second lattice material 20.

[0051] For another example, such as Figure 4.3 As shown, the exposed upper portion 34 of the first capacitor electrode 30 may extend beyond the first lattice material 16. Therefore, a portion of the second silicate material 18 and the first silicate material 14 can be removed to expose the upper portion 34 of the first capacitor electrode 30 extending beyond the first lattice material 16. Similar to reference... Figure 4 As described, after exposing the upper portion 34 of the first capacitor electrode 30, a portion of the upper portion 34 of the first capacitor electrode 30 can be removed (e.g., thinned). Figure 4.3 As shown, the width of the upper portion 34 of the first capacitor electrode 30 may be smaller than the width of the lower portion 38 of the first capacitor electrode 30. Therefore, a stepped transition region 40 may be formed in the first capacitor electrode between the upper portion 34 and the lower portion 38. The difference in thickness between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may have a dimension D, which is substantially the same as the thickness of material removed from the upper portion 34 of the capacitor electrode 30 during the thinning process.

[0052] In other embodiments, the semiconductor structure 10 may include additional lattice material. For example... Figure 4.4 As shown, the semiconductor structure may include a first lattice material 16, a second lattice material 20, and a third lattice material 16'. The third lattice material 16' may be formed substantially as described above with respect to the first lattice material 16. Therefore, the semiconductor structure 10 according to embodiments of the present disclosure may include any number of lattice materials.

[0053] like Figure 4.4 As shown, the exposed upper portion 34 of the first capacitor electrode 30 may extend between the first lattice material 16 and the third lattice material 16'. Similar to reference... Figure 4As described, after exposing the upper portion 34 of the first capacitor electrode 30, a portion of the upper portion 34 of the first capacitor electrode 30 can be removed (e.g., thinned). Figure 4.4 As shown, the width of the upper portion 34 of the first capacitor electrode 30 may be smaller than the width of the lower portion 38 of the first capacitor electrode 30. Therefore, a stepped transition region 40 may be formed in the first capacitor electrode between the upper portion 34 and the lower portion 38. The difference in thickness between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may have a dimension D, which is substantially the same as the thickness of material removed from the upper portion 34 of the capacitor electrode 30 during the thinning process.

[0054] In yet other embodiments, as referenced Figure 4 After the stepped transition region 40 is formed in the first capacitor electrode 30, a second stepped transition region 40' can be formed in the first capacitor electrode, such as... Figure 4.5 As shown in the figure. Therefore, a stepped transition region 40 is formed in the first capacitor electrode 30 (as shown in the reference). Figure 4 Following the description, additional silicate material can be removed to expose another portion of the first capacitor electrode 30. For example, the remainder of the second silicate material 18 and a portion of the first silicate material 14 can be removed to expose a second upper portion 34' of the first capacitor electrode 30 extending beyond the first lattice material 16, as described above. Figure 4.5 As shown in the reference. Figure 4 As described, after exposing the second upper portion 34' of the first capacitor electrode 30, a portion of the second upper portion 34' of the first capacitor electrode 30 can be removed (e.g., thinned). Simultaneously, additional portions of the upper portion 34' of the first capacitor electrode 30 can be removed, such as... Figure 4.5 As shown in the image.

[0055] Thinning the exposed upper portion 34 and the second upper portion 34' of the first capacitor electrode 30 may include removing approximately 1 angstrom of the first capacitor electrode 30. With the agreement The material between. In some embodiments, thinning the exposed upper portion 34 and the second upper portion 34' of the first capacitor electrode 30 may include removing approximately With the agreement The material between. In other embodiments, thinning the exposed upper portion 34 and the second upper portion 34' of the first capacitor electrode 30 may include removing approximately With the agreement The material between. In yet another embodiment, thinning the exposed upper portion 34 and the second upper portion 34' of the first capacitor electrode 30 may include removing approximately With the agreement The materials between.

[0056] like Figure 4.5 As shown, the width of the upper portion 34 of the first capacitor electrode 30 may be smaller than the width of the second upper portion 34' of the first capacitor electrode 30, and the second upper portion may be smaller than the lower portion 38 of the first capacitor electrode 30.

[0057] Therefore, a stepped transition region 40 may be formed in the first capacitor electrode 30 between the upper portion 34 and the second upper portion 34', and a second stepped transition region 40' may be formed in the first capacitor electrode 30 between the second upper portion 34' and the lower portion 38. The difference in thickness between the upper portion 34 and the second upper portion 34' of the first capacitor electrode 30 at the stepped transition region 40 may have a dimension D1. The difference in thickness between the second upper portion 34' and the lower portion 38 of the first capacitor electrode 30 at the stepped transition region 40 may have a dimension D2.

[0058] In some embodiments, the width difference (i.e., the sum of D1 and D2) between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 may be approximately With the agreement Therefore, the width difference between the upper portion 34 of the adjacent stepped transition region 40 of the first capacitor electrode 30 and the lower portion 38 of the adjacent second stepped transition region 40' of the first capacitor electrode 30 can be approximately between With the agreement In an additional embodiment, the width difference (i.e., the sum of D1 and D2) between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 may be between approximately With the agreement In other embodiments, the width difference (i.e., the sum of D1 and D2) between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 may be between approximately With the agreement In another embodiment, the width difference (i.e., the sum of D1 and D2) between the upper portion 34 and the lower portion 38 of the first capacitor electrode 30 may be between approximately With the agreement between.

[0059] Therefore, a DRAM capacitor is disclosed, comprising: a first capacitor electrode, the first capacitor electrode including a lower portion, an upper portion and a first stepped transition region between the lower portion and the upper portion, the width of the upper portion of the first capacitor electrode at the first stepped transition region being smaller than the width of the lower portion of the first capacitor electrode at the first stepped transition region; a capacitor dielectric on the first capacitor electrode; and a second capacitor electrode on the capacitor dielectric.

[0060] Therefore, a method for forming a DRAM capacitor is disclosed. The method includes forming a first capacitor electrode, which includes exposing an upper portion of the first capacitor electrode and removing a portion of the upper portion of the first capacitor electrode. The method further includes exposing a lower portion of the first capacitor electrode after removing a portion of the upper portion of the first capacitor electrode, forming a capacitor dielectric on the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric.

[0061] Figure 7 The diagram illustrates a memory device (e.g., DRAM device 100) including memory cells 110 comprising DRAM capacitors 50. DRAM device 100 includes a DRAM memory array comprising memory cells 110 including DRAM capacitors 50 according to some embodiments of the present disclosure. Memory cell 110 may be a DRAM memory cell including DRAM capacitors 50 and access means 112 operatively coupled to the DRAM capacitors 50, such as transistors. Access means 112 includes a source region, a drain region, and a channel region, and performs read and / or write operations on the charge stored in the DRAM capacitors 50. Figure 7 For simplicity and convenience, the DRAM capacitor 50 is described as a single structure. However, in embodiments where the DRAM capacitor 50 includes a first capacitor electrode 30 (e.g., bottom electrode), a capacitor dielectric 52, and a second capacitor electrode 54 (e.g., top electrode), as previously described, the first capacitor electrode is contained in a stepped transition region 40 between a lower portion 38 and an upper portion 34, wherein the capacitor dielectric 52 is between the first capacitor electrode 30 and the second capacitor electrode 54. The DRAM device 100 may also optionally include a first lattice material 16 and a second lattice material 20.

[0062] Figure 8This is a simplified block diagram of a DRAM device 100 implemented according to one or more embodiments described herein. The DRAM device 100 includes a memory array 202 and a control logic component 204. The memory array 202 may include memory cells 110 as described above. The control logic component 204 may be operatively coupled to the memory array 202 to read, write, or refresh any or all of the memory cells 110 within the memory array 202.

[0063] Therefore, a semiconductor device is disclosed. The semiconductor device includes a DRAM capacitor and an access means operatively coupled to the DRAM capacitor. At least one of the DRAM capacitors includes: a first capacitor electrode comprising a lower portion and an upper portion, and a distance between the upper portion of the first capacitor electrode and the lower portion of the first capacitor electrode at a stepped transition region is approximately... With the agreement The width difference between the two electrodes; the capacitor dielectric adjacent to the first capacitor electrode; and the second capacitor electrode adjacent to the capacitor dielectric.

[0064] System 300 is also disclosed. System 300 includes a memory array 202, which contains memory cells 110, such as... Figure 9 As shown in the diagram. Each memory cell 110 includes an access device 112 and a DRAM capacitor 50 operatively coupled to the access device 112, wherein the DRAM capacitor 50 is configured as described above. Figure 9 This is a simplified block diagram of a system 300 implemented according to one or more embodiments described herein. System 300 includes at least one input device 310. Input device 310 may be a keyboard, mouse, or touchscreen. System 300 further includes at least one output device 312. Output device 312 may be a monitor, touchscreen, or speaker. Input device 310 and output device 312 may not be separable from each other. System 300 further includes a storage device 314. Input device 310, output device 312, and storage device 314 are coupled to processor 316. System 300 further includes a DRAM device 100 coupled to processor 316, wherein DRAM device 100 includes at least one memory cell 110. DRAM device 100 may include an array of memory cells 110. System 300 may include computing, processing, industrial, or consumer products. For example, but not limited to, system 300 may include a personal computer or computer hardware component, server or other networked hardware component, handheld device, tablet computer, electronic notebook, camera, telephone, music player, wireless device, display, chipset, game, vehicle or other known system.

[0065] Therefore, a system is disclosed. The system includes a memory array comprising memory cells, each memory cell including a DRAM capacitor and an access means operatively coupled to the DRAM capacitor. At least one DRAM capacitor includes: a first capacitor electrode comprising a lower portion and an upper portion, the lower portion having a greater thickness than the upper portion; a capacitor dielectric adjacent to the first capacitor electrode; and a second capacitor electrode adjacent to the capacitor dielectric.

[0066] Additional non-limiting example embodiments of this disclosure are described below.

[0067] Example 1. A DRAM capacitor, comprising: a first capacitor electrode including a lower portion, an upper portion, and a first stepped transition region between the lower portion and the upper portion, wherein the width of the upper portion of the first capacitor electrode at the first stepped transition region is smaller than the width of the lower portion of the first capacitor electrode at the first stepped transition region; a capacitor dielectric adjacent to the first capacitor electrode; and a second capacitor electrode adjacent to the capacitor dielectric.

[0068] Example 2. The DRAM capacitor according to Example 1, wherein the width difference between the upper portion and the lower portion of the first capacitor electrode at the first stepped transition region is approximately With the agreement between.

[0069] Example 3. A DRAM capacitor according to any one of Examples 1 and 2, wherein the width difference between the upper portion and the lower portion of the first capacitor electrode at the first stepped transition region is approximately With the agreement between.

[0070] Example 4. A DRAM capacitor according to any one of Examples 1 to 3, wherein the width difference between the upper portion and the lower portion of the first capacitor electrode at the first stepped transition region is approximately With the agreement between.

[0071] Example 5. A DRAM capacitor according to any one of Examples 1 to 4, wherein the width difference between the upper portion and the lower portion of the first capacitor electrode at the first stepped transition region is approximately With the agreement between.

[0072] Example 6. A DRAM capacitor according to any one of Examples 1 to 5, wherein the first capacitor electrode comprises titanium nitride.

[0073] Example 7. A DRAM capacitor according to any one of Examples 1 to 6, wherein the first capacitor electrode comprises doped titanium nitride.

[0074] Example 8. The DRAM capacitor according to Example 7, wherein the doped titanium nitride includes titanium nitride doped with one or more of silicon, boron, aluminum, zirconium, hafnium, phosphorus, carbon, gallium, germanium, antimony, tellurium, arsenic or tungsten.

[0075] Example 9. A DRAM capacitor according to any one of Examples 1 to 8, further comprising at least one lattice material laterally adjacent to the first capacitor electrode.

[0076] Example 10. A DRAM capacitor according to any one of Examples 1 to 9, further comprising a second stepped transition region between a lower portion and an upper portion of a first capacitor electrode.

[0077] Example 11. The DRAM capacitor according to Example 10, wherein the width difference between the upper portion of the first capacitor electrode adjacent to the first stepped transition region and the lower portion of the first capacitor electrode adjacent to the second stepped transition region is approximately With the agreement between.

[0078] Example 12. A method of forming a DRAM capacitor, the method comprising: forming a first capacitor electrode; exposing an upper portion of the first capacitor electrode; removing a portion of the upper portion of the first capacitor electrode; and exposing a lower portion of the first capacitor electrode after removing a portion of the upper portion of the first capacitor electrode.

[0079] Example 13. The method according to Example 12, wherein the portion of removing the upper portion of the first capacitor electrode includes approximately With the agreement The upper part of the first capacitor electrode is thinned between them.

[0080] Example 14. The method according to any of Examples 12 and 13, wherein exposing the upper portion of the first capacitor electrode includes removing a portion of the silicate material laterally adjacent to the upper portion of the first capacitor electrode.

[0081] Example 15. The method according to any one of Examples 12 to 14, wherein exposing the lower portion of the first capacitor electrode includes removing the remaining portion of the silicate material laterally adjacent to the upper portion of the first capacitor electrode, and removing another portion of the silicate material laterally adjacent to the lower portion of the first capacitor electrode.

[0082] Example 16. The method according to any one of Examples 12 to 15, wherein removing the upper portion of the first capacitor electrode includes etching the upper portion of the first capacitor with a mixture of ammonia and hydrogen peroxide.

[0083] Example 17. The method according to any one of Examples 12 to 16, wherein removing the upper portion of the first capacitor electrode includes etching the upper portion of the first capacitor with hydrogen peroxide.

[0084] Example 18. The method according to any one of Examples 12 to 17, wherein removing the upper portion of the first capacitor electrode includes etching the upper portion of the first capacitor with a mixture of ammonium hydroxide, hydrogen peroxide and water.

[0085] Example 19. The method according to any one of Examples 12 to 18, wherein removing the upper portion of the first capacitor electrode includes etching the upper portion of the first capacitor with oxygen plasma.

[0086] Example 20. The method according to any one of Examples 12 to 19, wherein removing the upper portion of the first capacitor electrode includes performing vapor phase etching on the upper portion of the first capacitor electrode.

[0087] Example 21. The method according to any one of Examples 12 to 20, further comprising: forming a capacitor dielectric on a first capacitor electrode; and forming a second capacitor electrode on the capacitor dielectric.

[0088] Example 22. The method according to any of Examples 12 to 21, wherein forming the first capacitor electrode includes forming the first capacitor electrode on a substrate material by stacking laterally adjacent to a first silicate material, a first lattice material, a second silicate material, and a second lattice material.

[0089] Example 23. A semiconductor device comprising: a DRAM capacitor, at least one of the DRAM capacitors comprising: a first capacitor electrode, the first capacitor electrode comprising a lower portion and an upper portion, and a distance between the upper portion of the first capacitor electrode and the lower portion of the first capacitor electrode at a stepped transition region being approximately With the agreement The width difference between them; the capacitor dielectric on the first capacitor electrode; and the second capacitor electrode on the capacitor dielectric; and the access means operatively coupled to the DRAM capacitor.

[0090] Example 24. The semiconductor device according to Example 23, wherein at least one DRAM capacitor has an aspect ratio greater than about 20:1.

[0091] Example 25. A semiconductor device according to any one of Examples 23 and 24, wherein at least one DRAM capacitor has an aspect ratio of about 50:1 to about 100:1.

[0092] Example 26. A system comprising: a memory array, the memory array including: memory cells, the memory cells including DRAM capacitors and access means operatively coupled to the DRAM capacitors, at least one of the DRAM capacitors including: a first capacitor electrode including a lower portion and an upper portion, the lower portion having a greater thickness than the upper portion; a capacitor dielectric adjacent to the first capacitor electrode; and a second capacitor electrode adjacent to the capacitor dielectric.

[0093] While certain illustrative embodiments have been described with reference to the figures, those skilled in the art will recognize and understand that the embodiments encompassed in this disclosure are not limited to those explicitly shown and described herein. Rather, various additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments encompassed in this disclosure (e.g., those claimed herein, including legal equivalents). Furthermore, features of one disclosed embodiment may be combined with features of another disclosed embodiment while still being included within the scope of this disclosure.

Claims

1. A DRAM capacitor, comprising: A first capacitor electrode includes a proximal substrate disposed on a substrate and an opposing portion extending from the proximal substrate. The opposing portion is configured as a container and includes a lower portion, an upper portion, and a first stepped transition region between the lower portion and the upper portion. The width of the upper portion at the first stepped transition region is smaller than the width of the lower portion at the first stepped transition region. The capacitor dielectric is located adjacent to the first capacitor electrode; as well as The second capacitor electrode is located adjacent to the capacitor dielectric.

2. The DRAM capacitor of claim 1, wherein the width difference between the upper portion and the lower portion at the first stepped transition region is between 1 Å and 50 Å.

3. The DRAM capacitor of claim 2, wherein the width difference between the upper portion and the lower portion at the first stepped transition region is between 5 Å and 20 Å.

4. The DRAM capacitor of claim 2, wherein the width difference between the upper portion and the lower portion at the first stepped transition region is between 20 Å and 40 Å.

5. The DRAM capacitor of claim 2, wherein the width difference between the upper portion and the lower portion at the first stepped transition region is between 40 Å and 50 Å.

6. The DRAM capacitor according to any one of claims 1 to 5, wherein the first capacitor electrode comprises titanium nitride.

7. The DRAM capacitor according to any one of claims 1 to 5, wherein the first capacitor electrode comprises doped titanium nitride.

8. The DRAM capacitor of claim 7, wherein the doped titanium nitride comprises titanium nitride doped with one or more of silicon, boron, aluminum, zirconium, hafnium, phosphorus, carbon, gallium, germanium, antimony, tellurium, arsenic or tungsten.

9. The DRAM capacitor according to any one of claims 1 to 5, further comprising at least one lattice material laterally adjacent to the first capacitor electrode.

10. The DRAM capacitor according to any one of claims 1 to 5, further comprising a second stepped transition region between the lower portion and the upper portion.

11. The DRAM capacitor of claim 10, wherein the width difference between the upper portion adjacent to the first stepped transition region and the lower portion adjacent to the second stepped transition region is between 1 Å and 50 Å.

12. A method for forming a DRAM capacitor, the method comprising: A first capacitor electrode is formed, the first capacitor electrode including a proximal substrate disposed on a substrate and an opposing portion extending from the proximal substrate, the opposing portion being configured as a container; The upper portion of the opposing portion of the first capacitor electrode is exposed; A portion of the upper portion is removed to form a first stepped transition region between the lower portion and the upper portion of the opposing portion, wherein the width of the upper portion at the first stepped transition region is smaller than the width of the lower portion at the first stepped transition region. The lower portion is exposed after the upper portion is removed; A capacitor dielectric is formed adjacent to the first capacitor electrode; as well as A second capacitor is formed adjacent to the capacitor dielectric.

13. The method of claim 12, wherein removing the upper portion comprises thinning the upper portion between 1 Å and 50 Å.

14. The method of claim 12, wherein exposing the upper portion comprises removing a portion of the silicate material laterally adjacent to the upper portion of the first capacitor electrode.

15. The method of claim 14, wherein exposing the lower portion comprises removing a remaining portion of the silicate material laterally adjacent to the upper portion, and removing another silicate material laterally adjacent to the lower portion.

16. The method according to any one of claims 12 to 15, wherein removing the upper portion comprises etching the upper portion of the first capacitor with a mixture of ammonia and hydrogen peroxide.

17. The method according to any one of claims 12 to 15, wherein removing the upper portion comprises etching the upper portion of the first capacitor with hydrogen peroxide.

18. The method according to any one of claims 12 to 15, wherein removing the upper portion comprises etching the upper portion of the first capacitor with a mixture of ammonium hydroxide, hydrogen peroxide, and water.

19. The method according to any one of claims 12 to 15, wherein removing the upper portion comprises etching the upper portion of the first capacitor with oxygen plasma.

20. The method according to any one of claims 12 to 15, wherein removing the upper portion comprises performing vapor phase etching on the upper portion.

21. The method according to any one of claims 12 to 15, further comprising: A capacitor dielectric is formed on the first capacitor electrode; as well as A second capacitor electrode is formed on the capacitor dielectric.

22. The method according to any one of claims 12 to 15, wherein forming the first capacitor electrode comprises forming the first capacitor electrode on a substrate material in a manner lateral to a stack of a first silicate material, a first lattice material, a second silicate material, and a second lattice material.

23. A semiconductor device comprising: DRAM capacitors, at least one of the DRAM capacitors comprising: A first capacitor electrode and a laterally adjacent first capacitor electrode, each comprising a lower portion and an upper portion, wherein the lower portion has a different width than the upper portion at a stepped transition region, the width difference between the lower portion and the upper portion at the stepped transition region being between 1 Å and 50 Å, and the distance between the outer surface of the first capacitor electrode and the outer surface of the laterally adjacent first capacitor electrode is greater than the distance between the respective upper portions of the first capacitor electrode and the laterally adjacent first capacitor electrode, and greater than the distance between the respective lower portions of the first capacitor electrode and the laterally adjacent first capacitor electrode; A capacitor dielectric, which is located on the first capacitor electrode and the laterally adjacent first capacitor electrode; and The second capacitor electrode and a laterally adjacent second capacitor electrode, which are located on the capacitor dielectric; and Access device, which is operatively coupled to the DRAM capacitor.

24. The semiconductor device of claim 23, wherein the aspect ratio of the at least one DRAM capacitor is greater than 20:

1.

25. The semiconductor device according to any one of claims 23 and 24, wherein the aspect ratio of the at least one DRAM capacitor is from 50:1 to 100:

1.

26. A semiconductor system comprising: Memory array, comprising: A memory cell including a DRAM capacitor and an access means operatively coupled to the DRAM capacitor, at least one of the DRAM capacitors comprising: A first capacitor electrode is formed on a substrate, the first capacitor electrode including a lower portion adjacent to the substrate and an upper portion configured to be away from the substrate, the lower portion having a greater thickness than the upper portion along the entire length of the first capacitor electrode; The capacitor dielectric, which is adjacent to the first capacitor electrode; and The second capacitor electrode is located adjacent to the capacitor dielectric.

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