Transistor and method of manufacturing the same

Abstract

The present disclosure provides a transistor, which comprises: a substrate layer; a semiconductor channel region formed above the substrate layer; a first electrode and a second electrode formed in the semiconductor channel region, and the first electrode and the second electrode are spaced apart by a preset distance; a gate dielectric layer formed at least on the opposite surfaces of the first electrode and the second electrode; and a gate electrode disposed between the first electrode and the second electrode, and the gate electrode is separated from the first electrode and the second electrode by the gate dielectric layer; wherein the substrate layer is formed with a recessed portion, the recessed portion has a bottom surface, and the lower surface of the semiconductor channel region and the bottom surface of the recessed portion are separated by a preset distance, or part of the semiconductor channel region is in contact with the bottom surface of the recessed portion. The present disclosure also provides a preparation method of the transistor.

Description

Technical Field

[0001] This disclosure relates to a transistor and a method for fabricating the same. Background Technology

[0002] During the fabrication of carbon nanotube transistors, various chemical processes are employed, resulting in impurities remaining between the carbon nanotubes and the substrate. These impurities are difficult to remove using conventional methods such as annealing and chemical cleaning, which adversely affects the performance of the transistors.

[0003] In particular, the high-purity, high-density semiconductor carbon nanotube arrays required for current integrated circuit applications first require the separation of a high-purity semiconductor carbon nanotube solution using a polymer encapsulation method, followed by the formation of a high-density array on a chemically treated substrate using a self-assembly method. However, the polymers encapsulating the carbon nanotubes and the modifications on the substrate negatively impact key parameters of transistors, such as on-state current, transconductance, and threshold voltage.

[0004] Therefore, there is an urgent need to design a transistor structure and its fabrication method to solve the above-mentioned technical problems. Summary of the Invention

[0005] To address one of the aforementioned technical problems, this disclosure provides a transistor and a method for fabricating the same.

[0006] According to one aspect of this disclosure, a transistor is provided, comprising:

[0007] Substrate layer;

[0008] A semiconductor channel region is formed above the substrate layer;

[0009] A first electrode and a second electrode are formed in the semiconductor channel region, and the first electrode and the second electrode are spaced apart by a predetermined distance.

[0010] A gate dielectric layer, the gate dielectric layer being formed on at least a portion of the upper surface of the semiconductor channel region; and

[0011] A gate electrode is disposed between the first electrode and the second electrode, such that a gate dielectric layer exists between the gate electrode and the first electrode, and between the gate electrode and the second electrode.

[0012] The substrate layer has a recessed portion with a bottom surface. The lower surface of the semiconductor channel region and the bottom surface of the recessed portion are at a predetermined distance, or a portion of the semiconductor channel region is in contact with the bottom surface of the recessed portion.

[0013] According to at least one embodiment of the transistor of the present disclosure, the lower surface of the semiconductor channel region is planar or substantially planar, such that the semiconductor channel region has a predetermined distance from the recessed bottom surface.

[0014] According to at least one embodiment of the transistor of the present disclosure, a portion of the lower surface of the semiconductor channel region protrudes downward such that a portion of the semiconductor channel region is located within the recess.

[0015] According to at least one embodiment of the transistor of the present disclosure, the recess is formed in the region between the first electrode and the second electrode.

[0016] According to at least one embodiment of the transistor of the present disclosure, the recess extends at least beyond one end of the semiconductor channel region along the length direction of the first electrode and the second electrode.

[0017] According to at least one embodiment of the transistor of the present disclosure, the gate dielectric layer covers the surfaces opposite to the first and second electrodes and the semiconductor channel region between the first and second electrodes.

[0018] According to at least one embodiment of the transistor of the present disclosure, after a semiconductor channel region is disposed on the substrate layer, the substrate material below the semiconductor channel region is etched to a certain depth by an etching process to form the recess.

[0019] According to at least one embodiment of the transistor of the present disclosure, when the substrate material below the semiconductor channel region is etched by an etching process, the semiconductor channel region is at least partially separated from the substrate layer, and the recess is formed at the separation of the semiconductor channel region from the substrate layer.

[0020] According to at least one embodiment of the transistor of the present disclosure, the semiconductor channel region is deformed so that a portion of the semiconductor channel region enters the recess.

[0021] According to at least one embodiment of the transistor of the present disclosure, the material forming the semiconductor channel region includes semiconductor metal oxide, two-dimensional transition metal sulfide, graphene, carbon nanotube, organic semiconductor, black phosphorus, or molybdenum disulfide.

[0022] According to another aspect of this disclosure, a method for fabricating a transistor is provided, comprising:

[0023] Prepare the substrate and clean the substrate;

[0024] A semiconductor channel region is fabricated on the substrate layer;

[0025] A first electrode and a second electrode are fabricated on the semiconductor channel region;

[0026] The substrate layer below the semiconductor channel region is etched to a certain depth in order to form a recess in the substrate layer;

[0027] A gate dielectric layer is fabricated on the first electrode, the second electrode, and the semiconductor channel region;

[0028] A gate electrode is fabricated on the gate dielectric layer.

[0029] According to another aspect of this disclosure, a method for fabricating a transistor is provided, comprising:

[0030] Prepare the substrate and clean the substrate;

[0031] A semiconductor channel region is fabricated on the substrate layer;

[0032] The substrate layer below the semiconductor channel region is etched to a certain depth in order to form a recess in the substrate layer;

[0033] A first electrode and a second electrode are fabricated on the semiconductor channel region;

[0034] A gate dielectric layer is fabricated on the first electrode, the second electrode, and the semiconductor channel region;

[0035] A gate electrode is fabricated on the gate dielectric layer.

[0036] A method for fabricating a transistor according to at least one embodiment of the present disclosure includes:

[0037] After the recess is formed in the substrate layer, the semiconductor channel region above the recess is solvent cleaned and / or annealed.

[0038] According to at least one embodiment of the transistor fabrication method of this disclosure, the material forming the semiconductor channel region includes semiconductor metal oxide, two-dimensional transition metal sulfide, graphene, carbon nanotube, organic semiconductor, black phosphorus, or molybdenum disulfide.

[0039] According to another aspect of this disclosure, a transistor is provided, which is fabricated by the transistor fabrication method described above. Attached Figure Description

[0040] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0041] Figure 1 This is a schematic diagram of a transistor according to one embodiment of the present disclosure.

[0042] Figure 2Aand Figure 2B This is a schematic diagram of the structure of a substrate layer according to one embodiment of the present disclosure.

[0043] Figure 3A and Figure 3B This is a schematic diagram of the structure of a semiconductor channel region according to one embodiment of the present disclosure.

[0044] Figure 4A and Figure 4B This is a schematic diagram of the source and drain electrodes according to one embodiment of the present disclosure.

[0045] Figure 5A and Figure 5B This is a schematic diagram of the structure of a recess according to one embodiment of the present disclosure.

[0046] Figure 6A and Figure 6B This is a schematic diagram of the gate dielectric layer according to one embodiment of the present disclosure.

[0047] Figure 7A and Figure 7B This is a schematic diagram of the structure of a gate electrode according to one embodiment of the present disclosure.

[0048] Figure 8 This is an electron microscope image of a transistor according to one embodiment of the present disclosure.

[0049] Figure 9 This is a performance curve of a transistor according to one embodiment of the present disclosure.

[0050] Figure 10 This is a flowchart of a method for fabricating a transistor according to one embodiment of the present disclosure.

[0051] Figure 11 This is a flowchart of a method for fabricating a transistor according to another embodiment of the present disclosure.

[0052] Figure 12 This is a flowchart of a method for fabricating a transistor according to another embodiment of the present disclosure.

[0053] Figure 13 This is a flowchart of a method for fabricating a transistor according to another embodiment of the present disclosure.

[0054] The specific labels in the attached figures are as follows:

[0055] 100 transistors

[0056] 110 substrate layer

[0057] 111 Depression

[0058] 120 Semiconductor Channel Region

[0059] 130 First Electrode

[0060] 140 Second Electrode

[0061] 150 gate dielectric layer

[0062] 160 gate electrode. Detailed Implementation

[0063] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0064] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0065] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0066] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0067] When a component is referred to as being "on" or "above" another component, "connected to," or "joined to" another component, the component may be directly on, directly connected to, or directly joined to the other component, or there may be intermediate components. However, when a component is referred to as being "directly on" another component, "directly connected to," or "directly joined to" another component, there are no intermediate components. Therefore, the term "connection" can refer to a physical connection, an electrical connection, etc., and may or may not have intermediate components.

[0068] For descriptive purposes, this disclosure may use spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side (e.g., in a “sidewall”)” to describe the relationship between one component and another component as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, a component described as “below” or “under” another component or feature would subsequently be positioned “above” said other component or feature. Thus, the exemplary term “below” can encompass both “above” and “below” orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0069] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0070] Figure 1 This is a schematic diagram of a transistor according to one embodiment of the present disclosure.

[0071] like Figure 1 As shown, the transistor 100 of this disclosure includes a substrate layer 110, a semiconductor channel region 120, a first electrode 130, a second electrode 140, a gate dielectric layer 150, and a gate electrode 160. The substrate layer 110 is preferably a silicon wafer covered with silicon dioxide. Of course, the substrate layer 110 can also be made of materials such as glass, quartz, ITO, or flexible materials such as PI and PET.

[0072] A semiconductor channel region 120 is formed above the substrate layer 110. In this disclosure, the materials used for the semiconductor channel region 120 may include: semiconductor metal oxides, two-dimensional transition metal sulfides, graphene, carbon nanotubes, organic semiconductors, black phosphorus, molybdenum disulfide, and other two-dimensional semiconductor materials, and are preferably carbon nanotubes, for example, high-purity carbon nanotube films in a network or in tandem arrangement can be deposited. That is to say, the transistor and its fabrication method proposed in this disclosure are not only applicable to carbon nanotubes, but can also be widely applied to other low-dimensional materials. As a general rule, as long as the material is not directly grown in bulk, any process in obtaining semiconductor materials, including transfer, CVD growth involving catalysts, and dispersion purification using polymers, will result in contamination and affect transistor performance.

[0073] The first electrode 130 and the second electrode 140 are formed in the semiconductor channel region, such that the first electrode 130 and the second electrode 140 are formed as the source electrode and the drain electrode of the transistor 100. In this disclosure, the first electrode 130 and the second electrode 140 are spaced apart by a predetermined distance.

[0074] As a preferred embodiment, the semiconductor channel region 120 includes a first direction (X direction) and a second direction (Y direction). Taking the semiconductor channel region 120 as a thin film formed of carbon nanotubes as an example, the first direction can be the length direction of the semiconductor channel region 120, that is, the alignment direction of the carbon nanotube thin film, and the second direction can be a direction perpendicular to the first direction.

[0075] In a first direction, the first electrode 130 and the second electrode 140 are located between the two ends of the semiconductor channel region 120.

[0076] On the other hand, the length direction of the first electrode 130 and the second electrode 140 is the second direction. Preferably, the first electrode 130 and the second electrode 140 can be arranged in parallel or substantially parallel. The two ends of the length direction of the first electrode 130 and the second electrode 140 extend beyond the semiconductor channel region 120, and at least a portion of the surfaces of the first electrode 130 and the second electrode 140 are in contact with the upper surface of the substrate layer 110. This allows the first electrode 130 and the second electrode 140 to fix the semiconductor channel region 120. When the substrate layer 110 has a recess 111, it can prevent the semiconductor channel region 120 from peeling off from the surface of the substrate layer 110 during the etching process.

[0077] Preferably, along the second direction, both ends of the first electrode 130 and the second electrode 140 extend beyond the semiconductor channel region 120, so that the semiconductor channel region 120 can be more firmly fixed to the substrate layer 110 by the first electrode 130 and the second electrode 140.

[0078] In this disclosure, the first electrode 130 and the second electrode 140 can be formed from any suitable material or combination of materials. Examples of materials that can be used for the first electrode 130 and the second electrode 140 include, but are not limited to, metals, conductive or semiconductor metal oxides, conductive or semiconductor polymers, doped semiconductors, graphene, and two-dimensional (2D) semiconductors. As a preferred example, the materials for the first electrode 130 and the second electrode 140 can be one or more metallic materials such as Ti (titanium), Pd (palladium), or Au (gold).

[0079] Since the first electrode 130 and the second electrode 140 are arranged in parallel or substantially parallel, and the first electrode 130 and the second electrode 140 extend to a certain height, the first electrode 130 and the second electrode 140 have opposing surfaces, and the gate dielectric layer 150 is formed at least on the opposing surfaces of the first electrode 130 and the second electrode 140.

[0080] Preferably, the gate dielectric layer 150 is formed on at least a portion of the upper surface of the semiconductor channel region 120. In one embodiment, the gate dielectric layer 150 covers the surfaces opposite to the first electrode 130 and the second electrode 140 and the semiconductor channel region 120 between the first electrode 130 and the second electrode 140, thereby forming a receiving space in which the gate electrode 160 is disposed.

[0081] In another embodiment, considering that the gate dielectric layer 150 is obtained through ALD growth, the gate dielectric layer 150 can also be grown on the lower surface of the semiconductor channel region 120, or even on the inner surface of the recess in the substrate layer 110, forming a structure similar to a ring gate. However, those skilled in the art should know that the gate dielectric layer 150 located below the semiconductor channel region cannot form gate control because no voltage can be applied; only the gate dielectric layer 150 above the semiconductor channel region can form gate control.

[0082] In this disclosure, examples of materials forming the gate dielectric layer 150 include, but are not limited to, any one of the following: SiO2, HfO2, ZrO2, Ta2O5, Y2O3, Nb2O5, Al2O3, TiO2, CeO2, In2O3, RuO2, MgO, SrO, B2O3, SnO2, PbO, PbO2, Pb3O4, V2O3, La2O3, Pr2O3, Sb2O3, Sb2O5, CaO, etc.

[0083] The gate electrode 160 is disposed between the first electrode 130 and the second electrode 140, and a gate dielectric layer 150 exists between the gate electrode 160 and the first electrode 130, and between the gate electrode 160 and the second electrode 140. That is, the gate electrode 160 cannot be directly electrically connected to the first electrode 130, and correspondingly, the gate electrode 160 cannot be directly electrically connected to the second electrode 140. As one implementation, the gate electrode 160 can be made of metallic materials such as Ti, Al, Sc, Ni, Pd, Au, and Pt, or it can be a stacked structure of metallic materials.

[0084] In this disclosure, the substrate layer 110 has a recess 111, the recess 111 has a bottom surface, the lower surface of the semiconductor channel region 120 and the bottom surface of the recess 111 are at a predetermined distance, or a portion of the semiconductor channel region 120 is in contact with the bottom surface of the recess 111.

[0085] On one hand, the lower surface of the semiconductor channel region 120 is planar or substantially planar, so that the semiconductor channel region 120 and the recessed bottom surface have a predetermined distance. That is, after the recessed portion 111 is formed on the substrate layer 110, the semiconductor channel region 120 does not deform or the deformation is small. On the other hand, when the deformation of the semiconductor channel region 120 is large, a portion of the lower surface of the semiconductor channel region 120 protrudes downward, so that a portion of the semiconductor channel region 120 is located within the recessed portion 111. More preferably, the semiconductor channel region 120 deforms so that a portion of the semiconductor channel region 120 enters the recessed portion 111.

[0086] Furthermore, when at least a portion of the semiconductor channel region 120 is located within the recess 111, the semiconductor channel region 120 and the bottom surface of the recess 111 can also be spaced apart.

[0087] In this disclosure, the recess 111 is formed in the region between the first electrode 130 and the second electrode 140. More preferably, along the length direction of the first electrode 130 and the second electrode 140, the recess 111 extends at least beyond one end of the semiconductor channel region 120. That is, along the second direction, the recess 111 extends at least beyond one end of the semiconductor channel region 120.

[0088] More preferably, after the semiconductor channel region 120 is disposed on the substrate layer 110, the substrate material below the semiconductor channel region 120 is etched to a certain depth by an etching process to form the recess 111. Moreover, when the substrate material below the semiconductor channel region 120 is etched by the etching process, the semiconductor channel region 120 is at least partially separated from the substrate layer 110, and the recess 111 is formed at the separation point between the semiconductor channel region 120 and the substrate layer 110.

[0089] Figure 10 This is a flowchart of a method for fabricating a transistor according to one embodiment of the present disclosure.

[0090] According to another aspect of this disclosure, such as Figure 10 As shown, a method for fabricating a transistor 100 is provided. In this disclosure, the method for fabricating the transistor 100 can fabricate the aforementioned transistor 100, and includes:

[0091] Prepare substrate 110 and clean substrate 110, resulting in substrate 110 as shown. Figure 2A and Figure 2B As shown, where, Figure 2A This is a side view of the substrate layer 110. Figure 2B This is a top view of the substrate layer 110.

[0092] A semiconductor channel region 120 is fabricated on the substrate layer 110. Specifically, in fabricating the semiconductor channel region, a semiconductor material layer is deposited on the substrate layer 110, such as a carbon nanotube thin film or a two-dimensional semiconductor material, or carbon nanotubes, nanowires, or a two-dimensional transition metal sulfide. Then, photolithography and etching are used to pattern the active region of the semiconductor material layer, thereby forming the semiconductor channel region 120. The semiconductor channel region 120 obtained through this step is as follows: Figure 3A and Figure 3B As shown, where, Figure 3A This is a side view of the substrate layer 110 and the semiconductor channel region 120. Figure 3B This is a top view of the substrate layer 110 and the semiconductor channel region 120.

[0093] A first electrode 130 and a second electrode 140 are fabricated on the semiconductor channel region 120. Specifically, the first electrode 130 and the second electrode 140 can be formed by thin film growth, photolithography, and etching, thereby forming the first electrode 130 and the second electrode 140 as source and drain electrodes. The source and drain electrodes obtained through this step are as follows: Figure 4A and Figure 4B As shown, where, Figure 4A This is a side view of the source and drain electrodes. Figure 4B This is a top view of the source and drain electrodes.

[0094] For example, when the transistor is a MOSFET, the first electrode 130 can serve as the source of the MOSFET, and the second electrode 140 can serve as the drain of the MOSFET. Alternatively, the first electrode 130 can also serve as the drain of the MOSFET, and the second electrode 140 can serve as the source of the MOSFET. The region between the first electrode 130 and the second electrode 140 is the channel length of the MOSFET.

[0095] In this disclosure, after the source and drain electrodes are formed, a recess is formed on the substrate layer 110. Specifically, the substrate layer 110 below the semiconductor channel region 120 can be etched to a certain depth using photolithography and wet etching processes to form the recess 111 in the substrate layer 110. Moreover, forming the recess 111 after forming the first electrode 130 and the second electrode 140 can prevent the semiconductor channel region 120 from being peeled off from the surface of the substrate layer 110 during the wet etching process. After this process, the semiconductor material of the semiconductor channel region 120 can be in a suspended state or fall onto the exposed new substrate surface (the bottom surface of the recess) due to deformation.

[0096] Figure 12 This is a flowchart of a method for fabricating a transistor according to another embodiment of the present disclosure.

[0097] like Figure 12 As shown, the semiconductor channel region 120 above the recess 111 is processed. Specifically, annealing and / or solvent cleaning are used to perform solvent cleaning and / or annealing on the semiconductor channel region 120 above the recess 111 of the substrate layer 110 to further remove impurities on the surface of the semiconductor channel region 120.

[0098] The recess 111 obtained through this step is as follows: Figure 5A and Figure 5B As shown, where, Figure 5A This is a side view of the recessed portion 111. Figure 5B This is a top view of the recessed portion 111.

[0099] A gate dielectric layer 150 is prepared on the first electrode 130, the second electrode 140, and the semiconductor channel region 120. Specifically, the gate dielectric layer 150 can be prepared by photolithography, atomic layer deposition, or other methods. The gate dielectric layer 150 can be HfO2, Y2O3, or other insulating layers, and the gate dielectric region is formed by etching.

[0100] The gate dielectric layer 150 obtained through this step is as follows: Figure 6A and Figure 6B As shown, where, Figure 6A This is a side view of the gate dielectric layer 150. Figure 6B This is a top view of the gate dielectric layer 150.

[0101] A gate electrode 160 is fabricated on the gate dielectric layer 150. Specifically, the gate electrode 160 can be formed by thin film growth, photolithography, and etching. The gate electrode 160 obtained through this step is as follows: Figure 7A and Figure 7B As shown, where, Figure 7A This is a side view of the gate electrode 160. Figure 7B This is a top view of the gate electrode.

[0102] Figure 11 This is a flowchart of a method for fabricating a transistor according to another embodiment of the present disclosure.

[0103] As another implementation, such as Figure 11 As shown, before fabricating the first electrode and the second electrode on the semiconductor channel region, the substrate layer below the semiconductor channel region is etched to a certain depth to form a recess in the substrate layer.

[0104] Figure 13 This is a flowchart of a method for fabricating a transistor according to another embodiment of the present disclosure.

[0105] And preferably, such as Figure 13 As shown, after the recess 111 is formed, the recess 111 may also be subjected to annealing and / or solvent cleaning.

[0106] According to another aspect of this disclosure, a transistor 100 is provided, which is fabricated by the above-described method for fabricating a transistor 100.

[0107] like Figure 8 and Figure 9 As shown, Figure 8 (a) is a photograph of the surface of the silicon dioxide substrate after etching; Figure 8 (b) is a transistor scanning electron microscope (SEM) image of the silicon dioxide on the substrate surface after etching; Figure 8 (c) Transistor projection electron microscope (TEM) image of silicon dioxide on the substrate surface after etching.

[0108] Figure 9 (a) Transfer characteristic curves of carbon nanotube transistors before and after substrate surface etching; (b) Statistical results of on-state current of carbon nanotube transistors before and after substrate surface etching; (c) Statistical results of on-state current (over-gate voltage of -1V) of carbon nanotube transistors before and after substrate surface etching; (d) Statistical results of threshold voltage of carbon nanotube transistors before and after substrate surface etching; (e) Statistical results of hysteresis of carbon nanotube transistors before and after substrate surface etching; (f) Statistical results of on / off ratio of carbon nanotube transistors before and after substrate surface etching; (g) Statistical results of subthreshold slope swing of carbon nanotube transistors before and after substrate surface etching; (h) Statistical results of transconductance of carbon nanotube transistors before and after substrate surface etching.

[0109] like Figure 8 and Figure 9 As shown, in the transistor and its fabrication method disclosed herein, impurities on the contact surface between the semiconductor channel region 120 and the substrate layer 110 can be reduced, thereby improving the electrical performance of the transistor. Compared with the prior art, the transistor disclosed herein has a 35% increase in on-state current, a 59% reduction in hysteresis, a 6% increase in on / off ratio, an 11% reduction in subthreshold slope swing, and a 33% increase in transconductance.

[0110] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0111] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0112] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A transistor, characterized in that, include: Substrate layer; A semiconductor channel region is formed above the substrate layer; wherein the semiconductor channel region includes a first direction and a second direction, the first direction being the length direction of the semiconductor channel region, and the second direction being a direction perpendicular to the first direction; A first electrode and a second electrode are formed in the semiconductor channel region and are spaced apart by a predetermined distance; in a first direction, the first electrode and the second electrode are located between two ends of the semiconductor channel region; the length direction of the first electrode and the second electrode is the second direction; both ends of the length direction of the first electrode and the second electrode extend beyond the semiconductor channel region, such that at least a portion of the surface of the first electrode and the second electrode is in contact with the upper surface of the substrate layer. A gate dielectric layer, the gate dielectric layer being formed on at least a portion of the upper surface of the semiconductor channel region; and A gate electrode is disposed between the first electrode and the second electrode, such that a gate dielectric layer exists between the gate electrode and the first electrode, and between the gate electrode and the second electrode. The substrate layer has a recessed portion, the recessed portion has a bottom surface, the lower surface of the semiconductor channel region and the bottom surface of the recessed portion have a predetermined distance, or a portion of the semiconductor channel region is in contact with the bottom surface of the recessed portion; The gate dielectric layer covers the surfaces opposite to the first and second electrodes and the semiconductor channel region between the first and second electrodes. The gate dielectric layer is obtained by ALD growth and is grown on the lower surface of the semiconductor channel region and on the inner surface of the recess in the substrate layer. In this process, after the recess is formed in the substrate layer, the semiconductor channel region above the recess is solvent cleaned and / or annealed.

2. The transistor as claimed in claim 1, characterized in that, The lower surface of the semiconductor channel region is planar, so that the semiconductor channel region and the recessed bottom surface have a predetermined distance.

3. The transistor as claimed in claim 1, characterized in that, A portion of the lower surface of the semiconductor channel region protrudes downwards, such that a portion of the semiconductor channel region is located within the recess.

4. The transistor as claimed in claim 1, characterized in that, The recess is formed in the region between the first electrode and the second electrode.

5. The transistor as claimed in claim 1, characterized in that, Along the length direction of the first electrode and the second electrode, the recess extends at least beyond one end of the semiconductor channel region.

6. The transistor as claimed in claim 1, characterized in that, After the semiconductor channel region is formed on the substrate layer, the substrate material below the semiconductor channel region is etched to a certain depth by an etching process to form the recess.

7. The transistor as claimed in claim 1, characterized in that, When the substrate material below the semiconductor channel region is etched by an etching process, the semiconductor channel region is at least partially separated from the substrate layer, and the recess is formed at the separation point between the semiconductor channel region and the substrate layer.

8. The transistor as claimed in claim 7, characterized in that, The semiconductor channel region is deformed so that a portion of the semiconductor channel region enters the recess.

9. The transistor as claimed in claim 1, characterized in that, The materials forming the semiconductor channel region include semiconductor metal oxides, two-dimensional transition metal sulfides, graphene, carbon nanotubes, carbon nanowires, organic semiconductors, or black phosphorus.

10. The transistor as claimed in claim 1, characterized in that, The materials forming the semiconductor channel region include semiconductor nanowires or molybdenum disulfide.

11. A method for fabricating a transistor according to any one of claims 1-10, characterized in that, include: Prepare the substrate and clean the substrate; A semiconductor channel region is fabricated on the substrate layer; A first electrode and a second electrode are fabricated on the semiconductor channel region; The substrate layer below the semiconductor channel region is etched to a certain depth in order to form a recess in the substrate layer; A gate dielectric layer is fabricated on the first electrode, the second electrode, and the semiconductor channel region; A gate electrode is fabricated on the gate dielectric layer; In this process, after the recess is formed in the substrate layer, the semiconductor channel region above the recess is solvent cleaned and / or annealed.

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