Elastic wave device and module including the same

Abstract

An elastic wave device includes a wiring substrate, a resonator, a device chip provided with a wiring pattern electrically connected to the resonator and electrically connected to the wiring substrate, and a sealing portion that seals the device chip, the wiring pattern including a first wiring layer and a second wiring layer, the second wiring layer having a lower metal layer connected to an upper surface of the first wiring layer, a barrier layer connected to an upper surface of the lower metal layer and being a metal layer, and an upper metal layer connected to an upper surface of the barrier layer, the barrier layer being a metal having an electrical conductivity lower than that of the lower metal layer and that of the upper metal layer. Thus, an elastic wave device having a wiring structure with high quality and a module including the elastic wave device can be provided.

Description

Technical Field

[0001] This disclosure relates to an elastic wave device and a module comprising the elastic wave device. Background Technology

[0002] Japanese Patent Document 1 (International Publication No. 2011-089906) illustrates an elastic wave device. The elastic wave device is a high-frequency filter with a passband frequency range between tens of MHz and several GHz. The elastic wave device includes a piezoelectric substrate, comb-shaped electrodes disposed on the upper surface of the piezoelectric substrate, first wiring disposed on the upper surface of the piezoelectric substrate, an organic insulator covering at least a portion of the first wiring, a second wiring disposed on a first portion of the upper surface of the organic insulator, and an inorganic insulator covering a second portion of the upper surface of the organic insulator. An excitation space for exciting the piezoelectric substrate is formed above the comb-shaped electrodes, and the second portion of the upper surface of the organic insulator faces the excitation space through the inorganic insulator.

[0003] The quality of cabling structures needs to be improved. For example, a cabling structure with low loss, high reliability, and high durability is required. Summary of the Invention

[0004] In view of the above-mentioned problems, the present disclosure aims to provide an elastic wave device with a high-quality wiring structure and a module including the elastic wave device.

[0005] This disclosure discloses an elastic wave device, comprising a wiring substrate, a resonator, a device chip having a wiring pattern electrically connected to the resonator and electrically connected to the wiring substrate, and a sealing portion sealing the device chip. The wiring pattern includes a first wiring layer and a second wiring layer. The second wiring layer has a lower metal layer connected to the upper surface of the first wiring layer, a spacer layer connected to the upper surface of the lower metal layer and being a metal layer, and an upper metal layer connected to the upper surface of the spacer layer. The spacer layer is a metal with a lower conductivity than the conductivity of the lower metal layer and the upper metal layer.

[0006] In one embodiment of this disclosure, the total thickness of the lower metal layer and the upper metal layer is 6 to 70 times the thickness of the first wiring layer.

[0007] In one embodiment of this disclosure, the elastic wave device further includes a first insulating layer covering a portion of the upper surface of the first wiring layer, and the lower metal layer having a portion connected to the upper surface of the first wiring layer and a portion connected to the upper surface of the first wiring layer through the first insulating layer.

[0008] In one embodiment of this disclosure, the elastic wave device further includes a second insulating layer covering the upper surface of the first insulating layer and the side surface of the second wiring layer.

[0009] In one embodiment of this disclosure, the second wiring layer has a stepped portion, and the second insulating layer covers the stepped portion.

[0010] In one embodiment of this disclosure, the first wiring layer is not directly connected to the second insulating layer.

[0011] In one embodiment of this disclosure, the second wiring layer is directly connected to the first wiring layer, the first insulating layer, and the second insulating layer.

[0012] In one embodiment of this disclosure, the second wiring layer is directly connected to the first wiring layer, the first insulating layer, and the second insulating layer.

[0013] In one embodiment of this disclosure, the coefficient of thermal expansion of the first insulating layer is less than that of the second insulating layer.

[0014] In one embodiment of this disclosure, the width of the second wiring layer is smaller than the width of the first wiring layer.

[0015] In one embodiment of this disclosure, the device chip includes a piezoelectric substrate with the resonator and wiring pattern disposed on its upper surface, and a substrate made of sapphire, silicon, alumina, spinel, crystal or glass and connected to the lower surface of the piezoelectric substrate.

[0016] In one embodiment of this disclosure, the device chip includes a plurality of resonators, wherein the resonators of the device chip are surface wave resonators and have the function of bandpass filters or bidirectional circuits.

[0017] In one embodiment of this disclosure, the device chip includes a plurality of resonators, wherein the resonators of the device chip are thin-film acoustic resonators and have the function of a bandpass filter or a bidirectional circuit.

[0018] In one embodiment of this disclosure, the first wiring layer is a structure in which Ti, AlCu, and Ti are stacked from bottom to top, the lower metal layer is a structure in which Ti and Al are stacked from bottom to top, the separator is Ti, and the upper metal layer is Al.

[0019] The partition layer has an electrical conductivity of 10 × 10⁻⁶. 6 Metals with a conductivity of less than S / m, wherein the lower metal layer and the upper metal layer contain materials with a conductivity of 20 × 10⁻⁶. 6 Metals with a S / m ratio greater than 1.

[0020] This disclosure also includes a module comprising the elastic wave device.

[0021] The beneficial effects of the present invention are as follows: According to this disclosure, an elastic wave device with a high-quality wiring structure and a module including the elastic wave device can be provided. Attached Figure Description

[0022] Figure 1 This is a cross-sectional view of an example of a wiring pattern.

[0023] Figure 2 This is a cross-sectional view of an example of the structure of an elastic wave device.

[0024] Figure 3 It is a plan view of the structure of the device chip.

[0025] Figure 4 This is a plan view of an example of the structure of an elastic wave element.

[0026] Figure 5 This is a cross-sectional view of an example of a wiring pattern.

[0027] Figure 6A This is a schematic diagram of the wiring pattern in an embodiment.

[0028] Figure 6B This is a schematic diagram of the wiring pattern for a comparative example.

[0029] Figure 7 This is a table showing the wiring structures of the comparative examples and embodiments.

[0030] Figure 8 This is a schematic diagram of the simulation results of high-frequency impedance values.

[0031] Figure 9 This is a schematic diagram showing the results of measuring the attenuation of the transmitted signal.

[0032] Figure 10 It is a graph showing the relationship between the attenuation of the transmitted signal and the frequency.

[0033] Figure 11 This is a schematic diagram showing the results of measuring the attenuation of the received signal.

[0034] Figure 12 This is a graph showing the relationship between the attenuation of the received signal and the frequency.

[0035] Figure 13 This is a schematic diagram of the measurement results of the bump shear strength.

[0036] Figure 14 This is a cross-sectional view of an example of a wiring pattern.

[0037] Figure 15 This is a schematic diagram of the wiring pattern manufacturing method.

[0038] Figure 16 This is a schematic diagram of the wiring pattern manufacturing method.

[0039] Figure 17 This is a schematic diagram of the wiring pattern manufacturing method.

[0040] Figure 18 This is a schematic diagram of the wiring pattern manufacturing method.

[0041] Figure 19 This is a schematic diagram of the wiring pattern manufacturing method.

[0042] Figure 20 This is a schematic diagram of the wiring pattern manufacturing method.

[0043] Figure 21 This is a cross-sectional view of an example of the structure of an elastic wave device.

[0044] Figure 22 This is a schematic diagram of an example of a thin-film acoustic resonator.

[0045] Figure 23 This is a cross-sectional view of a module containing the elastic wave device. Detailed Implementation

[0046] The specific embodiments of the present invention will now be described with reference to the accompanying drawings. Identical or equivalent parts in the drawings are labeled the same. Descriptions of these identical or equivalent parts will be appropriately simplified or omitted.

[0047] (First implementation mode)

[0048] Figure 1 This is a cross-sectional view of the wiring pattern in the elastic wave device of the first embodiment. A wiring pattern including a first wiring layer 12 and a second wiring layer 19 is provided on the piezoelectric element 10. The first wiring layer 12 has one or more metal layers. The second wiring layer 19 has a lower metal layer 14 connected to the upper surface of the first wiring layer 12, a spacer 16, which is also a metal layer, connected to the upper surface of the lower metal layer 14, and an upper metal layer 18 connected to the upper surface of the spacer 16. According to one example, the lower metal layer 14 has one or more metal layers, and the upper metal layer 18 also has one or more metal layers. Figure 1 In one example, the width of the second wiring layer 19 is smaller than the width of the first wiring layer 12. According to one example, the total thickness of the lower metal layer 14 and the upper metal layer 18 is 6 to 70 times the thickness of the first wiring layer 12.

[0049] The separator 16 is formed between the lower metal layer 14 and the upper metal layer 18. According to one example, the separator 16 is a metal with a lower conductivity than both the lower metal layer 14 and the upper metal layer 18. According to other examples, the separator 16 is a metal with a lower conductivity than the first wiring layer 12, the lower metal layer 14, and the upper metal layer 18. For example, the separator 16 is made of one or more materials selected from Ti, Mn, Pd, Cr, Pt, and Sn. Furthermore, the lower metal layer 14 and the upper metal layer 18 comprise one or more materials selected from, for example, Ag, Cu, Au, Al, Be, and W. According to other examples, the separator 16 has a conductivity of 10 × 10⁻⁶. 6 Metals with a conductivity of less than S / m, wherein the lower metal layer 14 and the upper metal layer 18 contain metals with a conductivity of 20 × 10⁻⁶. 6 Metals with a conductivity of S / m or higher. According to one example, the spacer 16 connects the lower metal layer 14 to the upper metal layer 18, where the conductivity is 20 × 10⁻⁶. 6 Metal portions with a conductivity of S / m or higher. Furthermore, the first wiring layer 12 may also include a metal portion with a conductivity of 20 × 10⁻⁶. 6 Metals with a S / m ratio greater than 1.

[0050] According to one example, a first insulating layer 20 is formed to electrically insulate against conductors adjacent to the wiring pattern. The first insulating layer 20 is an insulator. Figure 1 As shown, the first insulating layer 20 is formed on the piezoelectric body 10, on the side of the first wiring layer 12, and on a portion of the upper surface of the first wiring layer 12.

[0051] Figure 2 This is a cross-sectional view of an example of the configuration of the elastic wave device 1. The elastic wave device 1 includes a wiring substrate 2. According to one example, the wiring substrate 2 is a multilayer substrate containing resin. According to other examples, the wiring substrate 2 is a low-temperature co-fired ceramic (LTCC) multilayer substrate formed of multiple dielectric layers. Passive components such as capacitors or inductors may also be disposed inside the wiring substrate 2.

[0052] exist Figure 2 In the example, the wiring substrate 2 includes a plurality of conductive pads 2b on its upper surface, which serves as a mounting surface for components. The lower surface of the wiring substrate 2 is, for example, the mounting surface of a motherboard. A plurality of conductive pads 2c are provided on the lower surface of the wiring substrate 2. The conductive pads 2b and the conductive pads 2c correspond to each other and are connected by an internal conductor 2a or a through-hole conductor.

[0053] The wiring substrate 2 has a device chip 3 electrically connected to it. The device chip 3 is, for example, a surface elastic wave device chip. The device chip 3 includes a piezoelectric substrate 3a made of a piezoelectric material. The piezoelectric body 10 is part of the piezoelectric substrate 3a. According to one example, the piezoelectric substrate 3a is a substrate made of piezoelectric single crystals such as lithium tantalate, lithium niobate, or quartz. According to another example, the piezoelectric substrate 3a is a substrate made of piezoelectric ceramic. According to yet another example, the piezoelectric substrate 3a is a substrate formed by combining a piezoelectric substrate and a support substrate. The support substrate is, for example, a substrate made of sapphire, silicon, alumina, spinel, quartz, or glass.

[0054] According to one example, the piezoelectric substrate 3a is a substrate for setting functional elements. For example, a receiving filter and a transmitting filter are formed on the main surface (lower surface) of the device chip 3 facing the wiring substrate 2.

[0055] The receiving filter allows electrical signals of the desired frequency band to pass through. For example, the receiving filter may be a trapezoidal filter formed by multiple series resonators and multiple parallel resonators.

[0056] The transmitting filter allows electrical signals of the desired frequency band to pass through. For example, the transmitting filter may be a trapezoidal filter formed by multiple series resonators and multiple parallel resonators.

[0057] like Figure 2 As shown, the main surface of the device chip 3 is provided with a wiring pattern 3b and a plurality of periodically arranged electrodes 3c. According to one example, the electrodes 3c are comb-shaped interdigital transducer (IDT) electrodes. A high-frequency electric field is applied to the IDT electrodes through the wiring pattern 3b from the power supply side leads to excite elastic surface waves, and the elastic surface waves are converted into a high-frequency electric field through the piezoelectric effect, thereby obtaining the characteristics of a filter.

[0058] The wiring pattern 3b and the conductive pad 2b are electrically connected by bumps 4. The bumps 4 are, for example, gold, conductive adhesive, or solder.

[0059] The elastic wave device 1 also includes a sealing portion 5. According to one example, the sealing portion 5 seals the resin of the device chip 3 while leaving a space 6 between the wiring substrate 2 and the device chip 3. According to one example, the device chip 3 is mounted on the wiring substrate 2, and then a resin layer is placed across the device chip 3. The resin layer is obtained by pressing liquid epoxy resin into a sheet shape. According to other examples, the resin layer can be a synthetic resin such as polyimide, which is different from epoxy resin. A protective film made of polyethylene terephthalate (PET) can be provided on the upper surface of the resin layer, or a base film made of polyester fiber can be provided on the lower surface of the resin layer. By placing the resin layer on the device chip 3, the resin layer is temporarily fixed to the device chip 3. The resin layer is then heated to its softening temperature to fill the sides of the device chip 3 and the upper surface of the wiring substrate 2. This method is called hot rolling. The resin layer is then heated to its curing temperature to harden it.

[0060] According to one example, the device chip 3 includes multiple resonators, which may be surface wave resonators. In this case, the device chip 3 may function as a bandpass filter or a bidirectional circuit.

[0061] Figure 3 This is a plan view illustrating an example of the configuration of device chip 3 and wiring substrate 2. For example... Figure 3 As shown, the elastic wave element 30 and the wiring pattern 32 are formed on the main surface of the device chip 3. The elastic wave element 30 has multiple series resonators S1, S2, S3, S4, S5 and multiple parallel resonators P1, P2, P3, P4.

[0062] According to one example, the series resonators S1, S2, S3, S4, S5 are configured with the parallel resonators P1, P2, P3, P4 in a manner that achieves the function of a transmit filter. Other series resonators are configured with other parallel resonators in a manner that achieves the function of a receive filter.

[0063] For example, the wiring pattern 32 can be formed of a suitable metal or alloy such as silver, aluminum, copper, titanium, palladium, etc. According to one example, at least a portion of the wiring pattern 32 has the following characteristics: Figure 1 The wiring pattern. According to other examples, the wiring pattern 32 generally has the following characteristics: Figure 1 The wiring pattern 32 has a thickness of, for example, 1500 nm to 4500 nm.

[0064] The wiring pattern 32 is electrically connected to the elastic wave element 30. The wiring pattern 32 includes antenna bump pads ANT, transmit bump pads Tx, receive bump pads Rx, and four ground bump pads GND. These bump pads have portions that are electrically connected to bumps 4 during installation. The wiring pattern 32 not only includes the bump pads but also includes wiring portions connecting the bump pads to the elastic wave element 30.

[0065] Figure 4 This is a schematic diagram of the elastic wave element 30. (As shown...) Figure 4 As shown, an IDT 31 and a pair of reflectors 39 are formed on the main surface of the device chip 3. The IDT 31 and the reflectors 39 are arranged in a manner that can excite elastic surface waves.

[0066] According to one example, the IDT 31 and the reflector 39 are formed of an alloy of aluminum and copper. According to other examples, the IDT 31 and the reflector 39 are formed of a suitable metal such as titanium, palladium, silver, or an alloy thereof. According to yet another example, the IDT 31 and the reflector 39 may be formed of a stacked metal film composed of multiple metal films. The IDT 31 and the reflector 39 are not limited to the above materials; for example, Ti may be added to the upper and lower surfaces of the above materials. According to one example, the thickness of the IDT 31 and the reflector 39 is 150 nm to 400 nm.

[0067] The IDT 31 has a pair of comb-shaped electrodes 31a. The comb-shaped electrodes 31a are opposite to each other. Each comb-shaped electrode 31a has a plurality of electrode fingers 31b and a busbar 31c. The electrode fingers 31b extend longitudinally. The busbar 31c connects the electrode fingers 31b. From a top view, the IDT 31 is sandwiched by the reflector 39. According to one example, the materials of the IDT 31 and the reflector 39 can be the same as... Figure 1 The first wiring layer 12 is made of the same material. In this case, the IDT 31, the reflector 39, and the first wiring layer 12 can be formed and patterned in the same process.

[0068] According to one example, the SAW (Surface Acoustic Wave) resonator is electrically connected to the wiring pattern 32. Furthermore, the device chip 3 is electrically connected to the wiring substrate 2, and the input signal from the wiring substrate 2 is output from the wiring substrate 2 after being filtered by the device chip 3.

[0069] Figure 5The example shows a cross-sectional view of the wiring pattern. The first wiring layer 12 is a structure in which Ti layer 12a, AlCu layer 12b, and Ti layer 12c are stacked from bottom to top. The lower metal layer 14 is a structure in which Ti layer 14a and Al layer 14b are stacked from bottom to top. The separator layer 16 is Ti. The upper metal layer 18 is Al.

[0070] According to one example, wiring patterns can also be formed on the substrate formed by the piezoelectric substrate 10a and the substrate 10b connected to the lower surface of the piezoelectric substrate 10a. According to one example, a resonator and wiring patterns are formed on the upper surface of the piezoelectric substrate 10a. The substrate 10b is made of, for example, sapphire, silicon, alumina, spinel, crystal, or glass. Figure 5 In this case, the device chip 3 includes the piezoelectric substrate 10a and the substrate 10b.

[0071] See Figures 6 to 7. Figure 13 The embodiments and comparative examples are explained. Figure 6A This is a cross-sectional view of the wiring pattern in the embodiment. Figure 6B This is a cross-sectional view of the wiring pattern structure of a comparative example. Figure 6A The wiring pattern includes a first wiring layer 12, a Ti layer, an A1 layer, a Ti layer, and an A1 layer. The Ti layer, the A1 layer, the Ti layer, and the A1 layer are formed sequentially on the first wiring layer 12. Figure 6B The wiring pattern structure includes a first wiring layer 12, a Ti layer, and an Al layer. The Ti layer and the Al layer are formed sequentially on the first wiring layer 12. In both the embodiment and the comparative example, the first wiring layer 12 includes a structure in which a Ti layer, an AlCu layer, and a Ti layer are formed sequentially on the piezoelectric substrate. In other words, the first wiring layer 12 and the IDT in the embodiment and the comparative example have the same layered structure.

[0072] Figure 7 The table showing the layer thicknesses of the embodiments and comparative examples is provided. The outermost Al layer of Comparative Example 1 is 1500 nm, while the outermost Al layer of Comparative Example 2 is 4000 nm. The thickness of the separator 16 described in Examples 1-4 is different. The separator 16 is 110 nm in Example 1, 115 nm in Example 2, 120 nm in Example 3, and 150 nm in Example 4.

[0073] Figure 8 This is a schematic diagram showing the simulation results of the high-frequency impedance values ​​for Example 1 and Comparative Example 2. From... Figure 8 It is understood that, within the frequency range of 0.5 GHz to 8 GHz, the high-frequency impedance value of Example 1 is lower than that of Comparative Example 2. Therefore, the wiring structure of Example 1 has lower wiring loss compared to Comparative Example 2, making it more suitable for wiring high-frequency devices.

[0074] Figure 9 This is a schematic diagram showing the measurement results of the attenuation of the transmitted signal in the comparative examples and embodiments. Twenty-one samples were prepared for each wiring structure of Comparative Examples 1 and 2 and Embodiments 1-4, and the results of measuring the attenuation of the transmitted signal are shown below. Figure 9 .from Figure 9 Comparative Example 2 shows that it suppresses signal loss better than Comparative Example 1, indicating that thickening the Al layer of the lower metal layer 14 can suppress signal loss. Furthermore, it can be understood that the wiring structures of Examples 1-4 have lower signal loss compared to Comparative Examples 1 and 2. Therefore, compared to simply thickening the Al layer of the lower metal layer 14 as in Comparative Example 2, thickening both the partition layer 16 and the upper metal layer 18 can more effectively suppress the attenuation of the transmitted signal. Moreover, comparing Examples 1, 2, 3, and 4, it can be observed that Example 1 has the lowest signal loss, Example 2 has a higher signal loss than Example 1, Example 3 has a higher signal loss than Example 2, and Example 4 has a higher signal loss than Example 3. Therefore, thinning the partition layer 16 of the wiring pattern is effective in reducing the loss of the transmitted signal.

[0075] Figure 10 This is a graph showing the relationship between frequency and the attenuation of the transmitted signal. Figure 10 The relationship between the attenuation of the transmitted signal and the frequency is shown in Comparative Example 1 and Example 1. Figure 10 It is understood that, regardless of the frequency, the wiring structure of Example 1 has lower attenuation of the transmitted signal than the wiring structure of Comparative Example 1.

[0076] Figure 11 This is a schematic diagram showing the measurement results of the attenuation of the received signal in the comparative examples and embodiments. Twenty-one samples were prepared for each wiring structure of Comparative Examples 1 and 2 and Embodiments 1-4, and the results of measuring the attenuation of the received signal are shown below. Figure 11 .from Figure 11 It is understood that the wiring structures of Examples 1-4 are better at suppressing signal loss than Comparative Examples 1 and 2. Furthermore, considering that Comparative Example 2 is better at suppressing signal loss than Comparative Example 1, it is understood that thickening the Al layer of the lower metal layer 14 can suppress signal loss. However, compared to simply thickening the Al layer of the lower metal layer 14 as in Comparative Example 2, thickening both the spacer layer 16 and the upper metal layer 18 can more effectively suppress the attenuation of the received signal.

[0077] Figure 12 This is a graph showing the relationship between frequency and the attenuation of the received signal. Figure 12 The relationship between the attenuation of the received signal and the frequency is shown in Comparative Example 1 and Example 1. Figure 12 It is understood that, regardless of the frequency, the wiring structure of Example 1 has lower signal attenuation than the wiring structure of Comparative Example 1.

[0078] Figure 13 This is a schematic diagram of the bump shear strength test results. After forming the wiring pattern, bumps are formed on the wiring pattern. To test the adhesion of the bumps, a shear test is performed. Corresponding to... Figure 13 The leftmost data sample is the baseline (BL) sample. The BL sample uses a 1.5μm thick Al layer as the wiring pattern, with bumps formed on top of it. From... Figure 13 It is understood that the BL sample has better shear strength because it has a thinner wiring pattern.

[0079] Comparative Example 2 (4.0 μm Tape liftoff) shows that the underlying metal layer 14 comprises a 4.0 μm Al layer. In this case, the shear strength is worse compared to other samples. Comparative Example 3 (M2Top Ti 0nm) has the same characteristics as the other samples. Figure 7 The wiring pattern is similar to that of the first embodiment, but the 10nm Ti connecting the lower metal layer 14 in the spacer 16 is omitted, which is similar to... Figure 7 The wiring pattern differs from that of the first embodiment. Therefore, the wiring patterns of Comparative Example 3 and Examples 1-4 are different in the thickness portion of the Ti layer in the interlayer 16. The interlayer 16 gradually increases in thickness according to the order of Comparative Example 3, Examples 1-4 (M2 Top Ti 10nm, M2 Top Ti 15nm, M2 Top Ti 20nm, M2 Top Ti 50nm). The wiring patterns of Comparative Example 3 and Examples 1-4 both possess sufficient shear strength. Assuming a bump shear strength of 14.2 gf is required, Figure 13 All the samples listed met the requirements. However, the shear strength of Comparative Example 2 showed a significant decreasing trend compared to Comparative Example 3 and Examples 1-4. In Comparative Example 2, the wiring pattern was thickened using only one Al layer. Although a thicker Al-Au compound was formed between the Al layer and the Au bumps in this case, and the voids and grains also increased, the shear strength decreased. In contrast, Comparative Examples 3 and Examples 1-4 thickened the wiring pattern by adding the spacer 16 between two Al layers. In this case, the formation of the compound between the Al layer and the Au bumps was suppressed by the spacer 16. Therefore, better shear strength was obtained. It can be seen that adding the spacer 16 as an intermediate layer to the wiring pattern is effective in obtaining higher shear strength.

[0080] (Second Implementation)

[0081] Figure 14 This is a cross-sectional view of a wiring pattern configuration example of the second embodiment. A first insulating layer 40 covers a portion of the upper surface of the first wiring layer 12. The lower metal layer 14 has a portion connected to the upper surface of the first wiring layer 12, and a portion connected to the upper surface of the first wiring layer 12 across the first insulating layer 40. A second insulating layer 42 covers the upper surface of the first insulating layer 40 and the side surface of the second wiring layer 19. According to one example, the second insulating layer 42 exposes at least a portion of the upper surface of the upper metal layer 18.

[0082] Figure 14 The second wiring layer 19 is stepped. The second insulating layer 42 covers the stepped portion. Figure 14 In the example, the first wiring layer 12 is not directly connected to the second insulating layer 42. The second wiring layer 19 is directly connected to the first wiring layer 12, the first insulating layer 40, and the second insulating layer 42. Furthermore, the first insulating layer 40 is directly connected to the first wiring layer 12, the second wiring layer 19, and the second insulating layer 42. Therefore, Figure 14 The wiring pattern is covered by the first insulating layer 40 and the second insulating layer 42. According to one example, the coefficient of thermal expansion of the first insulating layer 40 is smaller than that of the second insulating layer 42. This helps to suppress the peeling of the second insulating layer 42.

[0083] Figure 14 The width X1 shown is the difference between the width of the first wiring layer 12 and the width of the lower metal layer 14. The width X1 is, for example, 1.5 μm. The width X2 is the overlap width between the first insulating layer 40 and the lower metal layer 14. The width X2 is, for example, 2.0 μm. The width X3 is the overlap width between the second insulating layer 42 and the spacer layer 16. The width X3 is, for example, 2.0 μm. The width X4 is the overlap width between the second insulating layer 42 and the upper metal layer 18. The width X4 is, for example, 2.0 μm.

[0084] refer to Figure 15-20 The method for manufacturing the wiring pattern according to the second embodiment is described. First, the first wiring layer 12 is patterned, and the first insulating layer 40 is formed. Next, as... Figure 15 The first photoresist PR1 is formed as shown. The first photoresist PR1 exposes a portion of the first wiring layer 12 and a portion of the first insulating layer 40.

[0085] Next, the lower metal layer 14 is formed. Figure 16The diagram shows a cross-sectional view after the formation of the lower metal layer 14. According to one example, the lower metal layer 14 has a Ti layer with a thickness of 100 nm and an AlCu layer with a thickness of 1500 nm formed on the Ti layer. Along with the formation of the lower metal layer 14, a metal layer 14a is also formed on the first photoresist PR1.

[0086] Next, a first lift-off process is performed. This removes the first photoresist PR1 and the metal layer 14a. Figure 17 This is a cross-sectional view after the first stripping process. Next, the second photoresist PR2 is formed. Figure 18 This is a schematic diagram of the second photoresist PR2. The second photoresist PR2 exposes a portion of the underlying metal layer 14.

[0087] Next, the partition layer 16 and the upper metal layer 18 are formed. Figure 19 This is a schematic diagram showing the formation of the spacer layer 16 and the upper metal layer 18. According to one schematic, the spacer layer 16 is a 100nm thick Ti layer, and the upper metal layer 18 is a 1500nm thick AlCu layer. Along with the formation of the spacer layer 16, a metal layer 17 is formed on the second photoresist PR2.

[0088] Next, a second stripping process is performed. This removes the second photoresist PR2 and the metal layer 17. Figure 20 This is a cross-sectional view after the second stripping process. Next, a second insulating layer 42 is formed as required. According to the manufacturing method described above, the width of the spacer layer 16 is the same as the width of the upper metal layer 18. According to other examples, such as... Figure 14 As shown, the width of the partition 16 can also be the same as the width of the lower metal layer 14.

[0089] (Third implementation)

[0090] Figure 21 This is a cross-sectional view of the elastic wave device of the third embodiment. Figure 21 As shown, the elastic wave device 50 includes a first device chip 51 and a second device chip 52. According to one example, the first device chip 51 and the second device chip 52 have bandpass filter functions. For example, the first device chip 51 has the function of either a transmit filter or a receive filter. The second device chip 52 has the function of the other of a transmit filter and a receive filter.

[0091] The first device chip 51 and the second device chip 52 may have almost the same structure as the device chip 3 in the first embodiment. The first device chip 51 may, for example, include the same elastic wave element 30 as in the first embodiment. Specifically, the first device chip 51 is provided with a bandpass filter composed of multiple elastic surface wave resonators. The second device chip 52 may, for example, include the same elastic wave element 30 as in the first embodiment. Specifically, the second device chip 52 is provided with a bandpass filter composed of multiple elastic surface wave resonators.

[0092] According to other examples, the second device chip 52 includes an elastic wave element different from that in the first embodiment. Specifically, the second device chip 52 is provided with a bandpass filter composed of a plurality of acoustic thin-film resonators.

[0093] Figure 22 This is a schematic diagram of the elastic wave element of the second device chip 52 being a thin-film acoustic resonator. Figure 22 In this embodiment, the second device chip 52 includes a chip substrate 60. The chip substrate 60 is, for example, a semiconductor substrate such as silicon, or an insulating substrate such as sapphire, alumina, spinel, or glass. A piezoelectric film 62 is disposed on the chip substrate 60. The piezoelectric film 62 is made of aluminum nitride. A lower electrode 64 and an upper electrode 66 are designed to enclose the piezoelectric film 62. The lower electrode 64 and the upper electrode 66 are formed, for example, of a metal such as ruthenium. A gap 68 is the space located between the lower electrode 64 and the chip substrate 60. In this acoustic thin-film resonator, the lower electrode 64 and the upper electrode 66 can excite elastic waves in a thickness-longitudinal vibration mode within the piezoelectric film 62. In this case, the second device chip 52 has multiple resonators, which function as an acoustic thin-film resonator. The second device chip 52 may also function as a bandpass filter or a bidirectional circuit.

[0094] According to the third embodiment described above, a bandpass filter composed of a plurality of the aforementioned surface wave resonators is formed in the second device chip 52. Furthermore, a bandpass filter composed of a plurality of the aforementioned thin-film acoustic resonators is formed in the second device chip 52. Both the first device chip 51 and the second device chip 52 employ the aforementioned wiring pattern.

[0095] (Example 4)

[0096] Figure 23This is a cross-sectional view of module 100 including the elastic wave device. Module 100 includes a wiring substrate 130, an integrated circuit element IC, an elastic wave device 101, an inductor 111, and a sealing portion 117. According to one example, the wiring substrate 130 may be the same as the wiring substrate 2 described in the first embodiment. The integrated circuit element IC is mounted inside the wiring substrate 130. The integrated circuit element IC includes switching circuitry and a low-noise amplifier.

[0097] The elastic wave device 101 is mounted on the main surface of the wiring substrate 130. The elastic wave device 101 can be any of the elastic wave devices described above. In other words, the wiring pattern of the elastic wave device 101 has a partition layer 16.

[0098] The inductor 111 is mounted on the main surface of the wiring substrate 130. The inductor 111 is mounted for impedance matching. For example, the inductor 111 is an integrated passive device (IPD). The sealing portion 117 seals multiple electronic components, including the elastic wave device 101.

[0099] While at least one embodiment has been described above, it should be understood that various changes, modifications, or improvements will readily occur to those skilled in the art. These changes, modifications, or improvements are also part of and fall within the scope of this disclosure.

[0100] It should be understood that the embodiments of the methods or apparatus described herein are not limited to the architecture and arrangement of the constituent elements described above or illustrated in the accompanying drawings. The methods and apparatus can be installed or performed in other embodiments.

[0101] The embodiments described are for illustrative purposes only and are not intended to be limiting.

[0102] Furthermore, the descriptions or terms used here are for illustrative purposes only and are not intended to be limiting. The use of "including," "possessing," "having," "comprise," and their variations here means to include the items listed below, their equivalents, and additional items.

[0103] The word “or”, or any word used in a description, may be interpreted as one, more than one, or all of the descriptive words.

[0104] The references to front, back, left, right, top, bottom, upper, lower, horizontal, vertical, and front and back are for ease of description and are not intended to limit the position and spatial arrangement of any constituent element in this invention. Therefore, the above description and drawings are merely exemplary.

Claims

1. An elastic wave device, comprising a wiring substrate, a resonator, a device chip having a wiring pattern electrically connected to the resonator and electrically connected to the wiring substrate, and a sealing portion sealing the device chip, characterized in that: The wiring pattern includes a first wiring layer and a second wiring layer. The second wiring layer has a lower metal layer connected to the upper surface of the first wiring layer, a spacer layer connected to the upper surface of the lower metal layer and being a metal layer, and an upper metal layer connected to the upper surface of the spacer layer. The spacer layer is a metal with a lower conductivity than both the lower and upper metal layers. The elastic wave device further includes a first insulating layer covering a portion of the upper surface of the first wiring layer. The lower metal layer has a portion connected to the upper surface of the first wiring layer and a portion connected to the upper surface of the first wiring layer through the first insulating layer. The elastic wave device further includes a second insulating layer covering the upper surface of the first insulating layer and the side surface of the second wiring layer.

2. The elastic wave device according to claim 1, characterized in that: The total thickness of the lower metal layer and the upper metal layer is 6 to 70 times the thickness of the first wiring layer.

3. The elastic wave device according to claim 1 or 2, characterized in that: The second wiring layer has a stepped portion, and the second insulating layer covers the stepped portion.

4. The elastic wave device according to claim 1 or 2, characterized in that: The first wiring layer is not directly connected to the second insulating layer.

5. The elastic wave device according to claim 1 or 2, characterized in that: The second wiring layer is directly connected to the first wiring layer, the first insulating layer, and the second insulating layer.

6. The elastic wave device according to claim 1 or 2, characterized in that: The first insulating layer is directly connected to the first wiring layer, the second wiring layer, and the second insulating layer.

7. The elastic wave device according to claim 1 or 2, characterized in that: The coefficient of thermal expansion of the first insulating layer is less than that of the second insulating layer.

8. The elastic wave device according to claim 1, characterized in that: The width of the second wiring layer is smaller than the width of the first wiring layer.

9. The elastic wave device according to claim 1, characterized in that: The device chip includes a piezoelectric substrate with the resonator and wiring pattern on its upper surface, and a substrate made of sapphire, silicon, alumina, spinel, crystal or glass and connected to the lower surface of the piezoelectric substrate.

10. The elastic wave device according to claim 1, characterized in that: The device chip includes multiple resonators, which are elastic surface wave resonators and have the functions of bandpass filters or bidirectional circuits.

11. The elastic wave device according to claim 1, characterized in that: The device chip includes multiple resonators, which are thin-film acoustic resonators and have the functions of bandpass filters or bidirectional circuits.

12. The elastic wave device according to claim 1, characterized in that: The first wiring layer is a structure of Ti, AlCu, Ti stacked from bottom to top, the lower metal layer is a structure of Ti and Al stacked from bottom to top, the separator is Ti, and the upper metal layer is Al.

13. The elastic wave device according to claim 1, characterized in that: The partition layer has an electrical conductivity of 10 × 10⁻⁶. 6 Metals with a conductivity of less than S / m, wherein the lower metal layer and the upper metal layer contain materials with a conductivity of 20 × 10⁻⁶. 6 Metals with a S / m ratio greater than 1.

14. A module comprising the elastic wave device according to any one of claims 1 to 13.

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