Latch and circuit and operating method thereof

Abstract

Embodiments of the present invention provide a latch and circuit and method of operation thereof. The latch circuit includes cross-coupled inverters including a first inverter and a second inverter. The first inverter and the second inverter are cross-coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled inverters and a power supply node. The input unit controls the cross-coupled inverters in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power supply node and a supply node. The first transistor connects the power supply node to the supply node in response to the enable signal changing to a first value. A second transistor is connected between the power supply node and ground. The second transistor connects the power supply node to ground in response to the enable signal changing to a second value.

Description

Technical Field

[0001] Embodiments of the present invention relate to latches, their circuits, and operating methods. Background Technology

[0002] A latch is a circuit with two stable states used to store information, i.e., a data storage element. A latch stores a single data bit. For example, one of the two states of a latch represents a bit value of one, and the other represents a bit value of zero. A latch can change its state by applying signals to one or more control inputs and can have one or two outputs. Latches are fundamental storage elements in sequential logic. For example, latches are basic building blocks of digital electronic systems used in computers, communications, and many other types of systems. Summary of the Invention

[0003] According to one aspect of the present invention, a latch circuit is provided, comprising: a cross-coupled inverter, including a first inverter and a second inverter, wherein the first inverter and the second inverter are cross-coupled at a first data node and a second data node; an input unit coupled between the cross-coupled inverter and a power supply node, wherein the input unit controls the cross-coupled inverter in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit; a first transistor connected between the power supply node and a power supply node, wherein the first transistor connects the power supply node to the power supply node in response to an enable signal changing to a first value; and a second transistor connected between the power supply node and ground, wherein the second transistor connects the power supply node to ground in response to an enable signal changing to a second value.

[0004] According to another aspect of the present invention, a latch is provided, comprising: a first transistor, wherein the source of the first transistor is connected to a first internal node, and the drain of the first transistor is connected to a first data node; a second transistor, wherein the source of the second transistor is connected to the first data node, the drain of the second transistor is connected to ground, and wherein the gate of the second transistor is connected to the gate of the first transistor at a second data node; a third transistor, wherein the source of the third transistor is connected to a second internal node, and the drain of the third transistor is connected to the second data node; a fourth transistor, wherein the source of the fourth transistor is connected to the second data node, the drain of the fourth transistor is connected to ground, and wherein the gate of the fourth transistor is connected to the gate of the third transistor at a first data node; and a fifth transistor, wherein the source of the fifth transistor is connected to the first internal node, and the drain of the fifth transistor is connected to the second data node; and a fifth transistor, wherein the source of the fifth transistor is connected to the first internal node, and the drain of the fifth transistor is connected to the first data node; and a sixth transistor, wherein the source of the fifth transistor is connected to the first internal node, and the drain of the fifth transistor is connected to the first internal node, and the drain of the fifth transistor is connected to the first data node; and a seventh ... A fifth transistor is connected to a power node, with its drain connected to a first internal node and its gate connected to a first input terminal; a sixth transistor has its source connected to a power node, its drain connected to a second internal node, and its gate connected to a second input terminal; a seventh transistor has its source connected to a power supply voltage node and its drain connected to a power node, wherein the power node is connected to the power supply voltage node when the seventh transistor is enabled; and an eighth transistor has its source connected to a power node and its drain connected to ground, wherein the power node is connected to ground when the eighth transistor is enabled, and wherein a latch is used to store a first bit value at a first data node and a second bit value at a second data node.

[0005] According to another aspect of the present invention, a method of operating a latch is provided, the method comprising: receiving a first input signal at a first input terminal of an input unit of the latch; receiving a second input signal at a second input terminal of the input unit; controlling a cross-coupled inverter of the latch in response to receiving the first input signal and the second input signal, wherein the cross-coupled inverter is connected to the input unit, and wherein the input unit is connected between a power supply node and the cross-coupled inverter; enabling a first transistor connected between a power supply node and a supply voltage node in response to receiving the first input signal and the second input signal, wherein when the first transistor is enabled, the first transistor connects the power supply node to the supply voltage node, wherein enabling the first transistor includes enabling the first transistor by changing an enable signal to a first value; storing a first bit value at a first data node of the latch, storing a second bit value at a second data node of the latch; and enabling a second transistor connected between a power supply node and ground, wherein enabling the second transistor includes enabling the second transistor by changing an enable signal to a second value. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a diagram illustrating an example latch according to some embodiments.

[0008] Figure 2 This is a circuit diagram of an example latch according to some embodiments.

[0009] Figure 3 This is a diagram illustrating an example latch with parasitic capacitors according to some embodiments.

[0010] Figure 4 This is a diagram illustrating an example latch with an initial transistor according to some embodiments.

[0011] Figure 5 This is a flowchart illustrating an example method for operating a latch according to some embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0014] Figure 1 This is a diagram illustrating an example latch 100 according to some embodiments. Figure 1As shown, latch 100 includes a first input terminal (also referred to as terminal Q) and a second input terminal (also referred to as terminal QB). Additionally, latch 100 includes a first output terminal (also referred to as terminal Z) and a second output terminal (also referred to as terminal ZB). In this example, terminal QB is complementary to terminal Q, and terminal ZB is complementary to terminal Z.

[0015] Two input terminals, Q and QB, are used to set and reset latch 100. Setting latch 100 is equivalent to storing a bit value of 1. When set, terminal Z goes high and terminal ZB goes low. Resetting has the opposite effect. When both inputs, Q and QB, are low, the current state of latch 100 is maintained. In some examples, latch 100 can be used as a sense amplifier. For example, latch 100 can receive a differential input signal at terminals Q and QB, amplify the received differential input signal, and provide an amplified output signal at terminals Z and ZB.

[0016] Figure 2 This is a circuit diagram of latch 100 according to some embodiments. For example, such as... Figure 2 As shown, latch 100 includes a cross-coupled inverter 202. The cross-coupled inverter 202 stores the first bit value at node Z and the second bit value at node ZB. Therefore, node Z can also be referred to as the first data node, and node ZB can also be referred to as the second data node. Terminal Z is connected to node ZB, and terminal ZB is connected to node ZB. In this example, node ZB is complementary to node Z.

[0017] like Figure 2 As shown, the cross-coupled inverter 202 includes a first inverter 202a and a second inverter 202b. The first inverter 202a is connected between node W (also referred to as the first internal node) and ground. The second inverter 202b is connected between node WB (also referred to as the second internal node) and ground. In the example, the first inverter 202a is cross-coupled with the second inverter 202b at nodes Z and ZB.

[0018] The first inverter 202a includes a first inverter first transistor 202a1 and a first inverter second transistor 202a2. The source of the first inverter first transistor 202a1 is connected to node W, and the drain of the first inverter first transistor 202a1 is connected to node Z. The source of the first inverter second transistor 202a2 is connected to node Z, and the drain of the first inverter second transistor 202a2 is floating or grounded (i.e., VSS). The gate of each of the first inverter first transistor 202a1 and the first inverter second transistor 202a2 is connected to node ZB, thereby cross-coupling the first inverter 202a1 and the second inverter 202a2.

[0019] In the example, the first inverter first transistor 202a1 is a p-channel metal-oxide-semiconductor (pMOS) transistor, and the first inverter second transistor 202a2 is an n-channel metal-oxide-semiconductor (nMOS) transistor. However, upon reading this disclosure, it will be apparent to those skilled in the art that other types of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), nMOS transistors, pMOS transistors, or complementary metal-oxide-semiconductor (CMOS) transistors, can be used for each of the first inverter first transistor 202a1 and the first inverter second transistor 202a2. Furthermore, the first inverter first transistor 202a1 and the first inverter second transistor 202a2 are symmetrical. That is, the source of each of the first inverter first transistor 202a1 and the first inverter second transistor 202a2 can be the drain, and the drain can be the source.

[0020] The second inverter 202b includes a second inverter first transistor 202b1 and a second inverter second transistor 202b2. The source of the second inverter first transistor 202b1 is connected to node WB, and the drain of the second inverter first transistor 202b1 is connected to node ZB. The source of the second inverter second transistor 202b2 is connected to node ZB, and the drain of the second inverter second transistor 202b2 is floating or connected to ground (i.e., VSS). The gates of the second inverter first transistor 202b1 and the second inverter second transistor 202b2 are each connected to node Z, thereby cross-coupled the second inverter 202a2 with the first inverter 202a1.

[0021] In the example, the second inverter first transistor 202b1 is a pMOS transistor, and the second inverter second transistor 202b2 is an nMOS transistor. However, it will be apparent to those skilled in the art, upon reading this disclosure, that other types of transistors, such as MOSFETs, nMOS transistors, pMOS transistors, or CMOS transistors, can be used for each of the second inverter first transistor 202b1 and the second inverter second transistor 202b2. Furthermore, the second inverter first transistor 202b1 and the second inverter second transistor 202b2 are symmetrical. That is, the source of each of the second inverter first transistor 202b1 and the second inverter second transistor 202b2 can be the drain, and the drain can be the source.

[0022] Continue to refer to Figure 2The latch 100 also includes a third transistor 204a and a fourth transistor 204b. In an example, the third transistor 204a and the fourth transistor 204b together form an input unit for controlling the cross-coupled inverter 202. For example, when enabled, the third transistor 204a connects the first inverter 202a of the cross-coupled inverter 202 to the supply voltage. Similarly, when enabled, the fourth transistor 204b connects the second inverter 202b of the cross-coupled inverter 202 to the supply voltage. In some examples, the third transistor 204a is enabled in response to receiving a first input signal at terminal Q, and the fourth transistor 204b is enabled in response to receiving a second input signal at terminal QB. For example, the third transistor 204a is enabled in response to sensing a bit line current at a selected bit line of the memory device at terminal Q, and the fourth transistor 204b is enabled in response to sensing a complementary bit line current at a selected complementary bit line of the memory device at terminal QB.

[0023] like Figure 2 As shown, the source of the third transistor 204a is connected to node 210 (also known as the power node), and the drain of the third transistor 204a is connected to node W. The gate of the third transistor 204a is connected to terminal Q. Additionally, the source of the fourth transistor 204b is connected to node 210 (i.e., the power node), and the drain of the fourth transistor 204b is connected to node WB. The gate of the fourth transistor 204b is connected to terminal QB. Terminals Q and QB are also referred to as differential input terminals.

[0024] In the example, each of the third transistor 204a and the fourth transistor 204b is a pMOS transistor. However, it will be apparent to those skilled in the art, upon reading this disclosure, that other types of transistors, such as MOSFETs, nMOS transistors, or CMOS transistors, can be used for each of the third transistor 204a and the fourth transistor 204b. Furthermore, each of the third transistor 204a and the fourth transistor 204b is symmetrical. That is, the source of each of the third transistor 204a and the fourth transistor 204b can be the drain, and the drain can be the source.

[0025] Continue to refer to Figure 2 The latch 100 also includes a fifth transistor 206. The fifth transistor 206 is connected between the supply voltage node and the power supply node (i.e., node 210). The source of the fifth transistor 206 is connected to the supply voltage node at a predetermined voltage or at the supply voltage (i.e., VDD). The drain of the fifth transistor 206 is connected to node 210 (i.e., the power supply node). The gate of the fifth transistor 206 is connected to terminal ENB. Terminal ENB is used to receive an enable signal.

[0026] When enabled, the fifth transistor 206 connects the supply voltage node to the power supply node. Therefore, in some examples, the fifth transistor 206 is also referred to as a pull-up transistor because, when enabled, it connects node 210 (i.e., the power supply node) to the supply voltage (i.e., VDD). In this example, the fifth transistor 206 is enabled by an enable signal. For example, when the enable signal changes to a first logic value (e.g., logic low) that connects the power supply node to the supply voltage, the fifth transistor 206 is turned on. When the enable signal changes to a second logic value (e.g., logic high) that disconnects the power supply node from the supply voltage node, the fifth transistor 206 is turned off.

[0027] In the example, the fifth transistor 206 is a pMOS transistor. However, it will be apparent to those skilled in the art, upon reading this disclosure, that other types of transistors, such as MOSFETs, nMOS transistors, or CMOS transistors, can be used for the fifth transistor 206. The fifth transistor 206 is symmetrical. That is, the source of the fifth transistor 206 can be the drain, and the drain can be the source.

[0028] Continue to refer to Figure 2 The latch 100 also includes a sixth transistor 208. The sixth transistor 208 is connected between a power node (i.e., node 210) and ground. For example, the source of the sixth transistor 208 is connected to node 210, and the drain of the sixth transistor 208 is connected to ground (i.e., VSS). The gate of the sixth transistor 208 is connected to the terminal ENB.

[0029] When enabled, the sixth transistor 208 is used to ground the power node (i.e., node 210). Therefore, in some examples, the sixth transistor 208 is also referred to as a pull-down transistor when the enabled sixth transistor 208 grounds node 210 (i.e., the power node). In the example, the fifth transistor 206 is also enabled by an enable signal. For example, when the enable signal changes to a second logic value (e.g., logic high) that grounds the power node, the sixth transistor 208 is turned on. When the enable signal changes to a first logic value (e.g., logic low) that disconnects the power node from ground, the sixth transistor 208 is turned off. Therefore, according to the example embodiment, when the fifth transistor 206 is on, the sixth transistor 208 is turned off, and when the fifth transistor 206 is off, the sixth transistor 208 is turned on.

[0030] Terminal ENB is used to receive an enable signal. In this example, the sixth transistor 208 is an nMOS transistor. However, it will be apparent to those skilled in the art, upon reading this disclosure, that the sixth transistor 208 may comprise other types of transistors, such as MOSFETs, pMOS transistors, or CMOS transistors. Furthermore, the sixth transistor 208 is symmetrical. That is, the source of the sixth transistor 208 can be the drain, and the drain can be the source.

[0031] Figure 3 This is a diagram showing the parasitic capacitors of latch 100. For example, as... Figure 3 As shown, latch 100 includes a first parasitic capacitance C 302a and a second parasitic capacitance C 302b. The first parasitic capacitance C 302a is formed between terminal Q and the power supply node (i.e., node 210). The second parasitic capacitance C 302b is formed between the power supply node (i.e., node 210) and terminal QB.

[0032] In the example embodiment, the first parasitic capacitance C 302a and the second parasitic capacitance C 302b do not form a coupling path between the first input terminal and the second input terminal (i.e., between terminal Q and terminal QB). For example, when the enable signal is logic low, the fifth transistor 206 is turned on, interrupting the formation of the coupling path between the first parasitic capacitance C 302a and the second parasitic capacitance C 302b. Similarly, when the enable signal is logic high, the sixth transistor 208 is turned on, interrupting the formation of the coupling path between the first parasitic capacitance C 302a and the second parasitic capacitance C 302b. Therefore, according to the example embodiment, latch 100 or components of latch 100 can be shared with another latch without coupling the input signal through the parasitic capacitor associated with latch 100.

[0033] Figure 4 This is a diagram showing the enable transistor of latch 100. For example, as shown... Figure 4 As shown, latch 100 includes a first enable transistor 402 and a second enable transistor 404. The first enable transistor 402 and the second enable transistor 404 are used to enable or operate the cross-coupled inverter 202. For example, the source of the first enable transistor 402 is connected to node Z of the cross-coupled inverter 202, while the drain of the first enable transistor 402 is grounded. The gate of the first enable transistor 402 is connected to terminal ENB. When the enable signal is logic high, the first enable transistor 402 is enabled. When enabled, the first enable transistor 402 connects node Z of the cross-coupled inverter 202 to ground (i.e., sets node Z to the logic value "0").

[0034] Similarly, the source of the second enable transistor 404 is connected to node ZB of the cross-coupled inverter 202, and the drain of the second enable transistor 404 is connected to ground (i.e., VSS). The gate of the second enable transistor 404 is connected to terminal ENB. The second enable transistor 404 is enabled when the enable signal is logic high. When enabled, the second enable transistor 404 connects node ZB of the cross-coupled inverter 202 to ground (i.e., sets node ZB to the logic value "0"). In this example, each of the first enable transistor 402 and the second enable transistor 404 is enabled during the evaluation phase of latch 100, and when enabled, each of nodes Z and ZB of the cross-coupled inverter 202 is set to logic low (i.e., logic value "0").

[0035] In the example, each of the first enabling transistor 402 and the second enabling transistor 404 is an nMOS transistor. However, upon reading this disclosure, it will be apparent to those skilled in the art that each of the first enabling transistor 402 and the second enabling transistor 404 may include other types of transistors, such as MOSFETs, pMOS transistors, or CMOS transistors. Furthermore, each of the first enabling transistor 402 and the second enabling transistor 404 is symmetrical. That is, the source of each of the first enabling transistor 402 and the second enabling transistor 404 can be the drain, and the drain can be the source.

[0036] Continue to refer to Figure 4 The latch 100 also includes a third enable transistor 406 and a fourth enable transistor 408. The source of the third enable transistor 406 is connected to node W, and the drain of the third enable transistor 406 is grounded (i.e., VSS). The gate of the third enable transistor 406 is connected to terminal ENB. The third enable transistor 406 is enabled when the enable signal is logic high. When enabled, the third enable transistor 406 connects node W to ground (i.e., sets node W to the logic value "0").

[0037] The source of the fourth enable transistor 408 is connected to node WB, and the drain of the fourth enable transistor 408 is grounded. The gate of the fourth enable transistor 408 is connected to terminal ENB. The fourth enable transistor 408 is enabled when the enable signal is logic high. When enabled, the fourth enable transistor 408 connects node WB to ground (i.e., sets node WB to the logic value "0"). In this example, each of the third enable transistor 406 and the fourth enable transistor 408 is enabled during the evaluation phase of latch 100, and when enabled, sets nodes W and WB to logic low (i.e., the logic value "0"). In this example embodiment, the evaluation phase determines the actual logic response of latch 100.

[0038] In the example, each of the third enable transistor 406 and the fourth enable transistor 408 is an nMOS transistor. However, upon reading this disclosure, it will be apparent to those skilled in the art that each of the third enable transistor 406 and the fourth enable transistor 408 may comprise other types of transistors, such as MOSFETs, pMOS transistors, or CMOS transistors. Furthermore, each of the third enable transistor 406 and the fourth enable transistor 408 is symmetrical. That is, the source of each of the third enable transistor 406 and the fourth enable transistor 408 can be the drain, and the drain can be the source.

[0039] In the example embodiment, after the evaluation phase, the enable signal changes from logic high to logic low (i.e., from logic value "1" to logic value "0"). This is also called the latching phase. When the enable signal goes low, each of the first enable transistor 402, the second enable transistor 404, the third enable transistor 406, and the fourth enable transistor 408 is turned off, thereby disconnecting nodes Z, ZB, W, and WB from ground, respectively. Additionally, during the latching phase, i.e., when the enable signal is low, the fifth transistor 206 is turned on, connecting node 210 to the supply voltage (i.e., VDD), and the sixth transistor 208 is turned off to disconnect node 210 from ground. This turns on both the third transistor 204a and the fourth transistor 204b, which causes nodes Z and ZB to be set.

[0040] Figure 5 This is a flowchart illustrating a method 500 for operating a latch according to some embodiments. For example, method 500 may be implemented as an operation reference. Figures 1-5 The latch 100 is described. Additionally, the steps of method 500 can be stored as instructions in a memory device or a computer-readable medium, which can be executed by a processor to implement method 500. The computer-readable medium can be a non-transitory computer-readable medium.

[0041] At block 510 of method 500, a first input signal is received at the first input terminal of the input unit. For example, in Figure 2 The latch 100 receives a first input signal, such as a bit line current, at terminal Q of the third transistor 204a. In block 520 of method 500, a second input signal is received at the second input terminal of the input unit. For example, in... Figure 2 The latch 100 receives a second input signal, such as a complementary bit line current, at terminal QB of the fourth transistor 204b.

[0042] At block 530 of method 500, the cross-coupled inverter is controlled in response to receiving a first input signal and a second input signal. For example, the control is performed in response to receiving the first input signal at terminal Q of the third transistor 204a of latch 100 and the second input signal at terminal Q of the third transistor 204a of latch 100. Figure 2 The latch 100 has a cross-coupled inverter 202. In response to receiving a first input signal and a second input signal at the input unit, the cross-coupled inverter 202 of the latch 100 is enabled, that is, connected to the power supply node (i.e., node 210 of the latch 100).

[0043] At block 540 of method 500, in response to receiving the first input signal and the second input signal, a first transistor connected between the power supply node and the supply node is enabled. When enabled, the first transistor (i.e., the pull-up transistor) connects the power supply node to the supply node. The first transistor is enabled by changing the enable signal to a first value. For example, when the enable signal goes low, the first transistor is enabled. Figure 2 The latch 100 has a fifth transistor 206. When enabled, the fifth transistor 206 connects the power node (i.e., node 210) to the supply voltage node.

[0044] At block 550 of method 500, the first bit is stored at the first node of the latch, and the second bit is stored at the second node of the latch. For example, bit 1 or bit 0 is stored at node Z of latch 100, while bit 0 or bit 1 is stored at node ZB of latch 100.

[0045] At block 560 of method 500, a second transistor connected between the power node and ground is enabled. When enabled, the second transistor (i.e., a pull-down transistor) grounds the power node. The second transistor is enabled in response to a change in the enable signal from a first value to a second value. For example, when the enable signal goes high, the second transistor is enabled. Figure 2 The latch 100 has a sixth transistor 208. When enabled, the sixth transistor 208 grounds the power node (i.e., node 210). In the example embodiment, the pull-up transistor is enabled when the pull-up transistor is disabled. That is, the sixth transistor 208 is enabled when the fifth transistor 206 is disabled. That is, one of the fifth transistor 206 and the sixth transistor 208 is enabled to prevent the coupling of the first parasitic capacitor C 302a and the second parasitic capacitor C 302b between terminals Q and QB.

[0046] According to an example embodiment, the circuit includes: a cross-coupled inverter, including a first inverter and a second inverter, wherein the first inverter and the second inverter are cross-coupled at a first data node and a second data node; an input unit coupled between the cross-coupled inverter and a power node, wherein the input unit controls the cross-coupled inverter in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit; a first transistor connected between the power node and a supply node, wherein the first transistor connects the power node to the supply node in response to an enable signal changing to a first value; and a second transistor connected between the power node and ground, wherein the second transistor connects the power node to ground in response to an enable signal changing to a second value.

[0047] In the circuit described above, the first inverter is connected between the first internal node and ground, and the second inverter is connected between the second internal node and ground.

[0048] In the circuit described above, the input unit includes a third transistor and a fourth transistor, wherein the source of the third transistor is connected to a power supply node and the drain of the third transistor is connected to a first internal node, and wherein the source of the fourth transistor is connected to a power supply node and the drain of the fourth transistor is connected to a second internal node.

[0049] In the circuit described above, the gate of the third transistor is connected to the first input terminal, and the gate of the fourth transistor is connected to the second input terminal.

[0050] In the circuit described above, when the third transistor is enabled, the third transistor connects the first internal node to the power supply node, and when the fourth transistor is enabled, the fourth transistor connects the second internal node to the power supply node.

[0051] In the circuit described above, the third transistor is enabled in response to the first input signal, and the fourth transistor is enabled in response to the second input signal.

[0052] In the circuit described above, the first inverter includes a fifth transistor and a sixth transistor, wherein the source of the fifth transistor is connected to a first internal node and the drain of the fifth transistor is connected to a first data node, wherein the source of the sixth transistor is connected to the first data node and the drain of the sixth transistor is connected to ground, and wherein the gate of the fifth transistor is connected to the gate of the sixth transistor, and the gate of the sixth transistor is connected to a second data node.

[0053] In the circuit described above, the second inverter includes a seventh transistor and an eighth transistor, wherein the source of the seventh transistor is connected to the second internal node and the drain of the seventh transistor is connected to the second data node, wherein the source of the eighth transistor is connected to the second data node and the drain of the eighth transistor is connected to ground, and wherein the gate of the seventh transistor is connected to the gate of the eighth transistor, which in turn is connected to the first data node.

[0054] The circuit described above also includes a first enable transistor and a second enable transistor, wherein the source of the first enable transistor is connected to the first data node, the drain of the first enable transistor is connected to ground, and the gate of the first enable transistor is connected to the enable terminal, and wherein the source of the second enable transistor is connected to the second data node, the drain of the second enable transistor is connected to ground, and the gate of the second enable transistor is connected to the enable terminal.

[0055] In the circuit described above, when the first enabling transistor and the second enabling transistor are enabled, the first enabling transistor and the second enabling transistor set the first data node and the second data node to bit values ​​of zero, respectively.

[0056] The circuit described above also includes a third enable transistor and a fourth enable transistor, wherein the source of the third enable transistor is connected to the first internal node, the drain of the third enable transistor is connected to ground, and the gate of the third enable transistor is connected to the enable terminal, and wherein the source of the fourth enable transistor is connected to the second internal node, the drain of the fourth enable transistor is connected to ground, and the gate of the fourth enable transistor is connected to the enable terminal.

[0057] In the circuit described above, when the third and fourth enable transistors are enabled, they set the first and second internal nodes to a bit value of zero, respectively.

[0058] In an example embodiment, the latch includes: a first transistor, wherein the source of the first transistor is connected to a first internal node, and the drain of the first transistor is connected to a first data node;

[0059] A second transistor, wherein the source of the second transistor is connected to the first data node, the drain of the second transistor is connected to ground, and the gate of the second transistor is connected to the gate of the first transistor at the second data node; a third transistor, wherein the source of the third transistor is connected to the second internal node, and the drain of the third transistor is connected to the second data node; a fourth transistor, wherein the source of the fourth transistor is connected to the second data node, the drain of the fourth transistor is connected to ground, and the gate of the fourth transistor is connected to the gate of the third transistor at the first data node; a fifth transistor, wherein the source of the fifth transistor is connected to the power node, the drain of the fifth transistor is connected to the first internal node, and the gate of the fifth transistor is connected to... The transistor is connected to a first input terminal; a sixth transistor, wherein the source of the sixth transistor is connected to a power supply node, the drain of the sixth transistor is connected to a second internal node, and the gate of the sixth transistor is connected to a second input terminal; a seventh transistor, wherein the source of the seventh transistor is connected to a power supply voltage node, and the drain of the seventh transistor is connected to a power supply node, wherein the power supply node is connected to the power supply voltage node when the seventh transistor is enabled; and an eighth transistor, wherein the source of the eighth transistor is connected to a power supply node, the drain of the eighth transistor is connected to ground, wherein the power supply node is connected to ground when the eighth transistor is enabled, and wherein the latch is used to store a first bit value at a first data node and a second bit value at a second data node.

[0060] In the latch described above, the fifth transistor and the sixth transistor form an input unit, wherein the input unit is used to receive differential input signals at the first input terminal and the second input terminal.

[0061] In the above latch, the first transistor, the second transistor, the third transistor, and the fourth transistor are enabled in response to receiving a differential input signal.

[0062] The latch described above also includes a first enable transistor and a second enable transistor, wherein the source of the first enable transistor is connected to the first data node, the drain of the first enable transistor is connected to ground, and the gate of the first enable transistor is connected to the enable terminal, and wherein the source of the second enable transistor is connected to the second data node, the drain of the second enable transistor is connected to ground, and the gate of the second enable transistor is connected to the enable terminal.

[0063] In the latch described above, when the first enable transistor and the second enable transistor are enabled, the first enable transistor and the second enable transistor set the first data node and the second data node to bit values ​​of zero, respectively.

[0064] According to an example embodiment, a method for operating a latch includes: receiving a first input signal at a first input terminal of an input unit of the latch; receiving a second input signal at a second input terminal of the input unit; controlling a cross-coupled inverter of the latch in response to receiving the first and second input signals, wherein the cross-coupled inverter is connected to the input unit, and wherein the input unit is connected between a power supply node and the cross-coupled inverter; enabling a first transistor connected between a power supply node and a supply voltage node in response to receiving the first and second input signals, wherein when the first transistor is enabled, the first transistor connects the power supply node to the supply voltage node, wherein enabling the first transistor includes enabling the first transistor by changing an enable signal to a first value; storing a first bit value at a first data node of the latch, storing a second bit value at a second data node of the latch; and enabling a second transistor connected between a power supply node and ground, wherein enabling the second transistor includes enabling the second transistor by changing an enable signal to a second value.

[0065] The above method further includes: changing the enable signal to a second value; setting the first internal node and the second internal node to zero values, wherein the input unit is connected to a cross-coupled inverter at the first internal node and the second internal node; and setting the first data node and the second data node to bit values ​​of zero.

[0066] The above method also includes: a latching start phase, wherein the latching start phase includes changing the enable signal to a first value.

[0067] This disclosure outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A latch circuit, comprising: A cross-coupled inverter includes a first inverter and a second inverter, wherein a first terminal of the first inverter is connected to a first internal node and a second terminal of the first inverter is directly connected to ground, a first terminal of the second inverter is connected to a second internal node and a second terminal of the second inverter is directly connected to the ground, and the first inverter and the second inverter are cross-coupled at a first data node and a second data node. An input unit is coupled between the first internal node and the second internal node and the power supply node, wherein the input unit controls the cross-coupled inverter in response to a first input signal received at the first input terminal of the input unit and a second input signal received at the second input terminal of the input unit; A first transistor is connected between the power node and the supply node, wherein the first transistor connects the power node to the supply node in response to an enable signal changing to a first value during a latching phase, wherein the enable signal changes to the first value during the latching phase; and A second transistor is connected between the power node and the ground, wherein the second transistor connects the power node to the ground and disconnects the power node from the power supply node in response to the enable signal changing to a second value during the evaluation phase.

2. The latch circuit according to claim 1, wherein, The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

3. The latch circuit according to claim 1, wherein, The input unit includes a third transistor and a fourth transistor, wherein the source of the third transistor is connected to the power node and the drain of the third transistor is connected to the first internal node, and wherein the source of the fourth transistor is connected to the power node and the drain of the fourth transistor is connected to the second internal node.

4. The latch circuit according to claim 3, wherein, The gate of the third transistor is connected to the first input terminal, and the gate of the fourth transistor is connected to the second input terminal.

5. The latch circuit according to claim 4, wherein, When the third transistor is enabled, the third transistor connects the first internal node to the power node, and wherein, when the fourth transistor is enabled, the fourth transistor connects the second internal node to the power node.

6. The latch circuit according to claim 5, wherein, The third transistor is enabled in response to the first input signal, and the fourth transistor is enabled in response to the second input signal.

7. The latch circuit according to claim 1, wherein, The first inverter includes a fifth transistor and a sixth transistor, wherein the source of the fifth transistor is connected to the first internal node and the drain of the fifth transistor is connected to the first data node, wherein the source of the sixth transistor is connected to the first data node and the drain of the sixth transistor is connected to ground, and wherein the gate of the fifth transistor is connected to the gate of the sixth transistor, and the gate of the sixth transistor is connected to the second data node.

8. The latch circuit according to claim 1, wherein, The second inverter includes a seventh transistor and an eighth transistor, wherein the source of the seventh transistor is connected to the second internal node and the drain of the seventh transistor is connected to the second data node, wherein the source of the eighth transistor is connected to the second data node and the drain of the eighth transistor is connected to ground, and wherein the gate of the seventh transistor is connected to the gate of the eighth transistor, and the gate of the eighth transistor is connected to the first data node.

9. The latch circuit according to claim 1 further includes a first enable transistor and a second enable transistor, wherein, The source of the first enable transistor is connected to the first data node, the drain of the first enable transistor is connected to ground, and the gate of the first enable transistor is connected to the enable terminal. The source of the second enable transistor is connected to the second data node, the drain of the second enable transistor is connected to ground, and the gate of the second enable transistor is connected to the enable terminal.

10. The latch circuit according to claim 9, wherein, When the first enable transistor and the second enable transistor are enabled, the first enable transistor and the second enable transistor set the first data node and the second data node to bit values ​​of zero, respectively.

11. The latch circuit according to claim 9, further comprising a third enable transistor and a fourth enable transistor, wherein, The source of the third enabling transistor is connected to the first internal node, the drain of the third enabling transistor is connected to ground, and the gate of the third enabling transistor is connected to the enabling terminal. The source of the fourth enabling transistor is connected to the second internal node, the drain of the fourth enabling transistor is connected to ground, and the gate of the fourth enabling transistor is connected to the enabling terminal.

12. The latch circuit according to claim 11, wherein, When the third and fourth enable transistors are enabled, they set the first internal node and the second internal node to a bit value of zero, respectively.

13. A latch, comprising: A first transistor, wherein the source of the first transistor is connected to a first internal node, and the drain of the first transistor is connected to a first data node; The second transistor has its source connected to the first data node, its drain directly connected to ground, and its gate connected to the gate of the first transistor at the second data node. A third transistor, wherein the source of the third transistor is connected to a second internal node, and the drain of the third transistor is connected to a second data node; A fourth transistor, wherein the source of the fourth transistor is connected to the second data node, the drain of the fourth transistor is directly connected to the ground, and wherein the gate of the fourth transistor is connected to the gate of the third transistor at the first data node; A fifth transistor, wherein the source of the fifth transistor is connected to a power supply node, the drain of the fifth transistor is connected to the first internal node, and the gate of the fifth transistor is connected to a first input terminal; A sixth transistor, wherein the source of the sixth transistor is connected to the power supply node, the drain of the sixth transistor is connected to the second internal node, and the gate of the sixth transistor is connected to the second input terminal; A seventh transistor, wherein the source of the seventh transistor is connected to a supply voltage node, and the drain of the seventh transistor is connected to the power supply node, wherein the power supply node is connected to the supply voltage node when the seventh transistor is enabled during the latching phase; and An eighth transistor, wherein the source of the eighth transistor is connected to the power node, the drain of the eighth transistor is connected to the ground, wherein the power node is connected to the ground when the eighth transistor is enabled during the evaluation phase, and wherein the latch is used to store a first bit value at the first data node and a second bit value at the second data node.

14. The latch according to claim 13, wherein, The fifth transistor and the sixth transistor form an input unit, wherein the input unit is used to receive differential input signals at the first input terminal and the second input terminal.

15. The latch according to claim 14, wherein, In response to receiving the differential input signal, the first transistor, the second transistor, the third transistor, and the fourth transistor are enabled.

16. The latch of claim 13, further comprising a first enable transistor and a second enable transistor, wherein, The source of the first enabling transistor is connected to the first data node, the drain of the first enabling transistor is connected to ground, and the gate of the first enabling transistor is connected to the enable terminal. The source of the second enabling transistor is connected to the second data node, the drain of the second enabling transistor is connected to ground, and the gate of the second enabling transistor is connected to the enable terminal.

17. The latch according to claim 16, wherein, When the first enable transistor and the second enable transistor are enabled, the first enable transistor and the second enable transistor set the first data node and the second data node to bit values ​​of zero, respectively.

18. A method of operating a latch, the method comprising: The first input signal is received at the first input terminal of the input unit of the latch; The second input signal is received at the second input terminal of the input unit; A cross-coupled inverter for controlling the latch in response to receiving the first input signal and the second input signal, wherein a first terminal of the first inverter is connected to a first internal node, a second terminal of the first inverter is directly connected to ground, a first terminal of the second inverter is connected to a second internal node, and a second terminal of the second inverter is directly connected to the ground, the cross-coupled inverter is connected to the input unit, and wherein the input unit is connected between the power supply node and the first internal node and the second internal node; In response to receiving the first input signal and the second input signal, a first transistor connected between the power node and the supply voltage node is enabled, wherein when the first transistor is enabled during the latching phase, the first transistor connects the power node to the supply voltage node, wherein enabling the first transistor includes enabling the first transistor during the latching phase by changing the enable signal to a first value. The first bit value is stored at the first data node of the latch, and the second bit value is stored at the second data node of the latch; and During the evaluation phase, enabling a second transistor connected between the power node and the ground to connect the power node to the ground, wherein enabling the second transistor includes enabling the second transistor by changing the enable signal to a second value.

19. The method of claim 18, further comprising: Change the enable signal to the second value; Set the first internal node and the second internal node to a bit value of zero, wherein the input unit is connected to the cross-coupled inverter at the first internal node and the second internal node; as well as Set the first data node and the second data node to the bit value zero.

20. The method of claim 18, further comprising: Initiating the latching phase includes changing the enable signal to the first value.

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