Clock generation circuit and voltage generation circuit including clock generation circuit

Abstract

This application relates to clock generation circuits and voltage generation circuits including clock generation circuits. One clock generation circuit includes a control clock generation circuit, a first clock synchronization circuit, and a second clock synchronization circuit. The control clock generation circuit compares a reference voltage with each of a first feedback clock signal and a second feedback clock signal to generate a first control clock signal and a second control clock signal. The first clock synchronization circuit causes the first and second feedback clock signals to switch synchronously with the first and second control clock signals. The second clock synchronization circuit generates a first phase clock signal and a second phase clock signal synchronously with each switching point of the first and second feedback clock signals.

Description

Technical Field

[0001] Various implementations generally relate to clock generation circuits and voltage generation circuits including clock generation circuits, and more specifically, to clock generation circuits configured to generate multi-phase clock signals with different phases and voltage generation circuits including the clock generation circuits. Background Technology

[0002] Typically, integrated circuits, such as semiconductor devices and semiconductor memory devices, perform predetermined operations based on clock signals. Therefore, integrated circuits are equipped with clock generation circuits configured to generate clock signals. Depending on the clock signal used, the clock generation circuits generate various types of clock signals. Multi-phase clock signals are an example of various types of clock signals. A multi-phase clock signal refers to a clock signal with multiple phases that are different from each other.

[0003] Clock generation circuits configured to generate multi-phase clock signals are typically implemented using a ring oscillator comprising multiple inverters. These inverters generate the multi-phase clock signal by inverting and delaying the signal. However, variations in PVT (process, voltage, temperature) significantly affect the multiple inverters, which have a chained structure. Therefore, the expected duty cycle and transition timing of the multi-phase clock signal, reflecting variations in PVT, cannot be guaranteed. Summary of the Invention

[0004] According to embodiments of this disclosure, a clock generation circuit may include a control clock generation circuit, a first clock synchronization circuit, and a second clock synchronization circuit. The control clock generation circuit compares a reference voltage with each of a first feedback clock signal and a second feedback clock signal to generate a first control clock signal and a second control clock signal. The first clock synchronization circuit synchronizes the first and second feedback clock signals with the first and second control clock signals. The second clock synchronization circuit synchronizes the generation of a first phase clock signal and a second phase clock signal with each transition point of the first and second feedback clock signals.

[0005] According to embodiments of this disclosure, a voltage generation circuit may include a clock generation circuit and a pumping circuit. The clock generation circuit may include a control clock generation circuit, a first clock synchronization circuit, and a second clock synchronization circuit. The control clock generation circuit may compare a reference voltage with each of a first feedback clock signal and a second feedback clock signal to generate a first control clock signal and a second control clock signal. The first clock synchronization circuit may synchronize the first feedback clock signal and the second feedback clock signal with the first control clock signal and the second control clock signal. The second clock synchronization circuit may synchronize the generation of a first phase clock signal and a second phase clock signal with the timing of each transition between the first feedback clock signal and the second feedback clock signal. The pumping circuit may generate a pumping voltage based on the first phase clock signal and the second phase clock signal through a pumping operation.

[0006] According to embodiments of this disclosure, the clock generation circuit may include an initialization control circuit, a first clock generation circuit, and a second clock generation circuit. The initialization control circuit may generate a first initialization signal and a second initialization signal that switch at different time points based on a control pulse signal. The first clock generation circuit may generate a first-phase clock signal and a second-phase clock signal with different phases based on the first initialization signal through synchronous operation. The second clock generation circuit may generate a third-phase clock signal and a fourth-phase clock signal with different phases based on the second initialization signal through synchronous operation. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the construction of a clock generation circuit according to an embodiment of the present disclosure.

[0008] Figure 2 This is an example Figure 1 The diagram shows the construction of the control clock generation circuit.

[0009] Figure 3 This is an example Figure 2 The circuit diagram shown illustrates the circuit construction of the first input circuit.

[0010] Figure 4 This is an example Figure 2 The circuit diagram shown illustrates the circuit construction of the first comparator circuit.

[0011] Figure 5 This is an example Figure 1 The circuit diagram shown illustrates the circuit construction of the first clock synchronization circuit.

[0012] Figure 6 This is an example Figure 1 The circuit diagram shown illustrates the circuit construction of the second clock synchronization circuit.

[0013] Figure 7 This is an example Figure 1 The waveform diagram shows the oscillation operation of the clock generation circuit.

[0014] Figure 8 This is a block diagram illustrating the construction of a voltage generation circuit according to an embodiment of the present disclosure.

[0015] Figure 9 This is an example Figure 8 The circuit diagram shown illustrates the circuit construction of the pumping circuit.

[0016] Figure 10 This is a block diagram illustrating the construction of a clock generation circuit according to an embodiment of the present disclosure.

[0017] Figure 11 This is an example Figure 10 The waveform diagram shows the oscillation operation of the clock generation circuit. Detailed Implementation

[0018] The description in this disclosure is merely for describing the structural and / or functional embodiments. The scope of this disclosure should not be construed as limited to the embodiments described in the specification. That is, because embodiments can be modified in various ways and can take various forms, the scope of this disclosure should be understood to include equivalent forms that can achieve the technical spirit. Furthermore, the purposes or effects set forth in this disclosure do not imply that a particular embodiment should include all purposes or effects or only such effects. Therefore, the scope of this disclosure should not be construed as being limited thereto.

[0019] The meanings of the terms described in this application should be understood as follows.

[0020] Terms such as “first” and “second” are used to distinguish one element from another, and the scope of this disclosure should not be limited by these terms. For example, a first element may be named a second element. Similarly, a second element may be named a first element.

[0021] Unless otherwise expressly stated in the context, singular expressions should be understood to include plural expressions. Terms such as “including” or “having” should be understood to indicate the presence of a defined characteristic, quantity, step, operation, element, component, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other characteristics, quantities, steps, operations, elements, components, or combinations thereof.

[0022] In each step, symbols (e.g., a, b, and c) are used for ease of description, and these symbols do not describe the order of the steps. Unless a specific order is clearly described in the context, steps may be performed in an order different from the order described in the context. That is, steps may be performed according to the described order, steps may be performed substantially simultaneously with the described order, or steps may be performed in the reverse order of the described order.

[0023] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. Unless expressly defined in this application, terms defined in common dictionaries shall be interpreted as having the same meaning as in the context of the relevant art and shall not be interpreted as having an ideal or excessive form of meaning.

[0024] According to embodiments of this disclosure, the clock generation circuit can generate a multi-phase clock signal through a synchronous structure of multiple inverting gates instead of their chained structure.

[0025] According to embodiments of this disclosure, the voltage generation circuit can generate voltage by utilizing a multi-phase clock signal generated from the clock generation circuit.

[0026] Figure 1 This is a block diagram illustrating the construction of a clock generation circuit 100 according to an embodiment.

[0027] Reference Figure 1 The clock generation circuit 100 may include a control clock generation circuit 110, a first clock synchronization circuit 120, and a second clock synchronization circuit 130.

[0028] The control clock generation circuit 110 compares the reference voltage V_REF with each of the first feedback clock signal FD_CLK1 and the second feedback clock signal FD_CLK2 to generate the first control clock signal CTR_C1 and the second control clock signal CTR_C2. The first feedback clock signal FD_CLK1 and the second feedback clock signal FD_CLK2 can be output from the first clock synchronization circuit 120, which will be described later. The second clock synchronization circuit 130 can synchronously generate the first phase clock signal M_CLK1 and the second phase clock signal M_CLK2 with the transition time points of each of the first feedback clock signal FD_CLK1 and the second feedback clock signal FD_CLK2.

[0029] Figure 2 This is an example Figure 1 The block diagram shown illustrates the construction of the control clock generation circuit 110.

[0030] Reference Figure 2The control clock generation circuit 110 may include a first control clock generation circuit 210 and a second control clock generation circuit 220.

[0031] The first control clock generation circuit 210 can compare the voltage level of the first feedback clock signal FD_CLK1 with the voltage level of the reference voltage V_REF to generate the first control clock signal CTR_C1. The first control clock generation circuit 210 may include a first input circuit 211 and a first comparison circuit 212.

[0032] The first input circuit 211 can receive, buffer, and output the first feedback clock signal FD_CLK1. The first comparator circuit 212 can compare the voltage level of the reference voltage V_REF with the voltage level of the output signal BF_CLK1 of the first input circuit 211 to output the first control clock signal CTR_C1. It can receive the output signal BF_CLK1 of the first input circuit 211 through its negative (-) node, and can receive the reference voltage V_REF through its positive (+) node.

[0033] The second control clock generation circuit 220 can compare the voltage level of the second feedback clock signal FD_CLK2 with the voltage level of the reference voltage V_REF to generate the second control clock signal CTR_C2. The second control clock generation circuit 220 may include a second input circuit 221 and a second comparison circuit 222.

[0034] The second input circuit 221 can receive, buffer, and output the second feedback clock signal FD_CLK2. The second comparator circuit 222 can compare the voltage level of the reference voltage V_REF with the voltage level of the output signal BF_CLK2 of the second input circuit 221 to output the second control clock signal CTR_C2. It can receive the output signal BF_CLK2 of the second input circuit 221 through its negative (-) node, and can receive the reference voltage V_REF through its positive (+) node.

[0035] The first input circuit 211 and the second input circuit 221 may have similar circuit configurations. In the following text, for ease of description, the circuit configuration of the first input circuit 211 will be described in detail as representative.

[0036] Figure 3 This is an example Figure 2 The circuit diagram shown illustrates the circuit configuration of the first input circuit 211.

[0037] Reference Figure 3 The first input circuit 211 may include a first PMOS transistor PM1 and a first NMOS transistor NM1.

[0038] The first PMOS transistor PM1 and the first NMOS transistor NM1 can be connected in series between the power supply voltage node VDD and the ground voltage node VSS. The gates of the first PMOS transistor PM1 and the first NMOS transistor NM1 can be connected to the input node, through which they can receive the first feedback clock signal FD_CLK1. The drains of the first PMOS transistor PM1 and the first NMOS transistor NM1 can be connected to the output node. The first buffered clock signal BF_CLK1, i.e., the output signal BF_CLK1 of the first input circuit 211, can be output through the output node.

[0039] With the above-described configuration, the first input circuit 211 can receive and buffer the first feedback clock signal FD_CLK1 so as to output the first feedback clock signal FD_CLK1 as the first buffered clock signal BF_CLK1.

[0040] Return to reference Figure 2 The second input circuit 221 can be connected with Figure 3 The first input circuit 211 shown has the same construction. However, the second input circuit 221 can receive the second feedback clock signal FD_CLK2 instead of the first feedback clock signal FD_CLK1. Therefore, the second input circuit 221 can receive and buffer the second feedback clock signal FD_CLK2 to output the second feedback clock signal FD_CLK2 as the second buffered clock signal BF_CLK2, that is, the output signal BF_CLK2 of the second input circuit 221.

[0041] The first comparator circuit 212 and the second comparator circuit 222 may have similar circuit configurations. In the following text, for ease of description, the circuit configuration of the first comparator circuit 212 will be described in detail in a representative manner.

[0042] Figure 4 This is an example Figure 2 The circuit diagram shown illustrates the circuit construction of the first comparator circuit 212.

[0043] Reference Figure 4 The first comparator circuit 212 may include second PMOS transistors to fourth PMOS transistors PM2, PM3 and PM4, and second NMOS transistors to fourth NMOS transistors NM2, NM3 and NM4.

[0044] The second PMOS transistor PM2 can be connected to the power supply voltage node VDD at its source and can receive an enable signal ENB at its gate. The enable signal ENB can be a signal used to control the activation operation of the first comparator circuit 212. The second NMOS transistor NM2 can be connected to the ground voltage node VSS at its source and can receive a bias voltage V_BAS at its gate. The bias voltage V_BAS can be a voltage applied to use the second NMOS transistor NM2 as a current source.

[0045] Between the second PMOS transistor PM2 and the second NMOS transistor NM2, the third PMOS transistor PM3 and the third NMOS transistor NM3 can be connected in series, and the fourth PMOS transistor PM4 and the fourth NMOS transistor NM4 can also be connected in series. The gates of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 can be connected to a common node, and the drain of the third NMOS transistor NM3 can be connected to this common node. The third NMOS transistor NM3 can receive a reference voltage V_REF at its gate. The fourth NMOS transistor NM4 can receive a first buffered clock signal BF_CLK1 at its gate. The fourth PMOS transistor PM4 and the fourth NMOS transistor NM4 can be connected to the output node. The first control clock signal CTR_C1 can be output through the output node.

[0046] With the above-described configuration, the first comparator circuit 212 can compare the voltage level of the reference voltage V_REF with the first buffer clock signal BF_CLK1 (i.e., Figure 2 The voltage level of the output signal BF_CLK1 of the first input circuit 211 shown is compared to output the first control clock signal CTR_C1.

[0047] Return to reference Figure 2 The second comparator circuit 222 can have the same characteristics as... Figure 4 The first comparator circuit 212 shown has the same construction. However, the second comparator circuit 222 can receive the second buffered clock signal BF_CLK2 instead of the first buffered clock signal BF_CLK1 to output the second control clock signal CTR_C2.

[0048] Return to reference Figure 1 The first clock synchronization circuit 120 can be configured to synchronously switch between the first feedback clock signal FD_CLK1 and the second feedback clock signal FD_CLK2 and the first control clock signal CTR_C1 and the second control clock signal CTR_C2. The first feedback clock signal FD_CLK1 generated by the first clock synchronization circuit 120 can be fed back... Figure 2The first input circuit 211 shown, and the second feedback clock signal FD_CLK2 generated by the first clock synchronization circuit 120 can be fed back. Figure 2 The second input circuit 221 is shown. As will be described in detail later, the first clock synchronization circuit 120 can perform an initialization operation based on the initialization signals INT and INTB.

[0049] Figure 5 This is an example Figure 1 The circuit diagram shown illustrates the circuit configuration of the first clock synchronization circuit 120.

[0050] Reference Figure 5 The first clock synchronization circuit 120 may include a latch circuit 510 and an initialization circuit 520.

[0051] The latch circuit 510 can perform a set operation based on the first control clock signal CTR_C1 and a reset operation based on the second control clock signal CTR_C2. For example, the latch circuit 510 can be implemented by an SR latch. The latch circuit 510 may include first inverter gates to fourth inverter gates INV1, INV2, INV3 and INV4, as well as a first NAND gate NAND1 and a second NAND gate NAND2.

[0052] In an implementation, the latch circuit 510 may be configured to have a substantially constant duty cycle, and the second clock synchronization circuit 130 may include a first flip-flop and a second flip-flop to generate a first phase clock signal M_CLK1 and a second phase clock signal M_CLK2, respectively, such that there is a substantially constant 90-degree delay phase difference between the first phase clock signal M_CLK1 and the second phase clock signal M_CLK2.

[0053] like Figure 5 As shown, the first inverter INV1 can receive and invert the first control clock signal CTR_C1, and output the inverted signal. The first NAND gate NAND1 can perform a NAND operation on the output signal of the first inverter INV1 and the output signal of the second NAND gate NAND2 (described later) to output the result of the NAND operation. The second inverter INV2 can receive and invert the output signal of the first NAND gate NAND1 to output the first feedback clock signal FD_CLK1. The third inverter INV3 can receive and invert the second control clock signal CTR_C2, and output the inverted signal. The second NAND gate NAND2 can perform a NAND operation on the output signal of the first NAND gate NAND1 and the output signal of the third inverter INV3 to output the result of the NAND operation. The fourth inverter INV4 can receive and invert the output signal of the second NAND gate NAND2 to output the second feedback clock signal FD_CLK2.

[0054] Through such a construction, as described above, Figure 5 As shown, the latch circuit 510 can generate a first feedback clock signal FD_CLK1 and a second feedback clock signal FD_CLK2. When the first control clock signal CTR_C1 is at a logic high level, a set operation can switch the first feedback clock signal FD_CLK1 to a logic low level, and the second feedback clock signal FD_CLK2 can switch to a logic high level. When the second control clock signal CTR_C2 is at a logic high level, a reset operation can switch the first feedback clock signal FD_CLK1 to a logic high level, and the second feedback clock signal FD_CLK2 to a logic low level.

[0055] like Figure 5 As shown, the initialization circuit 520 can initialize the latch circuit 510 based on the initialization signals INT and INTB, wherein the initialization signals INT and INTB can include a positive initialization signal INT and a negative initialization signal INTB. The positive initialization signal INT and the negative initialization signal INTB can have opposite phases. The initialization circuit 520 can include a fifth PMOS transistor PM5 and a fifth NMOS transistor NM5.

[0056] The fifth PMOS transistor PM5 can be connected between the power supply voltage node VDD and the input node of the first control clock signal CTR_C1 through its source and drain, and can receive the negative initialization signal INTB through its gate. The fifth NMOS transistor NM5 can be connected between the input node of the second control clock signal CTR_C2 and the ground voltage node VSS through its drain and source, and can receive the positive initialization signal INT through its gate.

[0057] With the above-described configuration, the initialization circuit 520 can perform an initialization operation when the negative initialization signal INTB is at a logic low level and the positive initialization signal INT is at a logic high level. During the initialization operation, the fifth PMOS transistor PM5 can be turned on and can hold the first control clock signal CTR_C1 at a logic high level, and the fifth NMOS transistor NM5 can be turned on and can hold the second control clock signal CTR_C2 at a logic low level. That is, the initialization circuit 520 can set the first control clock signal CTR_C1 and the second control clock signal CTR_C2 to predetermined logic levels through the initialization operation.

[0058] According to the implementation, the clock generation circuit 100 can generate a multi-phase clock signal through an oscillation operation after the initialization operation. That is, after the initialization operation, when the negative initialization signal INTB has a logic high level and the positive initialization signal INT has a logic low level, the clock generation circuit 100 can begin to perform an oscillation operation. At this time, the fifth PMOS transistor PM5 and the fifth NMOS transistor NM5 of the initialization circuit 520 can be turned off, so that through the oscillation operation based on the positive initialization signal INT and the negative initialization signal INTB, the clock generation circuit 100 can generate a first-phase clock signal M_CLK1 and a second-phase clock signal M_CLK2 as multi-phase clock signals.

[0059] Return to reference Figure 1 The second clock synchronization circuit 130 can synchronously generate a first phase clock signal M_CLK1 and a second phase clock signal M_CLK2 at each transition time point of the first feedback clock signal FD_CLK1 and the second feedback clock signal FD_CLK2. The first phase clock signal M_CLK1 and the second phase clock signal M_CLK2 can have a phase difference corresponding to a quantity of 90 degrees.

[0060] Figure 6 This is an example Figure 1 The circuit diagram shown illustrates the circuit construction of the second clock synchronization circuit 130.

[0061] Reference Figure 6 The second clock synchronization circuit 130 may include a first frequency divider circuit 610 and a second frequency divider circuit 620.

[0062] The first frequency divider circuit 610 can be configured to receive a first feedback clock signal FD_CLK1 and divide the first feedback clock signal FD_CLK1 to generate a first phase clock signal M_CLK1. The first frequency divider circuit 610 can be implemented by a T flip-flop. The first frequency divider circuit 610 may include a first AND gate AND1 and a second AND gate AND2, as well as a first NOR gate NOR1 and a second NOR gate NOR2.

[0063] like Figure 6As shown, the first AND gate AND1 can receive the first phase clock signal M_CLK1 and the first feedback clock signal FD_CLK1, and perform an AND operation on the first phase clock signal M_CLK1 and the first feedback clock signal FD_CLK1 to output the result of the AND operation. The second AND gate AND2 can receive the first feedback clock signal FD_CLK1 and the output signal of the second NOR gate NOR2, and perform an AND operation on the first feedback clock signal FD_CLK1 and the output signal of the second NOR gate NOR2 to output the result of the AND operation. The first NOR gate NOR1 can receive the output signal of the first AND gate AND1 and the output signal of the second NOR gate NOR2, and perform a NOR operation on the output signal of the first AND gate AND1 and the output signal of the second NOR gate NOR2 to output the result of the NOR operation. The second NOR gate NOR2 can receive the output signal of the first NOR gate NOR1 and the output signal of the second AND gate AND2, and perform a NOR operation on the output signal of the first NOR gate NOR1 and the output signal of the second AND gate AND2 to output the result of the NOR operation.

[0064] The second frequency divider circuit 620 can be configured to receive the second feedback clock signal FD_CLK2 and divide the second feedback clock signal FD_CLK2 to generate the second phase clock signal M_CLK2. The second frequency divider circuit 620 can be implemented by a toggle flip-flop (TFF). The second frequency divider circuit 620 may include a third AND gate AND3 and a fourth AND gate AND4, as well as a third NOR gate NOR3 and a fourth NOR gate NOR4.

[0065] The third AND gate (AND3) can receive the second phase clock signal M_CLK2 and the second feedback clock signal FD_CLK2, and perform an AND operation on the second phase clock signal M_CLK2 and the second feedback clock signal FD_CLK2 to output the result of the AND operation. The fourth AND gate (AND4) can receive the second feedback clock signal FD_CLK2 and the output signal of the fourth NOR gate (NOR4), and perform an AND operation on the second feedback clock signal FD_CLK2 and the output signal of the fourth NOR gate (NOR4) to output the result of the AND operation. The third NOR gate (NOR3) can receive the output signal of the third AND gate (AND3) and the output signal of the fourth NOR gate (NOR4), and perform a NOR operation on the output signals of the third AND gate (AND3) and the fourth NOR gate (NOR4) to output the result of the NOR operation. The fourth NOR gate (NOR4) can receive the output signal of the third NOR gate (NOR3) and the output signal of the fourth AND gate (AND4), and perform a NOR operation on the output signals of the third NOR gate (NOR3) and the fourth AND gate (AND4) to output the result of the NOR operation.

[0066] The first four AND gates, AND1, AND2, AND3, and AND4, can receive the output signal of the fifth inverter, INV5. The fifth inverter, INV5, inverts the enable signal ENB and outputs the inverted signal. The enable signal ENB can be a reference... Figure 4 The described enable signal. Therefore, in Figure 4 The first comparator circuit 212 shown performs a comparator operation based on the enable signal ENB, while Figure 6 The first frequency divider circuit 610 and the second frequency divider circuit 620 shown can perform frequency division operations based on the enable signal ENB.

[0067] With the above-described configuration, the second clock synchronization circuit 130 can generate the first phase clock signal M_CLK1 and the second phase clock signal M_CLK2 synchronously with each transition point in the first feedback clock signal FD_CLK1 and the second feedback clock signal FD_CLK2 through frequency division operation.

[0068] Figure 7 This is an example Figure 1 The waveform diagram shows the oscillation operation of the clock generation circuit 100. For ease of description, the oscillation operation after the initialization operation will be described. Figure 7 Examples are shown as follows Figure 5 The waveforms of the first control clock signal CTR_C1, the second control clock signal CTR_C2, the first input node S, the second input node R, the first output node Q, the second output node QB, the first feedback clock signal FD_CLK1, the second feedback clock signal FD_CLK2, the first phase clock signal M_CLK1, and the second phase clock signal M_CLK2 are shown.

[0069] Figure 1 The control clock generation circuit 110 shown can compare the first feedback clock signal FD_CLK1 with the reference voltage V_REF to generate a first control clock signal CTR_C1. The control clock generation circuit 110 can also compare the second feedback clock signal FD_CLK2 with the reference voltage V_REF to generate a second control clock signal CTR_C2. Each of the first control clock signal CTR_C1 and the second control clock signal CTR_C2 can be output as a pulse signal based on the comparison result, wherein the pulse width of the pulse signal can vary according to the capacitance value reflected in each of the first control clock signal CTR_C1 and the second control clock signal CTR_C2, or according to the voltage level of the reference voltage V_REF.

[0070] in addition, Figure 1The first clock synchronization circuit 120 shown can generate a first feedback clock signal FD_CLK1 and a second feedback clock signal FD_CLK2 that are synchronized with the first control clock signal CTR_C1 and the second control clock signal CTR_C2. (See reference...) Figure 5 As described, the first inverter INV1 inverts the first control clock signal CTR_C1 to output an inverted signal to the first input node S, and the third inverter INV3 inverts the second control clock signal CTR_C2 to output an inverted signal to the second input node R. Therefore, the first output node Q can have a logic high level when the first input node S is logic low, and a logic low level when the second input node R is logic low. The second output node QB can have a level opposite to that of the first output node Q. For example, the second inverter INV2 inverts the output signal of the first output node Q to generate a first feedback clock signal FD_CLK1. The fourth inverter INV4 inverts the output signal of the second output node QB to generate a second feedback clock signal FD_CLK2.

[0071] Figure 1 The second clock synchronization circuit 130 shown can synchronously generate the first phase clock signal M_CLK1 and the second phase clock signal M_CLK2 at each transition point in the first feedback clock signal FD_CLK1 and the second control clock signal CTR_C2. (See reference...) Figure 6 As described, the first frequency divider circuit 610 can divide the first feedback clock signal FD_CLK1 to generate a first phase clock signal M_CLK1, and the second frequency divider circuit 620 can divide the second feedback clock signal FD_CLK2 to generate a second phase clock signal M_CLK2. Therefore, from Figure 7 It can be seen that the first phase clock signal M_CLK1 and the second phase clock signal M_CLK2 can have a phase difference corresponding to a quantity of 90 degrees.

[0072] According to the implementation, the clock generation circuit 100 can generate a multi-phase clock signal including a first phase clock signal M_CLK1 and a second phase clock signal M_CLK2 by means of the synchronization structure of the first clock synchronization circuit 120 and the second clock synchronization circuit 130.

[0073] Figure 8 This is a block diagram illustrating the construction of a voltage generation circuit 800 according to an embodiment of the present disclosure.

[0074] Reference Figure 8 The voltage generation circuit 800 may include a clock generation circuit 810 and a pumping circuit 820.

[0075] The clock generation circuit 810 can be configured to generate a first-phase clock signal M_CLK1 and a second-phase clock signal M_CLK2 as a multi-phase clock signal based on the initialization signals INT and INTB through synchronous operation. The clock generation circuit 810 can correspond to a reference... Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figures 6 to 7 The clock generation circuit 100 is described. That is, from... Figure 8 The clock generation circuit 810 shown generates a first-phase clock signal M_CLK1 and a second-phase clock signal M_CLK2 that can have a phase difference corresponding to a quantity of 90 degrees.

[0076] The pumping circuit 820 can generate a pumping voltage VPP based on a first phase clock signal M_CLK1 and a second phase clock signal M_CLK2 through a pumping operation. The pumping circuit 820 can receive an input voltage V_IN and can generate a pumping voltage VPP with a higher voltage level than the input voltage V_IN through the pumping operation.

[0077] Figure 9 This is an example Figure 8 The circuit diagram shown illustrates the circuit configuration of the pumping circuit 820. The pumping circuit 820 may include multiple unit pumping circuits, each configured to perform a pumping operation based on a corresponding one of a first phase clock signal M_CLK1 and a second phase clock signal M_CLK2. In the following description, reference is made to... Figure 9 The circuit construction of a unit pumping circuit configured to perform pumping operations based on the first phase clock signal M_CLK1 is described in detail in a representative manner.

[0078] Reference Figure 9 The pumping circuit 820 may include a first capacitor C1, a second capacitor C2, first pumping NMOS transistors to fourth pumping NMOS transistors P_NM1, P_NM2, P_NM3 and P_NM4, and first pumping PMOS transistors to fourth pumping PMOS transistors P_PM1, P_PM2, P_PM3 and P_PM4.

[0079] The first capacitor C1 can receive the first positive phase clock signal M_CLK1, and the second capacitor C2 can receive the first negative phase clock signal / M_CLK1. The first positive phase clock signal M_CLK1 can be a clock signal corresponding to the first phase clock signal M_CLK1, and the first negative phase clock signal / M_CLK1 can be a clock signal that is inverted from the first phase clock signal M_CLK1.

[0080] The first capacitor C1 and the second capacitor C2 can be connected to multiple transistors, namely, the first pumped NMOS transistor to the fourth pumped NMOS transistors P_NM1, P_NM2, P_NM3 and P_NM4, and the first pumped PMOS transistor to the fourth pumped PMOS transistors P_PM1, P_PM2, P_PM3 and P_PM4. The first pumped NMOS transistor P_NM1, the second pumped NMOS transistor P_NM2, the first pumped PMOS transistor P_PM1 and the second pumped PMOS transistor P_PM2 can have a cross-connection structure. The third pumped NMOS transistor P_NM3, the fourth pumped NMOS transistor P_NM4, the third pumped PMOS transistor P_PM3 and the fourth pumped PMOS transistor P_PM4 can also have a cross-connection structure.

[0081] With the above configuration, the pumping circuit 820 can generate an output voltage V_OUT with a higher voltage level than the input voltage V_IN by pumping the input voltage V_IN based on the first positive phase clock signal M_CLK1 and the first negative phase clock signal M_CLK1. The output voltage V_OUT can be provided as an input voltage to the unit pumping circuit that performs the pumping operation based on the second phase clock signal M_CLK2. The unit pumping circuit can perform the pumping operation based on the second phase clock signal M_CLK2 and can generate a pumping voltage VPP with a higher voltage level than the input voltage through the pumping operation.

[0082] Figure 10 This is a block diagram illustrating the construction of a clock generation circuit 1000 according to an embodiment.

[0083] Reference Figure 10 The clock generation circuit 1000 can generate first-phase clock signals to fourth-phase clock signals M_CLK1, M_CLK2, M_CLK3, and M_CLK4 through synchronous operation. The first-phase clock signals to the fourth-phase clock signals M_CLK1, M_CLK2, M_CLK3, and M_CLK4 can have different phases from each other. For example, the first-phase clock signal M_CLK1 and the second-phase clock signal M_CLK2 can have a phase difference corresponding to 90 degrees, the second-phase clock signal M_CLK2 and the third-phase clock signal M_CLK3 can have a phase difference corresponding to 90 degrees, and the third-phase clock signal M_CLK3 and the fourth-phase clock signal M_CLK4 can have a phase difference corresponding to 90 degrees. The clock generation circuit 1000 may include an initialization control circuit 1010, a first clock generation circuit 1020, and a second clock generation circuit 1030.

[0084] The initialization control circuit 1010 can be configured to generate first initialization signals INT1 and INTB1 and second initialization signals INT2 and INTB2 that change at different time points based on the control pulse signal CTR.

[0085] The control pulse signal CTR can have information corresponding to half a period of the target phase clock signal. For example, the control pulse signal CTR can correspond to the first phase clock signal M_CLK1. The control pulse signal CTR can include a pulse corresponding to half a period of the first phase clock signal M_CLK1. Therefore, for example, the initialization control circuit 1010 can control the timing of the transition between the first initialization signals INT1 and INTB1 based on the rising edge of the pulse of the control pulse signal CTR, and can control the timing of the transition between the second initialization signals INT2 and INTB2 based on the falling edge of the pulse of the control pulse signal CTR. Each pair of the first initialization signals INT1 and INTB1 and the second initialization signals INT2 and INTB2 can correspond to Figure 1 The pair of initialization signals INT and INTB are shown.

[0086] The first clock generation circuit 1020 can generate a first-phase clock signal M_CLK1 and a second-phase clock signal M_CLK2 with different phases from each other through synchronous operation based on the first initialization signals INT1 and INTB1. The first clock generation circuit 1020 can correspond to reference. Figures 1 to 7 The clock generation circuit 100 is described. Therefore, the first clock generation circuit 1020 can generate a first phase clock signal M_CLK1 and a second phase clock signal M_CLK2 with a phase difference corresponding to a quantity of 90 degrees based on the first initialization signals INT1 and INTB1.

[0087] The second clock generation circuit 1030 can generate a third-phase clock signal M_CLK3 and a fourth-phase clock signal M_CLK4 with different phases from each other through synchronous operation based on the second initialization signals INT2 and INTB2. The second clock generation circuit 1030 can correspond to the reference. Figures 1 to 7 The clock generation circuit 100 is described. Therefore, the second clock generation circuit 1030 can generate a third phase clock signal M_CLK3 and a fourth phase clock signal M_CLK4 with a phase difference corresponding to a quantity of 90 degrees based on the second initialization signals INT2 and INTB2.

[0088] As described above, the control pulse signal CTR can have information corresponding to half a period of the first phase clock signal M_CLK1. Therefore, the transition times of the first initialization signals INT1 and INTB1, and the transition times of the second initialization signals INT2 and INTB2, can have a phase difference corresponding to half a period of the first phase clock signal M_CLK1. That is, the transition times of the first initialization signals INT1 and INTB1, and the transition times of the second initialization signals INT2 and INTB2, can have a phase difference of approximately 180 degrees relative to the first phase clock signal M_CLK1.

[0089] Figure 11 This is an example Figure 10 The waveform diagram of the oscillation operation of the clock generation circuit 1000 shown. Figure 11 Examples Figure 10 The waveforms of the control pulse signal CTR, the first initialization signals INT1 and INTB1, the second initialization signals INT2 and INTB2, and the first phase clock signal to the fourth phase clock signal M_CLK1, M_CLK2, M_CLK3 and M_CLK4 are shown.

[0090] Reference Figure 11 The control pulse signal CTR may include pulses that correspond to half a cycle of the first phase clock signal M_CLK1. Figure 10 The initialization control circuit 1010 shown can generate first initialization signals INT1 and INTB1 and second initialization signals INT2 and INTB2 that change at different time points based on the control pulse signal CTR.

[0091] Return to reference Figure 11 The first initialization signals INT1 and INTB1 can include a first positive initialization signal INT1 and a first negative initialization signal INTB1. Therefore, the first positive initialization signal INT1 and the first negative initialization signal INTB1 can be switched based on the rising edge of the control pulse signal CTR. That is, based on the rising edge of the control pulse signal CTR, the first positive initialization signal INT1 can switch from logic high to logic low, and the first negative initialization signal INTB1 can switch from logic low to logic high. (See reference...) Figure 5 As described, when the first positive initialization signal INT1 transitions to logic low and the first negative initialization signal INTB1 transitions to logic high, Figure 10 The first clock generation circuit 1020 shown can perform an oscillation operation. That is, the first clock generation circuit 1020 can generate a first phase clock signal M_CLK1 and a second phase clock signal M_CLK2 with a phase difference corresponding to a quantity of 90 degrees.

[0092] Reference Figure 11 The second initialization signals INT2 and INTB2 may include a second positive initialization signal INT2 and a second negative initialization signal INTB2. Therefore, the second positive initialization signal INT2 and the second negative initialization signal INTB2 can be switched based on the falling edge of the control pulse signal CTR. That is, based on the falling edge of the control pulse signal CTR, the second positive initialization signal INT2 can switch from logic high to logic low, and the second negative initialization signal INTB2 can switch from logic low to logic high. Similar to the first clock generation circuit 1020, the second clock generation circuit 1030 can generate a third phase clock signal M_CLK3 and a fourth phase clock signal M_CLK4 with a phase difference corresponding to a 90-degree difference through oscillation operation.

[0093] As described above, the transition times of the first initialization signals INT1 and INTB1, and the transition times of the second initialization signals INT2 and INTB2, can have a phase difference corresponding to a quantity of 180 degrees relative to the first phase clock signal M_CLK1. Therefore, the first phase clock signal M_CLK1 generated based on the first initialization signals INT1 and INTB1, and the third phase clock signal M_CLK3 generated based on the second initialization signals INT2 and INTB2, can have a phase difference corresponding to a quantity of 180 degrees.

[0094] In summary, the clock generation circuit 1000 can generate first initialization signals INT1 and INTB1 and second initialization signals INT2 and INTB2 based on the control pulse signal CTR corresponding to the target phase clock signal (e.g., the first phase clock signal M_CLK1). Based on the first initialization signals INT1 and INTB1, the first clock generation circuit 1020 can generate a first phase clock signal M_CLK1 and a second phase clock signal M_CLK2 with a phase difference corresponding to a quantity of 90 degrees. Based on the second initialization signals INT2 and INTB2, the second clock generation circuit 1030 can generate a third phase clock signal M_CLK3 and a fourth phase clock signal M_CLK4 with a phase difference corresponding to a quantity of 90 degrees.

[0095] According to embodiments of this disclosure, the clock generation circuit 1000 can generate first phase clock signals to fourth phase clock signals M_CLK1, M_CLK2, M_CLK3 and M_CLK4, each having a phase difference corresponding to a quantity of 90 degrees, through a synchronization structure.

[0096] According to embodiments of this disclosure, a multi-phase clock signal can be generated through a synchronization structure, so changes in PVT have almost no impact on the multi-phase clock signal, which increases the reliability of the multi-phase clock signal.

[0097] According to embodiments of this disclosure, an internal voltage can be generated using a stable multi-phase clock signal, which increases the stability of the internal voltage.

[0098] While some embodiments have been described above, those skilled in the art will understand that the described embodiments are merely examples. Therefore, the clock generation circuit and the voltage generation circuit including the clock generation circuit should not be limited based on the described embodiments. Rather, the clock generation circuit and the voltage generation circuit including the clock generation circuit described herein should be limited only in view of the appended claims in conjunction with the foregoing description and drawings.

[0099] Cross-reference of related applications

[0100] This application claims priority to Korean Patent Application No. 10-2021-0006849, filed on January 18, 2021, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference as if fully set forth herein.

Claims

1. A clock generation circuit, the clock generation circuit comprising: A control clock generation circuit that compares a reference voltage with each of a first feedback clock signal and a second feedback clock signal to generate a first control clock signal and a second control clock signal. A first clock synchronization circuit, wherein the first clock synchronization circuit causes the first feedback clock signal and the second feedback clock signal to be switched synchronously with the first control clock signal and the second control clock signal, wherein the first clock synchronization circuit generates each of the first feedback clock signal and the second feedback clock signal based on both the first control clock signal and the second control clock signal; as well as The second clock synchronization circuit generates a first phase clock signal and a second phase clock signal synchronously with each transition point of the first feedback clock signal and the second feedback clock signal.

2. The clock generation circuit of claim 1, wherein, The control clock generation circuit includes: A first control clock generation circuit compares the voltage level of the first feedback clock signal with the voltage level of the reference voltage to generate the first control clock signal; and The second control clock generation circuit compares the voltage level of the second feedback clock signal with the voltage level of the reference voltage to generate the second control clock signal.

3. The clock generation circuit of claim 2, wherein, Each of the first control clock generation circuit and the second control clock generation circuit includes: Input circuit, wherein the input circuit receives, buffers, and outputs a corresponding one of the first feedback clock signal and the second feedback clock signal; and A comparator circuit compares the voltage level of the reference voltage with the voltage level of the output signal of the input circuit to output a corresponding one of the first control clock signal and the second control clock signal.

4. The clock generation circuit of claim 1, wherein, The first clock synchronization circuit includes: A latching circuit, wherein the latching circuit performs a set operation based on the first control clock signal and a reset operation based on the second control clock signal; and An initialization circuit is provided, which initializes the latch circuit based on an initialization signal.

5. The clock generation circuit of claim 1, wherein, The second clock synchronization circuit includes: A first frequency divider circuit receives the first feedback clock signal and divides the first feedback clock signal to generate the first phase clock signal; and The second frequency divider circuit receives the second feedback clock signal and divides the second feedback clock signal to generate the second phase clock signal.

6. A voltage generating circuit, the voltage generating circuit comprising: A clock generation circuit, comprising: a control clock generation circuit that compares a reference voltage with each of a first feedback clock signal and a second feedback clock signal to generate a first control clock signal and a second control clock signal; a first clock synchronization circuit that synchronously switches the first feedback clock signal and the second feedback clock signal with the first control clock signal and the second control clock signal, wherein the first clock synchronization circuit generates each of the first feedback clock signal and the second feedback clock signal based on both the first control clock signal and the second control clock signal; and a second clock synchronization circuit that synchronously generates a first phase clock signal and a second phase clock signal with the timing of each switch of the first feedback clock signal and the second feedback clock signal; and A pumping circuit that generates a pumping voltage through a pumping operation based on the first phase clock signal and the second phase clock signal.

7. The voltage generation circuit of claim 6, wherein, The pumping circuit includes: A first capacitor receives the first phase clock signal; A second capacitor, the second capacitor receiving the second phase clock signal; and Multiple transistors are connected to the first capacitor and the second capacitor and have a cross-connection structure.

8. The voltage generation circuit of claim 6, wherein, The control clock generation circuit includes: A first control clock generation circuit compares the voltage level of the first feedback clock signal with the voltage level of the reference voltage to generate the first control clock signal; and The second control clock generation circuit compares the voltage level of the second feedback clock signal with the voltage level of the reference voltage to generate the second control clock signal.

9. The voltage generation circuit of claim 8, wherein, Each of the first control clock generation circuit and the second control clock generation circuit includes: Input circuit, wherein the input circuit receives, buffers, and outputs a corresponding one of the first feedback clock signal and the second feedback clock signal; and A comparator circuit compares the voltage level of the reference voltage with the voltage level of the output signal of the input circuit to output a corresponding one of the first control clock signal and the second control clock signal.

10. The voltage generation circuit of claim 6, wherein, The first clock synchronization circuit includes: A latching circuit, wherein the latching circuit performs a set operation based on the first control clock signal and a reset operation based on the second control clock signal; and An initialization circuit is provided, which initializes the latch circuit based on an initialization signal.

11. The voltage generation circuit of claim 6, wherein, The second clock synchronization circuit includes: A first frequency divider circuit receives the first feedback clock signal and divides the first feedback clock signal to generate the first phase clock signal; and The second frequency divider circuit receives the second feedback clock signal and divides the second feedback clock signal to generate the second phase clock signal.

12. A clock generation circuit, the clock generation circuit comprising: An initialization control circuit is used to generate a first initialization signal and a second initialization signal that are converted at different time points based on a control pulse signal. A first clock generation circuit generates a first phase clock signal and a second phase clock signal with different phases from each other by means of a synchronization operation based on the first initialization signal. as well as The second clock generation circuit generates a third-phase clock signal and a fourth-phase clock signal with different phases from each other through a synchronization operation based on the second initialization signal. The control pulse signal includes pulses corresponding to half a period of the target phase clock signal, and The initialization control circuit controls the timing of the first initialization signal transition based on the first edge of the pulse included in the control pulse signal, and controls the timing of the second initialization signal transition based on the second edge of the pulse included in the control pulse signal.

13. The clock generation circuit of claim 12, wherein, The first phase clock signal to the fourth phase clock signal have different phases from each other.

14. The clock generation circuit of claim 12, wherein, The control pulse signal has information corresponding to half a cycle of the target phase clock signal.

15. The clock generation circuit according to claim 14, wherein, The target phase clock signal corresponds to the first phase clock signal.

16. The clock generation circuit of claim 12, wherein, The first phase clock signal and the second phase clock signal have a phase difference corresponding to a quantity of 90 degrees, and the third phase clock signal and the fourth phase clock signal have a phase difference corresponding to a quantity of 90 degrees.

17. The clock generation circuit of claim 12, wherein, The first phase clock signal and the third phase clock signal have a phase difference corresponding to a quantity of 180 degrees.

18. The clock generation circuit of claim 12, wherein, The first clock generation circuit includes: A control clock generation circuit that compares a reference voltage with each of a first feedback clock signal and a second feedback clock signal to generate a first control clock signal and a second control clock signal. A first clock synchronization circuit performs an initialization operation based on the first initialization signal, and synchronously switches the first feedback clock signal and the second feedback clock signal with the first control clock signal and the second control clock signal; and A second clock synchronization circuit generates the first phase clock signal and the second phase clock signal synchronously with each transition point of the first feedback clock signal and the second feedback clock signal.

19. The clock generation circuit of claim 12, wherein, The second clock generation circuit includes: A control clock generation circuit that compares a reference voltage with each of a first feedback clock signal and a second feedback clock signal to generate a first control clock signal and a second control clock signal. A first clock synchronization circuit performs an initialization operation based on the second initialization signal, and synchronously switches the first feedback clock signal and the second feedback clock signal with the first control clock signal and the second control clock signal; and a second clock synchronization circuit that generates the third phase clock signal and the fourth phase clock signal in synchronization with a point in time at which each of the first feedback clock signal and the second feedback clock signal is converted.

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