CAN transmitter

Abstract

The present disclosure relates to a controller area network (CAN) transmitter in which transitions between output levels are smoothed by using multiple digital-to-analog converters (DACs) that are switched using a multi-phase clock signal. An example embodiment includes a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally-spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n digital-to-analog converters DACs (102 1‑3 ), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC configured to provide an output signal that transitions between a first output level and a second output level in M discrete steps when triggered by a transition in the signal on the data input line that is synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of the output signals from each of the n DACs (102 1‑3 ).

Description

Technical Field

[0001] This disclosure relates to a Controller Area Network (CAN) transmitter in which transitions between output levels are smoothed by using a plurality of digital-to-analog converters (DACs) that are switched using a multiphase clock signal. Background Technology

[0002] CAN transceivers need to be able to withstand or resist high-voltage signals, typically up to about 40V. The CAN bus signal itself is a 2V differential signal, concentrated at about VCC / 2, typically 2.5V. However, the common-mode voltage can range from -40V to +40V due to electromagnetic interference (EMI). For higher bit-rate specifications, such as the currently proposed CAN XL specification, a mixed-signal architecture may be required. The transistor feature size in high-voltage mixed-signal processing is typically limited in both size and frequency; for example, a 130nm processing node is limited to a synchronous design up to about 500MHz. A smaller processing node is not cost-effective for standalone CAN transceivers. Limited clock speeds reduce the ability of the CAN transmitter to generate smooth transitions between output levels, which may necessitate limiting EMI from abrupt transitions. Therefore, it would be advantageous to be able to design the desired transitions between high and low levels of the CAN transmitter output to reduce EMI without requiring more expensive processing. Summary of the Invention

[0003] According to the first aspect, a CAN transmitter is provided, comprising:

[0004] An oscillator configured to generate a clock signal having n equally spaced phases, where n is an integer greater than 1;

[0005] n digital-to-analog converters (DACs), each DAC having an input connected to one of the n phases of the clock signal and connected to a common data input line, each DAC being configured to provide an output signal that transitions between a first output level and a second output level with M discrete steps when triggered by a transition of the signal on the data input line synchronized with one of the n phases of the clock signal; and

[0006] An output amplifier stage is configured to provide a differential CAN output signal based on a combination of output signals from each of the n DACs.

[0007] The advantage of a CAN transmitter is that multiple clock phases allow multiple DACs to operate together at an effective clock frequency equal to n times the frequency of the clock signal. This allows for the use of a larger number of discrete steps to transition between the first and second output levels, making each transition smoother and thus reducing electromagnetic interference (EMI). Another advantage is that the frequency of the step interval is increased several times compared to the frequency of the transmitted data, thereby raising the EMI frequency to a different part of the spectrum, which can be suppressed, for example, by a low-pass filter. The effect of this is a significant reduction in EMI.

[0008] Each DAC can be configured to provide the same M discrete step lengths. These M discrete step lengths can be graded, becoming smaller closer to the first and second output levels and larger closer to the midpoint between the first and second output levels, thereby estimating the Gaussian shape of each transition in the CAN output signal. Other transition shapes can also be configured. Because each DAC is triggered sequentially, the general Gaussian shape of each DAC allows them to operate together to provide a smoother overall transition. Which DAC is triggered first is not important, as each DAC operates identically with the same M discrete step lengths.

[0009] Each DAC may, for example, include a shift register and a plurality of switched resistors for providing the output signal. The shift register stores M discrete lengths for sequentially operating the plurality of switched resistors. Alternative embodiments may, for example, use switched current sources instead of switched resistors. In either embodiment, after the shift register is triggered by a transition of an input signal on a common data input line, timed by one of the clock phases, the shift register operates the plurality of switched resistors or switched current sources in a set sequence to output M discrete lengths of the output signal. Subsequent DACs are then sequentially triggered to provide the same set sequence combined to provide the CAN output signal.

[0010] The number of step sizes M can be an integer of 4 or greater. There is no specific restriction on the value M, which can be chosen depending on the desired resolution. The total number of step sizes in each transformation is a multiple of M and n.

[0011] The oscillator can be a ring oscillator, where the number of clock phases and the number of DACs, n, can be an odd number of 3 or greater, such as 3, 5, 7, 9, or greater. An even number of clock phases is also possible using other oscillator topologies capable of providing an even number of clock phases. Higher numbers will gradually yield limited benefits because the same discrete step length in each DAC causes linear interpolation between each discrete step length. However, higher numbers will be advantageous in increasing the frequency of any resulting electromagnetic interference, which makes filtering such interference easier. Practical implementations using ring oscillators can have an odd number of phases, up to a maximum of 9. Specific examples may employ ring oscillators with 3 or 5 clock phases.

[0012] The output amplifier stage may typically include a first output transistor and a second output transistor, which are configured to provide a corresponding first output level and a second output level for the differential CAN output signal. Each output transistor may be, for example, a MOSFET transistor, wherein the first output transistor is a P-channel MOSFET transistor and the second output transistor is an N-channel MOSFET transistor.

[0013] Since the output transistors may require a higher voltage signal to drive them than is practical for the DACs, each DAC may include a first high-side DAC and a second low-side DAC. The first high-side DAC is configured to provide an output to the first output transistor to drive the first high side of the differential CAN output signal, and the second DAC is configured to provide an output to the second output transistor to drive the second low side of the differential CAN output signal. A first level shifter may be provided for each clock phase, each level shifter connected between a common data input line and the corresponding DAC. Each first level shifter is configured to provide a first high-side shifted input signal to the corresponding first high-side DAC, synchronized with the input data signal using one of the corresponding n phases, and a second low-side shifted input signal to the corresponding second low-side DAC, synchronized with the input data signal using one of the corresponding n phases. Second level shifters may also be connected between each of the n phases of the corresponding DAC, each second level shifter configured to provide a first high-side shifted clock phase to the corresponding first high-side DAC and a second low-side shifted clock phase to the corresponding second low-side DAC.

[0014] According to a second aspect, a method is provided for operating a CAN transmitter comprising an oscillator, n digital-to-analog converters (DACs)—where n is an integer greater than 1—and an output amplifier stage, the method comprising:

[0015] The oscillator generates a clock signal with n equally spaced phases;

[0016] Each of the n DACs sequentially receives one of the n phases of the clock signal and the data input signal from a common data input line;

[0017] Each DAC provides an output signal that transitions between a first output level and a second output level with M discrete steps, triggered by a transition of the data input signal synchronized with one of the n phases of the clock signal; and

[0018] The output amplifier stage provides a differential CAN output signal based on a combination of output signals from each of the n DACs.

[0019] The data input signal can be asynchronous with the clock signal from the oscillator.

[0020] Other features related to the first aspect can also be applied to the method of the second aspect.

[0021] These and other aspects of the invention will become apparent from the embodiments described below, and will be explained with reference to the embodiments described below. Attached Figure Description

[0022] The embodiments will be described by way of example only with reference to the accompanying drawings, in which:

[0023] Figure 1 This is a simplified schematic diagram of an example CAN transmitter;

[0024] Figure 2 This is a schematic graph showing how the CAN output signal voltage changes over time.

[0025] Figure 3 This is a schematic diagram of an example CAN transmitter;

[0026] Figure 4 This is a schematic diagram of an example CAN transmitter; and

[0027] Figure 5 It is used for Figure 4 A schematic diagram of an example level shifter circuit for a CAN transmitter.

[0028] It should be noted that the figures are illustrative and not drawn to scale. For clarity and convenience in the figures, the relative dimensions and proportions of the parts have been shown by enlarging or reducing them in size. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments. Detailed Implementation

[0029] This paper describes a DAC concept conceived for designing a robust and easily implementable solution. Since the existing 2ns time resolution of current CAN FD and CANFD SIC transmitters at 500MHz is not fine enough, this concept is particularly relevant to supporting increased data rates for CAN XL with faster edge timing. Preferably, a time resolution of less than 1ns is required. However, clock signals exceeding 1GHz may be too fast for the digital machines generating the transmitter DAC control signals. Therefore, timing convergence may not be achievable using existing techniques.

[0030] Instead of using a single-phase clock, a multi-phase timing scheme can be implemented. Multiple phases can each have relatively low speeds, but their combination generates the required finer time resolution in a synthetic manner. A 3-phase timing scheme may prove sufficient, and the three phases can be easily generated using a ring oscillator consisting of three inverters connected in a ring. The 3-phase clock, 0 / 120 / 240 degrees, can be directly obtained from the core of the ring oscillator. By adding three DACs in parallel, each using one of the three phases for timing, the effective clock speed is increased by three times.

[0031] A 350MHz clock can be selected, resulting in an effective clock of 1050MHz, ensuring a time resolution of slightly less than 1ns.

[0032] To minimize electromagnetic emissions (EME) of the CAN XL transmitter, Gaussian waveform shaping is used for high-to-low transitions and low-to-high transitions. The Gaussian waveform combination provides the fastest possible transitions with a narrow bandwidth, resulting in minimal spectral emissions.

[0033] For CAN XL, the transition time is quantized in 48 steps using three 16-tap DACs. Repeating the same tap coefficients three times produces a good piecewise linear approximation of the ideal Gaussian waveform and a low transmit spectrum. Therefore, the 48 steps during the transition can be generated by three identical parallel 16-tap DACs, each timing using one of the three phases of a ring oscillator. The CAN XL signal is a true differential signal, so the transition is symmetrical from start to finish, resulting in symmetrical tap coefficients. The transition gradually accelerates from the start towards the middle and then gradually decelerates towards the end. The step size at the start of the transition is the same as the step size at the end of the transition. Therefore, the 16-tap DACs are symmetrical. A total of seven different tap coefficient values ​​can be implemented for the 16-tap DACs. The middle segments of the transition can be generated using taps of equal weight (unformed).

[0034] Figure 1 The diagram shows a ring oscillator 101 and multiple DACs 102. 1-3An example of a CAN transmitter 100 with output amplifier stage 103. In this example, ring oscillator 101 is a 3-phase ring oscillator that provides clock signals clk_0, clk_120, and clk_240 to the corresponding DACs 1021, 1022, and 1023. In this example, the clock signals are equally spaced in phase, resulting in phases of 0 degrees, 120 degrees, and 240 degrees. Each DAC 102... 1-3 It is a waveform-shaped DAC, meaning that the output of each DAC has a defined shape in response to an input trigger transition, whether the input trigger transition is a high-to-low transition or a low-to-high transition. From each DAC 102 1-3 The shape of the output signal is predefined and ideally produces an approximation of a Gaussian shape; the degree of approximation depends on the resolution of the DAC. In a typical example, each DAC has 102... 1-3 It can have 16 taps. The number of taps may vary depending on the desired implementation, with 4 taps being the practical minimum, used to provide some degree of shaping for each transition when using multiple DACs. Each DAC is constructed identically so that the output waveform is the same. The effect of connecting each DAC to a different clock signal phase is to superimpose waveforms that are time-shifted relative to each other, thereby effectively improving the resolution of the output signal.

[0035] Output amplifier stage 103 is a high-voltage common-source cascode amplifier that provides a differential CAN output signal in the form of a first high level CANH and a second low level CANL. This differential CAN output signal is provided to, for example, an automotive CAN bus. CAN buses typically require operation using common-mode voltage levels up to approximately 40V, while the differential signal provided by amplifier 103 is approximately 2V. Technicians will be familiar with the specific details of the CAN bus and other aspects of the network.

[0036] 102 per DAC 1-3 Receive signals from the data input line, such as Figure 3 As shown in more detail, the signal is timed according to the corresponding phase of the clock signal, such that each transition on the data input line is synchronized with the phase of the clock signal. After receiving a transition of the signal from the data input line (which may arrive at any time asynchronous with the clock signal), each DAC begins to provide an output waveform according to M predefined discrete step lengths. Figure 2 Examples comparing the ideal waveform with the quantized waveforms of one and three DAC outputs are shown. Only a portion of the ideal requested signal 201 is shown, which follows a Gaussian shape, where the slope increases towards its maximum at the midpoint of the transition. Figure 2The example transition is illustrated. The requested signal 201 can be approximated by a single DAC output signal 202, where the size of each step is limited to match the desired level of the requested signal at each interval. Resolution can be improved by combining the outputs from more than one DAC, where the output from each DAC is shifted by a small fraction of the step interval in each DAC. Figure 2 The example shown illustrates the effect of combining the outputs from three DACs. Since each DAC provides the same sequence of steps, the step size between each step of the individual DAC output 202 is linearly interpolated, rather than precisely following the requested signal 201. However, the effect is still to reduce the quantization error of the output signal because the signal is closer to the requested signal.

[0037] like Figure 3 The example CAN transmitter 300 shown in the example has three DACs 102 connected in parallel. 1-3 Each can be implemented as a shift register 302, one of which is shown. Each shift register 302 can, for example, be based on a standard logic cell that drives a MOS switch, which activates / deactivates a resistor using a scaling value based on a tap value from the (quantized) desired Gaussian waveform. The high-level CANH output of the transmitter 100, provided by the output amplifier stage 303, is served by a PMOS pull-up switch / resistor, and the low-level CANL output is served by an NMOS pull-down switch / resistor.

[0038] Similar to Figure 1 In the example, Figure 3 In the example CAN transmitter 300 shown, a ring oscillator 301 provides a clock signal with three phases, clk_0, clk_120, and clk_240, to the corresponding DAC 302, providing one DAC 302 for each of the n phases of the clock signal. A data input signal, data_in, is provided on the data input line 304 and is synchronized with the clock signal phase for each phase using a synchronizer 305. Each synchronizer 305, which can be implemented using a dual cascaded flip-flop, ensures that each transition of the data_in signal is synchronized with each phase of the clock signal provided by the oscillator 301, because the arrival time of transitions in the data_in signal is asynchronous with the clock signal provided by the ring oscillator 301.

[0039] Output amplifier stage 303 includes a P-channel MOSFET 306 on the high-level CANH side driving the differential CAN output signal and an N-channel MOSFET 308 on the low-level CANL side driving the differential CAN output signal. The P-channel MOSFET has its source connected to the high-level output of each of the DACs 302, its gate connected to ground, and its drain connected to the CANH output via a first output diode 307. The N-channel MOSFET 308 has its source connected to the low-level output of each of the DACs 302, its gate connected to the power supply voltage Vcc, and its drain connected to the CANL output via a second output diode 309. The arrangement of output amplifier stage 303 is such that each side of the output signal depends on the sum of the outputs from each of the DACs 302, because the current supplied from each DAC 302 is added together at the input of output amplifier stage 303.

[0040] The nominal power supply rating of each standard cell in the DAC 302 is 1.5V (typical nominal power supply rating for currently used processes). These cells can be used directly on the NMOS side. This side can be defined as the "low side". For the PMOS side (referred to as the "high side"), the standard logic cell can alternatively refer to the VCC power rail, which can be at 5.0V. This voltage may be too high to be applied directly to the standard logic cell. Therefore, an additional power rail 1.5V lower than VCC may be required. A dedicated regulator (LDO) can be used to provide both the low-side power supply (1.5V higher than ground) and the high-side power supply (1.5V lower than VCC). This regulator has two output stages biased from a common reference generator. The low-side output stage consists of NMOS transistors, while the high-side output stage consists of PMOS transistors. The high-side circuitry is topologically identical to the low-side circuitry. The high-side version can be considered a "flipped" version of the low-side version, where the NMOS and PMOS transistors are interchanged. Figure 4 An example CAN transmitter 400 in which a low-side DAC and a high-side DAC are implemented is shown. The arrangement is similar to... Figure 3 The arrangement of transistors 406 and 408 in the output amplifier stage 403 is similar to that in the previous stage, but each DAC 402 includes a first high-side DAC 4021 and a second low-side DAC 4022. The first high-side DAC 4021 is configured to provide an output to the high-side transistor 406, while the second low-side DAC 4022 is configured to provide an output to the low-side transistor 408. Figure 3 The transistors in the circuit include output diodes 407 and 409, which connect transistors 406 and 408 to the high output level CANH and the low output level CANL that provide the differential CAN output signal.

[0041] For each clock phase, each DAC 402 is connected to the clock signal phase provided by the data input signal data_in on the ring oscillator 401 and data input line 404 via first and second high-side / low-side level shifters 411, 412. The level shifters 411, 412 and DACs 4021, 4022 are equipped with high-side voltage supplies and low-side voltage supplies ldo_hs, ldo_ls via high-side / low-side LDO 413, which derives its voltage supply from the power supply VCC and the ground GND level.

[0042] The data input signals and the 3-phase clock signals originate from the "low-side" circuitry and therefore need to be level-shifted to the high-side to drive the high-side shift register of each DAC. (An example is shown in...) Figure 5 The AC-coupled level shifter 500 can be used with positive DC feedback and an internal static level reset function, which softly latches the new state and thus ensures the circuit's stable state. This soft positive feedback is also known as a "bus hold" circuit, where a weak inverter is used in the feedback path of the strong inverter and a stable state is ensured when the input signal becomes tri-state, a common practice in bus systems. Therefore, it is called a "bus hold". The feedback needs to be weak (soft) so that any intentional signal on the bus can easily change the state of the strong inverter without being hindered by the bus hold. This is achieved by adding a 100 kΩ series resistor (shown as...). Figure 5 The R in the diagram can weaken the feedback. Circuit 500 combines speed (>1GHz) with quasi-static performance (DC). To ensure timing balance between the high-side and low-side shift registers, the same level shifter unit is used for all data and clock signals, regardless of whether it is intended for the high side (actual level shifted towards the VCC reference) or the low side, where strict level shifting is not required. Therefore, the timing offset between the high and low sides is solely due to the mismatch of the level shifter unit and has no other contribution; the two paths are identical.

[0043] Figure 5 The level shifter circuit 500 includes identical high-side level shifter 501 and low-side level shifter 502, which are decoupled from the input signal Vin via capacitor C. The capacitor is only needed to isolate the higher-level DC signal in the high-side level shifter 501, but is implemented on level shifters 501 and 502 to ensure that the output signals from said level shifters 501 and 502 are closely synchronized.

[0044] If clock phases clk_0, clk_120, and clk_240 occur in a strict order, the entire DAC assembly can accept asynchronous data input signals. Synchronizer blocks 305 and 405 preceding each DAC input ensure that any arriving data input signal is synchronized with a locally generated clock signal for each specific DAC instance, and the locally synchronized data is propagated to the low-side shift registers and high-side shift registers 4021 and 4022 by means of the aforementioned AC-coupled level shifter units 501 and 502 of the level shifter circuit 500. This assembly forms an architecture that is largely resistant to clock variations, jitter, frequency drift, and other clock-related defects.

[0045] Although operating freely, the frequencies of oscillators 101, 301, and 401 can be adjusted on an industrial testing instrument. The adjustment process for ring oscillators is generally simple. Due to frequency adjustment, the transition times of the synthesized waveform on the CAN bus can become very precise. Waveforms generated in this way can appear close to waves generated solely by analog components, but with significantly reduced process spread, power supply voltage dependence, and temperature drift. The synthesized waveform is very stable under environmental conditions and is highly suitable for mass production.

[0046] By reading this disclosure, those skilled in the art will understand other changes and modifications. Such changes and modifications may involve equivalent and other features known in the field of controller area networks that can be used in place of or in addition to the features described herein.

[0047] Although the appended claims are directed to specific combinations of features, it should be understood that the scope of the disclosure of this invention also includes any novel feature or combination of novel features or any generalization of such novel features as expressly or implicitly disclosed herein, regardless of whether such novel feature relates to the same invention as currently claimed in any of the claims or whether such novel feature alleviates any or all of the same technical problem as the technical problem alleviated by this invention.

[0048] Features described in the context of a single embodiment may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, various features described in the context of a single embodiment may also be provided individually or in any suitable sub-combination. The applicant hereby reminds that new claims may be made for such features and / or combinations of such features during the examination of this application or any other application derived therefrom.

[0049] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude multiple, a single processor or other unit can perform the functions of several components described in the claims, and the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

Claims

1. A Controller Area Network (CAN) transmitter, characterized in that, include: An oscillator configured to generate clock signals having n equally spaced phases clk_0, clk_120, and clk_240, where n is an integer greater than 1; n digital-to-analog converters (DACs), each DAC having an input connected to one of the n phases of the clock signal and connected to a common data input line, each DAC being configured to provide an output signal that transitions between a first output level and a second output level with M discrete steps, where M is an integer of 4 or greater, when triggered by a transition of the signal on the common data input line synchronized with one of the n phases of the clock signal; and An output amplifier stage is configured to provide a differential CAN output signal based on a combination of output signals from each of the n DACs. The output amplifier stage includes a first output transistor and a second output transistor, which are configured to provide a corresponding first output level and a second output level of the differential CAN output signal. Each DAC includes a first high-side DAC and a second low-side DAC. The first high-side DAC is configured to provide an output to the first output transistor to drive a first high level of the differential CAN output signal, and the second low-side DAC is configured to provide an output to the second output transistor to drive a second low level of the differential CAN output signal.

2. The CAN transmitter according to claim 1, characterized in that, The M discrete step values ​​are classified as smaller as they are closer to the first output level and the second output level, and larger as they are closer to the midpoint between the first output level and the second output level, where M is an integer of 4 or a larger integer.

3. The CAN transmitter according to claim 1, characterized in that, Each DAC includes a shift register and a plurality of switched resistors or switched current sources for providing the output signal. The shift register stores the M discrete step sizes for sequentially operating the plurality of switched resistors or switched current sources, where M is an integer of 4 or greater.

4. The CAN transmitter according to claim 1, characterized in that, The oscillator is a ring oscillator and n is an odd number 3 or a larger odd number.

5. The CAN transmitter according to claim 1, characterized in that, include: For each of the n phases of the clock signal, a first level shifter is connected between the common data input line and the corresponding DAC. Each first level shifter is configured to provide a first high-side shifted input signal of the input data signal synchronized with the corresponding one of the n phases to the corresponding first high-side DAC, and a second low-side shifted input signal of the input data signal synchronized with the corresponding one of the n phases to the corresponding second low-side DAC. as well as A second level shifter is connected between each of the n phases of the clock signal and the corresponding DAC, each second level shifter being configured to provide a first high-side shifted clock phase to the corresponding first high-side DAC and a second low-side shifted clock phase to the corresponding second low-side DAC.

6. A method for operating a CAN transmitter comprising an oscillator, n digital-to-analog converters (DACs), and an output amplifier stage, characterized in that, n is an integer greater than 1, and the method includes: The oscillator generates a clock signal with n equally spaced phases clk_0, clk_120, and clk_240; Each of the n DACs receives, sequentially from the data input line, a corresponding one of the n phases of the clock signal and the data input signal; Each DAC provides an output signal that transitions between a first output level and a second output level with M discrete steps, triggered by a transition of the data input signal synchronized with one of the n phases of the clock signal; and The output amplifier stage provides a differential CAN output signal based on a combination of output signals from each of the n DACs. The output amplifier stage includes a first output transistor and a second output transistor, which are configured to provide a corresponding first output level and a second output level of the differential CAN output signal. Each DAC includes a first high-side DAC and a second low-side DAC. The first high-side DAC is configured to provide an output to the first output transistor to drive a first high level of the differential CAN output signal, and the second low-side DAC is configured to provide an output to the second output transistor to drive a second low level of the differential CAN output signal.

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