Power operating state for core logic in memory physical layer

Abstract

An electronic device has a memory functional block including a memory circuit and a memory physical layer (PHY) functional block having core logic that controls operations in the memory functional block, a memory PHY voltage regulator, a system voltage regulator, and a controller. The electronic device also includes a switch having an input coupled to an output of the memory PHY voltage regulator, another input coupled to an output of the system voltage regulator, and an output coupled to a power input of the core logic. The controller sets the switch so that power is provided to the core logic from the memory PHY voltage regulator in a full power operating state. The controller sets the switch so that power is provided to the core logic from the system voltage regulator in one or more low power operating states.

Description

[0001] background Background Technology

[0002] For many electronic devices, especially those that operate using power supplied from batteries, power consumption is a significant issue. Some electronic devices therefore support low-power operating states to help conserve power during operation. For example, some electronic devices support at least one low-power operating state in which the voltage supplied to the circuitry (e.g., integrated circuits, discrete components, etc.) within the electronic device is reduced relative to the voltage supplied to the same circuitry in full-power operation. Because power consumption is proportional to the voltage used in the circuitry, reducing the voltage in this low-power operating state has the effect of reducing the power consumed by such electronic devices. As another example, electronic devices may support low-power operating states in which operating parameters such as current, control clock frequency, and operating rate are reduced individually or in combination (and / or voltage) to save power.

[0003] While low-power operating states can help electronic devices save power, they can also be associated with inherent inefficiencies. For example, power circuitry that supplies power to other circuitry within an electronic device might be designed and supplied to operate efficiently under maximum power loads for those other circuitry, and could operate inefficiently under lower power operating states. For instance, a voltage regulator supplied for maximum power loads, but also used to reduce relatively high input voltages to lower voltages to be supplied to circuitry operating in a low-power state, might itself experience significant power losses under low-power operating states. As another example, entering and exiting low-power states can be relatively slow and / or require considerable effort, which can lead to undesirable delays in transitions between operating states. For example, in a low-power operating state, an electronic device might need to store its operating state before reducing the voltage below a given voltage, and then restore that operating state before resuming operation in a high-power operating state. Attached Figure Description

[0004] Figure 1 A block diagram illustrating an electronic device according to some embodiments is presented.

[0005] Figure 2 A block diagram illustrating a voltage regulator in an electronic device according to some embodiments is presented.

[0006] Figure 3 A block diagram illustrating the core logic of the controller, switches, and memory physical layer (PHY) according to some implementation schemes is presented.

[0007] Figure 4 A state diagram is presented, showing multiple operating states and transitions between operating states according to some implementation schemes.

[0008] Figure 5 A flowchart illustrating a process for setting the operational state in the core logic of the memory PHY, according to some implementation schemes, is presented.

[0009] Figure 6 A flowchart illustrating a process for determining the operational state in which the memory PHY core logic will operate, according to some implementation schemes, is presented.

[0010] Throughout the accompanying drawings and description, similar reference numerals refer to the same elements. Detailed Implementation

[0011] The following description is presented to enable any person skilled in the art to make and use the described embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications. Therefore, the described embodiments are not limited to the embodiments shown, but are to be given the widest scope consistent with the principles and features disclosed herein.

[0012] the term

[0013] In the following description, various terms are used to describe the implementation scheme. The following is a simplified and general description of one of these terms. Note that such a term may have important additional aspects, which are not listed herein for clarity and brevity, and therefore the description is not intended to limit the term.

[0014] Functional Block: A functional block refers to a group, set, and / or collection of one or more interconnected circuit elements (such as integrated circuit elements / circuit systems, discrete circuit elements / circuit systems, etc.). Circuit elements are "interconnected" because they share at least one property. For example, interconnected circuit elements may be included in, manufactured on, or otherwise coupled to a particular integrated circuit chip, substrate, circuit board, or part thereof, may relate to the execution of a given function (computing or processing function, memory function, etc.), may be controlled by a common control element and / or a common clock, etc. A functional block may include circuit systems with any number of circuit elements, ranging from a single circuit element (e.g., a single integrated circuit logic gate or discrete circuit element) to millions or billions of circuit elements (e.g., integrated circuit memory).

[0015] Overview

[0016] In the described embodiments, the electronic device includes subsystems such as a processing subsystem, a display subsystem, a media processing subsystem, and a memory subsystem, which are communicatively coupled via a structure (e.g., one or more buses, interconnects, networks, etc.). The memory subsystem includes a memory circuitry for storing copies of data (e.g., inputs or results from computational operations, instructions, control or configuration values, etc.) and a memory physical layer (PHY) circuitry for accessing data stored in the memory. The memory PHY includes a core logic circuitry that manages memory access and controls other operations within the memory subsystem. The electronic device also includes multiple voltage regulators that provide power to the subsystems within the electronic device. The voltage regulators include a system voltage regulator that provides power to at least a portion of the media processing subsystem, the display subsystem, and the structure, and a memory PHY voltage regulator that provides power to the memory subsystem. In the described embodiments, the system voltage regulator and the memory PHY voltage regulator are selectively used to provide power to the core logic in corresponding operating states of the core logic.

[0017] In the described implementation, the electronic device supports several operating states of core logic in the memory PHY. The operating states include a full-power operating state and multiple low-power operating states, each of which is associated with a correspondingly different voltage that supplies power to the core logic. Typically, for the full-power operating state, the core logic is powered at the full-power voltage and therefore operates normally or normally (i.e., without degrading the performance associated with the reduced voltage level). For each low-power operating state, the core logic is powered at a correspondingly reduced voltage level and therefore operates with a correspondingly reduced performance.

[0018] In some implementations, for the full-power operating state of the core logic in the memory PHY, power is supplied to the core logic by the memory PHY voltage regulator via a local low-dropout (LDO) voltage regulator in the memory PHY (or elsewhere in the electronic device). The memory PHY voltage regulator, which also supplies power to the memory circuitry and input-output (I / O) circuitry in the memory PHY, provides power at a higher voltage (e.g., sufficient to operate the memory circuitry and I / O circuitry). The LDO receives the power output from the memory PHY voltage regulator and supplies power to the core logic at full-power voltage (e.g., 0.6V or another voltage). For the low-power operating state of the core logic in the memory PHY, power is supplied to the core logic from the system voltage regulator. In the low-power operating state, power is supplied directly to the core logic from the system voltage regulator, where the local LDO voltage regulator is bypassed (and may be de-energized). The system voltage regulator, which also supplies power to the display subsystem and media processing subsystem, provides various voltage levels of power depending on the activity-related standards and / or the busyness of the electronic device or its functional blocks.

[0019] In some implementations, low-power operating states include a "low-activity" operating state, during which the system voltage regulator supplies power to the core logic at a low-activity voltage (e.g., 0.5V or another voltage) below the full-power voltage. The low-activity voltage is sufficient to allow the circuitry in the core logic to continue limited operation—but low enough to cause the core logic to experience a corresponding performance degradation (e.g., performing operations more slowly than in full-power operating states). Low-power operating states also include a "hold" operating state, during which the system voltage regulator supplies power to the core logic at a hold voltage (e.g., 0.4V or another voltage) below the low-activity voltage. The hold voltage is insufficient to allow the circuitry in the core logic to continue reliable operation, but sufficient to preserve state information for the circuitry in the core logic. Low-power operating states also include a "power-down" operating state, during which the system voltage regulator does not supply power to the core logic.

[0020] In the described implementation, the electronic device includes a two-input, one-output switching circuit for controlling a voltage regulator from which core logic in the memory PHY receives power. A first input of the switch is coupled to the power output of the memory PHY voltage regulator, a second input is coupled to the power output of the system voltage regulator, and the output is coupled to the power input of the core logic. For full-power operation, the controller in the electronic device sets the switch such that the memory PHY voltage regulator supplies power to the core logic via a local LDO. For low-activity, hold, and power-down operation states, the controller sets the switch such that the system voltage regulator supplies power to the core logic.

[0021] In some implementations, a controller in the electronic device monitors memory access activity and the busy / idle state of the core logic, and sets the operating state of the core logic based on the rate of memory access activity and / or the length of idle periods in the core logic. In these implementations, the controller monitors memory access activity in the electronic device and sets a switch such that when memory access activity is above a rate threshold (e.g., N memory accesses within the last M milliseconds, etc.), the memory PHY voltage regulator supplies power to the core logic in a full-power operating state. Conversely, the controller sets a switch such that when memory access activity is below a rate threshold, the system voltage regulator supplies power to the core logic in a low-power operating state within a low-power operating state.

[0022] In some implementations, regarding low-power operation, as long as memory access activity is below a rate threshold, but at least some kind of memory access activity exists, the controller maintains the core logic in the memory PHY in a low-activity operation state. In this case, the controller (or another entity in the electronic device) sets the system voltage regulator to provide power to the core logic at a low-activity voltage. However, when there is no memory access activity, the controller sets the core logic to either a hold-in operation state or a power-down operation state based on the core logic's idle time. More specifically, the controller monitors for periods of core logic idleness, i.e., periods during which one or more specified activities, such as handling interrupts, are not performed. When the core logic experiences an idle period shorter than a time threshold, the controller sets the system voltage regulator to provide power to the core logic at a hold-in voltage in the hold-in operation state. When the core logic experiences an idle period longer than a time threshold, the controller sets the system voltage regulator to not provide power to the core logic in the power-down operation state. Note that in some implementations, using a power-down operation state involves saving core logic operation state information (e.g., register values, etc.) to memory (e.g., state memory in a memory PHY) and then restoring the core logic operation state information from memory to the core logic before starting subsequent operations in operation states other than the power-down operation state.

[0023] In some implementations, the controller includes one or more operating state change limiting mechanisms that limit the rate at which the controller switches the operating state of core logic in the memory PHY. For example, the controller may maintain a record of previous operating state transitions (e.g., from full-power operation to low-activity operation, etc.) and use this record to determine the rate at which operating states are switched. The controller may limit some or all of the switches based on the record. For example, when the operating state switching rate has exceeded a threshold, the controller may preferentially maintain the core logic in a higher power operating state (instead of automatically switching the core logic to a lower power operating state). As another example, the controller may use the average, maximum / minimum, or other values ​​of memory access activity levels and / or core logic idle time periods over a specified period, rather than the instantaneous memory access activity levels and / or core logic idle time periods, to determine whether to switch the operating state of the core logic.

[0024] By using full-power and low-power operating states for the core logic in the memory PHY, the described implementation ensures that the core logic is in an appropriate operating state based on memory access activity and / or idle periods. This helps save power where possible, but also ensures that the core logic—and therefore the memory subsystem—is fully responsive to memory access requests. By using a combination of memory PHY voltage regulators and system voltage regulators to supply power to the core logic in appropriate full-power and low-power operating states, the described implementation enables more efficient use of power in electronic devices (e.g., lower dynamic power consumption, etc.). Therefore, the electronic device remains relatively responsive, but also avoids unnecessary power consumption, leading to greater user satisfaction with the electronic device.

[0025] electronic devices

[0026] Figure 1 A block diagram illustrating an electronic device 100 according to some embodiments is presented. (See also...) Figure 1As can be seen, the electronic device 100 includes a processing subsystem 102, a graphics processing subsystem 104, a display subsystem 106, a media processing subsystem 108, a memory subsystem 110, and a structure subsystem 114. Typically, the processing subsystem 102, graphics processing subsystem 104, display subsystem 106, media processing subsystem 108, memory subsystem 110, networking subsystem 112, and structure subsystem 114 are functional blocks implemented in hardware, i.e., using various circuit systems, circuit elements, and devices. For example, the processing subsystem 102, graphics processing subsystem 104, display subsystem 106, media processing subsystem 108, memory subsystem 110, networking subsystem 112, and structure subsystem 114 can be entirely fabricated on one or more semiconductor chips, including on one or more separate semiconductor chips, can be made from semiconductor chips combined with discrete circuit elements, can be made from individual discrete circuit elements, and so on. As described herein, at least some of the processing subsystem 102, graphics processing subsystem 104, display subsystem 106, media processing subsystem 108, memory subsystem 110, networking subsystem 112, and architecture subsystem 114 perform operations associated with setting the operational state of the core logic in the memory physical layer (PHY) of the memory subsystem 110.

[0027] The processing subsystem 102 is a functional block in the electronic device 100 that performs calculations and other operations (e.g., control operations, configuration operations, etc.). For example, the processing subsystem 102 may be or include one or more microprocessors, central processing unit (CPU) cores and / or other processing mechanisms.

[0028] The graphics processing subsystem 104 is a functional block that performs computational and other operations (e.g., control operations, configuration operations, etc.) associated with graphics processing (e.g., rendering, etc.) and / or general computing operations in the electronic device 100. For example, the processing subsystem 102 may be or include one or more general-purpose graphics processing unit (GPGPU) cores and / or other graphics processing mechanisms.

[0029] The display subsystem 106 is a functional block that performs operations for displaying information on a display (e.g., a screen) (not shown) of the electronic device 100. The display subsystem 106 includes one or more controllers, drivers, and / or other circuitry for providing information to and / or receiving information from the display.

[0030] The media processing subsystem 108 is a functional block that performs operations for processing audio media (e.g., audio files, audio streams, etc.), video media (e.g., video files, video streams, etc.), and tactile and / or other forms of media stored in memory (e.g., in memory subsystem 110) or streamed over a network and / or output through speakers, displays, and / or other human-machine interface devices. The media processing subsystem 108 includes one or more receivers, processors, encoders / decoders, controllers, drivers, and / or other circuitry for processing media.

[0031] The memory subsystem 110 is a functional block that performs operations of memory (e.g., "main" memory). The memory subsystem 110 includes volatile and / or non-volatile memory circuitry, such as fourth-generation dual data rate synchronous DRAM (DDR4 SDRAM) and / or other types of memory circuitry for storing data and instructions for use by other functional blocks in the electronic device 100, as well as control circuitry for processing access to the data and instructions stored in the memory circuitry and for performing other control or configuration operations. As described below, in the described embodiment, the memory subsystem includes a memory physical layer (PHY) with a core logic circuitry system that can operate in multiple different operating states.

[0032] The networking subsystem 112 is a functional block that performs operations of searching, connecting, configuring, and communicating on wired and / or wireless electronic communication networks. The networking subsystem 112 includes transceivers, controllers, processors, and / or other circuit systems for communicating on wired and / or wireless networks.

[0033] For illustrative purposes, electronic device 100 is simplified. However, in some embodiments, electronic device 100 includes additional or different functional blocks, subsystems, components, and / or communication paths. For example, electronic device 100 may include input-output (I / O) subsystems, etc. Electronic device 100 typically includes sufficient functional blocks to perform the operations described herein.

[0034] Electronic device 100 may be or may be included in any device that performs the operations described herein. For example, electronic device 100 may be or may be included in the following: desktop computer, laptop computer, wearable computing device, tablet computer, a virtual or augmented reality device, smartphone, artificial intelligence (AI) or machine learning device, server, network device, toy, audiovisual device, home appliance, vehicle, etc., and / or combinations thereof.

[0035] Voltage regulator

[0036] In the embodiment described, the electronic device 100 includes a set of voltage regulators, each of which provides power to a corresponding functional block in the electronic device 100. Figure 2 A block diagram illustrating a voltage regulator in an electronic device 100 according to some embodiments is presented. (See also...) Figure 2 As can be seen, the voltage regulator includes voltage regulator 200, system voltage regulator 204, and memory physical layer (PHY) voltage regulator 210 (collectively referred to as "voltage regulators"). Each voltage regulator includes a voltage regulator circuitry, such as a switching voltage regulator or another type of voltage regulator. For example, in some embodiments, some or all of the voltage regulators are or include one or more buck converters or boost converters. Each voltage regulator receives an input voltage, for example, from a power rail in electronic device 100 or another source (not shown), and provides power at a regulated voltage.

[0037] In the described embodiments, the specific regulated voltage of the power supplied by each voltage regulator in the voltage regulator is set using circuit elements within that voltage regulator. The circuit elements used to control the output of each voltage regulator depend on the type of voltage regulator and therefore also on the circuit elements within that voltage regulator. For example, in some embodiments, a bias or reference voltage supplied to the circuit elements of a given voltage regulator can be set to a specified value so that those circuit elements begin to supply power at the corresponding voltage. As another example, in some embodiments, amplifiers, resistors, capacitors, inductors, etc., in a given voltage regulator can be configured or set to cause the given voltage regulator to begin supplying power at a specified voltage. As yet another example, in some embodiments, values ​​in registers or memory elements used by one or more control circuits or elements of the given voltage regulator to determine how to set the output voltage of the given voltage regulator can be set to specified values ​​so that the given voltage regulator begins to supply power at the specified voltage.

[0038] In some implementations, each voltage regulator in the voltage regulator provides power to a designated "domain" comprising a corresponding independent subset of functional blocks in electronic device 100. For example, voltage regulator 200 provides power to a portion of a processing subsystem 102, a graphics processing subsystem 104, and a structural subsystem 114 (in... Figure 2The domains shown as structure 202 are powered (e.g., for specific bus, driver, or receiver circuitry systems on communication interconnects used by the processing subsystem). In some embodiments, the domains, and therefore the functional blocks included in said domains, are arranged such that the constituent functional blocks can operate as a group in various operating states. For example, in some embodiments, system voltage regulator 204 powers the domains including functional blocks that are generally at least partially effective even in low-power operating states of the electronic device—when other voltage regulators, such as voltage regulator 200, are providing power at significantly reduced voltages or not at all. For example, when processing subsystem 102 and graphics processing subsystem 104 are in a low-voltage holding operation state or are powered down, a portion of media processing subsystem 108, display subsystem 106, and structure subsystem 114 (in Figure 2 The structure shown as 206 can be in a low-power but still effective operating state for decoding and viewing video media on the display of the electronic device. In some of these embodiments, the power domain to which the system voltage regulator 204 is supplied is referred to as an "intermittent" domain because the functional blocks in this domain can switch between on and off states as needed, or "intermittently" to perform corresponding operations in certain low-power modes (e.g., displaying information on the display of the electronic device 100, etc.).

[0039] like Figure 2As shown, the memory subsystem 110 includes a memory physical layer (MEM PHY) core logic 214, a memory physical layer (MEM PHY) input-output (IO) 216, and memory circuitry 218. Memory circuitry 218 is a functional block that includes a memory circuitry for storing copies of data accessible (e.g., read, write, delete, modify, etc.) by other functional blocks in the electronic device 100; and a circuitry for accessing data within the memory circuitry. For example, memory circuitry 218 may include an array of DDR4 SDRAM circuitry with a capacity for storing gigabytes or terabytes of data. Memory PHY IO 216 is a functional block that performs operations for sending data retrieved from memory circuitry 218 to other functional blocks in the electronic device 100 (e.g., processing subsystem 102, etc.) and for receiving data to be stored in memory circuitry 218 from other functional blocks in the electronic device 100. Memory PHY IO 216 includes circuitry such as drivers, receivers, buffers, etc., for sending and receiving data. The memory PHY core logic 214 is a functional block that includes circuitry for managing access to the memory circuitry 218 and controlling other operations within the memory subsystem 110. The memory PHY core logic 214 includes circuitry such as a memory access state machine circuitry, a memory access routing controller circuitry, a memory PHY clock generation circuitry, and a memory PHY state information storage circuitry.

[0040] The memory PHY IO 216 and memory circuitry 218 are powered by the memory PHY voltage regulator 210 (regardless of the operating state of the memory PHY core logic 214). In some embodiments, the memory PHY voltage regulator 210 provides power at a fixed and substantially stable voltage, which is high enough to ensure reliable operation of the circuitry in the memory PHY IO 216 and memory circuitry 218.

[0041] Power is supplied to the memory PHY core logic 214 from either the system voltage regulator 204 or the memory PHY voltage regulator 210 via switch (SW) 212. Switch 212 is a dual-input single-output switch (e.g., a multiplexer) controlled by controller 208 to selectively supply power from either the system voltage regulator 204 or the memory PHY voltage regulator 210 depending on the operating state of the memory PHY core logic 214. One input of switch 212 is coupled to the power output of the memory PHY voltage regulator 210, the other input is coupled to the power output of the system voltage regulator 204, and the output of switch 212 is coupled to the power input of the memory PHY core logic 214. For full-power operation, controller 208 sets switch 212 via its switch control input, causing the memory PHY voltage regulator 210 to supply power to the core logic. For low-activity, hold, and power-down operating states, controller 208 sets switch 212 so that system voltage regulator 204 supplies power to memory PHY core logic 214. The function of switch 212 and the full-power, low-activity, hold, and power-down operating states are described in more detail below.

[0042] In this specification, a voltage regulator is described as "providing power" at a specified voltage (e.g., full power voltage, low activity voltage, etc.). As used herein, "providing power" refers to providing sufficient current to meet the needs of an electrical load (e.g., circuit system, functional block, etc.) at a substantially stable regulated voltage. A "substantially stable" voltage is one that is maintained by the voltage regulator as close as possible to the required regulated voltage, but may vary depending on changes in power demand from the electrical load, etc.

[0043] although Figure 2 The image shows a specific number and arrangement of voltage regulators, but in some embodiments, electronic device 100 includes a different number and / or arrangement of voltage regulators. For example, in some embodiments, electronic device 100 includes a method for supplying voltage regulators to… Figure 2 Functional blocks (such as networking subsystem 112) not shown in the diagram provide additional voltage regulators for power. Typically, electronic device 100 includes sufficient voltage regulators to perform the operations described herein.

[0044] Controller and memory PHY core logic

[0045] In the described implementation, the controller configures a switch such that the desired voltage regulator supplies power to the core logic circuitry in the memory PHY via the switch. Figure 3A block diagram illustrating a controller 208, a switch 212, and memory PHY core logic 214 according to some embodiments is presented. (See also...) Figure 3 As can be seen, controller 208 includes control logic 300, activity monitor 302, idle monitor 304, and state machine 306. Control logic 300 is a function block that executes operations to control switch 212 using state machine 306 based on inputs received from activity monitor 302 and idle monitor 304. Control logic 300 drives signals to switch 212, causing switch 212 to forward power received from either system voltage regulator 204 or memory PHY voltage regulator 210 to memory PHY core logic 214. For example, in an embodiment where switch 212 is a multiplexer, control logic 300 controls switch 212 via logic high / low levels of multiplexer control signals. As another example, in an embodiment where switch 212 is part of other circuitry, control logic 300 may transmit one or more values ​​(e.g., bit sequences, signal levels, or edges) that cause other circuitry to set switch 212 accordingly.

[0046] Activity monitor 302 is a functional block that performs operations to determine the rate at which memory accesses are occurring or will occur in memory circuitry 218 and to report the rate of such memory accesses to control logic 300. For example, in some embodiments, activity monitor 302 determines the rate of memory accesses based on information received or acquired from memory PHY core logic 214 regarding memory access operations that have been, are being, or will be performed by memory PHY core logic 214. As another example, in some embodiments, activity monitor 302 determines the rate of memory accesses based on information regarding queue depth, software or hardware workload profiles, estimated memory access rates, and / or other information received from other functional blocks in electronic device 100 (e.g., processing subsystem 102, etc.). In some embodiments, activity monitor 302 maintains a record of past memory access rates and / or a running average of memory access rates over one or more time periods, and uses this record to help determine or estimate memory access rates.

[0047] Idle monitor 304 is a functional block that performs operations to determine the length of an idle period that the memory PHY core logic 214 is experiencing or will experience and reports that length to the control logic 300. In other words, idle monitor 304 determines the actual or estimated length of time the memory PHY core logic 214 is idle (i.e., not participating in memory access, control, interrupt handling, and / or other operations) and then provides a representation of the actual or estimated length of time to the control logic 300. For example, in some embodiments, idle monitor 304 determines the length or estimated length of the idle period of the memory PHY core logic 214 based on information obtained from the memory PHY core logic 214 regarding operations that have been, are being, or will be performed by the memory PHY core logic 214. As another example, in some embodiments, idle monitor 304 determines the length or estimated length of the idle period of the memory PHY core logic 214 based on information about queue depth, software or hardware workload profiles, future memory access operations, and / or other information received from other functional blocks in electronic device 100 (e.g., processing subsystem 102, etc.). In some implementations, the idle monitor 304 maintains a record of past idle periods of the memory PHY core logic 214 and / or an operating average of the length of past idle periods of the memory PHY core logic 214, and uses the record to help determine or estimate the length of a given idle period.

[0048] State machine 306 is a function block that performs operations to determine the operating state of memory PHY core logic 214 based on memory access rate and / or the length of idle time of memory PHY core logic 214. State machine 306 includes circuitry that stores or otherwise represents the states of memory PHY core logic 214 and transitions between states. In operation, state machine 306 receives information about memory access rate and / or the length of idle time of memory PHY core logic 214 and returns an indication of the operating state that memory PHY core logic 214 will be in based on the received information. The states of the state machine and the transitions between states are... Figure 4 It is shown in the figure and described below.

[0049] In some embodiments, state machine 306, control logic 300, and / or another functional block include an operation state change limiting mechanism that limits the rate at which control logic 300 switches the operation states of core logic in the memory PHY. For example, in some embodiments, the operation state change limiting mechanism includes one or more counters that hold the time elapsed since the last transition between two or more corresponding operation states. In these embodiments, the one or more counters are used to ensure that a specific amount of time has elapsed before a subsequent transition between the corresponding two or more operation states. In some of these embodiments, the specific amount of time is associated with or proportional to the delay used for transitioning between the two or more operation states, wherein operation states with higher transition delays have a longer specific amount of time. As another example, in some embodiments, the operation state change limiting mechanism includes one or more records of the average running time between transitions between two or more corresponding operation states, one or more records of the average number of operation state transitions between two or more corresponding operation states within a given time period, and / or other records representing the transition rate between operation states. In these embodiments, the one or more records are used to control the rate of transitions between operation states. Typically, operating state change limiting mechanisms prevent excessive back-and-forth transitions between two or more operating states to avoid inconsistent operation (caused by rapid switching between two or more operating states) and unnecessary effort when performing transitions between two or more operating states. In some implementations, the operating state change limiting mechanism preferentially keeps the memory PHY core logic 214 in a higher power operating state (e.g., full power operating state, low activity operating state, etc.) rather than allowing the memory PHY core logic 214 to rapidly bounce back and forth from a higher power operating state to a lower power operating state (e.g., low activity operating state, hold operating state, etc.).

[0050] The memory PHY core logic 214 includes a logic circuit system 308, a state memory (MEM) 310, and a low-dropout regulator (LDO) 312. The logic circuit system 308 is a functional block that performs operations for controlling, configuring, and operating the memory PHY core logic 214. For example, in some embodiments, the logic circuit system 308 includes a memory access state machine circuit system for controlling access to the memory circuit 218, a memory access routing controller circuit system for routing memory access to / from the memory circuit 218, a memory PHY clock generation circuit system for generating one or more clocks for memory access in the memory circuit 218 and / or operations in the memory PHY core logic 214, and / or other circuit systems.

[0051] State memory 310 is a functional block that performs operations for storing operational state information from the circuitry in memory PHY core logic 214. State memory 310 includes memory such as static random access memory (SRAM) used by logic circuitry 308 to store operational state information, such as register contents, configuration bits / flags, settings, operation values ​​(results, inputs, etc.); and / or other state information used by memory PHY core logic 214 or its functional blocks during operation. In some embodiments, operational state information is read, received, or otherwise obtained from the circuitry in memory PHY core logic 214 before entering a low-power operating state (e.g., holding an operating state, etc.), in which power is supplied to memory PHY core logic 214 at a sufficiently low voltage such that the operational state information is not reliably retained in the circuitry in memory PHY core logic 214. The state is then stored in state memory 310 until the circuitry in memory PHY core logic 214 is restored to a higher power operating state (e.g., full power operating state), in which power is supplied to memory PHY core logic 214 at a sufficiently high voltage so that the operating state information is reliably retained in the circuitry in memory PHY core logic 214. As the circuitry in memory PHY core logic 214 transitions from a low power operating state to a higher power operating state, the operating state information is read from state memory 310 and used to restore the operating state 214 of the circuitry in memory PHY core logic to the operating state prior to the transition to the low power operating state. In some embodiments, there are delays or waiting times associated with acquiring and storing the operating state information in state memory 310, as well as delays or waiting times associated with reading the operating state information from state memory 310 and using the operating state information to restore the operating state of the circuitry in memory PHY core logic 214.

[0052] LDO 312 is a voltage regulator, such as a low-dropout regulator, a linear voltage regulator, or another type of voltage regulator. LDO 312 provides power to the logic circuit system 308 and the state memory 310. More specifically, LDO 312 receives power from a memory PHY voltage regulator 210, which provides power at a sufficiently high voltage to enable reliable operation of the circuitry in the memory PHY IO 216 and memory circuitry 218. LDO 312 reduces (or otherwise regulates) the voltage supplied from the memory PHY voltage regulator 210 to the voltage level to be used in the logic circuit system 308 and the state memory 310. In some embodiments, LDO 312 includes circuit elements such as decoupling capacitors that reduce the effects of undesirable voltage fluctuations such as transients and noise.

[0053] In some embodiments, LDO 312 supplies power to logic system 308 and state memory 310 only in certain operating states—and system voltage regulator 204 supplies power to logic system 308 and state memory 310 in other operating states. In these embodiments, controller 208 uses switch 212 to control which voltage regulator, either memory PHY voltage regulator 210 or system voltage regulator 204, supplies power to logic system 308 and state memory 310. For example, in some embodiments, controller 208 sets switch 212 such that memory PHY voltage regulator 210 supplies power to logic system 308 and state memory 310 only in full-power operating states—via switch 212 and LDO 312. In these embodiments, controller 208 sets switch 212 such that system voltage regulator 204 supplies power to logic system 308 and state memory 310 in low-power operating states (e.g., low-activity operating states, etc.).

[0054] In some implementations, the LDO 312 is bypassed and may be de-energized when not used for voltage regulation in full-power operation. This is in Figure 3The dashed lines (shown for clarity) from system voltage regulator 204 to logic circuit system 308 and state memory 310, excluding LDO 312, illustrate the general path of power flow during low-power operation. As can be seen from the dashed lines, system voltage regulator 204 supplies power to logic circuit system 308 and state memory 310 more directly than memory PHY voltage regulator 210. Conversely, solid lines show the general path of power flow during full-power operation—from memory PHY voltage regulator 210, through switch 212, to LDO 312, and then to logic circuit system 308 and state memory 310. By bypassing LDO 312 and potentially de-energizing it, these implementations avoid unnecessary power loss in LDO 312 when it is not used to supply power to logic circuit system 308 and state memory 310.

[0055] In some implementations, some or all of the circuitry in the circuitry for controller 208 is physically located close to switch 212 and / or memory PHY core logic 214. For example, circuitry such as control logic 300 and state machine 306 may be located on the same region or area of ​​the integrated circuit chip as switch 212 and / or memory PHY core logic 214. Therefore, in these implementations, controller 208 is able to respond relatively quickly, thus causing transitions between operating states. When combined with the use of a hold operating state, in which the operating state is maintained within the logic circuitry 308, this ability to transition relatively quickly between operating states means that low-power operating states can be used more frequently and for shorter periods. This is true because, given the proximity of the circuitry in controller 208 and the state information retained in the logic circuitry 308, the latency to enter and exit low-power states is lower.

[0056] state machine

[0057] Figure 4 A state diagram illustrating multiple operating states according to some embodiments and the transitions between operating states in a state machine is presented. In some embodiments, the memory PHY core logic 214 operates at a time in a selected operating state. In these embodiments, the controller 208 uses a state machine to transition the memory PHY core logic 214 between operating states based on its associated criteria (such that the memory PHY core logic 214 is in one operating state).

[0058] As in Figure 4As can be seen, the operating states include full power 400, low activity 402, hold 404, and power-off 406 operating states (collectively referred to as "operating states"). In the full power 400 operating state, power is supplied to the memory PHY core logic 214 from the memory PHY voltage regulator 210 at a full power voltage (e.g., 0.6V or another voltage) via switch 212 and LDO 312. The full power voltage is the voltage at which the memory PHY core logic 214 operates normally or normally and does not degrade the performance associated with lower voltage levels. In other words, the full power voltage is high enough for the memory PHY core logic 214 to operate at a specified full speed (which may not be the fastest possible operating speed) and is not hindered by a lack of voltage during operation. In some embodiments, the controller 208 places and holds the memory PHY core logic 214 in the full power 400 operating state (i.e., holds switch 212 accordingly) as long as the rate of memory access activity is above a rate threshold. For example, the rate threshold could be N memory accesses within M milliseconds, where N and M are specified numbers.

[0059] For the low-activity 402 operating state, power is supplied to the memory PHY core logic 214 from the system voltage regulator 204 via switch 212 at a low-activity voltage. The low-activity voltage is below the full-power voltage (e.g., 0.5V or another voltage). The low-activity voltage is sufficient to allow the circuitry in the memory PHY core logic to continue limited operation—but also low enough that the memory PHY core logic experiences a corresponding performance degradation. For example, the memory PHY core logic may operate more slowly at a low-activity voltage than at full-power voltage. In some embodiments, when the rate of memory access activity is below a rate threshold, but at least some kind of memory access activity exists, the controller 208 places and maintains the memory PHY core logic 214 in the low-activity 402 operating state.

[0060] For the hold 404 operating state, power is supplied to the memory PHY core logic 214 from the system voltage regulator 204 via switch 212 at a hold voltage. The hold voltage is lower than a low activity voltage (e.g., 0.4V or another voltage). The hold voltage is low enough that it is insufficient to allow the circuitry in the memory PHY core logic 214 (e.g., logic circuitry 308, etc.) to continue reliable operation, but sufficient to preserve the state information of the circuitry in the memory PHY core logic 214. For example, at the hold voltage, registers, memory elements, etc., in the memory PHY core logic 214 used to store register values, configuration bits / flags, settings, operation values ​​(results, inputs, etc.), and / or other state information can continue to reliably store these values. In some embodiments, when there is no ongoing memory access and the memory PHY core logic 214 is experiencing a short idle period (e.g., an idle period shorter than a time threshold T), the controller 208 places and maintains the memory PHY core logic 214 in the hold 404 operating state.

[0061] In the power-down 406 operating state, no power is supplied to the memory PHY core logic 214 from the system voltage regulator 204. In the power-down operating state, due to the lack of power, the memory PHY core logic 214 is shut down or de-energized and does not perform any operation. Furthermore, unlike the maintenance 404 operating state, the memory PHY core logic 214 does not retain operating state information. Instead, before entering the power-down 406 operating state, the operating state information is copied to the state memory 310, where it is stored until it is used to restore the operating state of the memory PHY core logic 214 when transitioning from the power-down 406 operating state to another operating state. In some embodiments, when there is no ongoing memory access and the memory PHY core logic 214 is experiencing a long idle period (e.g., an idle period longer than a time threshold T), the controller 208 places and maintains the memory PHY core logic 214 in the power-down 406 operating state.

[0062] like Figure 4As indicated by the arrows, in some embodiments, the controller can transition the memory PHY core logic from any operating state to any other operating state. For example, the controller can transition the memory PHY core logic from a full-power 400 operating state to a low-activity 402, hold 404, or power-down 406 operating state, and vice versa. In these embodiments, the controller 208 transitions the memory PHY core logic 214 between states based on the memory access rate and / or the length of the idle period. However, in some embodiments, a specified order of transitions is performed. For example, in some of these embodiments, the transition order is full-power 400, low-activity 402, hold 404, and power-down 406 in the order of full power 400, low activity 402, hold 404, and power-down 406, and vice versa. Generally, in the described embodiments, the controller is capable of transitioning the memory PHY core logic between at least some operating states based on the memory access rate and / or the length of the idle period.

[0063] Although the above describes an embodiment in which the memory PHY core logic 214 is individually powered at various voltages in corresponding operating states, in some embodiments, one or more other functional blocks in the electronic device 100 are powered at the same voltage from the system voltage regulator 204 in some or all operating states. For example, in some embodiments, the system voltage regulator 204 provides power to the display subsystem 106, media processing subsystem 108, etc., at low active voltage, holding voltage, and / or no power (in the power-off 406 operating state). Therefore, in these embodiments, the memory PHY core logic 214 is in the same low-power state as other functional blocks in the power domain supplied by the system voltage regulator 204.

[0064] Despite Figure 4 Many operating states are illustrated, but in some embodiments, different numbers or arrangements of operating states, standards for transitioning to / from operating states, and / or pressure regulators are used. For example, in some embodiments, the memory PHY voltage regulator 210 supplies power to the memory PHY core logic 214 at a correspondingly reduced voltage (not shown) in one or more low-power operating states. Generally, in the embodiments described, any number of operating states can be used, provided that at least some of the operating states are those described herein.

[0065] The process used to set the operational state of the core logic of the physical memory layer (PHY).

[0066] In the embodiment described, the controller (e.g., controller 208) controls the operating state of the memory PHY core logic (e.g., memory PHY core logic 214) and thus controls the voltage that supplies power to the memory PHY core logic. Figure 5A flowchart illustrating the process for setting the operational states in the memory PHY core logic according to some implementation schemes is presented. Note that... Figure 5 The operations shown are presented as general examples of operations performed by some implementations. Operations performed by other implementations include different operations, operations performed in different orders, and / or operations performed by different functional blocks.

[0067] Figure 5 The process begins when the controller determines the power operating state in which the memory PHY core logic will be operated (step 500). For this operation, the controller keeps track of the rate at which memory accesses are performed and / or the length of idle periods in the memory PHY core logic, and uses the rate at which memory accesses are performed and / or the length of those idle periods to determine the operating state in which the memory PHY core logic will be operated. In some embodiments, the controller uses a state machine circuit system (e.g., state machine 306) to determine the operating state in which the memory PHY core logic will be operated. The following is a description of... Figure 6 Describe the specific operation in more detail.

[0068] When the memory PHY core logic is not operating in a low-power state (step 502), the controller sets a switch (e.g., switch 212) to supply power from the memory PHY voltage regulator (e.g., memory PHY voltage regulator 210) to the memory PHY core logic operating in a full-power state (step 504). For this operation, the controller configures the path of power flow to the memory PHY core logic via the switch, such that power originates from the memory PHY voltage regulator, passes through the switch to the local LDO (e.g., LDO 312) within the memory PHY core logic, and is then supplied from the LDO to the circuitry within the memory PHY core logic (e.g., logic circuitry 308, etc.).

[0069] When the memory PHY core logic is to operate in a low-power state (step 502), the controller sets a switch (e.g., switch 212) to supply power from the system voltage regulator (e.g., system voltage regulator 204) to the memory PHY core logic in the low-power operating state (step 506). For this operation, the controller configures the path of power flow to the memory PHY core logic via the switch, such that the power originates from the system voltage regulator and is delivered through the switch to the circuitry within the memory PHY core logic (e.g., logic circuitry 308, etc.). As described above, in some embodiments, the LDO is bypassed and may be de-energized during the low-power operating state.

[0070] Figure 6A flowchart illustrating a process for determining the operational state in which the memory PHY core logic will operate, according to some embodiments, is presented. In some embodiments, Figure 6 The operations described in step 500 can be performed as part of step 500, but this is not required. Note that... Figure 6 The operations shown are presented as general examples of operations performed by some implementations. Operations performed by other implementations include different operations, operations performed in different orders, and / or operations performed by different functional blocks.

[0071] Figure 6 The process begins when the controller (e.g., controller 208) monitors memory access activity in the memory subsystem (memory subsystem 110) (step 600). For this operation, the controller determines the rate at which memory accesses occur in the memory subsystem based on information received from an activity monitor (e.g., activity monitor 302) and / or another functional block. For example, the activity monitor may periodically supply the controller with information indicating the number of memory accesses in the last second, the average percentage of all available time used to perform memory accesses employed during the execution of memory accesses, etc. The controller also monitors the idle state of the core logic (e.g., memory PHY core logic 214) in the memory PHY (step 602). For this operation, the controller determines the length of one or more idle periods in which the memory PHY core logic is idle based on information received from an idle monitor (e.g., idle monitor 304) and / or another functional block. For example, the idle monitor may periodically supply the controller with information indicating the length of a specified idle period, the average length of two or more idle periods, and the average percentage of all available time used to perform operations in the memory PHY core logic employed during the execution of operations.

[0072] When the memory access rate exceeds a rate threshold (step 604), the controller configures the memory PHY core logic to operate at full power (step 606). For this operation, when the memory subsystem is sufficiently busy performing memory accesses, the controller maintains the memory PHY core logic in full power operation, where it is powered at full power by a memory PHY voltage regulator (e.g., memory PHY voltage regulator 210) via a local LDO (e.g., LDO 312). In full power operation, the memory PHY core logic responds normally or normally to memory access requests and is used to perform other operations.

[0073] When the memory access rate is below a rate threshold (step 604), but memory access activity exists (step 608), the controller configures the memory PHY core logic to a low-activity operating state (step 610). For this operation, when the memory subsystem is not busy performing memory accesses but is performing at least some memory accesses, the controller keeps the memory PHY core logic in a low-activity operating state, in which the system voltage regulator (e.g., system voltage regulator 204) supplies power to the memory PHY core logic at a low-activity voltage. In some embodiments, due to the difference between the low-activity voltage and the full-power voltage, the memory PHY core logic operates at a lower speed in the low-activity operating state than in the full-power operating state. Therefore, in the low-activity operating state, the memory PHY core logic responds more slowly to memory access requests and performs other operations, but also saves power.

[0074] When there is no memory access activity (step 608) and the memory PHY core logic is experiencing an idle period shorter than a time threshold (step 612), the controller configures the memory PHY core logic to be in a hold-up operation state (step 614). For this operation, when the memory subsystem is not performing memory accesses and the core logic is experiencing a relatively short idle period, the controller holds the memory PHY core logic in a hold-up operation state, in which power is supplied to the memory PHY core logic at a hold-up voltage. In the hold-up operation state, although the memory PHY core logic cannot reliably perform operations due to the low hold-up voltage, the hold-up voltage is high enough that the operation state information can be maintained in the memory PHY core logic. Maintaining the operation state information stored in the memory PHY core logic (instead of storing the operation state information in state memory) allows for a faster recovery from the hold-up operation state to a higher-power operation state (i.e., low-activity operation state, full-power operation state, etc.).

[0075] When there is no memory access activity (step 608) and the memory PHY core logic is experiencing an idle period longer than a time threshold (step 612), the controller configures the memory PHY core logic to be in a power-down operation state (step 616). For this operation, when the memory subsystem does not perform memory accesses and the core logic experiences a relatively long idle period, the controller powers down the memory PHY core logic, thereby not providing power to the memory PHY core logic. In the power-down operation state, the memory PHY core logic cannot perform operations. In some embodiments, entering the power-down operation state involves saving the operational state information of the memory PHY core logic. For example, the operational state information can be obtained from the memory PHY core logic and stored in a state memory (e.g., state memory 310) and / or another memory (e.g., a memory in memory subsystem 110, etc.).

[0076] In some embodiments, at least one electronic device (e.g., electronic device 100) uses code and / or data stored on a non-transitory computer-readable storage medium to perform some or all of the operations described herein. More specifically, when performing the described operations, the at least one electronic device reads code and / or data from the computer-readable storage medium and executes the code and / or uses the data. The computer-readable storage medium can be any means, medium, or combination thereof that stores code and / or data for use by the electronic device. For example, the computer-readable storage medium can include, but is not limited to, volatile and / or non-volatile memories, including flash memory, random access memory (e.g., eDRAM, RAM, SRAM, DRAM, DDR4 SDRAM, etc.), non-volatile RAM (e.g., phase-change memory, ferroelectric random access memory, spin-torque random access memory, magnetoresistive random access memory, etc.), read-only memory (ROM), and / or magnetic or optical storage media (e.g., disk drives, magnetic tape, CDs, DVDs, etc.).

[0077] In some embodiments, one or more hardware modules perform the operations described herein. For example, a hardware module may include, but is not limited to, one or more central processing units (CPUs) / CPU cores, graphics processing units (GPUs) / GPU cores, application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs), compressors or encoders, computing units, embedded processors, accelerated processing units (APUs), controllers, neural network processors, and / or other functional blocks. When a circuit system (e.g., integrated circuit elements, discrete circuit elements, etc.) in such a hardware module is activated, that circuit system performs some or all of the operations. In some embodiments, the hardware module includes general-purpose circuit systems, such as execution pipelines, computing or processing units, etc., which perform the operations when executing instructions (program code, firmware, etc.). In some embodiments, the hardware module includes special-purpose or dedicated circuit systems that perform the operations, possibly including circuit systems that perform some or all of the operations "in hardware" without executing instructions.

[0078] In some implementations, data structures representing some or all of the functional blocks and circuit elements described herein (e.g., electronic device 100 or a portion thereof) are stored on a non-transitory computer-readable storage medium, including databases or other data structures, which can be read by the electronic device and used directly or indirectly to manufacture hardware including functional blocks and circuit elements. For example, the data structures may be behavioral-level descriptions or register-transfer-level (RTL) descriptions of hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. These descriptions can be read by a synthesis tool that synthesizes them against a synthesis library representing the hardware functionality including the aforementioned functional blocks and circuit elements to generate a netlist including a list of transistors / circuit elements. The netlist can then be placed and routed to generate a dataset describing the geometry to be applied to a mask. The mask can then be used in various semiconductor manufacturing steps to produce one or more semiconductor circuits (e.g., integrated circuits) corresponding to the aforementioned functional blocks and circuit elements. Alternatively, the database on the computer-accessible storage medium may be a netlist (with or without a synthesis library), a dataset (as needed), or Graphical Data System (GDS) II data.

[0079] In this specification, variables or unspecified values ​​(i.e., a general description of a value in the absence of a specific instance of a value) are represented by letters such as N, M, and X. As used herein, although similar letters may be used in different places in this specification, the variables and unspecified values ​​in each case are not necessarily the same; that is, some or all of the general variables and unspecified values ​​may be expected to have different variables and values. In other words, specific instances of N and any other letters used to represent variables and unspecified values ​​in this description are not necessarily related to each other.

[0080] As used herein, the expressions “et cetera” or “etc.” are intended to represent one and / or a situation, that is, an equivalent of “at least one” of the elements in the list associated with “etc.” For example, in the statement “the electronic device performs a first operation, a second operation, etc.”, the electronic device performs at least one of a first operation, a second operation, and other operations. Furthermore, the elements in the list associated with “etc.” are merely examples from a set of examples, and at least some of the examples may not appear in some implementations.

[0081] The foregoing description of embodiments is presented for illustrative and descriptive purposes only. This prior description is not intended to be exhaustive or to limit the embodiments to the disclosed form. Accordingly, many modifications and variations will be apparent to those skilled in the art. Furthermore, the foregoing disclosure is not intended to limit the embodiments. The scope of the embodiments is defined by the appended claims.

Claims

1. An electronic device, the electronic device comprising: A memory function block, which includes multiple memory circuits and a memory physical layer function block, wherein the memory physical layer function block includes core logic that controls the operation of the memory physical layer function block; Memory physical layer voltage regulator; System voltage regulator; A switch having a first input coupled to the output of the memory physical layer voltage regulator, a second input coupled to the output of the system voltage regulator, and an output coupled to the power input of the core logic; as well as A controller, coupled to the switch and configured to: The switch is configured to supply power from the memory physical layer voltage regulator to the core logic in full-power operation. as well as The switch is configured such that power is supplied from the system voltage regulator to the core logic in each of a variety of low-power operating states.

2. The electronic device of claim 1, wherein the plurality of low-power operating states include: In a low-activity operating state, the system voltage regulator supplies power to the core logic at a reduced voltage, wherein the reduced voltage is lower than the full operating voltage of the circuitry in the core logic, but sufficient to allow the circuitry in the core logic to continue limited operation. A holding operation state is maintained in which the system voltage regulator supplies power to the core logic at a holding voltage, wherein the holding voltage is lower than the reduced voltage and insufficient to allow the circuitry in the core logic to reliably continue the limited operation, but sufficient to maintain the state information of the circuitry in the core logic. as well as In the power-off operation state, the system voltage regulator does not provide power to the core logic.

3. The electronic device of claim 2, wherein the controller is further configured to: Determine the memory access activity rate in the memory function block; When the memory access activity rate is higher than the rate threshold, the core logic is configured to be in the full-power operation state. The configuration includes setting the switch to supply power to the core logic from the memory physical layer voltage regulator. When the memory access activity rate is lower than the rate threshold but the memory access activity rate is greater than zero, the core logic is configured to be in the low-activity operation state. The configuration includes setting the switch so that power is supplied to the core logic from the system voltage regulator at the reduced voltage. as well as When the memory access activity rate is zero and therefore the memory function block is not performing memory access, the core logic is configured to be in the low-power operation state or the power-down operation state based on the idle level of the core logic.

4. The electronic device of claim 3, wherein the controller is further configured to: Determine the length of the idle period during which the core logic is idle; When the memory access activity rate is zero and the length of the idle period is shorter than the length of a time threshold, the core logic is configured to be in the hold-up operation state, the configuration including setting the system voltage regulator to supply power to the core logic at the hold-up voltage; and When the memory access activity rate is zero and the length of the idle period is longer than the length of the time threshold, the core logic is configured to be in the power-down operation state, the configuration including setting the system voltage regulator so that no power is supplied to the core logic.

5. The electronic device as claimed in claim 4, wherein: The controller includes a state machine circuit system; and The controller is also configured to: Based on the memory activity rate and / or the length of the idle period, the state machine circuitry is used to determine the transitions between the full-power operation state, the low-activity operation state, the hold operation state, and the power-down operation state.

6. The electronic device of claim 4, wherein: The controller includes one or more operating state change limiting mechanisms; as well as The controller is configured to use the operating state change limiting mechanism to limit the rate at which the controller transitions the operating states of the core logic between the full-power operating state, the low-activity operating state, the hold operating state, and the power-off operating state.

7. The electronic device of claim 2, further comprising: A low-dropout regulator for the core logic, the low-dropout regulator having a first input coupled to the power input of the core logic and an output coupled to the circuitry in the core logic, the low-dropout regulator being configured to provide power to the circuitry in the core logic; The low-dropout regulator is activated in the full-power operation state, allowing the circuitry to receive power from the memory physical layer voltage regulator via the low-dropout regulator; and The low-dropout regulator is disabled or bypassed during the low-activity operating state, so that the circuit system receives power from the system voltage regulator.

8. The electronic device of claim 7, wherein the low-dropout regulator includes circuit elements for reducing noise and transient signals.

9. The electronic device as claimed in claim 1, wherein: The memory physical layer functional block also includes input / output circuit elements; and The memory physical layer voltage regulator provides power to the input / output circuit elements, regardless of the operating state of the core logic.

10. The electronic device of claim 1, wherein the core logic includes one or more of the following: a memory access state machine circuit system, a memory access routing controller circuit system, a memory physical layer clock generation circuit system, and a memory physical layer state information storage circuit system.

11. The electronic device of claim 1, wherein: The electronic device includes one or more external functional blocks, which are separate from the memory functional blocks; as well as The system voltage regulator is configured to provide power to the external functional block, regardless of the operating state of the core logic.

12. A method for supplying power to a functional block in an electronic device, the electronic device comprising: A memory function block, which includes multiple memory circuits and a memory physical layer function block, wherein the memory physical layer function block includes core logic that controls the operation of the memory physical layer function block; Memory physical layer voltage regulator; system voltage regulator; A switch having a first input coupled to the output of the memory physical layer voltage regulator, a second input coupled to the output of the system voltage regulator, and an output coupled to the power input of the core logic; and a controller, the controller being coupled to the switch, the method comprising: The controller sets the switch so that power is supplied from the memory physical layer voltage regulator to the core logic in full-power operation. as well as The controller sets the switch so that, in each of a variety of low-power operating states, power is supplied from the system voltage regulator to the core logic.

13. The method of claim 12, wherein the plurality of low-power operating states include: In a low-activity operating state, the system voltage regulator supplies power to the core logic at a reduced voltage, wherein the reduced voltage is lower than the full operating voltage of the circuitry in the core logic, but sufficient to allow the circuitry in the core logic to continue limited operation. A holding operation state is maintained in which the system voltage regulator supplies power to the core logic at a holding voltage, wherein the holding voltage is lower than the reduced voltage and insufficient to allow the circuitry in the core logic to reliably continue the limited operation, but sufficient to maintain the state information of the circuitry in the core logic. as well as In the power-off operation state, the system voltage regulator does not provide power to the core logic.

14. The method of claim 13, further comprising: The controller determines the memory access activity rate within the memory function block; When the memory access activity rate is higher than the rate threshold, the controller configures the core logic to be in the full-power operation state. The configuration includes setting the switch to supply power to the core logic from the memory physical layer voltage regulator. When the memory access activity rate is lower than the rate threshold but the memory access activity rate is greater than zero, the controller configures the core logic to be in the low-activity operation state. The configuration includes setting the switch so that power is supplied to the core logic from the system voltage regulator at the reduced voltage. as well as When the memory access activity rate is zero and therefore the memory function block is not performing memory access, the controller configures the core logic to be in the hold-up operation state or the power-down operation state based on the idle level of the core logic.

15. The method of claim 14, further comprising: The length of the idle period during which the core logic is idle is determined by the controller; When the memory access activity rate is zero and the length of the idle period is shorter than the length of a time threshold, the controller configures the core logic to be in the hold operation state, the configuration including setting the system voltage regulator to provide power to the core logic at the hold voltage; as well as When the memory access activity rate is zero and the length of the idle period is longer than the length of the time threshold, the controller configures the core logic to be in the power-down operation state, the configuration including setting the system voltage regulator so that no power is supplied to the core logic.

16. The method of claim 15, wherein: The controller includes a state machine circuit system; and The method further includes: The controller uses the state machine circuitry to determine the transitions between the full-power operation state, the low-activity operation state, the hold operation state, and the power-off operation state based on the memory activity rate and / or the length of the idle period.

17. The method of claim 15, further comprising: The controller limits the rate at which the core logic switches between the full-power operation state, the low-activity operation state, the hold operation state, and the power-off operation state.

18. The method of claim 13, wherein: The memory physical layer functional block also includes a low-dropout regulator for the core logic, the low-dropout regulator having a first input coupled to the power input of the core logic and an output coupled to the circuit system in the core logic, the low-dropout regulator being configured to provide power to the circuit system in the core logic; The method further includes: The controller enables the low-dropout regulator in the full-power operation state, so that the circuit system receives power from the memory physical layer voltage regulator through the low-dropout regulator; and The controller disables or bypasses the low-dropout regulator during the low-activity operating state, so that the circuit system receives power from the system voltage regulator.

19. The method of claim 18, wherein the low differential pressure regulator includes circuit elements for reducing noise and transient signals.

20. The method of claim 12, wherein: The memory physical layer functional block also includes input / output circuit elements; and The method further includes: The input / output circuit elements are powered by the memory physical layer voltage regulator, regardless of the operating state of the core logic.

21. The method of claim 12, wherein the core logic includes one or more of the following: a memory access state machine circuit system, a memory access routing controller circuit system, a memory physical layer clock generation circuit system, and a memory physical layer state information storage circuit system.

22. The method of claim 12, wherein: The electronic device includes one or more external functional blocks, which are separate from the memory functional blocks; The method further includes: The system voltage regulator supplies power to the external functional block regardless of the operating state of the core logic.

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