Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display. The display panel comprises a plurality of second pixel circuit groups in the first display area, which comprises a first type of second pixel circuit group far away from the second display area and a second type of second pixel circuit group close to the second display area. The first type of second pixel circuit group is connected with a first type of second light emitting unit group in the second display area and far away from the first display area through a first connection wire, and the second type of second pixel circuit group is connected with a second type of second light emitting unit group in the second display area and close to the first display area through a second connection wire. Since the scheme of the application can provide driving signals for the second type of second light emitting unit group through the second connection wire which is located in a different layer from the first connection wire, the number of the second light emitting unit groups that can be arranged in the second display area can be increased without increasing the first connection wire, and the display effect of the second display area in the display panel is ensured.

Description

[0001] This application claims priority to patent application No. 202011356201.7, filed on November 27, 2020, entitled "Display Substrate and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0003] Organic light-emitting diode (OLED) display panels are widely used due to their advantages such as self-illumination, low driving voltage, and fast response speed. An OLED display panel includes multiple pixel units, each pixel unit comprising a light-emitting unit and pixel circuitry connected to that light-emitting unit.

[0004] In related technologies, to increase the screen-to-body ratio of a display panel, the camera of the display device can be placed in the display area of ​​the display panel. Furthermore, to increase the transmittance of the area where the camera is located, the pixel circuits of each pixel unit in that area are typically placed in a non-camera area. The pixel circuits located in the non-camera area are connected to the light-emitting units located in the camera area via connecting traces, thereby providing driving signals to the light-emitting units located in the camera area.

[0005] However, due to the limited number of connection traces that can be set in the display area, it is difficult to set a large number of light-emitting units in the camera area, resulting in poor display effect in the camera area. Summary of the Invention

[0006] This application provides a display panel and display device that can solve the problem of poor display effect in the camera area in related technologies. The technical solution is as follows:

[0007] On one hand, a display panel is provided, the display panel comprising:

[0008] A substrate having adjacent first and second display areas;

[0009] A plurality of first light-emitting unit groups, wherein the plurality of first light-emitting unit groups are located in the first display area;

[0010] A plurality of first pixel circuit groups are located in the first display area, and each first pixel circuit group is connected to a first light-emitting unit group.

[0011] A plurality of second light-emitting unit groups are located in the second display area. The plurality of second light-emitting unit groups include: at least one first type of second light-emitting unit group and at least one second type of second light-emitting unit group. The at least one second type of second light-emitting unit group is closer to the first display area than the at least one first type of second light-emitting unit group.

[0012] A plurality of second pixel circuit groups are located in the first display area. The plurality of pixel circuit groups include: at least one first type of second pixel circuit group and at least one second type of second pixel circuit group. The at least one second type of second pixel circuit group is closer to the second display area than the at least one first type of second pixel circuit group.

[0013] Multiple dummy electrode pattern groups are located in the first display area. The multiple dummy electrode pattern groups include: at least one first pattern group and at least one second pattern group. The at least one second pattern group is closer to the second display area than the at least one first pattern group.

[0014] Multiple first connection traces are located on different layers from the multiple dummy electrode pattern groups. One end of each first connection trace is connected to a first type of second light-emitting unit group, and the other end is connected to a first type of second pixel circuit group through a first pattern group.

[0015] In addition, there are multiple second connection traces, which are located on different layers from the multiple first connection traces. One end of each second connection trace is connected to a second type of second light-emitting unit group, and the other end is connected to a second type of second pixel circuit group through a second pattern group.

[0016] Optionally, the orthographic projection of the dummy electrode pattern group on the substrate at least partially overlaps with the orthographic projection of at least one second pixel circuit group on the substrate, and the orthographic projection of the dummy electrode pattern group on the substrate does not overlap with the orthographic projection of any of the first light-emitting unit groups on the substrate.

[0017] Optionally, each of the first light-emitting unit groups and each of the second light-emitting unit groups includes a plurality of light-emitting units, wherein the light-emitting unit includes a first electrode, a light-emitting layer and a second electrode sequentially stacked along a direction away from the substrate.

[0018] The dummy electrode pattern group includes multiple dummy electrode patterns. The number of dummy electrode patterns in one dummy electrode pattern group is the same as the number of light-emitting units in one light-emitting unit group, and the dummy electrode patterns are located on the same layer as the first electrode.

[0019] Optionally, the display panel further includes a pixel defining layer located between the first electrode and the light-emitting layer;

[0020] The pixel defining layer has multiple openings, one of which exposes a first electrode of one of the light-emitting units, and the orthographic projections of the multiple openings on the substrate do not overlap with the orthographic projections of any of the dummy electrode patterns on the substrate.

[0021] Optionally, a plurality of dummy electrode patterns in a group of dummy electrode patterns correspond one-to-one with a plurality of first light-emitting units in a group of first light-emitting units, and the shape and area of ​​the dummy electrode pattern are the same as those of the first electrode in the corresponding first light-emitting unit.

[0022] Optionally, a first light-emitting unit group includes: a first light-emitting unit of a first color, two first light-emitting units of a second color, and a first light-emitting unit of a third color;

[0023] A second light-emitting unit group includes: a second light-emitting unit of a first color, two second light-emitting units of a second color, and a second light-emitting unit of a third color.

[0024] Optionally, the distance between the centers of two adjacent first light-emitting units of the first color in the first display area along the row direction is equal to the distance between the centers of two adjacent second light-emitting units of the first color in the second display area along the row direction.

[0025] The distance between the centers of two adjacent first light-emitting units of the second color in the first display area along the row direction is equal to the distance between the centers of two adjacent second light-emitting units of the second color in the second display area along the row direction.

[0026] The distance between the centers of two adjacent first light-emitting units of the third color in the first display area along the row direction is equal to the distance between the centers of two adjacent second light-emitting units of the third color in the second display area along the row direction.

[0027] Optionally, the area of ​​the orthographic projection of the opening of the first light-emitting unit exposing the first color in the first display area onto the substrate is equal to the area of ​​the orthographic projection of the opening of the second light-emitting unit exposing the first color in the second display area onto the substrate, and the area of ​​the orthographic projection of the first electrode of the first light-emitting unit of the first color in the first display area onto the substrate is greater than the area of ​​the orthographic projection of the first electrode of the second light-emitting unit of the first color in the second display area onto the substrate.

[0028] The area of ​​the orthographic projection of the opening of the first light-emitting unit of the second color in the first display area onto the substrate is equal to the area of ​​the orthographic projection of the opening of the second light-emitting unit of the second color in the second display area onto the substrate, and the area of ​​the orthographic projection of the first electrode of the first light-emitting unit of the second color in the first display area onto the substrate is greater than the area of ​​the orthographic projection of the first electrode of the second light-emitting unit of the second color in the second display area onto the substrate.

[0029] The area of ​​the orthographic projection of the opening of the first light-emitting unit of the third color in the first display area onto the substrate is equal to the area of ​​the orthographic projection of the opening of the second light-emitting unit of the third color in the second display area onto the substrate, and the area of ​​the orthographic projection of the first electrode of the first light-emitting unit of the third color in the first display area onto the substrate is greater than the area of ​​the orthographic projection of the first electrode of the second light-emitting unit of the third color in the second display area onto the substrate.

[0030] Optionally, the first electrode of the first light-emitting unit in the first light-emitting unit group includes: a first main pattern and a first connection pattern connected to the first main pattern, at least a portion of the first main pattern is in contact with the light-emitting layer of the first light-emitting unit, and the first connection pattern is connected to the first pixel circuit group.

[0031] The dummy electrode pattern includes: a second main pattern, and a second connection pattern and a third connection pattern respectively connected to the second main pattern. The second main pattern does not contact the light-emitting layer of any of the first light-emitting units, and the second connection pattern is connected to the second pixel circuit group. The third connection pattern is connected to the second light-emitting unit group through a first connection trace or a second connection trace.

[0032] Optionally, the first electrode of the first light-emitting unit further includes a fourth connecting pattern connected to the first main body pattern;

[0033] The orthographic projection of the first main pattern of the first electrode in the first light-emitting unit onto the substrate has the same shape and area as the orthographic projection of the second main pattern of the dummy electrode pattern corresponding to the first light-emitting unit onto the substrate.

[0034] The orthographic projection of the first connection pattern of the first electrode in the first light-emitting unit onto the substrate has the same shape and area as the orthographic projection of the second connection pattern of the dummy electrode pattern corresponding to the first light-emitting unit onto the substrate.

[0035] The orthographic projection of the fourth connection pattern of the first electrode in the first light-emitting unit onto the substrate has the same shape and area as the orthographic projection of the third connection pattern of the dummy electrode pattern corresponding to the first light-emitting unit onto the substrate.

[0036] Optionally, the orthographic projection of the first connection pattern on the substrate does not overlap with the orthographic projection of the plurality of first connection traces on the substrate, and the orthographic projection of the fourth connection pattern on the substrate at least partially overlaps with the orthographic projection of the plurality of first connection traces on the substrate.

[0037] The orthographic projection of the second connection pattern on the substrate does not overlap with the orthographic projection of the plurality of first connection traces on the substrate, and the orthographic projection of the third connection pattern on the substrate at least partially overlaps with the orthographic projection of the plurality of first connection traces on the substrate.

[0038] Optionally, the colors of the first light-emitting units corresponding to the two target dummy electrode patterns in two adjacent first pattern groups along the row direction are the same, and the third connection patterns of the two target dummy electrode patterns are respectively connected to the second light-emitting unit group through a first connection trace;

[0039] In the two target dummy electrode patterns, the line connecting the connecting portion of the third connecting pattern in one target dummy electrode pattern and the connecting portion of the third connecting pattern in the other target dummy electrode pattern intersects the row direction, and the connecting portion of the third connecting pattern is used to connect with the first connecting trace.

[0040] Optionally, the first pixel circuit group includes a plurality of first pixel circuit units, each first pixel circuit unit including at least a first pixel circuit and a second pixel circuit, and at least two pixel circuits in the first pixel circuit unit are configured to be electrically connected to the first electrode of the same first light-emitting unit in the first light-emitting unit group.

[0041] Optionally, the first electrode of the first light-emitting unit includes a first connection pattern comprising: a first main body connection portion extending along the target direction and two first ends located at both ends of the first main body connection portion;

[0042] The two first ends are electrically connected to the first pixel circuit and the second pixel circuit, respectively, and the target direction is approximately parallel to the row direction.

[0043] Optionally, the second pixel circuit group includes a plurality of second pixel circuit units, each second pixel circuit unit including at least a third pixel circuit and a fourth pixel circuit, and at least two pixel circuits in the second pixel circuit unit are configured to be electrically connected to the same dummy electrode pattern.

[0044] Optionally, the second connection pattern included in the dummy electrode pattern includes: a second main body connection portion extending along the target direction and two second ends located at both ends of the second main body connection portion;

[0045] The two second ends are electrically connected to the third pixel circuit and the fourth pixel circuit, respectively, and the target direction is approximately parallel to the row direction.

[0046] Optionally, the plurality of second connection traces are located on the same layer as the dummy electrode pattern group.

[0047] Optionally, the connection at the other end of the plurality of first connection traces is parallel to the edge of the first display area away from the second display area, and the distance between the connection at the other end of the plurality of first connection traces and the edge of the first display area away from the second display area is less than a distance threshold.

[0048] Optionally, the connecting lines at the other ends of the plurality of first connecting lines are generally parallel to the column direction of the edge of the first display area away from the second display area.

[0049] Optionally, the connection at the other end of the plurality of first connection traces is collinear with the edge of the first display area away from the second display area.

[0050] Optionally, the substrate further includes a third display area located on the same side as the first display area and the second display area, and the display panel further includes a plurality of third light-emitting unit groups and a plurality of third pixel circuit groups located in the third display area;

[0051] Each of the third pixel circuit groups is connected to a third light-emitting unit group, and the density of the plurality of third light-emitting unit groups is greater than the density of the plurality of first light-emitting unit groups and greater than the density of the plurality of second light-emitting unit groups.

[0052] Optionally, the substrate includes: two first display areas and one second display area, wherein the second display area is rectangular;

[0053] At least one edge of the rectangle extending along the row direction is connected to the third display area, and the two edges of the rectangle extending along the column direction are connected to the two first display areas respectively.

[0054] Optionally, the first display area is rectangular; the length of any edge of the first display area ranges from 0.1 mm to 20 mm.

[0055] The length of any edge of the second display area ranges from 0.2 mm to 10 mm.

[0056] Optionally, the display panel may further include: multiple data cables;

[0057] At least a portion of the orthographic projection of at least one target data line located in the second display area of ​​the plurality of data lines is located in the region of the second display area close to the first display area.

[0058] On the other hand, a display device is provided, the display device comprising: a power supply component and a display panel as described above;

[0059] The power supply component is used to supply power to the display panel.

[0060] The beneficial effects of the technical solution provided in this application include at least the following:

[0061] This application provides a display panel and a display device. The display panel includes multiple second pixel circuit groups located in a first display area, comprising a first type of second pixel circuit group located away from a second display area, and a second type of second pixel circuit group located closer to the second display area. The first type of second pixel circuit group is connected to a first type of second light-emitting unit group located in the second display area but away from the first display area via a first connection trace. The second type of second pixel circuit group is connected to a second type of second light-emitting unit group located in the second display area but closer to the first display area via a second connection trace. Since the solution provided in this application can also provide driving signals to the second type of second light-emitting unit group via a second connection trace located on a different layer than the first connection trace, the number of second light-emitting unit groups that can be set in the second display area can be increased without increasing the number of first connection traces, thereby ensuring the display effect of the second display area in the display panel. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0064] Figure 2A partial schematic diagram of a display panel provided in an embodiment of this application;

[0065] Figure 3 This is a partial schematic diagram of another display panel provided in an embodiment of this application;

[0066] Figure 4 This is a top view of a substrate provided in an embodiment of this application;

[0067] Figure 5 This is a schematic diagram of a light-emitting unit provided in an embodiment of this application;

[0068] Figure 6 This is a partial schematic diagram of another display panel provided in an embodiment of this application;

[0069] Figure 7 This is a partial schematic diagram of another display panel provided in an embodiment of this application;

[0070] Figure 8 This is a partial schematic diagram of another display panel provided in an embodiment of this application;

[0071] Figure 9 This is a partial schematic diagram of another display panel provided in an embodiment of this application;

[0072] Figure 10 This is a partial schematic diagram of another display panel provided in an embodiment of this application;

[0073] Figure 11 This is a partial schematic diagram of another display panel provided in an embodiment of this application;

[0074] Figure 12 This is a partial schematic diagram of another display panel provided in an embodiment of this application;

[0075] Figure 13 This is a partial schematic diagram of another display panel provided in an embodiment of this application;

[0076] Figure 14 This is a partial schematic diagram of another display panel provided in an embodiment of this application;

[0077] Figure 15 This is an equivalent circuit diagram of a first pixel circuit group or a second pixel circuit group provided in an embodiment of this application;

[0078] Figure 16 This is a partial planar structure diagram of the active semiconductor layer of the pixel circuit in the first display area provided in the embodiments of this application;

[0079] Figure 17 This is a schematic diagram of the first conductive layer within the first display area provided in an embodiment of this application;

[0080] Figure 18 This is a schematic diagram of the active semiconductor layer and the first conductive layer stacked in the first display area provided in the embodiments of this application;

[0081] Figure 19 This is a partial planar structural diagram of the second conductive layer within the first display area provided in an embodiment of this application;

[0082] Figure 20 This is a schematic diagram of the stacking of the active semiconductor layer, the first conductive layer and the second conductive layer in the first display area provided in the embodiments of this application;

[0083] Figure 21 This is a partial planar structural diagram of the source / drain metal layer of the first display area provided in an embodiment of this application;

[0084] Figure 22 This is a schematic diagram of the stacking of the active semiconductor layer, the first conductive layer, the second conductive layer, and the source / drain metal layer in the first display area provided in the embodiments of this application.

[0085] Figure 23 This is a schematic diagram showing the connection relationship between the first light-emitting unit group and the first pixel circuit group in the first display area provided in the embodiments of this application;

[0086] Figure 24 This is a schematic diagram of a first electrode and a dummy electrode pattern provided in an embodiment of this application;

[0087] Figure 25 This is a schematic diagram of the stacking of the first conductive layer, the second conductive layer, the source / drain metal layer, the first connection trace, the first electrode, and the dummy electrode pattern in the first display area provided in the embodiments of this application.

[0088] Figure 26 This is a schematic diagram showing the stacking of the active semiconductor layer, the first conductive layer, the second conductive layer, the source / drain metal layer, the first connection trace, the first electrode, and the dummy electrode pattern in the first display area provided in the embodiments of this application.

[0089] Figure 27 This is a schematic diagram showing the stacking of an active semiconductor layer, a first conductive layer, a second conductive layer, a source / drain metal layer, a first connection trace, a first electrode, a dummy electrode pattern, and a pixel defining layer in the first display area provided in this application embodiment.

[0090] Figure 28 yes Figure 23 The diagram shows the positional relationship between the first light-emitting unit group and the via in the first display area.

[0091] Figure 29 yes Figure 1 Partial plan view of the first and third display areas in the display panel shown;

[0092] Figure 30 This is a schematic diagram of a portion of the pixel circuit structure at the boundary between the third display area and the first display area provided in an embodiment of this application;

[0093] Figure 31 yes Figure 30 A schematic diagram of the membrane structure where the data cable connection part is located is shown;

[0094] Figure 32 yes Figure 30 A schematic diagram of the membrane structure where the data line is located is shown;

[0095] Figure 33 This is a schematic diagram of a portion of the pixel circuit structure at the boundary between the edge areas of the third display area and the second display area provided in an embodiment of this application;

[0096] Figure 34 This is a partial plan view of the third display area and the first display area in a display panel provided in another example of an embodiment of this application;

[0097] Figure 35 This is a schematic diagram of the first electrode of the light-emitting unit group located in the third display area according to an embodiment of this application;

[0098] Figure 36 This is a schematic diagram of the first electrode of the light-emitting unit group located at the non-edge of the first display area, provided in an embodiment of this application;

[0099] Figure 37 This is a schematic diagram of the first electrode of the light-emitting unit group located in the second display area according to an embodiment of this application;

[0100] Figure 38 This is a schematic diagram of the first electrode of each light-emitting unit in the two rows of light-emitting unit groups at the boundary between the first display area and the third display area provided in the embodiments of this application;

[0101] Figure 39 This is a schematic diagram of the first electrode of each light-emitting unit in the two rows of light-emitting unit groups at the boundary between the first display area and the third display area provided in the embodiments of this application;

[0102] Figure 40 yes Figure 3 Cross-sectional view along the direction from A1 to A2;

[0103] Figure 41 yes Figure 7 Cross-sectional view along the direction from B1 to B2;

[0104] Figure 42 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0105] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0106] The terminology used in the embodiments section of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," "third," and similar terms used in the patent application specification and claims of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising" or "including," and similar terms mean that the elements or objects preceding "comprising" or "including" encompass the elements or objects listed following "comprising" or "including" and their equivalents, and do not exclude other elements or objects. The terms "connected," "linked," and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0107] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Figure 2 A partial schematic diagram of a display panel is provided in an embodiment of this application. Figure 3 This is a partial schematic diagram of another display panel provided in an embodiment of this application. (In conjunction with...) Figures 1 to 3 As can be seen, the display panel 10 may include: a substrate 101, a plurality of first light-emitting unit groups 102, a plurality of first pixel circuit groups 103, a plurality of second light-emitting unit groups 104, a plurality of second pixel circuit groups 105, a plurality of dummy electrode pattern groups 106, a plurality of first connection lines 107, and a plurality of second connection lines 108.

[0108] Figure 4 This is a top view of a substrate provided in an embodiment of this application. (Reference) Figure 4 It can be seen that the substrate 101 may have an adjacent first display area 101a and a second display area 101b. Figure 4 The image shows two first display areas 101a and one second display area 101b. The second display area 101b can be an area where a camera is installed.

[0109] Combination Figures 1 to 4Multiple first light-emitting unit groups 102 are located in the first display area 101a, and multiple first pixel circuit groups 103 are located in the first display area 101a. The first pixel circuit group 103 is connected to one of the first light-emitting unit groups 102, and the first pixel circuit group 103 is used to provide a driving signal to the first light-emitting unit group 102 connected thereto, the driving signal being used to drive the first light-emitting unit group 102 to emit light.

[0110] Furthermore, combined Figures 1 to 4 A plurality of second light-emitting unit groups 104 are located in the second display area 101b, and a plurality of second pixel circuit groups 105 are located in the first display area 101a. The plurality of second light-emitting unit groups 104 include at least one first-type second light-emitting unit group 104a and at least one second-type second light-emitting unit group 104b. The at least one second-type second light-emitting unit group 104b is closer to the first display area 101a than the at least one first-type second light-emitting unit group 104a. The plurality of second pixel circuit groups 105 include at least one first-type second pixel circuit group 105a and at least one second-type second pixel circuit group 105b. The at least one second-type second pixel circuit group 105b is closer to the second display area 101b than the at least one first-type second pixel circuit group 105a. A plurality of dummy electrode pattern groups 106 are located in the first display area 101a, and the plurality of dummy electrode pattern groups 106 include at least one first pattern group 106a and at least one second pattern group 106b. The at least one second pattern group 106b is located closer to the second display area 101b than the at least one first pattern group 106a.

[0111] The plurality of first connection traces 107 can be located on different layers from the plurality of dummy electrode pattern groups 106, meaning that the plurality of first connection traces 107 and the plurality of dummy electrode pattern groups 106 need to be fabricated separately using two patterning processes. One end of each first connection trace 107 is connected to a first type of second light-emitting unit group 104a, and the other end is connected to a first type of second pixel circuit group 105a through a first pattern group 106a. That is, the first type of second pixel circuit group 105a located in the first display area 101a can be connected to the first type of second light-emitting unit group 104a located in the second display area 101b through the first connection traces 107 and the first pattern group 106a. This allows each first type of second pixel circuit group 105a to provide a driving signal to the first type of second light-emitting unit group 104a connected to it, and this driving signal is used to drive the first type of second light-emitting unit group 104a to emit light.

[0112] The plurality of second connection traces 108 can be located on different layers from the plurality of first connection traces 107, meaning that the plurality of second connection traces 108 and the plurality of first connection traces 107 need to be fabricated separately using two patterning processes. One end of each second connection trace 108 is connected to a second type of second light-emitting unit group 104b, and the other end is connected to a second type of second pixel circuit group 105b through a second pattern group 106b. That is, the second type of second pixel circuit group 105b located in the first display area 101a can be connected to the second type of second light-emitting unit group 104b located in the second display area 101b through the second connection traces 108 and the second pattern group 106b. This allows each second type of second pixel circuit group 105b to provide a driving signal to the second type of second light-emitting unit group 104b connected to it, and this driving signal is used to drive the second type of second light-emitting unit group 104b to emit light.

[0113] Due to limited space in the display panel 10, the number of first connection traces 107 that can be installed is limited. Therefore, by providing second connection traces 108, the second type of second pixel circuit group 105b near the second display area 101a is connected to the second type of second light-emitting unit group 104b near the first display area 101a in the second display area 101a via the second connection trace 108, thereby enabling the second type of second light-emitting unit group 104b to emit light. That is, even though the number of first connection traces 107 that can be installed in the display panel 10 is limited, the number of second light-emitting unit groups 104b in the second display area 101b can be increased. This not only ensures the display effect of the second display area 101b but also allows for the installation of larger cameras, with lower requirements for the manufacturing precision of the display panel 10.

[0114] Furthermore, since the distance between the second type of second pixel circuit group 105b and the second type of second light-emitting unit group 104b connected by the second connection line 108 is small, it is not only easy to manufacture, but also avoids the second connection line 108 from affecting the first type of second light-emitting unit group 104a of the first display area 101a, thus ensuring the light-emitting effect of the first type of second light-emitting unit group 104a.

[0115] In summary, this application provides a display panel in which a plurality of second pixel circuit groups located in a first display area include a first type of second pixel circuit group away from the second display area and a second type of second pixel circuit group closer to the second display area. The first type of second pixel circuit group is connected to a first type of second light-emitting unit group located in the second display area but away from the first display area via a first connection trace, and the second type of second pixel circuit group is connected to a second type of second light-emitting unit group located in the second display area but closer to the first display area via a second connection trace. Since the solution provided in this application can also provide driving signals to the second type of second light-emitting unit group via a second connection trace located on a different layer than the first connection trace, the number of second light-emitting unit groups that can be set in the second display area can be increased without increasing the number of first connection traces, thereby ensuring the display effect of the second display area in the display panel.

[0116] Optionally, the material of the first connection trace 107 can be a transparent material to avoid affecting the transmittance of the second display area 101b. For example, the material of the first connection trace 107 can be indium tin oxide (ITO). In addition, the extension direction of the plurality of first connection traces 107 can be the row direction X.

[0117] In the embodiments of this application, such as Figure 3 As shown, each row of pixels can be designed with a maximum of 13 first connection lines 107 (the number of first connection lines 107 is limited by the width of the first connection lines 107 and the pixel size). That is, the second display area 101b can be set with a maximum of 26 pixels along the row direction X (each of the two first display areas 101a is set with 13 first connection lines 107, so there can be 26 first connection lines 107 connected to 26 pixels one by one). However, if the second display area 101b needs more pixels along the row direction X, some pixels will lack the corresponding first connection lines 107 to connect to them. Therefore, by connecting the second type of second pixel circuit group 105b of the first display area 101a near the second display area 101b and the second type of second light-emitting unit group 104b of the second display area 101b near the first display area 101a through the set second connection lines 108, the second type of second light-emitting unit group 104b can be made to emit light. The remaining first type second pixel circuit group 105a is connected to the first type second pixel circuit group 105a of the first display area 101a through the first connection trace 107.

[0118] refer to Figure 1 and Figure 4 The second display area 101b may include a central area 101b1 and an edge area 101b2 surrounding the central area 101b1. For example, Figure 4The illustration shows that the second display area 101b is rectangular in shape, and the central area 101b1 of the second display area 101b is circular in shape. The edge area 101b2 is the area located in the rectangle excluding the central area of ​​the circle. Of course, the central area 101b1 and the edge area 101b2 of the second display area 101b can also be other shapes, which can be set according to the actual product requirements. This application embodiment does not limit this.

[0119] Optionally, the central area 101b can serve as an under-display camera area. A second light-emitting unit group 104 is disposed in the central area 101b1, and a second pixel circuit group 105 driving the second light-emitting unit group 104 to emit light is disposed in the first display area 101a. This allows the central area 101b1 to have high light transmittance for camera functionality, while also enabling it to emit light through connection with pixel circuit groups in other areas (the first display area 101a), without affecting the screen's display function.

[0120] In the embodiments of this application, reference is made to Figure 1 The orthographic projection of each dummy electrode pattern group 106 onto the substrate 101 can at least partially overlap with the orthographic projection of at least one second pixel circuit group 105 onto the substrate 101. Figure 1 The overlapping second pixel circuit group 105 and the dummy electrode pattern group 106 are represented by the same small square, and are labeled as 105 / 106. Optionally, the orthographic projection of each dummy electrode pattern group 106 on the substrate 101 may at least partially overlap with the orthographic projection of a second pixel circuit group 105 on the substrate 101.

[0121] Furthermore, the orthographic projection of each dummy electrode pattern group 106 onto the substrate 101 does not overlap with that of any first light-emitting unit group 102. This non-overlapping of the dummy electrode pattern group 106 with the first light-emitting unit group 102 avoids any impact on the first light-emitting unit 1021 within the first light-emitting unit group 102, thus ensuring the light-emitting effect of the first light-emitting unit 1021.

[0122] refer to Figure 2 and Figure 3 Each first light-emitting unit group 102 and each second light-emitting unit group 104 may include multiple light-emitting units. For example, the first light-emitting unit group 102 includes multiple first light-emitting units 1021, and the second light-emitting unit group 104 includes multiple second light-emitting units 1041. Figure 5 This is a schematic diagram of the structure of a light-emitting unit provided in an embodiment of this application. (Reference) Figure 5As can be seen, the light-emitting unit may include a first electrode a1, a light-emitting layer a2, and a second electrode a3, which are sequentially stacked along a direction away from the substrate 101. The first electrode a1 can be an anode, and the second electrode a3 can be a cathode.

[0123] Furthermore, refer to Figure 6 Each dummy electrode pattern group 106 may include multiple dummy electrode patterns 1061. The number of multiple dummy electrode patterns 1061 included in a dummy electrode pattern group 106 is the same as the number of multiple light-emitting units included in a light-emitting unit group (first light-emitting unit group 102 or second light-emitting unit group 104).

[0124] For example, each dummy electrode pattern group 106 includes four dummy electrode patterns 1061, and each light-emitting unit group includes four light-emitting units.

[0125] Optionally, the dummy electrode pattern 1061 in the dummy electrode pattern group 106 can be located on the same layer as the first electrode a1 in the light-emitting unit, and the second connection trace 108 can also be located on the same layer as the first electrode a1. That is, multiple second connection traces 108 can be located on the same layer as multiple dummy electrode pattern groups 106. Specifically, multiple second connection traces 108 located on the same layer as multiple dummy electrode pattern groups 106 can mean that multiple second connection traces 108 are located on the same layer as the dummy electrode pattern 1061 in the multiple dummy electrode pattern groups 106. The dummy electrode pattern 1061 can be a dummy anode pattern, and the second connection trace 108 can be an anode trace.

[0126] Alternatively, the dummy electrode pattern 1061 in the dummy electrode pattern group 106 can be located on the same layer as the first electrode a1 in the light-emitting unit, and the plurality of second connection traces 108 can be located on different layers from the plurality of dummy electrode pattern groups 106. That is, the plurality of second connection traces 108 may not be located on the same layer as the first electrode a1. Optionally, the plurality of second connection traces 107 can be located on other metal layers, for example, the plurality of second connection traces 107 can be located on the second source-drain layer. An insulating layer may be provided between the second source-drain metal layer and the plurality of second connection traces, and the second connection traces located on the second source-drain metal layer are connected to the dummy electrode pattern 1061 through vias in the insulating layer. The embodiments of this application do not limit the placement of the dummy electrode pattern 1061.

[0127] In addition, it should be noted that the dummy electrode pattern group 106 does not only represent dummy, but can also play a role in signal transmission.

[0128] refer to Figure 5It can be seen that the light-emitting unit may further include a pixel defining layer a4 located between the first electrode a1 and the light-emitting layer a2. The pixel defining layer a4 may have multiple openings a41, each opening a41 being used to expose the first electrode a1 of a light-emitting unit. Furthermore, the orthographic projection of the multiple openings a41 on the substrate 101 does not overlap with the orthographic projection of any dummy electrode pattern 1061 on the substrate 101.

[0129] By exposing the first electrode a1 of the light-emitting unit through the opening a41 of the pixel defining layer a4, the first electrode a1 of the light-emitting unit can be made to contact the light-emitting layer a2 to achieve light emission. Since the orthographic projection of the plurality of openings a41 on the substrate 101 does not overlap with the orthographic projection of any dummy electrode pattern 1061 on the substrate 101, no light is emitted at the dummy electrode pattern 1061.

[0130] It should be noted that, for ease of illustration, the top view provided in the embodiments of this application does not show the light-emitting layer a2 and the cathode layer a3. Only the opening a41 of the pixel defining layer a4 is used to distinguish the first electrode a1 and the dummy electrode pattern 1061. Among them, the pattern in the area with the opening a41 of the pixel defining layer a4 is the first electrode a1, and the pattern in the area without the opening a41 of the pixel defining layer a4 is the dummy electrode pattern 1061.

[0131] In this embodiment of the application, a plurality of dummy electrode patterns 1061 in the dummy electrode pattern group 106 correspond one-to-one with a plurality of first light-emitting units 1021 in a first light-emitting unit group 102, and the dummy electrode pattern 1061 and the first electrode a1 in the corresponding first light-emitting unit 1021 have the same shape and area.

[0132] Since the dummy electrode pattern 1061 has the same shape and area as the first electrode a1 in the corresponding first light-emitting unit 1021, the overlapping area of ​​the first electrode a1 and the first connecting line 107 in the first display area 101a can be the same as the overlapping area of ​​the dummy electrode pattern 1061 and the first connecting line 107. This makes the overlapping capacitance of the first electrode a1 in the first display area 101a and the dummy electrode pattern 1061 and the first connecting line 107 consistent, thus ensuring the display effect of the display panel 10.

[0133] Of course, the shape and area of ​​the dummy electrode pattern 1061 and the first electrode a1 in the corresponding first light-emitting unit 1021 can also be different. This application embodiment does not limit this. It is only necessary to make the overlapping area of ​​the first electrode a1 and the first connecting line 107 of the first display area 101a the same as the overlapping area of ​​the dummy electrode pattern 1061 and the first connecting line 107.

[0134] Optional, see reference Figure 7Each light-emitting unit group (e.g., the first light-emitting unit group 102 or the second light-emitting unit group 104) may include: at least one light-emitting unit of a first color, at least one light-emitting unit of a second color, and at least one light-emitting unit of a third color. The first, second, and third colors may be three primary colors. For example, the first color may be red (R), the second color may be green (G), and the third color may be blue (B).

[0135] Example, reference Figure 7 Each first light-emitting unit group 102 includes: a first light-emitting unit b1 of a first color, two first light-emitting units (b21 and b22) of a second color, and a first light-emitting unit b3 of a third color. The two first light-emitting units (b21 and b22) of the second color can be collectively referred to as the pair of first light-emitting units of the second color b2.

[0136] Furthermore, refer to Figure 2 Each second light-emitting unit group 104 includes: a second light-emitting unit b1 of a first color, two second light-emitting units (b21 and b22) of a second color, and a second light-emitting unit b3 of a third color. Among them, the two second light-emitting units (b21 and b22) of the second color can be collectively referred to as the second light-emitting unit pair b2 of the second color.

[0137] In this embodiment of the application, each dummy electrode pattern 1061 in each dummy electrode pattern group 106 also corresponds one-to-one with a plurality of second light-emitting units 1041 in a second light-emitting unit group 104, and the first light-emitting unit 1021 and the corresponding second light-emitting unit 1041 of each dummy electrode pattern 1061 have the same color.

[0138] Optionally, the distance between the centers of two adjacent first-color light-emitting units 1041 of the first color in the first display area 101a along the row direction X is equal to the distance between the centers of two adjacent second-color light-emitting units 1041 of the first color in the second display area 101b along the row direction X. The distance between the centers of two adjacent second-color first-light-emitting units 1021 of the first display area 101a along the row direction X is equal to the distance between the centers of two adjacent second-color second-light-emitting units 1041 of the second display area 101b along the row direction X. The distance between the centers of two adjacent third-color first-light-emitting units 1021 of the first display area 101a along the row direction X is equal to the distance between the centers of two adjacent third-color second-light-emitting units 1041 of the second display area 101b along the row direction X.

[0139] That is, the resolution of the portion of the display panel 10 located in the first display area 101a can be equal to the resolution of the portion located in the second display area 101b.

[0140] Optionally, the area of ​​the orthographic projection of the opening of the first light-emitting unit 1021 of the first color exposed in the first display area 101a onto the substrate 101 is equal to the area of ​​the orthographic projection of the opening of the second light-emitting unit 1041 of the first color exposed in the second display area 101b onto the substrate 101. This ensures that the area of ​​the light-emitting region of the first light-emitting unit 1021 of the first color in the first display area 101a is equal to the area of ​​the light-emitting region of the second light-emitting unit 1041 of the first color in the second display area 101b, guaranteeing the uniformity of the light-emitting effect of the first color light-emitting units in the first display area 101a and the second display area 101b.

[0141] The area of ​​the orthographic projection of the opening of the first light-emitting unit 1021 of the second color exposed in the first display area 101a onto the substrate 101 is equal to the area of ​​the orthographic projection of the opening of the second light-emitting unit 1041 of the second color exposed in the second display area 101b onto the substrate 101. This ensures that the area of ​​the light-emitting region of the first light-emitting unit 1021 of the second color in the first display area 101a is equal to the area of ​​the light-emitting region of the second light-emitting unit 1041 of the second color in the second display area 101b, guaranteeing the uniformity of the light-emitting effect of the second-color light-emitting units in both the first and second display areas 101a and 101b.

[0142] The area of ​​the orthographic projection of the opening of the first light-emitting unit 1021 exposing the third color in the first display area 101a onto the substrate 101 is equal to the area of ​​the orthographic projection of the opening of the second light-emitting unit 1041 exposing the third color in the second display area 101b onto the substrate 101. This ensures that the area of ​​the light-emitting region of the first light-emitting unit 1021 of the third color in the first display area 101a is equal to the area of ​​the light-emitting region of the second light-emitting unit 1041 of the third color in the second display area 101b, guaranteeing the uniformity of the light-emitting effect of the third-color light-emitting units in both the first and second display areas 101a and 101b.

[0143] Furthermore, in this embodiment, the area of ​​the orthographic projection of the first electrode a1 of the first light-emitting unit 1021 of the first color in the first display area 101a onto the substrate 101 is larger than the area of ​​the orthographic projection of the first electrode a1 of the second light-emitting unit 1041 of the first color in the second display area 101b onto the substrate 101. Similarly, the area of ​​the orthographic projection of the first electrode a1 of the first light-emitting unit 1021 of the second color in the first display area 101a onto the substrate 101 is larger than the area of ​​the orthographic projection of the first electrode a1 of the second light-emitting unit 1041 of the second color in the second display area 101b onto the substrate 101. Finally, the area of ​​the orthographic projection of the first electrode a1 of the first light-emitting unit 1021 of the third color in the first display area 101a onto the substrate 101 is larger than the area of ​​the orthographic projection of the first electrode a1 of the second light-emitting unit 1041 of the third color in the second display area 101b onto the substrate 101.

[0144] Figure 8 This is a partial schematic diagram of another display panel provided in an embodiment of this application. (See reference) Figure 8 The second pattern group in the plurality of dummy electrode pattern groups 106 includes a first dummy electrode pattern 1061a, a second dummy electrode pattern 1061b, a third dummy electrode pattern 1061c, and a fourth dummy electrode pattern 1061d. The second type of second light-emitting unit group in the plurality of second light-emitting unit groups 104 includes a first second light-emitting unit 1041a, a second second light-emitting unit 1041b, a third second light-emitting unit 1041c, and a fourth second light-emitting unit 1041d. Specifically, the first dummy electrode pattern 1061a corresponds to the first second light-emitting unit 1041a, the second dummy electrode pattern 1061b corresponds to the second second light-emitting unit 1041b, the third dummy electrode pattern 1061c corresponds to the third second light-emitting unit 1041c, and the fourth dummy electrode pattern 1061d corresponds to the fourth second light-emitting unit 1041d.

[0145] refer to Figure 8The first dummy electrode pattern 1061a is connected to the second second light-emitting unit 1041b via a second second connection trace 108b. The second dummy electrode pattern 1061b is connected to the first second light-emitting unit 1041a via a first second connection trace 108a. The third dummy electrode pattern 1061c is connected to the fourth second light-emitting unit 1041d via a fourth second connection trace 108d. The fourth dummy electrode pattern 1061d is connected to the third second light-emitting unit 1041 via a third second connection trace 108c. That is, each dummy electrode pattern 1061 in the second pattern group is not connected to the corresponding second light-emitting unit 1041 in the second type of second light-emitting unit group 104. Of course, the above-mentioned corresponding connection method is only an optional case, and other corresponding connection methods can also be used, such as each dummy electrode pattern 1061 in the second pattern group being connected to the corresponding second light-emitting unit 1041 in the second type of second light-emitting unit group 104. This application embodiment does not limit this.

[0146] Figure 9 This is a partial schematic diagram of a display panel provided in an embodiment of this application. (Reference) Figure 9 The first electrode a1 of the first light-emitting unit 1021 in the first light-emitting unit group 102 includes: a first main pattern 1021-1, and a first connecting pattern 1021-2 connected to the first main pattern 1021-1. The area where the first main pattern 1021-1 is located has an opening a41 of the pixel defining layer a4, so at least a portion of the first main pattern 1021-1 is in contact with the light-emitting layer a2 of the first light-emitting unit 1021, and the first connecting pattern 1021-2 can be connected to the first pixel circuit group 103.

[0147] Furthermore, refer to Figure 9 The dummy electrode pattern 1061 may include: a second main pattern 1061-1, and a second connecting pattern 1061-2 and a third connecting pattern 1061-3 respectively connected to the second main pattern 1061-1. The area where the second main pattern 1061-1 is located does not have an opening a41 of the pixel defining layer a4, so the second main pattern 1061-1 may not be in contact with the light-emitting layer a2 of any first light-emitting unit 1021. The second connecting pattern 1061-2 is connected to the second pixel circuit group 105, and the third connecting pattern 1061-3 is connected to the second light-emitting unit group 104 through the first connecting trace 107 or the second connecting trace 108.

[0148] Wherein, if a certain dummy electrode pattern 1061 is a dummy electrode pattern 1061 in the first pattern group 106a, then the third connection pattern 1061-3 of the dummy electrode pattern 1061 can be connected to the first type of second light-emitting unit group 104a through the first connection trace 107. Wherein, if a certain dummy electrode pattern 1061 is a dummy electrode pattern 1061 in the second pattern group 106b, then the third connection pattern 1061-3 of the dummy electrode pattern 1061 can be connected to the second type of second light-emitting unit group 104b through the second connection trace 108.

[0149] refer to Figure 9 The first electrode a1 of the first light-emitting unit 1021 may also include a fourth connecting pattern 1021-3 connected to the first main pattern 1021-1. Specifically, the first main pattern 1021-1 of the first electrode a1 may correspond to the second main pattern 1061-1 of the dummy electrode pattern 1061, the first connecting pattern 1021-2 of the first electrode a1 may correspond to the second connecting pattern 1061-2 of the dummy electrode pattern 1061, and the fourth connecting pattern 1021-3 of the first electrode a1 may correspond to the third connecting pattern 1061-3 of the dummy electrode pattern 1061. Optionally, the two corresponding patterns have the same shape and area, and the two corresponding patterns have the same overlap area with the first connecting trace 107.

[0150] That is, the orthographic projection of the first main pattern 1021-1 of the first electrode a1 in the first light-emitting unit 1021 onto the substrate 101 has the same shape and area as the orthographic projection of the second main pattern 1061-1 of the dummy electrode pattern 1061 corresponding to the first light-emitting unit 1021 onto the substrate 101. The orthographic projection of the first connecting pattern 1021-2 of the first electrode a1 in the first light-emitting unit 1021 onto the substrate 101 has the same shape and area as the orthographic projection of the second connecting pattern 1061-2 of the dummy electrode pattern 1061 corresponding to the first light-emitting unit 1021 onto the substrate 101. The orthographic projection of the fourth connecting pattern 1021-3 of the first electrode a1 in the first light-emitting unit 1021 onto the substrate 101 has the same shape and area as the orthographic projection of the third connecting pattern 1061-3 of the dummy electrode pattern 1061 corresponding to the first light-emitting unit 1021 onto the substrate 101.

[0151] In this embodiment, since the dummy electrode pattern 1061 corresponding to the first light-emitting unit 1021 includes a third connection pattern 1061-3 for connecting the first connection trace 107 or the second connection trace 108, in order to make the first electrode a1 have the same shape and area as the dummy electrode pattern 1061, the first electrode a1 may also include a fourth connection pattern 1021-3 with the same shape and area as the third connection pattern 1061-3. The fourth connection pattern 1021-3 does not need to be connected to the first connection trace 107 or the second connection trace 108.

[0152] In the embodiments of this application, combined with Figure 7 and Figure 9 The orthographic projection of the first connection pattern 1021-2 on the substrate 101 does not overlap with the orthographic projections of the plurality of first connection traces 107 on the substrate 101. Therefore, the connection point between the first connection pattern 1021-2 of the first electrode a1 and the first pixel circuit group 103 is not affected by the first connection traces 107, ensuring that the first light-emitting unit 1021 in the first light-emitting unit group 102 connected to the first pixel circuit group 103 emits light normally. Furthermore, the orthographic projection of the fourth connection pattern 1021-3 on the substrate 101 at least partially overlaps with the orthographic projections of the plurality of first connection traces 107 on the substrate 101.

[0153] Combination Figure 7 and Figure 9 The orthographic projection of the second connection pattern 1061-2 on the substrate 101 does not overlap with the orthographic projection of the plurality of first connection traces 107 on the substrate 101. Therefore, the connection point between the dummy electrode pattern 1061 and the second pixel circuit group 105 is not affected by the second connection trace 108, ensuring that the second light-emitting unit in the second light-emitting unit group 104 connected to the second pixel circuit group 105 emits light normally.

[0154] Furthermore, combined Figure 7 and Figure 9 The orthographic projection of the third connection pattern 1061-3 of the dummy electrode pattern 1061 onto the substrate 101 at least partially overlaps with the orthographic projection of the plurality of first connection traces 107 onto the substrate 101.

[0155] For the dummy electrode pattern 1061 in the first pattern group 106a, since the third connection pattern 1061-3 of the dummy electrode pattern 1061 needs to be connected to the first connection trace 107, the orthographic projection of the third connection pattern 1061-3 on the substrate 101 must at least partially overlap with the orthographic projection of the multiple first connection traces 107 on the substrate 101.

[0156] Normally, to ensure the uniformity of the arrangement of the dummy electrode pattern groups 106 in the first display area 101a, each second pattern group 106b can be arranged along the row direction X with a portion of the first pattern group 106a. For the dummy electrode pattern 1061 in the second pattern group 106b, the overlapping area of ​​the orthographic projection of the dummy electrode pattern 1061 in the second pattern group 106b onto the substrate 101 and the orthographic projection of the plurality of first connection traces 107 onto the substrate 101 can be the same as the overlapping area of ​​the orthographic projection of the dummy electrode pattern 1061 in the first pattern group 106a onto the substrate 101 and the orthographic projection of the plurality of first connection traces 107 onto the substrate 101.

[0157] That is, when the orthographic projection of the third connection pattern 1061-3 of the dummy electrode pattern 1061 in the first pattern group 106a onto the substrate 101 and the orthographic projection of the plurality of first connection lines 107 onto the substrate 101 overlaps at least partially, the orthographic projection of the third connection pattern 1061-3 of the dummy electrode pattern 1061 in the second pattern group 106b onto the substrate 101 and the orthographic projection of the plurality of first connection lines 107 onto the substrate 101 overlaps at least partially.

[0158] Figure 10 This is a partial schematic diagram of another display panel provided in an embodiment of this application. (See reference) Figure 10 The display panel 10 includes two adjacent first pattern groups 106a along the row direction X. Each of the two first pattern groups 106a includes multiple dummy electrode patterns 1061, and a target dummy electrode pattern c1 included in the first first pattern group 106a corresponds to another target dummy electrode pattern c2 included in the second first pattern group 106a. The first light-emitting units 1021 corresponding to the two target dummy electrode patterns (c1 and c2) have the same color. For example, Figure 10 Taking the example where the first light-emitting unit 1021 corresponding to the two target dummy electrode patterns (c1 and c2) is red, the example is that both of them are red.

[0159] refer to Figure 10 In the two target dummy electrode patterns (c1 and c2), the line connecting the connection portion d of the third connection pattern 1061-3 in one target dummy electrode pattern c1 and the connection portion d of the third connection pattern 1061-3 in the other target dummy electrode pattern c2 intersects with the row direction X. The connection portion d of the third connection pattern 1061-3 is used to connect with the first connection trace 107.

[0160] It should be noted that, since the two target dummy electrode patterns (c1 and c2) need to be connected to different first connection lines 107, and the first connection lines 107 usually extend along the row direction X, the connection part d used to connect the first connection lines 107 in the third connection pattern 1061-3 of the two target dummy electrode patterns c1 has a gap in the column direction, that is, the line connecting the two connection parts d can intersect with the row direction X.

[0161] Figure 11 This is a partial schematic diagram of another display panel provided in an embodiment of this application. (See reference) Figure 11 , Figure 11 Taking the example where the first light-emitting unit 1021 corresponding to the two target dummy electrode patterns (c1 and c2) is green, the example is given. Figure 12 This is a partial schematic diagram of another display panel provided in an embodiment of this application. (See reference) Figure 12 , Figure 12 Taking the example where the first light-emitting unit 1021 corresponding to the two target dummy electrode patterns (c1 and c2) is blue, both of them are examples.

[0162] refer to Figure 1 and Figure 4 It can be seen that the substrate 101 may also include a third display area 101c and a peripheral area 101d located on the same side as the first display area 101a and the second display area 101b.

[0163] Optional, see reference Figure 4 The substrate 101 includes two first display areas 101a. The first display areas 101a and the second display area 101b are both rectangular in shape. The two first display areas 101a are located on both sides of the second display area 101b, and the two first display areas 101a and the second display area 101b are arranged along the row direction X.

[0164] For example, the first display area 101a and the second display area 101b are located at the edges of the display area. The first display area 101a, the second display area 101b, and the third display area 101c are collectively referred to as the display area. The edges of the first display area 101a and the second display area 101b away from the third display area 101c are connected to the peripheral area 101d. One edge of the second display area 101b (which is rectangular in shape) extending along the row direction X is connected to the third display area 101c, and the other edge is connected to the fourth display area 101d. The two edges of the second display area 101b extending along the column direction Y are connected to the two first display areas 101a respectively.

[0165] Optionally, the length of any edge of the first display area 101a ranges from 0.1 mm to 20 mm. The length of any edge of the second display area 101b ranges from 0.2 mm to 10 mm. Furthermore, the shape and size of the two first display areas 101a included in the substrate 101 may be the same or different, and this embodiment does not limit this.

[0166] refer to Figure 1 It can be seen that the display panel 10 may further include: a plurality of third light-emitting unit groups 109 and a plurality of third pixel circuit groups 110 located in the third display area 101c. Each third pixel circuit group 110 is connected to a third light-emitting unit group 109 and provides a driving signal to the third light-emitting unit group 109 to drive the third light-emitting unit group 109 to emit light.

[0167] Optionally, the density of the plurality of third light-emitting unit groups 109 is greater than the density of the plurality of first light-emitting unit groups 102, and greater than the density of the plurality of second light-emitting unit groups 104. If the density (i.e., pixel density) of the second light-emitting unit groups 104 in the under-display camera area (the central area 101b1 of the second display area 101b) is lower than the density of the third light-emitting unit groups 109 in the normal display area (the third display area 101c), then the camera can be positioned below a low-pixel-density area that allows more light to pass through. The phrase "the density of the plurality of third light-emitting unit groups 109 is greater than the density of the plurality of first light-emitting unit groups 102, and greater than the density of the plurality of second light-emitting unit groups 104" means that, for the same area, the number of third light-emitting unit groups is greater than the number of second light-emitting unit groups, and greater than the number of first light-emitting unit groups.

[0168] In this embodiment, the third display area 101c is the main display area with a high pixel density (pixels per inch, PPI), meaning that the third display area 101c has a high density of third light-emitting unit groups 109 for display. Each third light-emitting unit group 109 corresponds to a third pixel circuit group 110, and each third light-emitting unit group 109 is driven to emit light by a corresponding third pixel circuit group 110. The second display area 101b allows light incident from the display side of the display panel to pass through the display panel and reach the back side of the display panel, thereby enabling the normal operation of components such as sensors located on the back side of the display panel. This embodiment is not limited to this; for example, the second display area 101b may also allow light emitted from the back side of the display panel to pass through the display panel and reach the display side of the display panel. The first display area 101a and the second display area 101b also include multiple light-emitting unit groups for display.

[0169] However, since the pixel circuit group that drives the light-emitting unit group to emit light is usually opaque, in order to improve the light transmittance of the central area 101b1 of the second display area 101b, the light-emitting unit group of the second display area 101b can be physically separated from the pixel circuit group that drives the light-emitting unit group. For example, the light-emitting unit group in the second display area 101b (e.g., Figure 1 The second pixel circuit group 105, connected to the second light-emitting unit group 104 (shown in the box within the second display area 101b), can be disposed in the first display area 101a. That is, the second pixel circuit group 105 will occupy a portion of the space in the first display area 101a. Furthermore, the remaining space in the first display area 101a is used to house the first light-emitting unit group 102 and the first pixel circuit group 103 of the first display area 101a. For example… Figure 1 In the first display area 101a, each point filled with a square represents a pixel (a pixel includes a first light-emitting unit group 102 and a first pixel circuit group 103). At this time, the pixels in the first display area 101a and the second pixel circuit group 105 connected to the second light-emitting unit group 104 in the second display area 101b are arranged in an array in the first display area 101a. Therefore, the resolution of the first display area 101a and the second display area 101b is lower than the resolution of the third display area 101c; that is, the pixel density of the third display area 101c is greater than the pixel density of the first display area 101a and greater than the pixel density of the second display area 101b.

[0170] Figure 13 This is a partial schematic diagram of another display panel provided in an embodiment of this application. (See reference) Figure 13 It can be seen that the connection e at the other end of the multiple first connection lines 107 can be parallel to the edge of the first display area 101a away from the second display area 101b, and the distance between the connection e at the other end of the multiple first connection lines 107 and the edge of the first display area 101 away from the second display area 101b can be less than the distance threshold.

[0171] The other end of the first connection trace 107 can be located away from one end of the second display area 101b. By designing the distance between the connection line e at the other end of the multiple first connection traces 107 and the edge of the first display area 101a away from the second display area 101b to be small, the first connection traces 107 can be present everywhere in the first display area 101a. This ensures that the overlapping capacitance is consistent throughout the first display area 101a, guaranteeing the uniformity of the display effect of the first display area 101a.

[0172] Optionally, the connecting line e at the other end of the plurality of first connecting lines 107 and the edge of the first display area 101a away from the second display area 101b can be approximately parallel to the column direction Y. The connecting line e at the other end of the plurality of first connecting lines 107 can be collinear with the edge of the first display area 101a away from the second display area 101b.

[0173] In this embodiment, since the number of first light-emitting units 1021 capable of emitting light in the first display area 101a is relatively small, while the number of third light-emitting units 1091 capable of emitting light in the third display area 101c is relatively large, the display brightness of the first display area 101a may be lower than that of the third display area 101c. Therefore, in order to improve the display brightness of the first display area 101a, each first light-emitting unit 1021 can be driven by at least two pixel circuits, thereby improving the brightness of the first light-emitting unit 1021 and ensuring the consistency of the display effect between the first display area 101a and the third display area 101c.

[0174] For example, the first pixel circuit group 103 includes a plurality of first pixel circuit units, each first pixel circuit unit including at least: a first pixel circuit and a second pixel circuit, and at least two pixel circuits in the first pixel circuit unit are configured to be electrically connected to the first electrode a1 of the same first light-emitting unit 1021 in the first light-emitting unit group 102.

[0175] refer to Figure 14 The first electrode a1 of the first light-emitting unit 1021 includes a first connection pattern 1021-2, which may include a first main body connection portion 1021-21 extending along a target direction and two first end portions 1021-22 located at both ends of the first main body connection portion 1021-21. The target direction may be approximately parallel to the row direction X, and the two first end portions 1021-22 may be connected to a first pixel circuit and a second pixel circuit, respectively.

[0176] Optionally, since the extension direction of the plurality of first connection traces 107 is the row direction X, the extension direction (target direction) of the first main body connection portion 1021-21 in the first connection pattern 1021-2 is usually made to be approximately parallel to the row direction X, so as to ensure that the orthographic projection of the first connection pattern 1021-2 on the substrate 101 does not overlap with the orthographic projection of the plurality of first connection traces 107 on the substrate 101.

[0177] In this embodiment, to ensure the transmittance of the second display area 101b, the number of second light-emitting units in the second display area 101b is typically small. This may result in the display brightness of the second display area 101b being lower than that of the third display area 101c. Therefore, to improve the display brightness of the second display area 101b, each second light-emitting unit can be driven by at least two pixel circuits, thereby increasing the brightness of the second light-emitting unit and ensuring the display effect of the second display area 101b.

[0178] For example, the second pixel circuit group 105 includes a plurality of second pixel circuit units, each second pixel circuit unit including at least a third pixel circuit and a fourth pixel circuit, and at least two pixel circuits in the second pixel circuit unit are configured to be connected to the same dummy electrode pattern 1061. Each dummy electrode pattern 1061 is connected to the first electrode a1 of a second light-emitting unit, thereby realizing that two pixel circuits are connected to the first electrode a1 of the same second light-emitting unit.

[0179] refer to Figure 14 The second connection pattern 1061-2 of the first electrode a1 of the second light-emitting unit may include: a second main body connection portion 1061-21 extending along the target direction and two second end portions 1061-22 located at both ends of the second main body connection portion 1061-21. The target direction may be approximately parallel to the row direction X, and the two second end portions 1061-22 may be connected to the third pixel circuit and the fourth pixel circuit, respectively.

[0180] Optionally, since the extension direction of the plurality of first connection traces 107 is the row direction X, the extension direction (target direction) of the second main body connection portion 1061-21 in the second connection pattern 1061-2 is usually made to be approximately parallel to the row direction X, so as to ensure that the orthographic projection of the second connection pattern 1061-2 on the substrate 101 does not overlap with the orthographic projection of the plurality of first connection traces 107 on the substrate 101.

[0181] In the embodiments of this application, "approximately" means that an error range of up to 15% is allowed. For example, "approximately parallel" can mean that the angle between the two is between 0 degrees and 30 degrees, such as 0 degrees to 10 degrees, 0 degrees to 15 degrees, etc.

[0182] In the embodiments of this application, the structures of the first pixel circuit unit and the second pixel circuit unit can be identical, and both can be referred to as pixel circuit pair f. For ease of description later, the two pixel circuits included in each pixel circuit unit in the first pixel circuit unit and the second pixel circuit unit can both be referred to as the first pixel circuit and the second pixel circuit. That is, for ease of description, the third pixel circuit included in the second pixel circuit unit can be referred to as the first pixel circuit, and the fourth pixel circuit included in the second pixel unit can be referred to as the second pixel circuit.

[0183] Figure 15 This is an equivalent circuit diagram of a first pixel circuit group or a second pixel circuit group provided in an embodiment of this application. (Reference) Figure 15 The first pixel circuit group 103 includes a plurality of first pixel circuit units. The second pixel circuit group 105 includes a plurality of second pixel circuit units. Furthermore, at least two pixel circuits in the first pixel circuit units are configured to be electrically connected to the first electrode a1 of the same first light-emitting unit 1021 in the first light-emitting unit group 102. At least two pixel circuits in the second pixel circuit units are configured to be electrically connected to the same dummy electrode pattern 1061.

[0184] refer to Figure 15 The first pixel circuit unit and the second pixel circuit unit may each include two pixel circuits, and both the first pixel circuit unit and the second pixel unit may be referred to as pixel circuit pair f. Embodiments of this application show that the first pixel circuit unit includes two pixel circuits, but it is not limited to this and may also include three or more pixel circuits. For example, the first light-emitting unit group 102 includes a plurality of first light-emitting units 1021, and the first pixel circuit group 103 includes a plurality of pixel circuit pairs f. Each pixel circuit pair f in the first pixel circuit group 103 is configured to be connected to a first electrode a1 of a first light-emitting unit 1021 to drive the first light-emitting unit 1021 to emit light. The second light-emitting unit group 104 includes a plurality of second light-emitting units 1041, and the second pixel circuit group 105 may include a plurality of pixel circuit pairs f. Each pixel circuit pair f in the second pixel circuit group 105 is configured to be electrically connected to the same dummy electrode pattern 1061 to drive a second light-emitting unit 1041 to emit light.

[0185] Optionally, the display panel 10 also includes a reset power signal line, a data line, a scan signal line, a power signal line, a reset control signal line, and a light emission control signal line located on the substrate.

[0186] Among the multiple data lines included in the display panel 10, at least a portion of the target data line located in the second display area 101b has its orthographic projection on the substrate 101 located in the area of ​​the second display area 101b close to the first display area 101a.

[0187] like Figure 15 As shown, each pixel circuit (first pixel circuit f1 and second pixel circuit f2) includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7. The first terminal of the threshold compensation transistor T2 is connected to the first terminal of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3. The first terminal of the first reset control transistor T7 is connected to the reset power supply signal line to receive the reset signal Vinit, and the second terminal of the first reset control transistor T7 is connected to the light-emitting unit. The first terminal of the data writing transistor T4 is connected to the second terminal of the driving transistor T3. For example, as... Figure 15 As shown, the pixel circuit of each pixel unit also includes a storage capacitor C, a first light-emitting control transistor T6, a second light-emitting control transistor T5, and a second reset transistor T1. The gate of data writing transistor T4 is electrically connected to the scan signal line to receive the scan signal Gate; the first terminal of storage capacitor C is electrically connected to the power supply signal line, and the second terminal of storage capacitor C is electrically connected to the gate of driving transistor T3; the gate of threshold compensation transistor T2 is electrically connected to the scan signal line to receive the compensation control signal; the gate of first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset; the first terminal of second reset transistor T1 is electrically connected to the reset power supply signal line to receive the reset signal Vinit, the second terminal of second reset transistor T1 is electrically connected to the gate of driving transistor T3, and the gate of second reset transistor T1 is electrically connected to the reset control signal line to receive the reset control signal Reset; the gate of first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM; the first terminal of second light-emitting control transistor T5 is electrically connected to the power supply signal line, the second terminal of second light-emitting control transistor T5 is electrically connected to the second terminal of driving transistor T3, and the gate of second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM. The aforementioned power signal line refers to the signal line for the output voltage signal VDD, which can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0188] Optionally, the scan signal and the compensation control signal can be the same. That is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can also be electrically connected to different signal lines. That is, the gate of the data writing transistor T3 is electrically connected to the first scan signal line, and the gate of the threshold compensation transistor T2 is electrically connected to the second scan signal line. The signals transmitted by the first scan signal line and the second scan signal line can be the same or different, so that the gate of the data writing transistor T3 and the threshold compensation transistor T2 can be controlled separately, increasing the flexibility of controlling the pixel circuit.

[0189] Optionally, the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can receive the same light-emitting control signal. That is, the gates of the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gates of the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can be electrically connected to different light-emitting control signal lines, and the signals transmitted by the different light-emitting control signal lines can be the same or different.

[0190] Optionally, the reset control signals input to the first reset transistor T7 and the second reset transistor T1 can be the same. That is, the gates of the first reset transistor T7 and the second reset transistor T1 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gates of the first reset transistor T7 and the second reset transistor T1 can also be electrically connected to different reset control signal lines. In this case, the signals on the different reset control signal lines can be the same or different.

[0191] For example, such as Figure 15As shown, when the display panel 10 is working, in the first stage of screen display, the second reset transistor T1 is turned on to initialize the voltage of node N1. In the second stage, the same data signal Data is stored in the two N1 nodes of the two pixel circuits through two connected data writing transistors T4, and two driving transistors T3 and two threshold compensation transistors T2 respectively connected to the two connected data writing transistors T4. In the third light-emitting stage, the second light-emitting control transistor T5, driving transistor T3 and first light-emitting control transistor T6 in the two pixel circuits (i.e., the pixel circuit pair f composed of the first pixel circuit f1 and / or the second pixel circuit f2) are all turned on to transmit the same data signal to the two N4 nodes. At this time, the N4 nodes of the two pixel circuits are connected and jointly drive the same light-emitting unit A to emit light, which can achieve the purpose of increasing current and brightness. Here, the light-emitting unit A can be the first light-emitting unit 1021 in the first light-emitting unit group 102 in the first display area 101a, or the second light-emitting unit 1041 in the second light-emitting unit group 104 in the second display area 101b.

[0192] It should be noted that, in the embodiments of this application, the pixel circuit of the pixel unit can be, in addition to being, Figure 15 Besides the 7T1C (seven transistors and one capacitor) structure shown, other structures with different numbers of transistors can also be used, such as 7T2C, 6T1C, 6T2C, or 9T2C structures. This application does not limit the specific implementation of these structures. The key is to connect the data writing transistors T4 of the two pixel circuits and connect the N4 nodes of the two pixel circuits to enable them to jointly drive the same light-emitting unit to emit light.

[0193] Figure 16 This is a partial planar structural diagram of the active semiconductor layer of the pixel circuit in the first display area provided in an embodiment of this application. For example... Figure 16 As shown, the active semiconductor layer 01 can be formed by patterning semiconductor material. The active semiconductor layer 01 can be used to fabricate the active layers of the aforementioned second reset transistor T1, threshold compensation transistor T2, drive transistor T3, data write transistor T4, second light-emitting control transistor T5, first light-emitting control transistor T6, and first reset control transistor T7. The active semiconductor layer 01 includes the active layer pattern (channel region) and doped region pattern (source / drain doped region) of each transistor in each pixel unit, and the active layer pattern and doped region pattern of each transistor in the same pixel circuit are integrally formed.

[0194] It should be noted that the active layer may include an integrally formed low-temperature polycrystalline silicon layer. The source and drain regions can be made conductive through doping to achieve electrical connections between the various structures. That is, the active semiconductor layer 01 of each transistor in each sub-pixel is an integral pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., source and drain regions) and an active layer pattern. The active layers of different transistors are separated by doped structures.

[0195] For example, the active semiconductor layer 01 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source and drain regions can be regions doped with n-type or p-type impurities.

[0196] Figure 17 This is a schematic diagram of the first conductive layer in the first display area provided in the embodiments of this application. Figure 18 This is a schematic diagram of the active semiconductor layer and the first conductive layer stacked in the first display area provided in an embodiment of this application. The display panel includes a gate insulating layer located on the side of the active semiconductor layer 01 away from the substrate, for insulating the active semiconductor layer 01 from the subsequently formed first conductive layer 02 (i.e., the gate metal layer). Figure 18 The first conductive layer 02 of the display substrate is shown. The first conductive layer 02 is disposed on the gate insulating layer, thereby isolating it from the active semiconductor layer 01. The first conductive layer 02 may include the second terminal CC2 of capacitor C, multiple scan signal lines g3 extending along the row direction X, multiple reset control signal lines g4, multiple light emission control signal lines g5, and the gates of a second reset transistor T1, a threshold compensation transistor T2, a drive transistor T3, a data writing transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, and a first reset control transistor T7.

[0197] For example, combining Figures 16 to 18 The gate of the data writing transistor T3 can be the portion where the scan signal line g3 overlaps with the active semiconductor layer 01; the gate of the first light-emitting control transistor T6 can be the first portion where the light-emitting control signal line g5 overlaps with the active semiconductor layer 01, and the gate of the second light-emitting control transistor T5 can be the second portion where the light-emitting control signal line g5 overlaps with the active semiconductor layer 01. The gate of the second reset transistor T1 is the first portion where the reset control signal line g4 overlaps with the active semiconductor layer 01, and the gate of the first reset control transistor T7 is the second portion where the reset control signal line g4 overlaps with the active semiconductor layer 01. The threshold compensation transistor T2 can be a dual-gate thin-film transistor. The first gate of the threshold compensation transistor T2 can be the portion where the scan signal line g3 overlaps with the active semiconductor layer 01, and the second gate of the threshold compensation transistor T2 can be the portion where the protruding structure P protruding from the scan signal line g3 overlaps with the active semiconductor layer 01. Figure 18 As shown, the gate of the driving transistor T1 can be the second terminal CC2 of the capacitor C.

[0198] It should be noted that, Figure 18 The dashed rectangles in the diagram illustrate the overlapping portions of the first conductive layer 02 and the active semiconductor layer 01. As the channel regions of each transistor, the active semiconductor layer 01 on both sides of each channel region is conductiveized through processes such as ion doping, serving as the first and second electrodes of each transistor. The source and drain electrodes of a transistor can be structurally symmetrical, so their physical structures can be indistinguishable. In the embodiments of this application, to distinguish the transistors, except for the gate which serves as the control electrode, one electrode is directly described as the first electrode and the other as the second electrode. Therefore, in the embodiments of this application, the first and second electrodes of all or some transistors can be interchanged as needed.

[0199] like Figure 18 As shown, the scan signal line g3, reset control signal line g4, and light emission control signal line g5 are arranged along the column direction Y. The scan signal line g3 is located between the reset control signal line g4 and the light emission control signal line g5.

[0200] In the column direction Y, the second terminal CC2 of capacitor C (i.e., the gate of driving transistor T1) is located between scan signal line g3 and light emission control signal line g5. The protruding structure P protruding from scan signal line g3 is located on the side of scan signal line g3 away from light emission control signal line g5.

[0201] A first insulating layer is formed on the first conductive layer 02 to insulate the first conductive layer 02 from the subsequently formed second conductive layer 03.

[0202] Figure 19 This is a partial planar structural diagram of the second conductive layer within the first display area provided in an embodiment of this application. Figure 20 This is a schematic diagram showing the stacking of the active semiconductor layer, the first conductive layer, and the second conductive layer in the first display area provided in an embodiment of this application. Figure 19 and Figure 20 As shown, the second conductive layer 03 includes the first terminal CC1 of capacitor C and multiple reset power signal lines g1 extending along the row direction X. The first terminal CC1 of capacitor C and the second terminal CC2 of capacitor C at least partially overlap to form capacitor C. The second conductive layer 03 can be a gate metal layer.

[0203] refer to Figure 19 and Figure 20The display panel 10 provided in this application embodiment also includes a plurality of first connection portions h1. At least a portion of the first connection portion h1 has its first end connected to the second pole of the data writing transistor T4 of the first pixel circuit f1 in the first pixel circuit unit (for example, the first end of the first connection portion h1 and the second pole of the data writing transistor T4 of the first pixel circuit f1 in the first pixel circuit unit can be directly connected or electrically connected through a conductive layer transition layer). The second end of the first connection portion h1 is connected to the second pole of the data writing transistor T4 of the second pixel circuit f2 in the first pixel circuit unit so that at least two data writing transistors T4 of the first pixel circuit unit are connected to the same data line. Along the column direction, at least a portion of the first connection portion h1 is located between the second pole of the data writing transistor T2 in the first pixel circuit f1 and the first pole of the first reset control transistor T7.

[0204] In this embodiment, the second terminals of the data writing transistors of at least two pixel circuits in the first display area 101a are connected via the first connection portion h1 to drive a light-emitting unit A to emit light, which can increase the current and brightness of the light-emitting unit in the first display area 101a. For example, the current and brightness of the first light-emitting unit 1021 in the first display area 101a can be increased to 1.8 to 2 times that when driven by a single pixel circuit, solving the problem of insufficient current and brightness in the first display area 101a and achieving a more uniform full-screen visual display effect.

[0205] Optionally, a portion of the first connection part h1 is connected to the second terminal of the data writing transistor T4 of the third pixel circuit in the second pixel circuit unit, and the second terminal of the first connection part h1 is connected to the second terminal of the data writing transistor T4 of the fourth pixel circuit in the second pixel circuit unit, so that at least two data writing transistors T4 of the second pixel circuit unit are connected to the same data line. Furthermore, along the column direction Y, the first connection part h1 is located between the second terminal of the data writing transistor T2 in the third pixel circuit and the first terminal of the first reset control transistor T7. For ease of subsequent description, the first pixel circuit unit and the second pixel circuit unit in the embodiments of this application are collectively referred to as pixel circuit pair f. Each pixel circuit unit includes two pixel circuits, both referred to as the first pixel circuit and the second pixel circuit. That is, the third pixel circuit in the second pixel circuit unit can be referred to as the first pixel circuit, and the fourth pixel circuit in the second pixel circuit unit can be referred to as the second pixel circuit.

[0206] Optionally, along the column direction Y, the first connection portion h1 is located between the second terminal of the threshold compensation transistor T3 and the first terminal of the first reset control transistor T7 in the first pixel circuit f1.

[0207] Optionally, the first connection part h1 is arranged on the same layer as the reset power signal line g1.

[0208] Optionally, a second insulating layer is formed on the second conductive layer 03 to insulate the second conductive layer 03 from the subsequently formed source-drain metal layer 04.

[0209] Figure 21 This is a partial planar structural diagram of the source / drain metal layer of the first display area provided in an embodiment of this application. Figure 22 This is a schematic diagram showing the stacked structure of the active semiconductor layer, the first conductive layer, the second conductive layer, and the source / drain metal layer within the first display area provided in an embodiment of this application. Figure 21 and Figure 22 As shown, the source-drain metal layer 04 includes a data line g2 extending along the column direction Y and a power signal line g6. The data line g2 is electrically connected to the second terminal of the data writing transistor T2 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The power signal line g6 is electrically connected to the first terminal of the second light-emitting control transistor T5 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The power signal line g6 and the data line g2 are alternately arranged along the row direction. The power signal line g6 is electrically connected to the first terminal CC1 of the capacitor C through a via penetrating the second insulating layer.

[0210] In this embodiment, a third insulating layer may be provided on the side of the source / drain metal layer 04 away from the substrate 101 to protect the source / drain metal layer 04.

[0211] For example, Figures 20 to 22 The illustration schematically shows a portion of the pixel circuits in the first pixel circuit group 103 and a portion of the pixel circuits in the second pixel circuit group 105. This embodiment schematically shows that both the first pixel circuit group 103 and the second pixel circuit group 105 include pixel circuit pairs f. Each pixel circuit pair f includes a first pixel circuit f1 and a second pixel circuit f2 arranged along the row direction X. The second terminals of the data writing transistors T4 in the two pixel circuits of each pixel circuit pair f are connected through a first connection portion h1 to drive the same light-emitting unit to emit light. This embodiment is not limited to this; for example, only the first pixel circuit group 103 or only the second pixel circuit group 105 may include the aforementioned pixel circuit pairs f.

[0212] For example, such as Figures 20 to 22As shown, the first pixel circuit group 103 and the second pixel circuit group 105 may include eight pixel circuits arranged in two rows, i.e., four pixel circuit pairs f arranged in a two-dimensional array. The third pixel circuit group does not include the aforementioned pixel circuit pairs f (not shown), but only includes four pixel circuits arranged in a two-dimensional array. In the third pixel circuit group, each pair of adjacent pixel circuits arranged along the row direction X drives a light-emitting unit to emit light, and the two data write transistors in these adjacent pixel circuits are independent of each other and connected to different data lines. The layout difference between the third pixel circuit group and the first pixel circuit group 103 in this embodiment mainly lies in whether a first connection portion h1 is provided, and the position of the second electrode of the data write transistor connected to the first connection portion h1.

[0213] For example, such as Figures 20 to 22 As shown, the display panel 10 provided in this embodiment can adopt a quarter high definition (QHD) resolution. However, because the distance along the column direction between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor in each pixel circuit designed with this resolution is very small, for example, less than 2 micrometers, or for example, 1.4 micrometers to 1.8 micrometers. Therefore, it is difficult to set the first connection part h1 between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor to connect the second electrode (data input node) of the two data write transistors of the pixel circuit to f. Since the pixel size in QHD resolution products is generally smaller than the pixel size in full high definition (FHD) products, in this embodiment, the pixel circuit with QHD resolution is designed into the pixel pitch with FHD resolution, thereby increasing the distance along the column direction Y between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7 in each pixel circuit, so as to ensure that the data input nodes of the two pixel circuits of the pixel circuit to f are connected by a hole through the first connection part h1.

[0214] For example, such as Figures 20 to 22As shown, relative to a display panel, its first display area includes multiple light-emitting units and multiple pixel circuits connected one-to-one with the multiple light-emitting units. In the case where dummy pixel circuits that are not connected to any light-emitting units are set between adjacent pixel circuits, in this embodiment of the application, the first connecting part h1 is used to connect the dummy pixel circuit (the pixel circuit in the second pixel circuit group 105) and the pixel circuit connected to the first light-emitting unit 1021 in the first display area 101a. This can effectively utilize the dummy pixel circuit while minimizing changes to the overall structure of the pixel circuit, thereby increasing the current and brightness of the light-emitting units in the first display area 101a (at least one of the second display area 101b), and achieving a more uniform full-screen visual display effect.

[0215] Optionally, the distance between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7 along the column direction Y is 7 micrometers to 12 micrometers to provide a first connection portion h1 between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7.

[0216] like Figures 16 to 22 As shown, each pixel circuit further includes a second connection portion h2 and a third connection portion h3 disposed on the same layer as the data line g2. The second connection portion h2 is configured to connect the second electrode of the threshold compensation transistor T2 and the gate of the driving transistor T3. The third connection portion h3 is configured to connect the first electrode of the first reset control transistor T7 and the reset power supply signal line g1. Optionally, one end of the second connection portion h2 is electrically connected to the second electrode of the threshold compensation transistor T2 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The other end of the second connection portion h2 is electrically connected to the gate of the driving transistor T3 (i.e., the second electrode CC2 of the capacitor C) through a via penetrating the first insulating layer and the second insulating layer. One end of the third connection portion h3 is electrically connected to the reset power supply signal line g1 through a via penetrating the second insulating layer. The other end of the third connection portion h3 is electrically connected to the first electrode of the first reset control transistor T7 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer.

[0217] like Figures 16 to 22 As shown, in the first pixel circuit f1, the distance in the column direction between the adjacent edges of the second connecting portion h2 and the third connecting portion h3 is 7 micrometers to 12 micrometers so that the first connecting portion h1 is disposed between the second connecting portion h2 and the third connecting portion h3. For example, in the first pixel circuit f1, the distance in the column direction between the adjacent edges of the second connecting portion h2 and the third connecting portion h3 can be 8 micrometers to 11 micrometers.

[0218] like Figures 16 to 22As shown, the first connection portion h1 and the data line g2 are located on different layers and are along a third direction perpendicular to the substrate. Each first connection portion h1 overlaps with the data line g2 and the power signal line g6. For example, in a pixel circuit f, a data line 410 and a power signal line g6 are provided between the two data writing transistors T4. The first connection portion h1 connecting the two data writing transistors T4 overlaps with both the data line 410 and the power signal line g6.

[0219] like Figures 16 to 22 As shown, each pixel circuit also includes a fourth connection portion h4 disposed on the same layer as the data line g2. The fourth connection portion h4 is configured to connect the first connection portion h1 and the second terminal of the data writing transistor T4. The fourth connection portion h4 of one pixel circuit in the pixel circuit pair f (e.g., the second pixel circuit f2) has a gap with the adjacent data line g2. The fourth connection portion h4 of the other pixel circuit in the pixel circuit pair f (e.g., the first pixel circuit f1) is integrated with the data line g2 to achieve that the pixel circuit pair f is connected to only one data line g2. In the above statement "the fourth connection portion h4 has a gap with the adjacent data line g2," "adjacent data line" means that there are no other data lines between the fourth connection portion h4 and the data line g2.

[0220] like Figure 1 as well as Figures 16 to 22 As shown, multiple third light-emitting units 110 are arranged in an array along the row direction X and the column direction Y. Along the row direction X, multiple first pixel circuit groups 103 and multiple second pixel circuit groups 105 are alternately arranged, and along the column direction Y, multiple first pixel circuit groups 103 and multiple second pixel circuit groups 105 are alternately arranged, and the first pixel circuit groups 103 and the second pixel circuit groups 105 are connected to different data lines g2.

[0221] A straight line extending along the row direction X passes through the second terminal of the two data writing transistors in pixel circuit f, and the entire first connection portion h1 extends along the row direction. For example, different pixel circuit groups connect different data lines, so the length of the first connection portion h1 along the row direction X in different pixel circuit groups can be different. For example, in the same pixel circuit group, the length of the first connection portion h1 along the row direction X in different pixel circuit pairs f can also be different.

[0222] like Figure 21As shown, the fourth connecting part h4, which is integrated with the data line g2, is the first sub-part h41, and the fourth connecting part h4 that is spaced apart from the data line g2 is the second sub-part h42. Taking the second pixel circuit group 105, which includes eight pixel circuits arranged in an array (four pixel circuits arranged along the row direction and two pixel circuits arranged along the column direction), as an example, in the first pixel circuit group 103, the two first sub-parts h41 are arranged along the column direction (i.e., in a row), and the two second sub-parts h42 are arranged along the column direction Y (i.e., in a column), and the first sub-parts h41 and the second sub-parts h42 are arranged alternately in the row direction X. Similarly, the arrangement of the first sub-parts and the second sub-parts in the second pixel circuit group 105 is the same as the arrangement of the first sub-parts and the second sub-parts in the first pixel circuit group 103. For the first pixel circuit group 103 and the second pixel circuit group 105 arranged alternately along the column direction Y, the first sub-part of the first pixel circuit group 103 and the second sub-part of the second pixel circuit group 105 are located in different columns so that the first pixel circuit group 103 and the second pixel circuit group 105 are connected to different data lines.

[0223] Since there is no pixel circuit design for f in the third light-emitting unit 110, the fourth connection part in the two adjacent pixel circuits arranged along the row direction X or column direction in the third light-emitting unit 110 is integrated with the data line to realize the electrical connection between each pixel circuit and the corresponding data line.

[0224] like Figures 16 to 22 As shown, the display panel 10 also includes a plurality of cover portions S disposed on the same layer as the first connection portion h1. Each threshold compensation transistor T2 includes two gates T2-g1 and T2-g2 and an active semiconductor layer O1 located between the two gates. Along the direction perpendicular to the bearing surface of the substrate 101, the cover portion S overlaps with the active semiconductor layer O1 between the two gates, the data line g2, and the power signal line g6.

[0225] The active semiconductor layer 01 between the two channels of the dual-gate threshold compensation transistor T2 is in a floating state when the transistor is off. This floating layer is susceptible to voltage fluctuations from surrounding lines, affecting the leakage current and consequently the luminous intensity. To maintain voltage stability in the active semiconductor layer 01 between the two channels of the transistor, a capacitive capacitor is formed between the capacitive portion S and the active semiconductor layer 01. The capacitive portion S can be connected to the power signal line g6 to obtain a constant voltage, thus ensuring voltage stability in the floating state. The overlap between the capacitive portion S and the active semiconductor layer 01 between the two channels of the transistor also prevents illumination from altering the characteristics of the active semiconductor layer 01 between the two gates, such as preventing voltage changes in this portion and thus preventing crosstalk. The power signal line g6 can be electrically connected to the capacitive portion S through a via penetrating the second insulating layer to provide a constant voltage to the capacitive portion S.

[0226] The orthographic projection of the cover portion S, which overlaps with the active semiconductor layer 01, on the first straight line extending in the row direction X overlaps with the orthographic projection of the first connecting portion h1 on the first straight line. The orthographic projection of the fourth connecting portion h4, which extends in the second straight line in the column direction Y, overlaps with the orthographic projection of the cover portion S on the second straight line. Therefore, in order to maintain a distance from the cover portion S disposed in the same layer, the first connecting portion h1 is configured as a non-linear shape, such as a broken line shape.

[0227] For example, such as Figures 16 to 22 As shown, the first connecting portion h1 includes a main connecting portion h1 extending along the row direction X and two end portions h12 located at both ends of the main connecting portion h1 and extending along the column direction Y. The two end portions h12 are respectively connected to the two fourth connecting portions h4 of the pixel circuit pair f. The orthographic projections of the two end portions h12 on the second straight line overlap with the orthographic projections of the covering portion S on the second straight line. Thus, the main connecting portion and the two end portions form a zigzag shape to maintain a distance from the covering portion.

[0228] For example, in the column direction Y, the distance between the cover portion S and the second electrode of the threshold compensation transistor T2 is less than the distance between the cover portion S and the first electrode of the first reset control transistor T7, that is, the cover portion S is closer to the threshold compensation transistor T2. Therefore, for ease of design and to maintain a certain distance between the first connection portion h1 and the cover portion S, the first connection portion h1 is set to be closer to the first electrode of the first reset transistor T7. That is, in the column direction Y, the distance between the main body connection portion h1 and the second electrode of the threshold compensation transistor T2 in the first pixel circuit f1 is greater than the distance between the main body connection portion h1 and the first electrode of the first reset control transistor T7 in the first pixel circuit f2.

[0229] Figure 23 This is a schematic diagram showing the connection relationship between the first light-emitting unit group and the first pixel circuit group in the first display area provided in the embodiments of this application. Figure 24 This is a schematic diagram of a first electrode and a dummy electrode pattern provided in an embodiment of this application. Figure 25 This is a schematic diagram showing the stacking of a first conductive layer, a second conductive layer, a source / drain metal layer, a first connection trace, a first electrode, and a dummy electrode pattern within a first display area provided in this application embodiment. Figure 26 This is a schematic diagram showing the stacked structure of the active semiconductor layer, first conductive layer, second conductive layer, source / drain metal layer, first connection trace, first electrode, and dummy electrode pattern in the first display area provided in this application embodiment. Figure 27 This is a schematic diagram showing the stacking of an active semiconductor layer, a first conductive layer, a second conductive layer, a source / drain metal layer, a first connection trace, a first electrode, a dummy electrode pattern, and a pixel defining layer in the first display area provided in this application embodiment.

[0230] like Figures 1 to 27 As shown, each light-emitting unit group includes multiple light-emitting units. For example, the first light-emitting unit group 102 includes multiple first light-emitting units 1021, the second light-emitting unit group 104 includes multiple second light-emitting units 1041, and the third light-emitting unit group 109 includes multiple third light-emitting units 1091. Among these, combined with... Figures 24 to 27 Whether the pattern shown is the first electrode a1 or the dummy electrode pattern 1061 depends on whether the pixel defining layer a4 has an opening a41 at this point. The pattern of the area of ​​the pixel defining layer a4 with an opening a41 is the first electrode a1, and the pattern of the area of ​​the pixel defining layer a4 without an opening is the dummy electrode pattern 1061.

[0231] For example, each first light-emitting unit group 1021 includes a first light-emitting unit b1 of a first color, a pair of first light-emitting units b2 of a second color, and a first light-emitting unit b3 of a third color. The first light-emitting unit b1 of the first color and the first light-emitting unit b3 of the third color are arranged along the column direction Y, and the pair of first light-emitting units b2 of the second color includes two first light-emitting units 1021 of the second color arranged along the column direction Y. The first light-emitting unit b1 of the first color and the first light-emitting unit pair b2 of the second color are arranged along the row direction. For example, the orthographic projection of the first electrode a1 of the first light-emitting unit b1 of the first color on a straight line extending along the column direction Y overlaps with the orthographic projection of the first electrode a1 of the second color first light-emitting unit b21 on the same straight line. The orthographic projection of the first electrode a1 of the third color first light-emitting unit b3 on a straight line extending along the column direction Y overlaps with the orthographic projection of the interval between the first electrodes a1 of the two second color first light-emitting units 1021 on the same straight line. For example, the orthographic projection of the main pattern of the first light-emitting unit b3 of the third color (described later) on a straight line extending in the column direction Y does not overlap with the orthographic projection of the main patterns of the two first light-emitting units 1021 of the second color in the column direction Y.

[0232] For example, refer to Figure 5 Each light-emitting unit includes a first electrode a1, a light-emitting layer a2, and a second electrode a3 sequentially disposed along a direction away from the substrate 101. The display substrate also includes a pixel defining layer a4, which includes an opening a41 for defining the light-emitting area of ​​the pixel unit. This opening a41 exposes the first electrode a1 of the light-emitting unit A. When the light-emitting layer a2 of the subsequent light-emitting unit A is formed in the opening a41 of the pixel defining layer a4, the light-emitting layer a2 contacts the first electrode a1, thereby driving the light-emitting layer a2 to emit light to form an effective light-emitting area. Here, "effective light-emitting area" can refer to a two-dimensional planar region parallel to the substrate. It should be noted that, due to process reasons, the size of the opening a41 of the pixel defining layer away from the substrate is slightly larger than the size of the portion close to the substrate, or it gradually increases in size from the side close to the substrate to the side away from the substrate. Therefore, the size of the effective light-emitting area may be slightly different from the size of different positions of the opening a41 of the pixel defining layer, but the overall shape and size of the area are basically the same. For example, the orthographic projection of the effective light-emitting area on the substrate roughly coincides with the orthographic projection of the opening a41 of the corresponding pixel-defining layer on the substrate. For example, the orthographic projection of the effective light-emitting area on the substrate falls entirely within the orthographic projection of the opening a41 of the corresponding pixel-defining layer on the substrate, and the two are similar in shape. The projected area of ​​the effective light-emitting area on the substrate is slightly smaller than the projected area of ​​the opening a41 of the corresponding pixel-defining layer on the substrate.

[0233] like Figures 1 to 27 As shown, each pixel circuit also includes a fifth connection portion h5 disposed on the same layer as the data line g2. The first electrode a1 of the light-emitting unit A located in the second display area 101b and the third display area 101c can be directly electrically connected to the second electrode of the first light-emitting control transistor T6 through the fifth connection portion h5. For example, in the third display area 101c, the second electrode of each third light-emitting unit 1091 in the third light-emitting unit group 109 can be directly electrically connected to the second electrode of the first light-emitting control transistor T6 through the fifth connection portion h5 of the corresponding pixel circuit in the third pixel circuit group 110. In the first display area 101a, the second electrode of each first light-emitting unit 1021 in the first light-emitting unit group 102 can be directly electrically connected to the second electrode of the first light-emitting control transistor T6 through the fifth connection portion h5 of the corresponding pixel circuit in the first pixel circuit group 103. For example, in the first display area 101a, the second electrode of each first light-emitting unit 1021 in the first light-emitting unit group 102 can be connected to the fifth connection portion h5 through the first via i1 in the third insulating layer.

[0234] refer to Figures 1 to 27 As shown, the first pixel circuit group 103 includes multiple pixel circuit pairs f, and the first electrode a1 of each first light-emitting unit 1021 of the first light-emitting unit group 102 includes a first main pattern and a connecting pattern (first connecting pattern and second connecting pattern). The shape of the main pattern is substantially the same as the shape of the effective light-emitting area of ​​each first light-emitting unit 1021, and the connecting pattern (first connecting pattern 1021-2) is configured to be directly electrically connected to the fifth connecting part h5 to be electrically connected to the second electrode of the two first light-emitting control transistors T6 of the pixel circuit pair f.

[0235] like Figures 1 to 27 As shown, the display panel 10 also includes multiple first connection traces 107 located between the first electrode a1 and the film layer containing the data line g2, with each first connection trace 107 extending along the row direction X. For example, the second pixel circuit group 105 includes multiple pixel circuit pairs f, and the first connection traces 107 are configured to connect the first electrode a1 of the second light-emitting unit 1041 in the first type of second light-emitting unit group 104a and the fifth connection portion h5 so that the first electrode a1 of each second light-emitting unit 1041 in the first type of second light-emitting unit group 104 is electrically connected to the second electrode of the two first light-emitting control transistors T6 of the pixel circuit pair f of the second pixel circuit group 105.

[0236] In the first display area 101a, the first connecting trace 107 is electrically connected to the fifth connecting portion h5 in the second pixel circuit group 105 through the second via i21 in the third insulating layer. In the second display area 101b, the first electrode a1 of the second light-emitting unit 1041 is connected to the first connecting trace 107, thereby realizing the connection with the pixel circuit in the first display area 101a.

[0237] For example, Figure 28 yes Figure 23 The diagram shows the positional relationship between the first light-emitting unit group and the vias in the first display area. Figure 28 The dummy electrode pattern group 106 and the fourth connection pattern 1021-3 of the first electrode a1 of the light-emitting unit in the light-emitting unit group are not shown. Figure 23 and Figure 28 As shown, a first via group i1 is formed by multiple first vias i11 connecting a first light-emitting unit group 102 and a first pixel circuit group 103, and a second via group i2 is formed by multiple second vias i21 connecting a second light-emitting unit group 104310 and a second pixel circuit group 105. Along the row direction X, the multiple first via groups i1 and multiple second via groups i2 are arranged alternately; along the column direction Y, the multiple first via groups i1 and multiple second via groups i2 are arranged alternately. Compared to the case where both the first light-emitting unit group 102 and the second light-emitting unit group 104 are connected to the fifth connection portion through the film layer containing the first connection trace 105, in this embodiment, the first electrode a1 of the light-emitting unit of the first light-emitting unit group 102 is directly connected to the fifth connection portion, while the first electrode a1 of the light-emitting unit of the second light-emitting unit group 104 is connected to the fifth connection portion through the first connection trace 107. This allows for more space to be allocated to transparent traces, preventing signal crosstalk.

[0238] For example, Figure 29 yes Figure 1 A partial plan view of the first and third display areas of the display panel shown. Figure 1 and Figure 29 As shown in the embodiment of this application, the third display area 101c and the first display area 101a in the display panel 10 include a plurality of pixel circuits arranged along the row direction X and the column direction Y to form a plurality of pixel circuit rows j1 and a plurality of pixel circuit columns j2. The plurality of pixel circuits located in the third display area 101c include a plurality of third sub-pixel circuits k3. The plurality of pixel circuits located in the first display area 101a include a plurality of first sub-pixel circuits k1. The plurality of third light-emitting units 1091 (i.e., the light-emitting units of three colors included in the third light-emitting unit group 109, such as R, G1, G2, and B shown in the figure) in the third display area 101c are connected to the plurality of third sub-pixel circuits k3 in a one-to-one correspondence. Each first light-emitting unit 1021 (i.e., the light-emitting units of three colors included in the first light-emitting unit group 102, such as R, G1, G2, and B shown in the figure) in the first display area 101a is connected to at least two first sub-pixel circuits k1.

[0239] like Figure 1As shown, the third display area 101c and the first display area 101a are connected in the column direction Y (i.e., the direction of data line extension). The second display area 101b includes a central area 101b1 and an edge area 101b2 surrounding the central area 101b1, and the edge area 101b2 of the second display area 101b is connected to the third display area 101c in the column direction Y. Figure 1 The illustration shows that the second display area 101b is rectangular in shape, and the central area 101b1 of the second display area 101b is circular in shape. The edge area 101b2 is the area located in the rectangle excluding the central area of ​​the circle. The embodiments of this application are not limited to this, and the shapes of the central area 101b1 and the edge area 101b2 of the second display area 101b can be set according to actual product requirements.

[0240] For example, such as Figure 1 As shown, both the central area 101b1 and the edge area 101b2 of the second display area 101b are provided with second light-emitting unit groups 104. Multiple second light-emitting unit groups 104 located in the second display area 101b are electrically connected to multiple second pixel circuit groups 105 in the first display area 101a via a first connecting line 107 or a second connecting line 108, thereby driving the second light-emitting unit groups 104 to emit light. The central area 101b1 of the second display area 101b only has light-emitting unit groups and no pixel circuit groups, thus reducing the metal coverage area and achieving higher light transmittance. The edge area 101b2 of the second display area 101b, in addition to having light-emitting unit groups, also has a light-blocking structure so that the second display area 101b forms a light-transmitting area (i.e., the central area 101b1) with a preset shape. For example, in this embodiment, the light-blocking structure disposed in the edge region 101b2 of the second display area 101b can be multiple dummy pixel circuit groups 111. Each dummy pixel circuit group 111 includes a portion located between the second light-emitting unit group 104 and the substrate 101, and a portion spaced between adjacent second light-emitting unit groups 104. Each dummy pixel circuit group 111 is not connected to any light-emitting unit group and is merely a suspended pixel circuit. For example, the edge region 101b2 is a ring-shaped trace area. For example, the data lines, scan signal lines g3, power signal lines, reset control lines, light-emitting control signal lines, and reset power signal lines connecting the second pixel circuit group 105 are all located in the ring-shaped trace area.

[0241] For example, such as Figure 1As shown, the second light-emitting unit group 104 in the second display area 101b can be controlled in a left-right half-control manner, and is controlled by the second pixel circuit groups 105 in the two first display areas 101a that are symmetrical about the center line extending along the column direction Y of the second display area 101b. For example, the second light-emitting unit group 104 located on the left side of the center line is controlled by the second pixel circuit group 105 in the first display area 101a located on the left side of the center line, and the second light-emitting unit group 104 located on the right side of the center line is controlled by the second pixel circuit group 105 in the first display area 101a located on the right side of the center line. The traces used to drive the light-emitting units in the circular central area 101b1 are arranged in a dense manner in the edge area 101b2, so that the circular central area 101b1, which is the under-screen display area, can have the largest possible area.

[0242] For example, such as Figure 1 As shown, the third display area 101c and the first display area 101a include multiple pixel circuits arranged along the row direction X and the column direction Y to form multiple pixel circuit rows j1 and multiple pixel circuit columns j2. For example, the edge area 101b2 of the second display area 101b includes multiple dummy pixel circuits 1111 arranged along the row direction X and the column direction Y to form multiple dummy pixel circuit columns and multiple dummy pixel circuit rows. Here, the dummy pixel circuits in the second display area 101b are also referred to as pixel circuits. Although the dummy pixel circuits are not connected to any light-emitting unit, their structure can be roughly the same as the pixel circuit structure of other areas. For example, they all include a 7T1C (i.e., seven transistors and one capacitor) structure. Optionally, multiple data lines g2 extending along the column direction Y are respectively connected to multiple pixel circuit columns j2.

[0243] For example, such as Figures 1 to 23 As shown, each pixel circuit column j2 comprises a group of four adjacent columns. Each pixel circuit group includes a first pixel circuit column j21, a second pixel circuit column j22, a third pixel circuit column j23, and a fourth pixel circuit column j24 arranged sequentially along the row direction X (i.e., the direction intersecting with the extension direction of the data line g2). The first pixel circuit column j21, the second pixel circuit column j22, the third pixel circuit column j23, and the fourth pixel circuit column j24 within the third display area 101c are respectively connected to the first data line g21, the second data line g22, the third data line g23, and the fourth data line g24 arranged sequentially along the row direction X. At least some of the pixel circuits in the first pixel circuit column j21, the second pixel circuit column j22, the third pixel circuit column j23, and the fourth pixel circuit column j24 in the first display area 101a are respectively connected to the first data line g21, the second data line g22, the third data line g23, and the fourth data line g24 arranged sequentially along the row direction X.

[0244] For example, such as Figures 1 to 23 As shown, within the first display area 101a, in at least one pixel circuit column group, the data output terminals (i.e., the fourth connection portion h4) of two pixel circuits located in the same pixel circuit row j1 and located in the first pixel circuit column j21 and the second pixel circuit column j22 are electrically connected to form a first pixel circuit pair f1a. Similarly, the data output terminals (i.e., the fourth connection portion h4) of two pixel circuits located in the same pixel circuit row j1 and located in the third pixel circuit column j23 and the fourth pixel circuit column j24 are electrically connected to form a second pixel circuit pair f2a. This embodiment of the application schematically illustrates that each pixel circuit column group within the first display area 101a includes both a first pixel circuit pair f1a and a second pixel circuit pair f2a, but is not limited to this; the configuration can be adjusted according to actual product requirements.

[0245] For example, such as Figures 1 to 23 The third display area 101c, the first display area 101a, and the second display area 101b each include multiple light-emitting units A. Multiple light-emitting units 1091 in the third display area 101c are respectively connected to multiple pixel circuits in the third display area 101c. Multiple light-emitting units 1021 in the first display area 101a are respectively connected to a portion of the pixel circuits in the first display area 101a, and multiple light-emitting units 1041 in the second display area 101b are respectively connected to another portion of the pixel circuits in the first display area 101a. That is, in the first display area 101a, the light-emitting unit 20 in the first light-emitting unit group 102 is connected to the pixel circuits in the first pixel circuit group 103; and the second light-emitting unit 1041 in the second light-emitting unit group 104 in the second display area 101b is connected to the pixel circuits in the second pixel circuit group 105 in the first display area 101a. This application embodiment schematically shows that the first display area 101a includes only the first pixel circuit group 103 and the second pixel circuit group 105, but it is not limited to this. Depending on factors such as space design requirements in the product, the first display area 101a may also include other pixel circuit groups, such as dummy pixel circuit groups (not connected to the light-emitting unit), etc.

[0246] For example, such as Figures 1 to 23 As shown, the first pixel circuit group 103 and the second pixel circuit group 105 in the first display area 101a both include a first pixel circuit pair f1a and a second pixel circuit pair f2a. In the first display area 101a and the second display area 101b, multiple light-emitting units are respectively connected to multiple first pixel circuit pairs f1a and multiple second pixel circuit pairs f2a in the first display area 101a.

[0247] For example, in the embodiments of this application, the light-emitting unit provided in the third display area 101c can be called the third light-emitting unit 1091, the light-emitting unit provided in the first display area 101a can be called the first light-emitting unit 1021, and the light-emitting unit provided in the second display area 101b can be called the second light-emitting unit 1041.

[0248] Since the first pixel circuit group 103 and the second pixel circuit group 105 are arranged alternately in both the row direction X and the column direction Y, and the first pixel circuit group 103 and the second pixel circuit group 105 arranged in the same column along the column direction Y are connected to different data lines g2, some pixel circuits in the first pixel circuit column j21 located in the first display area 101a are connected to the first data line g21. For example, the pixel circuits in the first pixel circuit group 103 in the first pixel circuit column j21 are connected to the first data line g21, while the pixel circuits in the second pixel circuit group 105 in the first pixel circuit column j21 are not connected to the first data line g21. Similarly, some pixel circuits in the second pixel circuit column j22 located in the first display area 101a are connected to the second data line g22. For example, the pixel circuits in the second pixel circuit group 105 in the second pixel circuit column j22 are connected to the second data line g22, while the pixel circuits in the first pixel circuit group 103 in the second pixel circuit column j22 are not connected to the second data line g22. Some pixel circuits in the third pixel circuit column j23 located in the first display area 101a are connected to the third data line g23. For example, the pixel circuits in the second pixel circuit group 105 in the third pixel circuit column j23 are connected to the third data line g23, while the pixel circuits in the first pixel circuit group 103 in the third pixel circuit column j23 are not connected to the third data line g23. Some pixel circuits in the fourth pixel circuit column j24 located in the first display area 101a are connected to the fourth data line g24. For example, the pixel circuits in the first pixel circuit group 103 in the fourth pixel circuit column j24 are connected to the fourth data line 422, while the pixel circuits in the second pixel circuit group 105 in the fourth pixel circuit column j24 are not connected to the fourth data line g24.

[0249] like Figures 1 to 23 As shown, multiple first pixel circuit pairs f1a connected to multiple light-emitting units of the first display area 101a are connected to the first data line g21; multiple second pixel circuit pairs f2a connected to multiple light-emitting units of the first display area 101a are connected to the fourth data line g24; multiple first pixel circuit pairs f1a connected to multiple light-emitting units of the second display area 101b are connected to the second data line g22; and multiple second pixel circuit pairs f2a connected to multiple light-emitting units of the second display area 101b are connected to the third data line g23.

[0250] For example, in the first pixel circuit group 103, the two pixel circuits in the first pixel circuit pair f1a are connected to the first data line g21, and the two pixel circuits in the second pixel circuit pair f2a are connected to the fourth data line g24. In the second pixel circuit group 105, the two pixel circuits in the first pixel circuit pair f1a are connected to the second data line g22, and the two pixel circuits in the second pixel circuit pair f2a are connected to the third data line g23.

[0251] For example, such as Figures 1 to 23 As shown, the first pixel circuit pair f1a, which is connected to the first color light-emitting unit b1 and the third color light-emitting unit b3 in the first light-emitting unit group 102, is connected to the first data line g21, and the second pixel circuit pair f2a, which is connected to the second color light-emitting unit pair b2 in the first light-emitting unit group 102, is connected to the fourth data line g24.

[0252] Figure 30 This is a schematic diagram of a portion of the pixel circuit structure at the boundary between the third display area and the first display area provided in an embodiment of this application. Figure 31 yes Figure 30 A schematic diagram of the membrane structure where the data line connection part is located, as shown. Figure 32 yes Figure 30 A schematic diagram of the membrane structure where the data line is located, as shown. Figures 1 to 32As shown, at the boundary between the third display area 101c and the first display area 101a, the second data line g22, the third data line g23, and the fourth data line g24, which are connected to at least one pixel circuit group, are disconnected to form a first break m1, while the first data line g21 remains continuous without a break. That is, the portion of the second data line g22 located in the first display area 101a and the portion located in the third display area 101c are not connected at the boundary between the third display area 101c and the first display area 101a. Similarly, the portion of the third data line g23 located in the first display area 101a and the portion located in the third display area 101c are not connected at the boundary between the third display area 101c and the first display area 101a. The portion of the fourth data line g24 located in the first display area 101a and the portion located in the third display area 101c are not connected at the boundary between the third display area 101c and the first display area 101a. The portion of the second data line g22 located in the third display area 101c, near the endpoint m2 of the first display area 101a, is connected via a data line connector i to the endpoint m3 of the fourth data line g24 located in the first display area 101a, near the endpoint m3 of the third display area 101c. The data line connector i passes through the first break m1 of the third data line g23. Here, the first data line g21, the second data line g22, the third data line g23, and the fourth data line g24 can refer to a continuous data line, such as the first data line g21 being a continuous data line; or they can refer to non-continuous data lines connected to the same column of pixel circuits, such as the second data line g22, the third data line g23, and the fourth data line g24. Therefore, the second data line g22 connected to the third sub-pixel circuit and the second data line g22 connected to the first sub-pixel circuit are configured to transmit different signals; the third data line g23 connected to the third sub-pixel circuit and the third data line g23 connected to the first sub-pixel circuit are configured to transmit different signals; and the fourth data line g24 connected to the third sub-pixel circuit and the fourth data line g24 connected to the first sub-pixel circuit are configured to transmit different signals.

[0253] That is, although the data lines located on the same straight line in the third display area and the first display area are all referred to as the second data line, the third data line or the fourth data line in different display areas, the second data lines (third data lines or fourth data lines) located in different display areas are configured to transmit different signals.

[0254] This application embodiment schematically illustrates that the endpoint of the second data line in the third display area near the first display area is connected to the endpoint of the fourth data line in the first display area near the third display area via a data line connector, but is not limited thereto. The endpoint of the second data line in the third display area near the first display area can also be connected to the endpoint of the third data line in the first display area near the third display area via a data line connector.

[0255] In this embodiment, the pixel circuit located in the third display area is called the third sub-pixel circuit k3, the pixel circuit connected to the light-emitting unit located in the first display area 101a is called the first sub-pixel circuit k1, and the pixel circuit connected to the light-emitting unit located in the second display area 101b is called the second sub-pixel circuit k2.

[0256] like Figure 30 As shown, in this embodiment of the application, multiple light-emitting units connected to the first pixel circuit column j21 in the third display area 101c include light-emitting units of a first color and light-emitting units of a third color; multiple light-emitting units connected to the second pixel circuit column j22 in the third display area 101c include pairs of light-emitting units of a second color; multiple light-emitting units connected to the third pixel circuit column j23 in the third display area 101c include light-emitting units of a first color and light-emitting units of a third color; and multiple light-emitting units connected to the fourth pixel circuit column j24 in the third display area 101c include pairs of light-emitting units of a second color.

[0257] In this embodiment, data signals are transmitted via data lines from the source driver integrated circuit located on the side of the third display area 101c away from the first display area 101a to the pixel circuits in the third display area 101c and the first display area 101a. The data signals transmitted to the pixel circuits connected to a color-emitting unit in the first display area 101a should be the same as the data signals transmitted to the pixel circuits connected to the same color-emitting units in the third display area 101c. Therefore, when the same pixel circuit column in the third display area 101c is connected to the same data line, and the pixel circuit pairs f in the first display area 101a are connected to the same data line, it is easy for the data signals transmitted to the pixel circuits connected to the first color-emitting units in the third display area 101c to be the same as the data signals transmitted to the pixel circuit pairs f connected to the second color-emitting units in the first display area 101a, resulting in a data signal mismatch between the third display area 101c and the first display area 101a.

[0258] For example, in the third display area 101c, each third light-emitting unit group 109 includes a first-color light-emitting unit b1, a second-color light-emitting unit pair b2, and a third-color light-emitting unit b3. Each second-color light-emitting unit pair includes a first light-emitting unit block b21 and a second light-emitting unit block b22. The first-color light-emitting unit b1 and the third-color light-emitting unit b3 are arranged in a direction parallel to the extension direction of the data line (column direction Y). The first light-emitting unit block b21 and the second light-emitting unit block b22 of the second-color light-emitting unit pair b2 are arranged in the column direction Y. The first-color light-emitting unit b1 and the second-color light-emitting unit pair b2 are arranged in the row direction X. In two adjacent third light-emitting unit groups, the first-color light-emitting unit points in opposite directions toward the third-color light-emitting unit. That is, the light-emitting units connected to the four pixel circuits in the first row of pixel circuits in the third display area 101c, which are close to the first display area 101a and located in the pixel circuit column group, are, in order, a light-emitting unit b1 of the first color, a first light-emitting unit block b21, a light-emitting unit b3 of the third color, and a second light-emitting unit block b22. The four light-emitting units connected to the four pixel circuits in the second row of pixel circuits in the third display area 101c, which are close to the first display area 101a, are, in order, a light-emitting unit b3 of the third color, a second light-emitting unit block b22, a light-emitting unit b1 of the first color, and a first light-emitting unit block b21.

[0259] Therefore, the arrangement of the first-color light-emitting units and the third-color light-emitting units connected to the pixel circuits of the first pixel circuit column and the third pixel circuit column is different, and the arrangement of the first light-emitting unit block b21 and the second light-emitting unit block b22 connected to the pixel circuits of the second pixel circuit column and the fourth pixel circuit column is different. The data signal transmitted by the data line is related to the arrangement of the corresponding color light-emitting units, and both the third display area and the first display area should transmit matching data signals according to the above-mentioned arrangement of light-emitting units.

[0260] like Figures 1 to 32As shown, the plurality of light-emitting units connected to the first pixel circuit column j21 in the first display area 101a include alternating light-emitting units b1 of the first color and light-emitting units b3 of the third color. The light-emitting unit connected to the pixel circuit of the first pixel circuit column j21 located in the row of the first display area 101a near the third display area 101c is, for example, the light-emitting unit b3 of the third color. Similarly, the plurality of light-emitting units connected to the first pixel circuit column j21 in the third display area 101c include alternating light-emitting units b1 of the first color and light-emitting units b3 of the third color. The light-emitting unit connected to the pixel circuit of the first pixel circuit column j21 located in the row of the third display area 101c near the first display area 101a is the light-emitting unit b1 of the first color. Therefore, the pixel circuit in the row of pixel circuits in the third display area 101c that is close to the first display area 101a and connected to the first data line is connected to the first color light-emitting unit b1, and the pixel circuit in the row of pixel circuits in the first display area 101a that is close to the third display area 101c and connected to the same first data line is connected to the third color light-emitting unit b3. The arrangement of the light-emitting units matches the data signal transmitted by the first data line, so the first data line can remain connected at the junction of the third display area 101c and the first display area 101a without being disconnected at the junction of the two display areas.

[0261] like Figures 1 to 32 As shown, the plurality of second-color light-emitting unit pairs b2 connected to the fourth pixel circuit column j24 in the first display area 101a include alternating first light-emitting unit blocks b21 and second light-emitting unit blocks b22. The light-emitting unit connected to the pixel circuit located in the first display area 101a near the third display area 101c and in the fourth pixel circuit column j24 is, for example, the second light-emitting unit block b22. Similarly, the plurality of second-color light-emitting unit pairs connected to the fourth pixel circuit column j24 in the third display area 101c include alternating first light-emitting unit blocks b21 and second light-emitting unit blocks b22. The light-emitting unit connected to the pixel circuit located in the third display area 101c near the first display area 101a and in the fourth pixel circuit column j24 is also the second light-emitting unit block b22. Therefore, if the light-emitting unit connected to the pixel circuit of the row of pixel circuits near the first display area 101a in the third display area 101c and the light-emitting unit connected to the pixel circuit of the row of pixel circuits near the third display area 101c in the first display area and the light-emitting unit of the same type, then the data signal of the fourth data line connected to the fourth pixel circuit column in the third display area 101c and the data signal of the fourth data line connected to the fourth pixel circuit column in the first display area 101a do not match. Therefore, the fourth data line should be disconnected at the junction of the third display area 101c and the first display area 101a.

[0262] like Figures 1 to 32 As shown, the plurality of second-color light-emitting unit pairs b2 connected to the second pixel circuit column j22 in the third display area 101c include alternating first light-emitting unit blocks b21 and second light-emitting unit blocks b22, and the light-emitting unit connected to the pixel circuit of the second pixel circuit column j22 in the row of the third display area 101c close to the first display area 101a is the first light-emitting unit block b21. Therefore, when the data signal of the fourth data line connected to the fourth pixel circuit column of the first display area 101a and the data signal of the second data line connected to the second pixel circuit column of the third display area 101c are matched, the portion of the second data line located in the third display area 101c and the portion located in the first display area 101a are disconnected at the boundary between the two display areas, and the second data line located in the third display area 101c is connected to the fourth data line located in the first display area 101a through a data line connection part, so as to satisfy the unified algorithm processing of the integrated circuit (IC) in the third display area 101c and the first display area 101a.

[0263] In this embodiment, at the junction of the third display area 101c and the first display area 101a, the second data line, the third data line, and the fourth data line are disconnected. The endpoint of the second data line located in the third display area 101c near the first display area 101a is connected to the endpoint of the fourth data line located in the first display area 101a near the third display area 101c via a data line connector. This ensures that the data signal transmitted from the data line to the light-emitting unit in the third display area 101c matches the data signal transmitted from the data line to the light-emitting unit in the first display area 101a.

[0264] like Figures 30 to 32 As shown, the data line connector i and the multiple data lines g2 are located on different layers. For example, along the direction perpendicular to the substrate, the data line connector i overlaps with the power signal line g6. Since the data line connector needs to pass through the first break of the third data line and the two power signal lines to connect the endpoints of the second and fourth data lines, the data line connector needs to be located on a different layer from the data lines.

[0265] Optional, such as Figures 30 to 32 As shown, the data line connector i and the reset power signal line g1 are located on the same layer for ease of design.

[0266] like Figures 30 to 32 As shown, in the third display area 101c, a data line connection portion i is provided between the second terminal of the threshold compensation transistor T2 and the first terminal of the first reset control transistor T7 in the two pixel circuits of the first pixel circuit row j1 adjacent to the first display area 101a and located in the third pixel circuit column j23 and the fourth pixel circuit column j24.

[0267] In this embodiment, the boundary between the third display area 101c and the first display area 101a refers to the interval between the first electrode of the first reset transistor and the second electrode of the data write transistor in a row j1 of pixel circuits in the third display area 101c that is close to the first display area 101a.

[0268] For example, in the third display area 101c, in a row of pixel circuits adjacent to the first display area 101a, the distance in the column direction Y between the second electrode of the threshold compensation transistor T2 and the second electrode of the first reset control transistor T7 is 7 micrometers to 12 micrometers so that a data line connection portion i is provided between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7.

[0269] In the pixel circuit of the third display area 101c, the distance in the column direction Y between the adjacent edges of the second connection portion h2 and the third connection portion h3 is 7 micrometers to 12 micrometers, so that a data line connection portion i can be provided between the second connection portion h2 and the third connection portion h3. In the embodiments of this application, although the first connection portion h1 and the data line connection portion are respectively provided in the first display area and the boundary between the third display area and the first display area, by adjusting the distance between the second electrode of the threshold compensation transistor of the pixel circuit and the first electrode of the first reset control transistor, the first connection portion h1 and the data line connection portion can both be provided in the larger space reserved between the second electrode of the threshold compensation transistor of the pixel circuit and the first electrode of the first reset control transistor, so as to prevent interference with other signals.

[0270] Figure 33 This is a schematic diagram of a portion of the pixel circuit structure at the boundary between the edge areas of the third display area and the second display area, provided in an embodiment of this application. (Reference) Figure 33 The second display area 101b contains multiple dummy pixel circuit columns, including groups of four adjacent columns. Each dummy pixel circuit group includes a first dummy pixel circuit column n1, a second dummy pixel circuit column n2, a third dummy pixel circuit column n3, and a fourth dummy pixel circuit column n4 arranged sequentially along the column direction Y. At least a portion of the dummy pixel circuits 1111 of the first dummy pixel circuit column n1, at least a portion of the dummy pixel circuits 1111 of the second dummy pixel circuit column n2, and at least a portion of the dummy pixel circuits 1111 of the third dummy pixel circuit column n3 are dummy pixel circuits 1111. At least a portion of the dummy pixel circuit 1111 and the fourth dummy pixel circuit column n4 are connected to the first data line g21, the second data line g22, the third data line g23 and the fourth data line g24 arranged sequentially along the column direction Y. At the interval between the dummy pixel circuit 1111 and the first sub-pixel circuit k3 (for example, at the junction of the edge area 101b2 of the second display area 101b and the third display area 101c), the third data line g23 and the fourth data line g24 are disconnected to form a second break m4.

[0271] The first dummy pixel circuit column n1, the second dummy pixel circuit column n2, the third dummy pixel circuit column n3, and the fourth dummy pixel circuit column n4 mentioned above can also be referred to as the first pixel circuit column, the second pixel circuit column, the third pixel circuit column, and the fourth pixel circuit column, respectively.

[0272] like Figures 1 to 33 As shown, the pixel circuit pair f connected to the first color light-emitting unit b1 and the third color light-emitting unit b3 in the second light-emitting unit group 104 can be one of the first pixel circuit pair f1a and the second pixel circuit pair f2a, and the pixel circuit pair f connected to the second color light-emitting unit pair b2 in the second light-emitting unit group 104 can be the other of the first pixel circuit pair f1a and the second pixel circuit pair f2a.

[0273] Optionally, the pixel circuit pair f connected to the first-color light-emitting unit b1 and the third-color light-emitting unit b3 of the second light-emitting unit group 104 can be connected to one of the second data line g22 and the third data line g23, and the pixel circuit pair f connected to the first light-emitting unit block b21 and the second light-emitting unit block b22 of the second light-emitting unit group 104 can be connected to the other of the second data line g22 and the third data line g23. For example, the pixel circuit pair f connected to the first-color light-emitting unit b1 and the third-color light-emitting unit b3 of the second light-emitting unit group 104 can be connected to the third data line g23, and the pixel circuit pair f connected to the first light-emitting unit block b21 and the second light-emitting unit block b22 of the second light-emitting unit group 104 can be connected to the second data line g22.

[0274] Because the second and third data lines are disconnected at the boundary between the third display area 101c and the first display area 101a, the pixel circuits connected to the second light-emitting unit group 104 cannot receive matching data signals from the data lines in the third display area 101c connected to the first display area 101a. Therefore, in this embodiment, the continuous first and second data lines at the boundary between the edge area of ​​the second display area and the third display area 101c are used to connect the pixel circuit pairs f connected to the first light-emitting unit block b21 and the second light-emitting unit block b22 of the second light-emitting unit group 104, as well as the pixel circuit pairs f connected to the first color light-emitting unit b1 and the third color light-emitting unit b3 of the second light-emitting unit group 104. This achieves the input of matching data signals to the pixel circuits connected to the second light-emitting unit group 104, satisfying the unified algorithm processing of the integrated circuit in the third display area 101c and the second display area 101b.

[0275] In the second display area 101b, the plurality of light-emitting units connected to the third pixel circuit column j23 of the first display area 101a include alternating first-color light-emitting units b1 and third-color light-emitting units b3. The light-emitting unit connected to the pixel circuit of the first row of the first display area 101a away from the third display area 101c and to the third pixel circuit column j23 is the third-color light-emitting unit b3. In the third display area 101c, the plurality of light-emitting units 20 connected to the first pixel circuit column j21 include alternating first-color light-emitting units b1 and third-color light-emitting units b3. The data line connected to the pixel circuit of the second display area 101b in a row close to the third display area 101c and connected to the first-color light-emitting unit b1 is the first data line.

[0276] The plurality of light-emitting units in the second display area 101b connected to the second pixel circuit column j22 of the first display area 101a include alternating first light-emitting unit blocks b21 and second light-emitting unit blocks b22. The light-emitting unit connected to the pixel circuits in the first row of the first display area 101a away from the third display area 101c and in the second pixel circuit column j22 is the second light-emitting unit block b22. The plurality of light-emitting units in the third display area 101c connected to the second pixel circuit column j22 include alternating first light-emitting unit blocks b21 and second light-emitting unit blocks b22. The data line connected to the pixel circuits in the row of the second display area 101b close to the third display area 101c and connected to the first light-emitting unit block b21 is the second data line. Therefore, the data signals on the first and second data lines in the area where the third display area 101c and the edge area 101b2 of the second display area 101b meet are matched with the data signals on the third and second data lines in the first display area 101a, respectively. However, the data signals transmitted by the third and fourth data lines in the area where the third display area 101c and the edge area 101b2 of the second display area 101b meet are not matched with the data signals on the third and second data lines in the first display area 101a. Thus, at the boundary between the edge area 101b2 of the second display area 101b and the third display area 101c, the first and second data lines remain connected, while the third and fourth data lines are disconnected.

[0277] like Figures 1 to 33As shown, the display panel 10 also includes a peripheral area 101d located on the side of the second display area 101b away from the third display area 101c. A first data line g21 located in the edge area 101b2 of the second display area 101b bypasses the central area 101b1 to connect to one of the second data lines g22 and the third data line g23 of the first display area 101a in the peripheral area 101d. The other second data line g22 located in the edge area 101b2 of the second display area 101b bypasses the central area 101b1 to connect to the other of the second data lines g22 and the third data line g23 of the first display area 101a in the peripheral area 101d.

[0278] For example, an embodiment of this application schematically shows that a first data line g21 located in the edge area 101b2 of the second display area 101b bypasses the central area 101b1 to connect to a third data line g23 in the peripheral area 101d of the first display area 101a, and a second data line g22 located in the edge area 101b2 of the second display area 101b bypasses the central area 101b1 to connect to a second data line g22 in the peripheral area 101d of the first display area 101a, thereby facilitating the routing of data lines in the second display area and the first display area.

[0279] like Figures 1 to 33 As shown, another embodiment of this application provides a display panel 10 including a third display area 101c and a first display area 101a. The third display area 101c includes a plurality of third light-emitting units 1091 and a plurality of third sub-pixel circuits k3. The plurality of third light-emitting units 1091 include adjacent rows of first light-emitting units 1091-1 and second light-emitting units 1091-2, and each row of light-emitting units is connected to a corresponding row of third sub-pixel circuits k3. The first display area 101a includes a plurality of first light-emitting units 1021 and a plurality of first sub-pixel circuits k1. The plurality of first light-emitting units 1021 include adjacent rows of third light-emitting units 1021-4 and fourth light-emitting units 1021-5. Each row of light-emitting units in the first display area 101a is connected to a row of first sub-pixel circuit pairs q1, and each row of first sub-pixel circuit pairs q1 includes two adjacent rows of first sub-pixel circuits k1.

[0280] like Figures 1 to 33 As shown, the display panel 10 also includes multiple first sub-data lines r1, multiple second sub-data lines r2, multiple third sub-data lines r3, and multiple fourth sub-data lines r4 extending along the column direction Y. Each first sub-data line r1 is connected to each first light-emitting unit column 1091-1, each second sub-data line r2 is connected to each second light-emitting unit column 1091-2, each third sub-data line r3 is connected to each third light-emitting unit column 1021-4, and each fourth sub-data line r4 is connected to each fourth light-emitting unit column 1021-5.

[0281] like Figures 1 to 33As shown, the arrangement direction of the first light-emitting unit column 1091-1 and the second light-emitting unit column 1091-2 is the same as that of the third light-emitting unit column 1021-4 and the fourth light-emitting unit column 1021-5. A column of third sub-pixel circuits k3 connected to the first light-emitting unit column 1091-1 and a column of first sub-pixel circuits k1 connected to the third light-emitting unit column 1021-4 are located in the same column. The first sub-data line r1 and the third sub-data line r3 are a continuous data line extending along the column direction Y. The two columns of first sub-pixel circuits k1 connected to the fourth light-emitting unit column 1021-5 and the column of third sub-pixel circuits k3 connected to the second light-emitting unit column 1091-2 are located in different columns. The second sub-data line r2 and the fourth sub-data line r4 are connected through the data line connection part i, and the extension direction of the data line connection part i intersects the column direction Y.

[0282] The first sub-data line r1, the second sub-data line r2, the third sub-data line r3, and the fourth sub-data line r4 here have different meanings from the first data line g21, the second data line g22, the third data line g23, and the fourth data line g24 in the above embodiment. Here, the first sub-data line r1 refers only to the data line in the first data line g21 in the above embodiment that connects to the pixel circuit in the third display area. Here, the second sub-data line r2 refers only to the data line in the second data line g22 in the above embodiment that connects to the pixel circuit in the third display area. Here, the third sub-data line r3 refers only to the data line in the first data line g21 in the above embodiment that connects to the pixel circuit in the first display area 101a. Here, the fourth sub-data line r4 refers only to the data line in the fourth data line g24 in the above embodiment that connects to the pixel circuit in the first display area 101a.

[0283] At the junction of the pixel circuit in the third display area 101c and the pixel circuit in the first display area 101a, the second sub-data line r2 and the fourth sub-data line r4 are disconnected, and the second sub-data line r2 and the fourth sub-data line r4 are connected through the data line connection part i, thereby ensuring the matching of the data signal transmitted from the data line to the light-emitting unit in the third display area 101c with the data signal transmitted from the data line to the light-emitting unit in the first display area 101a.

[0284] like Figures 1 to 33 As shown, a column of third sub-pixel circuit k3 connected to the second light-emitting unit column 1091-2 and another column of first sub-pixel circuit k1 connected to the third light-emitting unit column 1021-4 are located in the same column.

[0285] like Figures 1 to 33As shown, the third display area 101c also includes a fifth light-emitting unit column 1091-3 and a sixth light-emitting unit column 1091-4 arranged adjacent to each other. The first light-emitting unit column 1091-1, the second light-emitting unit column 1091-2, the fifth light-emitting unit column 1091-3 and the sixth light-emitting unit column 1091-4 are arranged repeatedly along the row direction X, and the third light-emitting unit column 1021-4 and the fourth light-emitting unit column 1021-5 are arranged alternately along the row direction X.

[0286] like Figures 1 to 33 As shown, the display panel 10 also includes multiple fifth sub-data lines r5 and multiple sixth sub-data lines r6 extending along the column direction Y. Each fifth sub-data line r5 is connected to each fifth light-emitting unit column 1091-3, and each sixth sub-data line r6 is connected to each sixth light-emitting unit column 1091-4.

[0287] like Figures 1 to 33 As shown, a column of third sub-pixel circuits k3 connected to the fifth light-emitting unit column 1091-3 and a column of first sub-pixel circuits k1 connected to the fourth light-emitting unit column 1021-5 are located in the same column. Similarly, a column of third sub-pixel circuits k3 connected to the sixth light-emitting unit column 1091-4 and another column of first sub-pixel circuits k1 connected to the fourth light-emitting unit column 1021-5 are located in the same column. A gap is provided between the sixth sub-data line r6 or the fifth sub-data line r5 and the fourth sub-data line r4. Figure 29 The illustration shows a pixel circuit connected to the sixth sub-data line r6 and a pixel circuit connected to the fourth sub-data line r4 in the same column, with a gap between them, but this is not a limitation. When the pixel circuit connected to the fourth sub-data line r4 and the pixel circuit connected to the fifth sub-data line r5 are in the same column, a gap is provided between them. Here, the fifth sub-data line r5 refers only to the data line in the third data line g23 of the above embodiment that connects to the pixel circuit in the third display area 101c, and the sixth sub-data line r6 refers to the data line in the fourth data line g24 of the above embodiment that connects to the pixel circuit in the third display area 101c.

[0288] Figure 34 This is a partial plan view of the third display area and the first display area in a display panel provided in another example of an embodiment of this application. Figure 34 The example shown is the same as Figure 29 The difference in the example shown is the arrangement of the pixels. Figure 29 The pixel arrangement in the example shown is GGRB. Figure 34 The pixel arrangement in the example shown is real RGB. Figure 34As shown, every six RGB light-emitting units in the third display area 101c constitute one repeating cycle. The data line g2 connected to the first column of R light-emitting units in the third display area 101c and the data line g2 connected to the first column of R light-emitting units in the first display area 101a are the same continuous data line; there is a gap between the data line g2 connected to the second column of G light-emitting units in the third display area 101c and the data line g2 connected to the second column of R light-emitting units in the first display area 101a; the data line g2 connected to the second column of G light-emitting units in the third display area 101c is connected to the data line g2 connected to the third column of G (or fourth column of G) light-emitting units in the first display area 101a via the data line connection part i; there is a gap between the data line g2 connected to the third column of B light-emitting units in the third display area 101c and the data line g2 connected to the third column of G light-emitting units in the first display area 101a. The data line g2 connected to the third column B light-emitting unit of the third display area 101c is connected to the data line g2 connected to the fifth column B (or sixth column B) light-emitting unit of the first display area 101a via the data line connection part i; there is a gap between the data line g2 connected to the fourth column G light-emitting unit of the third display area 101c and the data line g2 connected to the fourth column G light-emitting unit of the first display area 101a; there is a gap between the data line g2 connected to the fifth column R light-emitting unit of the third display area 101c and the data line g2 connected to the fifth column B light-emitting unit of the first display area 101a; there is a gap between the data line g2 connected to the sixth column G light-emitting unit of the third display area 101c and the data line g2 connected to the sixth column B light-emitting unit of the first display area 101a. The embodiments of this application are not limited to the above-described connections. As long as one R light-emitting unit in the third display area 101c is connected to one R light-emitting unit in the first display area 101a via the same data line, one B light-emitting unit in the third display area 101c is connected to one B light-emitting unit in the first display area 101a via the same data line, and one G light-emitting unit in the third display area 101c is connected to one G light-emitting unit in the first display area 101a via the same data line, it is acceptable.

[0289] like Figures 1 to 34 As shown, the third display area 101c includes a plurality of first sub-light-emitting unit groups t1 and a plurality of second sub-light-emitting unit groups t2 arranged alternately along the row direction X and the column direction Y. The first sub-light-emitting unit group t1 includes the light-emitting units in the first light-emitting unit column 1091-1 and the second light-emitting unit column 1091-2. The second sub-light-emitting unit group t2 includes the light-emitting units in the fifth light-emitting unit column 1091-3 and the sixth light-emitting unit column 1091-4. The first display area 101a includes a plurality of third sub-light-emitting unit groups t3.

[0290] like Figures 1 to 34As shown, each sub-light-emitting unit group includes a first-color light-emitting unit R, a pair of second-color light-emitting units G1 and G2, and a third-color light-emitting unit B. The first-color light-emitting unit R and the third-color light-emitting unit B are arranged along the column direction Y. The second-color light-emitting unit pairs G1 and G2 include two second-color light-emitting units arranged along the column direction Y. The first-color light-emitting unit R and the second-color light-emitting unit pairs G1 and G2 are arranged along the row direction X, and the arrangement direction of the first-color light-emitting unit R and the third-color light-emitting unit B in the first sub-light-emitting unit group t1 is opposite to that in the second sub-light-emitting unit group t2. The relative position distribution of each light-emitting unit in the first sub-light-emitting unit group t1 is the same as that in the third sub-light-emitting unit group t3. This embodiment of the application illustrately uses red light-emitting units as the first-color light-emitting unit, green light-emitting unit pairs as the second-color light-emitting unit pairs, and blue light-emitting units as the third-color light-emitting unit, but it is not limited to this. For example, the first color light-emitting unit can be a blue light-emitting unit, the second color light-emitting unit pair can be a green light-emitting unit pair, and the third color light-emitting unit can be a red light-emitting unit. For example, the first color light-emitting unit is a green light-emitting unit, the second color light-emitting unit pair is a red light-emitting unit pair, and the third color light-emitting unit is a blue light-emitting unit.

[0291] like Figures 1 to 34 As shown, the first display area 101a further includes multiple second sub-pixel circuit pairs q2, and the second display area 101b includes multiple second light-emitting units 1041. The multiple second light-emitting units 1041 include adjacent seventh light-emitting unit columns 1041-1 and eighth light-emitting unit columns 1041-2. The arrangement direction of the first light-emitting unit columns 1091-1 and the second light-emitting unit columns 1091-2 is the same as the arrangement direction of the seventh light-emitting unit columns 1041-1 and the eighth light-emitting unit columns 1041-2. Each light-emitting unit column in the second display area 101b is connected to a column of second sub-pixel circuit pairs q2, and each column of second sub-pixel circuit pairs q2 includes two adjacent columns of second sub-pixel circuit pairs q2.

[0292] like Figures 1 to 34 As shown, the display panel 10 also includes multiple seventh sub-data lines r7 and multiple eighth sub-data lines r8 extending along the column direction Y. Each seventh sub-data line r7 is connected to each seventh light-emitting unit column 1041-1, and each eighth sub-data line r8 is connected to each eighth light-emitting unit column 1041-2.

[0293] like Figures 1 to 34As shown, at least one of the seventh sub-data line r7 and the eighth sub-data line r8 is disposed between the third sub-data line r3 and the fourth sub-data line r4. Here, the seventh sub-data line r7 refers only to the data line in the second data line g22 of the above embodiment that connects to the pixel circuit in the first display area 101a, and the eighth sub-data line r8 refers to the data line in the third data line g23 of the above embodiment that connects to the pixel circuit in the first display area 101a.

[0294] like Figures 1 to 34 As shown, the seventh sub-data line r7 and the eighth sub-data line r8 are both located between the third sub-data line r3 and the fourth sub-data line r4, and there is a gap between the eighth sub-data line r8 and the fifth sub-data line r5 to accommodate the data line connection part i.

[0295] For example, the eighth sub-data line r8 and the fifth sub-data line r5 have a break at the interval between the pixel circuit of the third display area 101c and the pixel circuit of the first display area 101a, and the data line connection part i is provided at the break.

[0296] like Figures 1 to 34 As shown, multiple second sub-pixel circuit pairs q2 are configured to be connected to multiple fourth sub-light-emitting unit groups t4. The relative position distribution of each light-emitting unit in each fourth sub-light-emitting unit group t4 is the same as the relative position distribution of each light-emitting unit in the third sub-light-emitting unit group t3. The first sub-pixel circuit pair q1 connected to the third sub-light-emitting unit group t3 and the second sub-pixel circuit pair q2 connected to the fourth sub-light-emitting unit group t4 are arranged alternately along the row direction X and the column direction Y.

[0297] like Figures 1 to 34 As shown, the second display area 101b includes a central area 101b1 and an edge area 101b2 surrounding the central area 101b1. The edge area 101b2 includes a plurality of dummy pixel circuits arranged along the row direction X and the column direction Y to form a plurality of dummy pixel circuit columns u1 and a plurality of dummy pixel circuit rows.

[0298] like Figures 1 to 34 As shown, the multiple dummy pixel circuit columns u1 in the second display area 101b include dummy pixel circuit column groups u11 composed of four adjacent columns. Each dummy pixel circuit column group u11 includes a first dummy pixel circuit column n1, a second dummy pixel circuit column n2, a third dummy pixel circuit column n3 and a fourth dummy pixel circuit column n4 arranged sequentially along the row direction X.

[0299] like Figures 1 to 34As shown, the display panel 10 also includes a first dummy data line v1, a second dummy data line v2, a third dummy data line v3, and a fourth dummy data line v4. The first dummy data line v1 is connected to the first dummy pixel circuit column n1, the second dummy data line v2 is connected to the second dummy pixel circuit column n2, the third dummy data line v3 is connected to the third dummy pixel circuit column n3, and the fourth dummy data line v4 is connected to the fourth dummy pixel circuit column n4.

[0300] like Figures 1 to 34 As shown, a column of third sub-pixel circuits k3 connected to the first light-emitting unit column 1091-1 and a column of first dummy pixel circuits n1 are located in the same column; a column of third sub-pixel circuits k3 connected to the second light-emitting unit column 1091-2 and a column of second dummy pixel circuits n2 are located in the same column; a column of third sub-pixel circuits k3 connected to the fifth light-emitting unit column 1091-3 and a column of third dummy pixel circuits n3 are located in the same column; and a column of third sub-pixel circuits k3 connected to the sixth light-emitting unit column 1091-4 and a column of fourth dummy pixel circuits n4 are located in the same column. The two data lines connected to the first sub-light-emitting unit group t1 and the corresponding two dummy data lines are consecutive data lines, or the two data lines connected to the second sub-light-emitting unit group t2 and the corresponding two dummy data lines are consecutive data lines.

[0301] like Figures 1 to 34 As shown, the display panel 10 also includes a peripheral area 101d located on the side of the second display area 101b away from the third display area 101c. Two dummy data lines connected to the first sub-light-emitting unit group t1 or the second sub-light-emitting unit group t2 bypass the central area 101b1 to connect the seventh sub-data line r7 and the eighth sub-data line r8 in the peripheral area 101d, respectively.

[0302] refer to Figure 33 The first dummy data line v1 and the first sub-data line r1 are a continuous data line, the second dummy data line v2 and the second sub-data line r2 are a continuous data line, the third dummy data line v3 and the fifth sub-data line r5 are separated by a gap, and the fourth dummy data line v4 and the sixth sub-data line r6 are separated by a gap.

[0303] like Figures 1 to 34 As shown, the first dummy data line v1 bypasses the central area 101b1 to connect to the seventh sub-data line r7 in the peripheral area 101d, and the second dummy data line v2 bypasses the central area 101b1 to connect to the eighth data line r8 in the peripheral area 101d.

[0304] Figure 35 This is a schematic diagram of the first electrode of the light-emitting unit group located in the third display area provided in an embodiment of this application. Figure 36This is a schematic diagram of the first electrode of the light-emitting unit group located at the non-edge of the first display area, provided in an embodiment of this application. Figure 37 This is a schematic diagram of the first electrode of the light-emitting unit group located in the second display area, provided in an embodiment of this application. (See diagram below.) Figures 1 to 37 As shown, the first electrode a1 of each light-emitting unit includes a main pattern a11 and a connecting pattern a12. The shape of the main electrode a11 is substantially the same as the shape of the effective light-emitting area of ​​each light-emitting unit. The connecting pattern a12 is configured to be electrically connected to the second electrode of the first light-emitting control transistor T6 of the pixel circuit via a fifth connecting portion h5. Each group of light-emitting units located in the display area includes multiple light-emitting units of different colors. For example, each group of light-emitting units includes a first-color light-emitting unit b1, a second-color light-emitting unit pair b2, and a third-color light-emitting unit b3.

[0305] In this embodiment, the area of ​​the main pattern of a light-emitting unit of one color located in at least one of the non-edge region of the first display area 101a and the second display area 101b is greater than the area of ​​the main pattern of a light-emitting unit of the same color located in the third display area 101c. The area of ​​the main pattern of each color light-emitting unit is related to the area of ​​its effective light-emitting area. In this embodiment, by setting the area of ​​the main pattern of a light-emitting unit of one color located in at least one of the non-edge region of the first display area and the second display area to be greater than the area of ​​the main pattern of a light-emitting unit of the same color located in the third display area, the area of ​​the effective light-emitting area of ​​the light-emitting unit of one color located in at least one of the non-edge region of the first display area and the second display area is greater than the area of ​​the effective light-emitting area of ​​the light-emitting unit of the same color located in the third display area.

[0306] In this embodiment, since the density of the light-emitting unit groups in the first display area 101a and the second display area 101b is less than the density of the light-emitting unit group in the third display area, the area of ​​the main pattern in at least one of the light-emitting units in the first display area 101a and the second display area 101b is designed to be larger than the area of ​​the main pattern in the light-emitting unit in the third display area. This allows the area of ​​the effective light-emitting area of ​​a light-emitting unit of one color located in the non-edge area of ​​the first display area and at least one of the second display areas to be larger than the area of ​​the effective light-emitting area of ​​a light-emitting unit of the same color as the aforementioned light-emitting unit located in the third display area. Therefore, while ensuring the lifespan of the light-emitting material, the brightness of at least one of the first and second display areas can be increased, achieving a more uniform full-screen visual display effect.

[0307] This application embodiment schematically illustrates that in the non-edge area of ​​the first display area 101a and the second display area 101b, the area of ​​the main pattern of a color-emitting unit is larger than the area of ​​the main pattern of a light-emitting unit in the third display area 101c that has the same color as the aforementioned color-emitting unit. This makes the area of ​​the effective light-emitting area of ​​the color-emitting unit in the non-edge area of ​​the first display area and the second display area larger than the area of ​​the effective light-emitting area of ​​the light-emitting unit in the third display area that has the same color as the aforementioned color-emitting unit. As a result, the brightness of the first and second display areas can be increased while ensuring the lifespan of the light-emitting material of the light-emitting unit, thereby achieving a more uniform full-screen visual display effect.

[0308] For example, in one embodiment of this application, each light-emitting unit in the third display area 101c, the first display area 101a, and the second display area 101b is connected to a pixel circuit. That is, each light-emitting unit in the first and second display areas may not be connected to a pixel circuit pair, but only to a single pixel circuit. In this case, the density of the light-emitting unit groups in the first display area 101a and the second display area 101b is less than the density of the light-emitting unit groups in the third display area. By setting the area of ​​the main pattern in at least one of the light-emitting units in the first display area 101a and the second display area 101b to be greater than the area of ​​the main pattern in the light-emitting unit in the third display area 101c, the area of ​​the effective light-emitting area of ​​the light-emitting unit of one color in the non-edge area of ​​the first display area 101a and the second display area 101b is designed to be greater than the area of ​​the effective light-emitting area of ​​the light-emitting unit of the same color as the light-emitting unit in the third display area 101c, the display effect of each display area can be made as uniform as possible.

[0309] For example, in another example of the embodiments of this application, each pixel circuit group includes multiple pixel circuits. At least one of the first pixel circuit group 103 and the second pixel circuit group 105 in the first display area includes multiple pixel circuit pairs f. The two pixel circuits included in each pixel circuit pair f are configured to be electrically connected to the first electrode a1 of the same light-emitting unit. For example, both the first pixel circuit group 103 and the second pixel circuit group 105 in the first display area 101a include multiple pixel circuit pairs f. Each pixel circuit pair f in the first pixel circuit group 103 is connected to each light-emitting unit in the first light-emitting unit group 102, and each pixel circuit pair f in the second pixel circuit group 105 is connected to each light-emitting unit in the second light-emitting unit group 104. The density of the light-emitting unit groups in the first display area 101a and the second display area 101b is less than that in the third display area 101c. By combining the design of the pixel circuit connected to the light-emitting units of the first display area 101a and the second display area 101b as a pixel circuit pair f, and the design of the area of ​​the main pattern in the light-emitting units of the first display area 101a and the second display area 101b as larger than the area of ​​the main pattern in the light-emitting unit of the third display area 101c, the current and brightness of the light-emitting units of the first display area 101a and the second display area 101b can be increased by 1.8 to 2 times under the condition of a pixel circuit drive, while ensuring the lifespan of the light-emitting material of the light-emitting unit. This solves the problem of low current and brightness in the first display area 101a and the second display area 101b, and achieves a more uniform full-screen visual display effect.

[0310] like Figures 1 to 37 As shown, each light-emitting unit group includes a light-emitting unit b1 of a first color. The area ratio of the main pattern b1-a11 of each first-color light-emitting unit located in the non-edge region of the first display area 101a and at least one of the second display area 101b to the area ratio of the main pattern b1-a11 of each first-color light-emitting unit located in the third display area 101c is 1.5 to 2.5. For example, each light-emitting unit group includes a light-emitting unit b1 of a first color. The area ratio of the main pattern b1-a11 of each first-color light-emitting unit located in the non-edge region of the first display area 101a and at least one of the second display area 101b to the area ratio of the main pattern b1-a11 of each first-color light-emitting unit located in the third display area 101c is 1.9 to 2.1.

[0311] Optionally, the area of ​​the effective light-emitting area of ​​each first-color light-emitting unit b1 located in the non-edge area of ​​the first display area 101a and at least one of the second display area 101b is 2 to the area of ​​the effective light-emitting area of ​​each first-color light-emitting unit b1 located in the third display area 101c.

[0312] like Figures 1 to 37As shown, the main pattern b1-a11 of the first electrode a1 of the first color light-emitting unit b1 located in each display area and the shape of the effective light-emitting area are both hexagonal. Of course, reference... Figure 9 The main pattern of the light-emitting unit of the first color located in each display area (e.g. Figure 9 The shape of the effective light-emitting area of ​​the first main pattern 1021-1 and the second main pattern 1061-1 of the dummy electrode pattern 1062 are both elliptical. This application embodiment does not limit the shape of the main pattern of the first electrode a1 of the first color light-emitting unit in each display area. Furthermore, the area of ​​the connection pattern b1-a12 of the first color light-emitting unit located in the non-edge of the first display area 101a can be larger than the area of ​​the connection pattern b1-a12 of the first color light-emitting unit located in the third display area 101c to achieve connection with the pixel circuit f.

[0313] Optionally, the area ratio of the main pattern b2-a11 of each pair of second-color light-emitting units located in the non-edge region of the first display area 101a and at least one of the second display area 101b to the area ratio of the main pattern b2-a11 of each pair of second-color light-emitting units located in the third display area 101c is 1.5 to 2.5. For example, the area ratio of the main pattern b2-a11 of each pair of second-color light-emitting units located in the non-edge region of the first display area 101a and at least one of the second display area 101b to the area ratio of the main pattern b2-a11 of each pair of second-color light-emitting units located in the third display area 101c is 1.9 to 2.1.

[0314] Optionally, the ratio of the area of ​​the effective light-emitting area of ​​each second-color light-emitting unit in the non-edge area of ​​the first display area 101a and the second display area 101b to the area of ​​the effective light-emitting area of ​​each second-color light-emitting unit in the third display area 101c to b2 is 2.

[0315] Optionally, the area ratio of the main pattern b21-a11 of each first light-emitting unit block located in the non-edge region of the first display area 101a and at least one of the second display area 101b to the area ratio of the main pattern b21-a11 of each first light-emitting unit block located in the third display area 101c is 1.5 to 2.5. For example, the area ratio of the main pattern b22-a11 of each second light-emitting unit block located in the non-edge region of the first display area 101a and at least one of the second display area 101b to the area ratio of the main pattern b22-a11 of each second light-emitting unit block located in the third display area 101c is 1.5 to 2.5. For example, the area ratio of the main pattern b21-a11 of each first light-emitting unit block located in the non-edge region of the first display area 101a and at least one of the second display area 101b to the area ratio of the main pattern b21-a11 of each first light-emitting unit block located in the third display area 101c is 1.9 to 2.1. For example, the area of ​​the main pattern b22-a11 of each second light-emitting unit block located in the non-edge area of ​​the first display area 101a and at least one of the second display area 101b is 1.9 to 2.1 compared with the area of ​​the main pattern b22-a11 of each second light-emitting unit block located in the third display area 101c.

[0316] Optionally, the area of ​​the connection pattern b21-a12 of each first light-emitting unit block located in the non-edge area of ​​the first display area 101a is larger than the area of ​​the connection pattern b21-a12 of each first light-emitting unit block located in the third display area 101c. The area of ​​the connection pattern 2b22-a12 of each second light-emitting unit block located in the non-edge area of ​​the first display area 101a is larger than the area of ​​the connection pattern 2b22-a12 of each second light-emitting unit block located in the third display area 101c to facilitate connection with the pixel circuit pair f.

[0317] The area ratio of the main pattern b3-a11 of each third-color light-emitting unit located in the non-edge area of ​​the first display area 101a and at least one of the second display area 101b to the area ratio of the main pattern b3-a11 of each third-color light-emitting unit located in the third display area 101c is 1.5 to 2.5. For example, the area ratio of the main pattern b3-a11 of each third-color light-emitting unit located in the non-edge area of ​​the first display area 101a and at least one of the second display area 101b to the area ratio of the main pattern b3-a11 of each third-color light-emitting unit located in the third display area 101c is 1.9 to 2.1.

[0318] For example, the area of ​​the main pattern b3-a11 of each third-color light-emitting unit in the non-edge area of ​​the first display area 101a and the second display area 101b is 2 times the area of ​​the main pattern b3-a11 of each third-color light-emitting unit in the third display area 101c. For example, the area of ​​the effective light-emitting area of ​​each third-color light-emitting unit b3 in the non-edge area of ​​the first display area 101a and the second display area 101b is 2 times the area of ​​the effective light-emitting area of ​​each third-color light-emitting unit b3 in the third display area 101c.

[0319] For example, the area of ​​the connection pattern b3-a12 of each third color light-emitting unit located in the non-edge area of ​​the first display area 101a is larger than the area of ​​the connection pattern b3-a12 of each third color light-emitting unit located in the third display area 101c to achieve connection with the pixel circuit pair f.

[0320] The main pattern and effective light-emitting area of ​​the third-color light-emitting unit in each display area are both hexagonal. Of course, the main pattern and effective light-emitting area of ​​the third-color light-emitting unit in each display area are both elliptical. This application embodiment does not limit the shape of the main pattern of the first electrode a1 of the third-color light-emitting unit in each display area. In this application embodiment, for the sake of simplicity, the main pattern of the first electrode in the light-emitting unit is referred to as the main pattern of the light-emitting unit, and the connection pattern of the first electrode in the light-emitting unit is referred to as the connection pattern of the light-emitting unit.

[0321] like Figure 36 and Figure 37 As shown, the first electrode a1 of the light-emitting unit of the light-emitting unit group in the first display area 101a is directly connected to the pixel circuit pair f, so the area of ​​the connection pattern of the light-emitting unit in the first display area 101a is relatively large. However, the first electrode a1 of the light-emitting unit of the light-emitting unit group in the second display area is connected to the pixel circuit pair f of the first display area through the first connection line or the second connection line, so the area of ​​the connection pattern of the light-emitting unit in the second display area can be set to be relatively small.

[0322] Figure 38 This is a schematic diagram of the first electrode of each light-emitting unit in the two rows of light-emitting unit groups at the boundary between the first display area and the third display area provided in the embodiments of this application. Figures 1 to 38As shown, the shape and area of ​​the main patterns b1-a11 of the first-color light-emitting units in the row of light-emitting units adjacent to the third display area 101c in the column direction Y of the first display area 101a are approximately the same as those of the main patterns b1-a11 of the first-color light-emitting units in the third display area 101c. In this embodiment, the shape and area of ​​the main patterns of the first-color light-emitting units in the two rows of light-emitting units adjacent to each other in the column direction Y of the first and third display areas are set to be approximately the same. That is, the area of ​​the main pattern of the first-color light-emitting unit located at the edge of the first display area is designed to be different from the area of ​​the main pattern of the first-color light-emitting unit located in the non-edge area of ​​the first display area. This design increases the brightness of most of the first-color light-emitting units in the first display area to achieve a uniform full-screen display effect while preventing spatial conflicts between the main patterns of the two rows of light-emitting units.

[0323] Optionally, the area ratio of the main pattern b2-a11 of each pair of second-color light-emitting units in a row of light-emitting units adjacent to the third display area 101c in the row direction X of the first display area 101a to the area ratio of the main pattern b2-a11 of each pair of second-color light-emitting units in the third display area 101c is 0.9 to 1.1. In this embodiment, the areas of the main patterns of the second-color light-emitting units in two rows of light-emitting units adjacent to each other in the column direction Y of the first and third display areas are set to be approximately the same. That is, the area of ​​the main pattern of the second-color light-emitting units located at the edge of the first display area is designed to be different from the area of ​​the main pattern of the second-color light-emitting units located in the non-edge area of ​​the first display area. This can increase the brightness of most of the second-color light-emitting units in the first display area to achieve a uniform full-screen display effect while preventing spatial conflict between the main patterns of the two rows of light-emitting units.

[0324] like Figures 1 to 38 As shown, the shape of the main pattern of the two second-color light-emitting units included in the second-color light-emitting unit pair b2 in the third display area 101c is different from the shape of the two main patterns of the second-color light-emitting unit pairs b2 in the row of light-emitting units adjacent to each other in the row direction X in the first display area 101a and the third display area 101c.

[0325] In this embodiment, the size of the pixel limiting layer gap (PDL gap) between two adjacent light-emitting units in the non-edge region of the first display area is approximately the same as the size of the PDL gap between two adjacent light-emitting units in the edge region of the first display area, so as to ensure the uniformity of the image light displayed in the first display area.

[0326] like Figures 1 to 38As shown, the main pattern shape of the two second-color pixel units included in b2 within the third display area 101c is a pentagon. Alternatively, the main pattern shape of the two second-color pixel units included in b2 within the third display area 101c is an ellipse. This embodiment does not limit the shape of the main pattern of the first electrode a1 of the second-color pixel unit.

[0327] In the case where the main pattern shape of the two second-color pixel units included in the second-color pixel unit pair b2 within the third display area 101c is pentagonal, refer to Figure 38 Each pentagon includes a first side 1 extending along the row direction X, two second sides 2 extending along the column direction Y, and two third sides 3 connecting the two second sides 2. The two third sides 3 intersect to form a sharp angle. The two sharp angles of the main patterns of the two second-color light-emitting units are close to each other. The main patterns 2021 of each pair of second-color light-emitting units b2 in the row of light-emitting units adjacent to the third display area 101c in the column direction Y of the first display area 101a include a fourth side 4 extending along the row direction X, two fifth sides 5 extending along the column direction Y, two sixth sides 6 connecting the two fifth sides 5, and a seventh side 7 connecting the two sixth sides 6. The two seventh sides 7 of the main patterns of the two second-color sub-pixels are close to each other.

[0328] like Figures 35 to 38 As shown, the length of the second side 2 of the main pattern of the second color light-emitting unit in the third display area 101c is less than the length of the fifth side 5 of the main pattern of the second color light-emitting unit at the edge of the first display area 101a, so as to ensure that the area of ​​the main pattern of the second color light-emitting unit in the third display area 101c is approximately equal to the area of ​​the main pattern of the second color light-emitting unit at the edge of the first display area.

[0329] For example, such as Figures 35 to 38 As shown, when the area of ​​the main pattern of the second-color light-emitting unit at the edge of the first display area 101a is set to be the same as the area of ​​the main pattern of the second-color light-emitting unit in the third display area 101c, in order to ensure that the PDL gap between the second-color light-emitting unit and the first-color light-emitting unit (or the third-color light-emitting unit) at the edge of the first display area 101a is consistent with the PDL gap between the second-color light-emitting unit and the first-color light-emitting unit (or the third-color light-emitting unit) in the non-edge area of ​​the first display area 101a, the center line connecting the two main patterns of each pair of second-color light-emitting units in the row of light-emitting units adjacent to the third display area 101c in the row direction X is not parallel to the center line connecting the two main patterns of each pair of second-color light-emitting units in the third display area.

[0330] When the area of ​​the main pattern of the second-color light-emitting unit at the edge of the first display area 101a is set to be the same as the area of ​​the main pattern of the second-color light-emitting unit in the third display area 101c, in order to ensure that the PDL gap between the second-color light-emitting units and the first-color light-emitting units (or the third-color light-emitting units) at the edge of the first display area 101a is consistent with the PDL gap between the second-color light-emitting units and the first-color light-emitting units (or the third-color light-emitting units) in the non-edge area of ​​the first display area 101a, if the shape of the main pattern of the second-color light-emitting unit at the edge of the first display area 101a is a pentagon including sharp corners, it will spatially conflict with the connection pattern of the first-color light-emitting units (or the third-color light-emitting units). Therefore, the shape of the main pattern of the second-color light-emitting unit at the edge of the first display area no longer includes sharp corners. At this point, in order to ensure that the area of ​​the main pattern of the second color light-emitting unit at the edge of the first display area is approximately the same as the area of ​​the main pattern of the second color light-emitting unit at the edge of the third display area, it is necessary to compensate for the shape of the main pattern of the second color light-emitting unit at the edge of the first display area, that is, to add two sixth sides 6 and a seventh side 7 connecting the two sixth sides 6, so as to achieve that the area of ​​the main pattern of the second color light-emitting unit at the edge of the first display area is equal to the area of ​​the second color light-emitting unit at the edge of the third display area without spatial conflict.

[0331] like Figures 1 to 38 As shown, the shape and area of ​​the main patterns b3-a11 of the third-color light-emitting units in the adjacent row of light-emitting units in the first display area 101a and the third display area 101c in the column direction Y are approximately the same as those of the main patterns b3-a11 of the third-color light-emitting units in the third display area 101c. In this embodiment, the shape and area of ​​the main patterns of the third-color light-emitting units in the two adjacent rows of light-emitting units in the first and third display areas in the column direction Y are set to be approximately the same. That is, the area of ​​the main pattern of the third-color light-emitting unit located at the edge of the first display area is designed to be different from the area of ​​the main pattern of the third-color light-emitting unit located in the non-edge area of ​​the first display area. This can increase the brightness of most of the third-color light-emitting units in the first display area to achieve a uniform full-screen display effect while preventing spatial conflicts between the main patterns of the two rows of light-emitting units.

[0332] Figure 39 This is a schematic diagram of the first electrode of each light-emitting unit in the two rows of light-emitting unit groups at the boundary between the first display area and the third display area provided in the embodiments of this application. Figure 39As shown, in a column of light-emitting units adjacent to the third display area 101c in the row direction X of the first display area 101a, the light-emitting unit pair b2 of the second color is located on the side of the light-emitting unit b1 of the first color and the light-emitting unit b3 of the third color close to the third display area 101c. The area and shape of the main pattern b2-a11 of each light-emitting unit pair of the second color in this column of light-emitting units are approximately the same as the area and shape of the main pattern b2-a11 of each light-emitting unit pair of the second color in the third display area 101c. In this embodiment, the shape and area of ​​the main patterns of each pair of second-color light-emitting units in two adjacent columns of light-emitting units in the first display area and the third display area in the row direction X are set to be approximately the same. That is, the area of ​​the main pattern of the pair of second-color light-emitting units located at the edge of the first display area is designed to be different from the area of ​​the pair of second-color light-emitting units located in the non-edge area of ​​the first display area. This can increase the brightness of most of the second-color light-emitting units in the first display area to achieve a uniform full-screen display effect, while preventing the main patterns of the two columns of light-emitting units from conflicting in space.

[0333] A second pixel circuit group 105 is disposed between two adjacent first light-emitting unit groups 102 arranged along the column direction Y. Therefore, no light-emitting unit group is disposed at the interval between two adjacent first light-emitting unit groups 102 arranged along the column direction Y. In the third display area 101c, a gap is disposed between two adjacent third light-emitting unit groups in a column of multiple third light-emitting unit groups close to the first display area 101a in the row direction X. This gap includes a third pixel circuit group that is not connected to the light-emitting unit group. Furthermore, along the row direction X, this third pixel circuit group and the light-emitting unit groups in the column of first light-emitting unit groups 102 adjacent to the third display area 101c are located on the same straight line. Therefore, the brightness distribution of the third display area and the first display area in the row direction X can be balanced.

[0334] Optionally, in a column of light-emitting units adjacent to the third display area 101c in the row direction X in the first display area 101a, the area ratio of the main pattern b1-a11 of each first-color light-emitting unit to the area ratio of the main pattern b1-a11 of each first-color light-emitting unit located in the third display area 101c is 1.5 to 2.5. For example, in a column of light-emitting units adjacent to the third display area 101c in the row direction X in the first display area 101a, the area ratio of the effective light-emitting area of ​​each first-color light-emitting unit b1 to the area ratio of the effective light-emitting area of ​​each first-color light-emitting unit b1 located in the third display area 101c is 2.

[0335] In this embodiment, while ensuring that the main patterns of the light-emitting units in a row of adjacent light-emitting units in the first display area and the third display area do not conflict in space, the shape and area of ​​the main pattern of the first color light-emitting unit located at the edge of the first display area are approximately the same as the shape and area of ​​the main pattern of the first color light-emitting unit located in the non-edge area of ​​the first display area. This can increase the brightness of most of the first color light-emitting units in the first display area to achieve a uniform full-screen display effect while preventing the main patterns of the two rows of light-emitting units from conflicting in space.

[0336] Optionally, in a row-direction X-column group of light-emitting units adjacent to the third display area 101c in the first display area 101a, the area ratio of the main pattern b3-a11 of each third-color light-emitting unit to the area ratio of the main pattern b3-a11 of each third-color light-emitting unit in the third display area 101c is 1.5 to 2.5. For example, in a row-direction X-column group of light-emitting units adjacent to the third display area 101c in the first display area 101a, the area ratio of the main pattern b3-a11 of each third-color light-emitting unit to the area ratio of the main pattern b3-a11 of each third-color light-emitting unit in the third display area 101c is 1.9 to 2.1.

[0337] Optionally, in a column of light-emitting units adjacent to the third display area 101c in the row direction X of the first display area 101a, the area of ​​the effective light-emitting area of ​​each third-color light-emitting unit b3 is 2 times the area of ​​the effective light-emitting area of ​​each third-color light-emitting unit b3 in the third display area 101c. In this embodiment, while ensuring that the main patterns of the light-emitting units in a column of light-emitting units adjacent to the third display area in the row direction X do not conflict spatially, the shape and area of ​​the main patterns of the third-color light-emitting units located at the edge of the first display area are approximately the same as the shape and area of ​​the main patterns of the third-color light-emitting units located in the non-edge area of ​​the first display area. This can increase the brightness of most of the third-color light-emitting units in the first display area to achieve a uniform full-screen display effect while preventing spatial conflicts between the main patterns of the two columns of light-emitting units.

[0338] Figure 40 yes Figure 3 Cross-sectional view along the direction from A1 to A2. Figure 41 yes Figure 7 Cross-sectional view along the direction from B1 to B2. (Combined with...) Figure 40 and Figure 41As can be seen, the display panel 10 may include a fourth insulating layer and a fifth insulating layer. The fourth insulating layer is located on one side of the pixel circuit film layer, and a plurality of first connection traces 107 are located on the side of the fourth insulating layer away from the pixel circuit film layer. The fifth insulating layer is located on the side of the plurality of first connection traces 107 away from the fourth insulating layer. The first electrode a1 of each light-emitting unit is located on the side of the fifth insulating layer away from the plurality of first connection traces 107, and the pixel defining layer a4 is located on the side of the first electrode a1 away from the fifth insulating layer.

[0339] The aforementioned pixel circuit film layer refers to the film layer included in the pixel circuit, for example, reference... Figure 40 and Figure 41 The pixel circuit film layer includes an active semiconductor layer 01, a gate insulating layer, a first conductive layer 02, a first insulating layer, a second conductive layer 03, a second insulating layer, a source / drain metal layer 04, and a third insulating layer, which are sequentially stacked along the side away from the substrate 101.

[0340] in, Figure 41 In the first conductive layer 02, the third and fifth squares from left to right are the second terminal CC2 of capacitor C, and the fourth square is the light-emitting control signal line. In the second conductive layer 03, the second and fifth squares from left to right are blocking blocks, and the third and fourth squares are the first terminal CC1 of capacitor C. In the source-drain metal layer 04, the first, fourth, seventh, tenth, thirteenth, sixteenth, nineteenth, twenty-first, and twenty-fourth squares from left to right are the signal lines for the output voltage signal VDD. In the source-drain metal layer 04, the fifth, eighth, eleventh, fourteenth, seventeenth, twentieth, twenty-second, and twenty-fifth squares from left to right are the data signal Data.

[0341] Figure 42 In the first conductive layer 02, the second and sixth squares from left to right are the light emission control signal lines, the third square is the reset control signal line, and the fifth square is the second terminal CC2 of capacitor C. In the second conductive layer 03, the second square from left to right is the blocking block, the third square is the connection block, the fourth square is the reset signal Vinit, and the fifth square is the first terminal CC1 of capacitor C. In the source-drain metal layer 04, the third, sixth, eleventh, and fourteenth squares from left to right are the data signal Data. In the source-drain metal layer 04, the fourth, seventh, tenth, and thirteenth squares from left to right are the signal lines for the output voltage signal VDD.

[0342] In summary, this application provides a display panel in which a plurality of second pixel circuit groups located in a first display area include a first type of second pixel circuit group away from the second display area and a second type of second pixel circuit group closer to the second display area. The first type of second pixel circuit group is connected to a first type of second light-emitting unit group located in the second display area but away from the first display area via a first connection trace, and the second type of second pixel circuit group is connected to a second type of second light-emitting unit group located in the second display area but closer to the first display area via a second connection trace. Since the solution provided in this application can also provide driving signals to the second type of second light-emitting unit group via a second connection trace located on a different layer than the first connection trace, the number of second light-emitting unit groups that can be set in the second display area can be increased without increasing the number of first connection traces, thereby ensuring the display effect of the second display area in the display panel.

[0343] Figure 42 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. (Reference) Figure 42 As can be seen, the display device may include a power supply component 20 and the display panel 10 provided in the above embodiments. The power supply component 20 can be used to supply power to the display panel 10. The display device may be a curved display device.

[0344] Optionally, the display device can be any product or component with display and fingerprint recognition functions, such as an organic light-emitting diode (OLED) display panel, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame or navigator.

[0345] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes: A substrate having adjacent first and second display areas; A plurality of first light-emitting unit groups, wherein the plurality of first light-emitting unit groups are located in the first display area; A plurality of first pixel circuit groups are located in the first display area, and each first pixel circuit group is connected to a first light-emitting unit group. A plurality of second light-emitting unit groups are located in the second display area. The plurality of second light-emitting unit groups include: at least one first type of second light-emitting unit group and at least one second type of second light-emitting unit group. The at least one second type of second light-emitting unit group is closer to the first display area than the at least one first type of second light-emitting unit group. A plurality of second pixel circuit groups are located in the first display area. The plurality of second pixel circuit groups include: at least one first type of second pixel circuit group and at least one second type of second pixel circuit group. The at least one second type of second pixel circuit group is closer to the second display area than the at least one first type of second pixel circuit group. Multiple dummy electrode pattern groups are located in the first display area. The multiple dummy electrode pattern groups include: at least one first pattern group and at least one second pattern group. The at least one second pattern group is closer to the second display area than the at least one first pattern group. Multiple first connection traces are located on different layers from the multiple dummy electrode pattern groups. One end of each first connection trace is connected to a first type of second light-emitting unit group, and the other end is connected to a first type of second pixel circuit group through a first pattern group. In addition, there are multiple second connection traces, which are located on different layers from the multiple first connection traces. One end of each second connection trace is connected to a second type of second light-emitting unit group, and the other end is connected to a second type of second pixel circuit group through a second pattern group. Each first light-emitting unit group includes multiple first light-emitting units, and each first light-emitting unit includes a first electrode, a light-emitting layer, and a second electrode stacked sequentially along a direction away from the substrate. The dummy electrode pattern group includes multiple dummy electrode patterns, and the multiple dummy electrode patterns in one dummy electrode pattern group correspond one-to-one with the multiple first light-emitting units in one first light-emitting unit group. The dummy electrode pattern has the same shape and area as the first electrode in the corresponding first light-emitting unit, and the dummy electrode pattern is located on the same layer as the first electrode.

2. The display panel according to claim 1, characterized in that, The orthographic projection of the dummy electrode pattern group on the substrate at least partially overlaps with the orthographic projection of at least one second pixel circuit group on the substrate, and the orthographic projection of the dummy electrode pattern group on the substrate does not overlap with the orthographic projection of any of the first light-emitting unit groups on the substrate.

3. The display panel according to claim 1, characterized in that, Each of the second light-emitting unit groups includes a plurality of second light-emitting units, and the second light-emitting unit also includes a first electrode, a light-emitting layer and a second electrode stacked sequentially along a direction away from the substrate. The number of dummy electrode patterns in one dummy electrode pattern group is the same as the number of second light-emitting units in one second light-emitting unit group.

4. The display panel according to claim 3, characterized in that, The display panel further includes a pixel defining layer located between the first electrode and the light-emitting layer; The pixel defining layer has multiple openings, one of which exposes a first electrode of a light-emitting unit, and the orthographic projection of the multiple openings on the substrate does not overlap with the orthographic projection of any of the dummy electrode patterns on the substrate.

5. The display panel according to claim 3, characterized in that, A first light-emitting unit group includes: a first light-emitting unit of a first color, two first light-emitting units of a second color, and a first light-emitting unit of a third color; A second light-emitting unit group includes: a second light-emitting unit of a first color, two second light-emitting units of a second color, and a second light-emitting unit of a third color.

6. The display panel according to claim 5, characterized in that, The distance between the centers of two adjacent first light-emitting units of the first color in the first display area along the row direction is equal to the distance between the centers of two adjacent second light-emitting units of the first color in the second display area along the row direction. The distance between the centers of two adjacent first light-emitting units of the second color in the first display area along the row direction is equal to the distance between the centers of two adjacent second light-emitting units of the second color in the second display area along the row direction. The distance between the centers of two adjacent first light-emitting units of the third color in the first display area along the row direction is equal to the distance between the centers of two adjacent second light-emitting units of the third color in the second display area along the row direction.

7. The display panel according to claim 5, characterized in that, The area of ​​the orthographic projection of the opening of the first light-emitting unit of the first color in the first display area onto the substrate is equal to the area of ​​the orthographic projection of the opening of the second light-emitting unit of the first color in the second display area onto the substrate, and the area of ​​the orthographic projection of the first electrode of the first light-emitting unit of the first color in the first display area onto the substrate is greater than the area of ​​the orthographic projection of the first electrode of the second light-emitting unit of the first color in the second display area onto the substrate. The area of ​​the orthographic projection of the opening of the first light-emitting unit of the second color in the first display area onto the substrate is equal to the area of ​​the orthographic projection of the opening of the second light-emitting unit of the second color in the second display area onto the substrate, and the area of ​​the orthographic projection of the first electrode of the first light-emitting unit of the second color in the first display area onto the substrate is greater than the area of ​​the orthographic projection of the first electrode of the second light-emitting unit of the second color in the second display area onto the substrate. The area of ​​the orthographic projection of the opening of the first light-emitting unit of the third color in the first display area onto the substrate is equal to the area of ​​the orthographic projection of the opening of the second light-emitting unit of the third color in the second display area onto the substrate, and the area of ​​the orthographic projection of the first electrode of the first light-emitting unit of the third color in the first display area onto the substrate is greater than the area of ​​the orthographic projection of the first electrode of the second light-emitting unit of the third color in the second display area onto the substrate.

8. The display panel according to claim 1, characterized in that, The first electrode of the first light-emitting unit in the first light-emitting unit group includes: a first main pattern and a first connection pattern connected to the first main pattern, at least a portion of the first main pattern is in contact with the light-emitting layer of the first light-emitting unit, and the first connection pattern is connected to the first pixel circuit group. The dummy electrode pattern includes: a second main pattern, and a second connection pattern and a third connection pattern respectively connected to the second main pattern. The second main pattern does not contact the light-emitting layer of any of the first light-emitting units, and the second connection pattern is connected to the second pixel circuit group. The third connection pattern is connected to the second light-emitting unit group through a first connection trace or a second connection trace.

9. The display panel according to claim 8, characterized in that, The first electrode of the first light-emitting unit further includes a fourth connecting pattern connected to the first main body pattern; The orthographic projection of the first main pattern of the first electrode in the first light-emitting unit onto the substrate has the same shape and area as the orthographic projection of the second main pattern of the dummy electrode pattern corresponding to the first light-emitting unit onto the substrate. The orthographic projection of the first connection pattern of the first electrode in the first light-emitting unit onto the substrate has the same shape and area as the orthographic projection of the second connection pattern of the dummy electrode pattern corresponding to the first light-emitting unit onto the substrate. The orthographic projection of the fourth connection pattern of the first electrode in the first light-emitting unit onto the substrate has the same shape and area as the orthographic projection of the third connection pattern of the dummy electrode pattern corresponding to the first light-emitting unit onto the substrate.

10. The display panel according to claim 9, characterized in that, The orthographic projection of the first connection pattern on the substrate does not overlap with the orthographic projection of the plurality of first connection traces on the substrate, and the orthographic projection of the fourth connection pattern on the substrate at least partially overlaps with the orthographic projection of the plurality of first connection traces on the substrate. The orthographic projection of the second connection pattern on the substrate does not overlap with the orthographic projection of the plurality of first connection traces on the substrate, and the orthographic projection of the third connection pattern on the substrate at least partially overlaps with the orthographic projection of the plurality of first connection traces on the substrate.

11. The display panel according to claim 8, characterized in that, The first light-emitting units corresponding to the two target dummy electrode patterns in two adjacent first pattern groups along the row direction have the same color, and the third connection patterns of the two target dummy electrode patterns are respectively connected to the second light-emitting unit group through a first connection trace; In the two target dummy electrode patterns, the line connecting the connecting portion of the third connecting pattern in one target dummy electrode pattern and the connecting portion of the third connecting pattern in the other target dummy electrode pattern intersects the row direction, and the connecting portion of the third connecting pattern is used to connect with the first connecting trace.

12. The display panel according to claim 1, characterized in that, The first pixel circuit group includes a plurality of first pixel circuit units, each first pixel circuit unit including at least a first pixel circuit and a second pixel circuit, and at least two pixel circuits in the first pixel circuit unit are configured to be electrically connected to the first electrode of the same first light-emitting unit in the first light-emitting unit group.

13. The display panel according to claim 12, characterized in that, The first electrode of the first light-emitting unit includes a first connection pattern comprising: a first main body connection portion extending along the target direction and two first ends located at both ends of the first main body connection portion; The two first ends are electrically connected to the first pixel circuit and the second pixel circuit, respectively, and the target direction is approximately parallel to the row direction.

14. The display panel according to claim 1, characterized in that, The second pixel circuit group includes a plurality of second pixel circuit units, each second pixel circuit unit including at least a third pixel circuit and a fourth pixel circuit, and at least two pixel circuits in the second pixel circuit unit are configured to be electrically connected to the same dummy electrode pattern.

15. The display panel according to claim 14, characterized in that, The virtual electrode pattern includes a second connection pattern comprising: a second main body connection portion extending along the target direction and two second ends located at both ends of the second main body connection portion; The two second ends are electrically connected to the third pixel circuit and the fourth pixel circuit, respectively, and the target direction is approximately parallel to the row direction.

16. The display panel according to any one of claims 1 to 15, characterized in that, The plurality of second connection traces are located on the same layer as the dummy electrode pattern group.

17. The display panel according to any one of claims 1 to 15, characterized in that, The connection at the other end of the plurality of first connection traces is parallel to the edge of the first display area away from the second display area, and the distance between the connection at the other end of the plurality of first connection traces and the edge of the first display area away from the second display area is less than a distance threshold.

18. The display panel according to claim 17, characterized in that, The connecting lines at the other ends of the plurality of first connecting lines are generally parallel to the column direction of the edge of the first display area away from the second display area.

19. The display panel according to claim 18, characterized in that, The other end of the plurality of first connection traces is collinear with the edge of the first display area away from the second display area.

20. The display panel according to any one of claims 1 to 15, characterized in that, The substrate further includes a third display area located on the same side as the first display area and the second display area, and the display panel further includes a plurality of third light-emitting unit groups and a plurality of third pixel circuit groups located in the third display area; Each of the third pixel circuit groups is connected to a third light-emitting unit group, and the density of the plurality of third light-emitting unit groups is greater than the density of the plurality of first light-emitting unit groups and greater than the density of the plurality of second light-emitting unit groups.

21. The display panel according to claim 20, characterized in that, The substrate includes: two first display areas and one second display area, wherein the second display area is rectangular; At least one edge of the rectangle extending along the row direction is connected to the third display area, and the two edges of the rectangle extending along the column direction are connected to the two first display areas respectively.

22. The display panel according to claim 21, characterized in that, The first display area is rectangular; the length of any edge of the first display area ranges from 0.1 mm to 20 mm. The length of any edge of the second display area ranges from 0.2 mm to 10 mm.

23. The display panel according to any one of claims 1 to 15, characterized in that, The display panel also includes: multiple data cables; At least a portion of the orthographic projection of at least one target data line located in the second display area of ​​the plurality of data lines on the substrate is located in the region of the second display area close to the first display area.

24. A display device, characterized in that, The display device includes: a power supply component and a display panel as described in any one of claims 1 to 23; The power supply component is used to supply power to the display panel.

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