This includes stacked die assemblies with indirect bonding of double-sided dies and methods for forming the same.

Abstract

Multiple bonding units are provided, each of which includes a corresponding front die and a back die. Two dies in each bonding unit may be a memory die and a logic die configured to control the operation of memory elements within the memory die. Alternatively, the two dies may be memory dies. The multiple bonding units may be attached such that the front external bonding pads have an upward-facing physical exposed surface and the back external bonding pads of each bonding unit have a downward-facing physical exposed surface. A first set of bonding leads may connect a pair of corresponding front external bonding pads, and a second set of bonding leads may connect a pair of corresponding back external bonding pads.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Nonprovisional Patent Application No. 16 / 886,164, filed May 28, 2020, and U.S. Nonprovisional Patent Application No. 16 / 886,221, filed May 28, 2020, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure generally relates to the field of semiconductor devices, and more particularly to stacked die assemblies including double-sided die indirect interconnection and methods for forming the same. Background Technology

[0004] Multiple semiconductor dies can be stacked together to form a stacked die assembly. Power signals can be transmitted through each of the semiconductor dies in the stacked die assembly. However, power signals carry high voltages, and routing power signals near logic circuitry, including noise-sensitive devices such as sense amplifiers, can increase the noise level in the logic circuitry. Furthermore, as the number of semiconductor dies in a stacked die assembly increases, the number of inter-die electrical connections also increases. Summary of the Invention

[0005] According to an aspect of this disclosure, a structure including a stacked die assembly is provided. The stacked die assembly includes: a vertically stacked plurality of bonding units, wherein each bonding unit includes: a memory die, the memory die including a memory-side die-to-die bonding pad and a memory-side external bonding pad located on opposite main surfaces of the memory die; and a logic die, the logic die including logic circuitry configured to control the operation of the memory die and including a logic-side die-to-die bonding pad and a logic-side external bonding pad located on opposite main surfaces of the logic die, wherein: the logic-side die-to-die bonding pad is bonded to the memory-side die-to-die bonding pad. The corresponding memory-side die-to-die bonding pad in the die-to-die bonding pad; and wherein the memory-side external bonding pad and the logic-side external bonding pad include an upward-facing set of external bonding pads and a downward-facing set of external bonding pads, the upward-facing set of external bonding pads having an upward-facing physical exposed surface, and the downward-facing set of external bonding pads having a downward-facing physical exposed surface; a first set of bonding leads connecting the upward-facing external bonding pad; and a second set of bonding leads connecting the downward-facing external bonding pad.

[0006] According to another aspect of this disclosure, a method for forming a structure including a stacked die assembly is provided. The method includes: providing a plurality of bonding units, wherein each bonding unit includes a memory die and a logic die, the memory die including a memory-side die-in-die bonding pad and a memory-side external bonding pad located on opposite main surfaces of the memory die, the logic die including logic circuitry configured to control operation of the memory die and including a logic-side die-in-die bonding pad and a logic-side external bonding pad located on opposite main surfaces of the logic die; forming a vertical stack of the plurality of bonding units by attaching the plurality of bonding units to each other, such that the memory of the plurality of bonding units... The side external bonding pads and the logic side external bonding pads form an upward-facing external bonding pad set and a downward-facing external bonding pad set, the upward-facing external bonding pad set having an upward-facing physical exposed surface and the downward-facing external bonding pad set having a downward-facing physical exposed surface; a first bonding lead set is formed, the first bonding lead set connecting a pair of corresponding upward-facing external bonding pads in the upward-facing external bonding pad set; and a second bonding lead set is formed, the second bonding lead set connecting a pair of corresponding downward-facing external bonding pads in the downward-facing external bonding pad set.

[0007] According to another aspect of this disclosure, a structure including a stacked die assembly is provided. The stacked die assembly includes: a vertically stacked plurality of bonding units, wherein each bonding unit includes a corresponding front-side semiconductor die and a corresponding back-side semiconductor die, the corresponding front-side semiconductor die including a front-side external bonding pad, the corresponding back-side semiconductor die including a back-side external bonding pad, wherein the corresponding back-side semiconductor die is bonded to the corresponding front-side semiconductor die, and wherein the front-side external bonding pad of each bonding unit has an upward-facing physical exposed surface, and the back-side external bonding pad of each bonding unit has a downward-facing physical exposed surface; a first bonding lead set connecting the front-side external bonding pad; and a second bonding lead set connecting the back-side external bonding pad.

[0008] According to another aspect of this disclosure, a method for forming a structure including a stacked die assembly is provided. The method includes: providing a plurality of bonding units, wherein each bonding unit includes a respective front-side semiconductor die and a respective back-side semiconductor die, the respective front-side semiconductor die including a front-side external bonding pad, the respective back-side semiconductor die including a back-side external bonding pad, wherein the back-side semiconductor die is bonded to the respective front-side semiconductor die; forming a vertical stack of the plurality of bonding units by attaching the plurality of bonding units to each other, such that the front-side external bonding pad of each bonding unit has an upward-facing physical exposed surface, and the back-side external bonding pad of each bonding unit has a downward-facing physical exposed surface; forming a first set of bonding leads connecting a pair of respective front-side external bonding pads; and forming a second set of bonding leads connecting a pair of respective back-side external bonding pads. Attached Figure Description

[0009] Figure 1A This is a schematic vertical cross-sectional view of a memory die after the formation of the inter-die pad on the memory side, according to a first embodiment of the present disclosure.

[0010] Figure 1B yes Figure 1A The layout of the memory die.

[0011] Figure 2A This is a schematic vertical cross-sectional view of a logic die after the formation of the intermolecular bonding pad, according to a first embodiment of the present disclosure.

[0012] Figure 2B yes Figure 2A The layout of the memory die.

[0013] Figure 3 yes Figure 1A memory chips and Figure 2A A vertical cross-sectional view of the bonding assembly of the logic die.

[0014] Figure 4 This is a vertical cross-sectional view of the bonding assembly of the memory die and logic die after the formation of the external bonding pad on the memory side, according to a first embodiment of the present disclosure.

[0015] Figure 5A This is a vertical cross-sectional view of the region of the bonding unit of the semiconductor die and the logic die after the formation of the logic-side external bonding pad, according to a first embodiment of the present disclosure.

[0016] Figure 5B yes Figure 5A Plan view of the joint unit.

[0017] Figure 6 It is based on the first embodiment of this disclosure. Figure 5A and Figure 5B Vertical cross-sectional view of the joint unit.

[0018] Figure 7 This is a vertical cross-sectional view of a first exemplary structure comprising a plurality of bonding units and a mounting substrate after attachment bonding leads, according to a first embodiment of the present disclosure.

[0019] Figure 8A This is a vertical cross-sectional view of a memory die after attachment processing substrate according to a second embodiment of the present disclosure.

[0020] Figure 8B yes Figure 8A A plan view of the memory die.

[0021] Figure 9A This is a vertical cross-sectional view of a bonding unit including a front semiconductor die and a back semiconductor die according to a second embodiment of the present disclosure.

[0022] Figure 9B yes Figure 9A A partial perspective top view of the joining unit.

[0023] Figure 9C yes Figure 9A A partial perspective inverted view of the joining unit.

[0024] Figure 10 This is a vertical cross-sectional view of a second exemplary structure comprising a plurality of bonding units and a mounting substrate after attachment bonding leads, according to a second embodiment of the present disclosure. Detailed Implementation

[0025] This disclosure relates to a stacked die assembly including inter-die connections on both sides and a method of forming the same, various aspects of which are described in detail below. Thus, the stacked die assembly including multiple dies accommodates inter-die electrical connections without occupying additional wafer space used by semiconductor devices, while minimizing noise and signal interference as well as parasitic coupling.

[0026] The accompanying drawings are not to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that no repetition of an element exists. Numbers such as “first,” “second,” and “third” are used only to identify similar elements and may be used differently throughout the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0027] As used herein, a “layer” refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Additionally, a layer may be a region of thickness less than that of a uniform or non-uniform continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0028] As used herein, the first and second surfaces are “vertically coincident” if the second surface is above or below the first surface and if there is a vertical or substantially vertical plane that includes both the first and second surfaces. A substantially vertical plane is a plane that extends in a straight line along an angle less than 5 degrees from the vertical direction. The vertical or substantially vertical plane is straight along the vertical or substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical or substantially vertical direction.

[0029] As used herein, a “memory level” or “memory array level” refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) that includes the topmost surface of the memory element array and a second horizontal plane that includes the bottommost surface of the memory element array. As used herein, a “through-stack” element refers to an element that extends vertically through the memory level.

[0030] As used in this article, "semiconductor material" refers to a material with a conductivity of 1.0 × 10⁻⁶ m / s. -5 S / m to 1.0×10 5 Materials with electrical conductivity in the range of S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the absence of electrical dopants in the presence of S / m. -5 Materials with electrical conductivity ranging from S / m to 1.0 S / m can be produced by appropriate doping with electrodopersive agents, exhibiting conductivity ranging from 1.0 S / m to 1.0 × 10⁻⁶. 5 Doped materials with electrical conductivity in the range of S / m. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band of the band structure, or an n-type dopant that adds electrons to the conduction band of the band structure. As used herein, “conductive material” refers to a material with conductivity greater than 1.0 × 10⁻⁶ S / m. 5 Materials with a conductivity of S / m. As used herein, "insulating material" or "dielectric material" refers to a material with a conductivity of less than 1.0 × 10⁻⁶ S / m. -5Materials with an electrical conductivity of S / m. As used herein, "heavily doped semiconductor material" refers to a material doped with an electrically conductive agent at a sufficiently high atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0 × 10⁻⁶) when formed into a crystalline material or converted into a crystalline material by an annealing process (e.g., starting from an initial amorphous state). 5 Semiconductor materials with a conductivity of S / m. "Doped semiconductor materials" can be heavily doped semiconductor materials, or can include those exhibiting a conductivity of 1.0 × 10⁻⁶ S / m. -5 S / m to 1.0×10 5 Semiconductor materials with electrical dopant concentrations (i.e., p-type and / or n-type dopant) in the range of S / m. "Intrinsic semiconductor material" refers to a semiconductor material undoped with electrical dopants. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. Doped semiconductor materials can be semiconductor or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material comprising at least one metallic element. All conductivity measurements were performed under standard conditions.

[0031] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed over a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolithic" refers to the fact that the layers of each level of the array are deposited directly on the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167 entitled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory level prior to bonding, but since the memory levels are initially formed over separate substrates, such a memory is not a true monolithic three-dimensional memory array. The substrate may include integrated circuits, such as driver circuitry for the memory device, fabricated thereon.

[0032] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are joined together, for example, by flip-chip bonding or another chip-to-chip bonding method. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of executing as many external commands simultaneously as the total number of planes therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. When the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each storage block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for read operations.

[0033] refer to Figure 1A and Figure 1B This illustration shows a memory die 900 according to a first embodiment of the present disclosure. The memory die 900 includes a memory die substrate 908. The memory die 900 also includes a memory die semiconductor device 920 covering the memory die substrate 908, a memory die dielectric layer 960 covering the memory die semiconductor device 920, and a memory die metal interconnect structure 980 embedded in the memory die dielectric layer 960. In one embodiment, the memory die substrate 908 may be a commercially available silicon wafer with a thickness ranging from 500 micrometers to 1 mm. The memory die 900 may be disposed in a wafer comprising a two-dimensional array of memory dies 900.

[0034] Generally, the memory die semiconductor device 920 may include any semiconductor memory device known in the art. In one embodiment, the memory die 900 may include a three-dimensional memory array, such as a three-dimensional NAND memory array. The three-dimensional memory device may include various device regions that encompass various subsets of the memory die semiconductor device 920. For example, the memory die 900 may include a plurality of planes that contain respective three-dimensional memory arrays. Each plane may include a memory array region 100 and at least one contact region 200.

[0035] In one embodiment, a substrate via cavity may be formed as the upper portion of a memory die substrate 908. Each substrate via cavity may be filled with a dielectric spacer 914 and a through-substrate via structure 916. Each through-substrate via structure 916 provides a vertical conductive path after subsequent thinning of the memory die substrate 908. Each through-substrate via structure 916 may be electrically connected to a corresponding memory-side metal interconnect structure 980 using a through-memory-level via structure 84. According to aspects of this disclosure, the through-substrate via structures 916 of the memory die 900 may be arranged in a row or in multiple rows near one edge of the memory die 900. In one embodiment, the memory die 900 may have a straight edge, and the through-substrate via structures 916 of the memory die 900 may be arranged in a row or in multiple rows near the straight edge of the memory die 900 and laterally spaced from the straight edge by a uniform lateral offset distance.

[0036] In one embodiment, the memory die semiconductor device 920 may include a two-dimensional array of vertically alternating stacks of insulating layers 32 and conductive layers 46, and memory openings extending vertically through the vertically alternating stacks (32, 46). The conductive layers 46 may contain word lines of a three-dimensional NAND memory device. Memory opening fill structures 58 may be formed within each memory opening. Each memory opening fill structure 58 may include a memory film and a vertical semiconductor channel contacting the memory film. The memory film may include a barrier dielectric, a tunneling dielectric, and a charge storage material located between the barrier dielectric and the tunneling dielectric. The charge storage material may include a charge trapping layer, such as a silicon nitride layer; or multiple discrete charge trapping regions, such as floating gates or discrete portions of a charge trapping layer. In this case, each memory opening fill structure 58 and adjacent portions of the conductive layers 46 constitute a vertical NAND string. Alternatively, the memory opening fill structure 58 may include any type of non-volatile memory element, such as a resistive memory element, a ferroelectric memory element, a phase-change memory element, etc. The memory opening fill structure 58 may be formed within a corresponding memory array region. Multiple vertical NAND strings can be provided. Each vertical NAND string may include a vertical stack of vertical semiconductor channels and memory elements (such as portions of memory films or floating gates) located at the level of conductive layer 46.

[0037] The conductive layers 46 can be patterned to provide a stepped region where each overlying conductive layer 46 has a smaller lateral extent than any underlying conductive layer 46. Stepped dielectric portions 65 can be formed around each vertical alternating stack (32, 46) to provide electrical isolation between adjacent vertical alternating stacks (32, 46). The stepped dielectric portions 65 can be formed on the stepped surfaces of the respective vertical alternating stacks (32, 46). Layer contact via structures (e.g., word line and select gate layer contact via structures) 86 can be formed on the conductive layers 46 in the stepped regions to provide electrical connections to the conductive layers 46. The layer contact via structures 86 can extend vertically through the respective stepped dielectric portions 65 and can contact the respective conductive layers in the conductive layers 46 (e.g., word lines or select gate electrodes).

[0038] A through-memory via 84 can pass through a dielectric material portion formed on a corresponding through-substrate via 916. A memory die dielectric layer 960 and a memory die metal interconnect structure 980 can be formed above the memory die semiconductor device 920 and the stepped dielectric material portion 65. The memory die metal interconnect structure 980 includes bit lines 982. Each bit line 982 electrically contacts a corresponding subset of the drain region within the memory opening-filled structure 58. The drain region can contact the top of a corresponding vertical semiconductor channel in the vertical semiconductor channel 60. Therefore, the bit lines 982 can be electrically connected to corresponding subsets of a plurality of vertical NAND strings. The memory die metal interconnect structure 980 includes interconnect metal lines and interconnect metal via structures.

[0039] Each memory die dielectric layer in the memory die dielectric layer 960 may include a corresponding dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, silicon nitride, dielectric metal oxide, or a combination thereof. A memory die pad-level dielectric layer 970 may be disposed on top of the memory die dielectric layer 960. The memory die pad-level dielectric layer 970 may include a dielectric diffusion barrier layer (such as a silicon nitride layer) or a first dielectric bonding layer (such as a silicon oxide layer) that can subsequently be bonded to another dielectric bonding material layer of a logic die to be subsequently provided.

[0040] A gasket cavity may be formed above the lower memory-side metal interconnect structure 980, extending through the upper portion of the memory die gasket layer 970 and the memory die dielectric material layer 960. The gasket cavity may be filled with at least one conductive material to form a memory-side die-to-die bonding gasket 988. The memory-side die-to-die bonding gasket 988 is formed within the gasket cavity, extending through the upper portion of the memory die gasket layer 970 and the memory die dielectric material layer 960. As used herein, a “die-to-die bonding gasket” refers to a bonding gasket located within a die and configured for die-to-die bonding through direct contact with another die-to-die bonding gasket located within another die.

[0041] Alternatively, a memory-side die-to-die bonding pad 988 is first formed on the memory die metal interconnect structure 980, and a memory die-pad level dielectric layer 970 may be formed above and around the memory-side die-to-die bonding pad 988. In this case, the memory die-pad level dielectric layer 970 may then be planarized to expose the top surface of the memory-side die-to-die bonding pad 988.

[0042] At least one conductive material may be a metallic (i.e., a metal or metal alloy) material that can be bonded to the same or another metallic material by metal-to-metal or hybrid bonding. For example, each memory-side die-to-die bonding pad 988 may include an optional metal barrier liner and a metal filler portion, the optional metal barrier liner including TiN, TaN, and / or WN, and the metal filler portion comprising a metallic material that can be bonded to the same or another metallic material by metal-to-metal bonding. For example, the metal filler portion may include any material and / or substantially consist of any material selected from Cu, copper alloys including copper with an atomic concentration greater than 70% (which may be greater than 90% and / or 95%), or cobalt or nickel alloys such as CoW, CoWP, CoMoP, NiW, and / or NiWP.

[0043] Each memory-side die-to-die bonding pad in the memory-side die-to-die bonding pad 988 is surrounded by a memory die-pad level dielectric layer 970 and contacts a corresponding lower-level memory die metal interconnect structure in the memory die metal interconnect structure 980. Each memory-side die-to-die bonding pad in the memory-side die-to-die bonding pad 988 is electrically connected to a corresponding node of the memory die semiconductor device 920. The memory die metal interconnect structure 980, embedded in the memory die dielectric layer 960, electrically connects corresponding components of the memory device 920 on the memory die substrate 908 to the corresponding memory-side die-to-die bonding pad in the memory-side die-to-die bonding pad 988.

[0044] refer to Figure 2A and Figure 2B The diagram illustrates a logic die 700. The logic die 700 includes a logic die substrate 708, a logic die semiconductor device 720 overlying the logic die substrate 708, a logic die dielectric layer 760 overlying the logic die semiconductor device 720, and a logic die metal interconnect structure 780 embedded in the logic die dielectric layer 760. In one embodiment, the logic die semiconductor device 720 may include at least one complementary metal-oxide-semiconductor (CMOS) circuit system, including a field-effect transistor. In one embodiment, the logic die substrate 708 may be a commercially available silicon substrate with a thickness ranging from 500 micrometers to 1 mm. The logic die 700 may be disposed in a wafer comprising a two-dimensional array of logic dies 700.

[0045] Generally, a logic die semiconductor device may include any semiconductor device that can operate in conjunction with a memory-side semiconductor device 920 in a memory-side semiconductor die 900 to realize the operation of the memory device therein and / or provide enhanced functionality. In one embodiment, the memory-side semiconductor die 900 may include a three-dimensional memory device comprising a three-dimensional array of memory elements, word lines (which may include a subset of conductive lines 46), and bit lines 982. The logic die semiconductor device 720 of the logic die 700 may include at least one sense amplifier region 702, at least one word line switch region 704, and at least one peripheral device region 706. Each sense amplifier region 702 includes a sense amplifier and a bit line driver electrically connected to a corresponding bit line in the bit line 982. Each bit line driver may include one or more bit line decoder circuits that decode the address of the bit line 982 and the bit line connection / connection region. Word line switch area 704 includes one or more word line driver circuits and one or more word line decoder circuits. The one or more word line driver circuits drive the word lines 46 of the corresponding three-dimensional array of memory elements of the memory-side semiconductor die 900, and the one or more word line decoder circuits decode the address of the word lines 46. Each peripheral device area 706 includes charge pump circuitry, bit line decoders, source power supply circuitry, data buffers and / or latches, input / output control circuitry, and / or any other semiconductor circuitry that can be used to operate the three-dimensional memory device 920 of the memory-side semiconductor die 900.

[0046] Shallow trench isolation structure 712 can be formed in the upper portion of logic die substrate 708 by forming shallow trenches and filling the shallow trenches with a dielectric material such as silicon oxide. Logic die semiconductor device 720 may include field-effect transistors, resistors, diodes, capacitors, inductors, and / or any additional semiconductor devices known in the art. Logic die dielectric material layer 760 with embedded logic die metal interconnect structure 780 may be formed above logic die semiconductor device 720. In one embodiment, substrate via cavities may be formed in the upper portion of memory die substrate 908. Each substrate via cavity may be filled with dielectric spacers 714 and through-substrate via structures 716. Each through-substrate via structure 716 provides a vertical conductive path after subsequent thinning of logic die substrate 708. The top surface of the through-substrate via structure 716 may protrude above the top surface of the logic die substrate 708 into the logic die dielectric layer 760, or may be coplanar with the top surface of the logic die substrate 708. Each through-substrate via structure 708 may be electrically connected to a corresponding logic die metal interconnect structure 780. According to aspects of this disclosure, the through-substrate via structures 716 of the logic die 700 may be arranged in a row or in multiple rows near one edge of the logic die 700. In one embodiment, the logic die 700 may have a straight edge, and the through-substrate via structures 716 of the logic die 700 may be arranged in a row or in multiple rows near the straight edge of the logic die 700 and laterally spaced from the straight edge by a uniform lateral offset distance.

[0047] Each logic die dielectric layer in the logic die dielectric layer 760 may include a corresponding dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, silicon nitride, dielectric metal oxide, or a combination thereof. A logic die pad-level dielectric layer 770 may be disposed on top of the logic die dielectric layer 760. The logic die pad-level dielectric layer 770 may include a dielectric diffusion barrier layer (such as a silicon nitride layer) or a first dielectric bonding layer (such as a silicon oxide layer) that can subsequently be bonded to another dielectric bonding material layer of a logic die to be subsequently supplied.

[0048] A pad cavity may be formed above the lower logic die metal interconnect structure 780, passing through the upper portion of the logic die pad layer 770 and the logic die dielectric material layer 760. The pad cavity may be filled with at least one conductive material to form a logic-side die-to-die bonding pad 788. The logic-side die-to-die bonding pad 788 is formed in the pad cavity, passing through the upper portion of the logic die pad layer 770 and the logic die dielectric material layer 760.

[0049] Alternatively, a logic-side die-to-die interconnect pad 788 is first formed on the logic die metal interconnect structure 780, and a logic die-to-die interconnect layer 770 may be formed above and around the logic-side die-to-die interconnect pad 788. In this case, the logic die-to-die interconnect layer 770 may then be planarized to expose the top surface of the logic-side die-to-die interconnect pad 788.

[0050] At least one conductive material may be a metallic (i.e., a metal or metal alloy) material that can be bonded to the same or another metallic material by metal-to-metal or hybrid bonding. For example, each logic-side die-to-die bonding pad in logic-side die-to-die 788 may include an optional metal barrier liner and a metal filler portion, the optional metal barrier liner including TiN, TaN, and / or WN, and the metal filler portion comprising a metallic material that can be bonded to the same or another metallic material by metal-to-metal bonding. For example, the metal filler portion may include any material and / or substantially consist of any material selected from Cu, copper alloys including copper with an atomic concentration greater than 70% (which may be greater than 90% and / or 95%), or cobalt or nickel alloys such as CoW, CoWP, CoMoP, NiW, and / or NiWP.

[0051] Each logic-side die-to-die bonding pad in the logic-side die-to-die bonding pad 788 is surrounded by a logic die-to-die layer dielectric layer 770 and contacts a corresponding lower logic die-to-die metal interconnect structure in the logic die-to-die metal interconnect structure 780. Each logic-side die-to-die bonding pad in the logic-side die-to-die bonding pad 788 is electrically connected to a corresponding node of a logic die semiconductor device 720. The logic die-to-die metal interconnect structure 780 embedded in the logic die dielectric layer 760 electrically connects a corresponding logic device 720 on the logic die substrate 708 to a corresponding logic-side die-to-die bonding pad in the logic-side die-to-die bonding pad 788.

[0052] refer to Figure 3The memory-side semiconductor die 900 and the logic die 700 are oriented and aligned such that memory-side die-to-die bonding pads 988 face logic-side die-to-die bonding pads 788. The logic die 700 is brought into contact with the memory-side semiconductor die 900 such that each memory-side die-to-die bonding pad 988 contacts a corresponding logic-side die-to-die bonding pad in the logic-side die-to-die bonding pads 788. In one embodiment, the pattern of the logic-side die-to-die bonding pads 788 may be a mirror image of the pattern of the memory-side die-to-die bonding pads 988, having an optional difference in the size of the die-to-die bonding pads (988, 788) between the memory-side semiconductor die 900 and the logic die 700. In one embodiment, the memory-side die-to-die bonding pads 988 and the corresponding logic-side die-to-die bonding pads 788 may have the same size (i.e., lateral width). In another embodiment, the memory-side die-to-die bonding pads 988 and the corresponding logic-side die-to-die bonding pads 788 may have different sizes. In one embodiment, the area overlap between each facet pair of the memory-side die indirect mating pad 988 and the logic-side die indirect mating pad 788 may be at least 80% and / or at least 90%, such as 90% to 100%, of the smaller of the area of ​​the memory-side die indirect mating pad 988 and the logic-side die indirect mating pad 788 within each mating pair.

[0053] Wafers comprising multiple memory dies 900 and wafers comprising multiple logic dies 700 can be bonded to each other using any suitable bonding method. For example, annealing can be performed such that logic-side die-to-die bonding pads 788 can be bonded to memory-side die-to-die bonding pads 988 using metal-to-metal bonding, memory die-to-die layer dielectric layers 970 can be bonded to logic die-to-die layer dielectric layers 770 using dielectric bonding, or both, logic-side die-to-die bonding pads 788 can be bonded to memory-side die-to-die bonding pads 988, and memory die-to-die layer dielectric layers 970 can be bonded to logic die-to-die layer dielectric layers 770 using hybrid bonding.

[0054] The annealing temperature can be selected based on the composition of the corresponding materials, such as the logic-side die-to-die bonding pad 788 and the memory-side die-to-die bonding pad 988. For example, if the logic-side die-to-die bonding pad 788 and the memory-side die-to-die bonding pad 988 include a metal-filled portion that is substantially composed of copper, the annealing temperature can be in the range of 150 degrees Celsius to 400 degrees Celsius. The bonding assembly of the memory die 900 and the logic die 700 includes bonding units (900, 700). Multiple bonding units (900, 700) can be formed. Generally, the memory die 900 and the logic die 700 within each bonding unit (900, 700) are bonded to each other by a metal-to-metal bond.

[0055] According to aspects of this disclosure, the through-substrate via structure 916 of the memory die 900 and the through-substrate via structure 716 of the logic die 700 may be arranged such that the through-substrate via structure 916 of the memory die 900 is located on opposite sides of the through-substrate via structure 716 of the logic die 700 during bonding. For example, bonding units (900, 700) may have a first pair of straight edges that are parallel to each other and laterally spaced apart by a second pair of straight edges, the through-substrate via structure 716 of the logic die 700 may be located near one of the straight edges of the first pair of straight edges, and the through-substrate via structure 916 of the memory die 900 may be located near the other straight edge of the first pair of straight edges.

[0056] refer to Figure 4 The memory die substrate 908 can be thinned by removing a portion of its back side. The back side portion of the memory die substrate 908 can be removed by grinding, wet etching, dry etching, and / or polishing. The through-substrate via structure 916 can be used as a planarization stop structure. The memory die substrate 908 can be selectively recessed relative to the through-substrate via structure 916 by an etching process (such as a wet etching process). A dielectric material (such as silicon oxide) can be deposited above the recessed back side surface of the memory die substrate and can be planarized to physically expose the back side surface of the through-substrate via structure 916. The remaining portion of the dielectric material comprises the memory die back dielectric layer 912.

[0057] Optional metal liner and under-bump metal (UBM) layer stacks may be deposited on the back surface of the back dielectric layer 912 of the memory die. The metal liner includes materials such as TiN, TaN, and / or WN, and may have a thickness ranging from 10 nm to 100 nm, but smaller and larger thicknesses are also possible. The UBM layer stack includes a stack of metal materials for bonding solder balls thereon. Exemplary UBM layer stacks include, but are not limited to, Al / Ni / Au stacks, Al / Ni / Cu stacks, Cu / Ni / Au stacks, Cu / Ni / Pd stacks, Ti / Ni / Au stacks, Ti / Cu / Ni / Au stacks, Ti / W / Cu stacks, Cr / Cu stacks, and Cr / Cu / Ni stacks. The thickness of the UBM layer stack may range from 1 micrometer to 30 micrometers, such as 3 micrometers to 10 micrometers, but smaller and larger thicknesses are also possible.

[0058] The UBM layer stack and optional metal liner can be patterned, for example, by applying and patterning a photoresist layer over the UBM layer stack and then transferring the pattern from the photoresist layer through the UBM layer stack and optional metal liner using an etching process. The etching process can include isotropic or anisotropic etching. Each remaining portion of the UBM layer stack and optional metal liner contains a bonding pad capable of accommodating wire bonding. Each such bonding pad is referred to herein as a memory-side external bonding pad 998. A through-substrate via structure 916 within the memory die 900 extends vertically through the memory die substrate 908 and is electrically connected to a corresponding memory-side external bonding pad in the memory-side external bonding pad 998. The memory-side external bonding pads 998 can be positioned adjacent to the back edge of the memory die 900 and can be arranged in a single row or multiple rows, such as two or three rows. Each row of memory-side external bonding pads 998 can be parallel to the back edge of the memory die 900. In one embodiment, the memory die 900 may have a rectangular horizontal cross-sectional shape, and the back edge of the memory die 900 may be straight. In this case, each row of memory-side external bonding pads 998 may be arranged in a straight line. The area where at least one row of memory-side external bonding pads 998 is located is referred to herein as the memory die back-side external pad area 999.

[0059] refer to Figure 5A , Figure 5B and Figure 6 The logic die substrate 708 can be thinned by removing a portion of its back side. The back side portion of the logic die substrate 708 can be removed by grinding, wet etching, dry etching, and / or polishing. The through-substrate via structure 716 can be used as a planarization stop structure. The logic die substrate 708 can be selectively recessed relative to the through-substrate via structure 716 by an etching process (such as a wet etching process). A dielectric material (such as silicon oxide) can be deposited above the recessed back side surface of the logic die substrate and can be planarized to physically expose the back side surface of the through-substrate via structure 716. The remaining portion of the dielectric material comprises the logic die back dielectric layer 712.

[0060] Optional metal liner and under-bump metal (UBM) layers or stacks may be deposited on the back surface of the back dielectric layer 712 of the logic die. The metal liner includes materials such as TiN, TaN, and / or WN, and may have a thickness ranging from 10 nm to 100 nm, but smaller and larger thicknesses are also possible. The UBM layer stack includes a stack of metal materials for bonding solder balls thereon. Exemplary UBM layers include Al or Al alloy layers, and exemplary UBM layer stacks include, but are not limited to, Al / Ni / Au stacks, Al / Ni / Cu stacks, Cu / Ni / Au stacks, Cu / Ni / Pd stacks, Ti / Ni / Au stacks, Ti / Cu / Ni / Au stacks, Ti / W / Cu stacks, Cr / Cu stacks, and Cr / Cu / Ni stacks. The thickness of the UBM layer stack may range from 1 micrometer to 30 micrometers, such as 3 micrometers to 10 micrometers, but smaller and larger thicknesses are also possible.

[0061] The UBM layer stack and optional metal liner can be patterned, for example, by applying and patterning a photoresist layer over the UBM layer stack and then transferring the pattern from the photoresist layer through the UBM layer stack and optional metal liner using an etching process. The etching process can include isotropic or anisotropic etching. Each remaining portion of the UBM layer stack and optional metal liner contains a bonding pad capable of accommodating wire bonding. Each such bonding pad is referred to herein as a logic-side external bonding pad 798. A through-substrate via structure 716 within the logic die 700 extends vertically through the logic die substrate 708 and is electrically connected to a corresponding logic-side external bonding pad in the logic-side external bonding pad 798. The logic-side external bonding pads 798 can be positioned adjacent to the back edge of the logic die 700 and can be arranged in a single row, two rows, or three rows. Each row of logic-side external bonding pads 798 can be parallel to the back edge of the logic die 700. In one embodiment, the logic die 700 may have a rectangular horizontal cross-sectional shape, and the back edge of the logic die 700 may be straight. In this case, each row of logic-side external bonding pads 798 may be arranged in a straight line. The area where at least one row of logic-side external bonding pads 798 is located is referred to herein as the logic die back external pad area 799.

[0062] The external pad area on the back of the logic die is along a direction perpendicular to the interface between memory die 900 and logic die 700 in a plan view (such as...). Figure 5BIn a view, the outer pad region 999 is located on the opposite side of the outer pad region on the back of the memory die. In one embodiment, the outer pad region 999 on the back of the memory die may be laterally spaced from the outer pad region 799 on the back of the logic die along a first horizontal direction hd1 (e.g., bit line direction). The logic-side outer bonding pads 798 may be arranged in rows (or rows) extending laterally along a second horizontal direction hd2 parallel to the edges of the bonding cells (900, 700), and the memory-side outer bonding pads 998 may be arranged in rows (or rows) extending laterally along the second horizontal direction hd2 (e.g., word line direction) and located on the opposite side of the outer pad region 799 on the back of the logic die. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1.

[0063] The primary direction of the input / output signals and power distribution wiring within the memory die 900 and logic die 700 may be along a first horizontal direction hd1, and the secondary direction of the input / output signals and power distribution wiring within the memory die 900 and logic die 700 may be along a second horizontal direction hd2. For example... Figure 5B As shown, in a junction cell (900, 700) containing four memory planar dies 900, a peripheral device region 706 is positioned adjacent to the side (i.e., edge) of the logic die 700 of the junction cell (900, 700) containing corresponding backside external pad regions (999, 799), while a sense amplifier region 702 is located between the peripheral device region 706 and the edge word line switch region 704 of the logic die 700 of the junction cell (900, 700). Therefore, power signals are routed directly from the corresponding backside external pad regions (999, 799) to the peripheral device region (e.g., to a charge pump circuit located within the peripheral device region) 706 without passing through the sense amplifier region 702. This means that the interconnect structure 780 electrically connecting the corresponding backside external pad regions (999, 799) to the peripheral device region 706 can be shorter, reducing its resistance and thus increasing charge pump power efficiency. Furthermore, this interconnect structure 780 does not require wiring around the bonding pad 788 in the sensing amplifier region 702, and does not generate noise in the sensing amplifier region 702 that interferes with the operation of the sensing amplifier.

[0064] In one embodiment, a through-substrate via structure 916 in the memory die 900 extends vertically through the memory die substrate 908 and is electrically connected to a corresponding memory-side external bonding pad in the memory-side external bonding pad 998. A memory die metal interconnect structure 980 is embedded in the memory die dielectric layer 960 and electrically connects a corresponding memory device 920 on the memory die substrate 908 to a corresponding memory-side inter-die bonding pad in the memory-side inter-die bonding pad 988.

[0065] In one embodiment, a through-substrate via structure 716 in logic die 700 extends vertically through logic die substrate 708 and is electrically connected to a corresponding logic-side external bonding pad in logic-side external bonding pad 798. A logic die metal interconnect structure 780 is embedded in logic die dielectric material layer 760 and electrically connects a corresponding logic device 720 on logic die substrate 708 to a corresponding logic-side inter-die bonding pad in logic-side inter-die bonding pad 788.

[0066] Multiple bonding units (900, 700) can be formed. Each bonding unit (900, 700) includes a memory die 900, which includes a memory-side die-to-die bonding pad 988 and a memory-side external bonding pad 998 located on opposite main surfaces of the memory die 900. Additionally, each bonding unit (900, 700) includes a logic die 700, which includes logic circuitry configured to control the operation of the memory die 900, and logic-side die-to-die bonding pads 788 and 798 located on opposite main surfaces of the logic die 700. In one embodiment, each bonding unit (900, 700) can be provided by bonding a respective logic die 700 and a respective memory die 900 such that the logic-side die-to-die bonding pad 788 of the respective logic die 700 bonds to the corresponding memory-side die-to-die bonding pad 988 of the memory-side die-to-die bonding pad of the respective memory die 900.

[0067] In one embodiment, a plurality of bonding units (900, 700) can be formed by bonding a wafer comprising a plurality of memory dies 900 to a wafer comprising a plurality of logic dies 700. In this case, the bonding assembly of the two wafers can be cut along a dicing channel to provide the plurality of bonding units (900, 700).

[0068] refer to Figure 7 This illustration shows a first exemplary structure including a stacked die assembly according to a first embodiment of the present disclosure. The stacked die assembly includes a vertical stack of a plurality of bonding units (900, 700) formed by attaching vertically adjacent bonding unit pairs using an adhesive layer 550. In one embodiment, the stacked die assembly includes a vertical stack of a plurality of bonding units (900, 700) connected to each other by adhesive layers 550 and a mounting substrate (e.g., a packaged printed circuit board or base) 300. Each pair of vertically adjacent bonding units (900, 700) can be attached to each other via a respective adhesive layer 550. The mounting substrate 300 may be attached to the vertical stack of the plurality of bonding units (900, 700) using an additional adhesive layer 550. Alternatively, other attachment methods, such as clamps, encapsulations, or bonding layers, may be used instead of adhesive layers 550 or in addition to adhesive layers 550.

[0069] Generally, a vertical stack of multiple bonding units (900, 700) can be formed by the following steps: attaching the multiple bonding units (900, 700) to each other such that the memory-side external bonding pads 998 and logic-side external bonding pads 798 of the multiple bonding units (900, 700) form an upward-facing external bonding pad set and a downward-facing external bonding pad set, the upward-facing external bonding pad set having an upward-facing physically exposed surface, and the downward-facing external bonding pad set having a downward-facing physically exposed surface relative to the bonding side of the mounting substrate 300. For example, the bonding units (900, 700) may be staggered such that the memory-side external bonding pads 998 are physically exposed and the logic-side external bonding pads 798 are physically exposed. In one embodiment, the memory-side external bonding pads 998 may be physically exposed upward-facing relative to the bonding side of the mounting substrate 300 and the logic-side external bonding pads 798 may be physically exposed downward-facing. In another embodiment, the memory-side external bonding pad 998 may be physically exposed face down relative to the bonding side of the mounting substrate 300, and the logic-side external bonding pad 798 may be physically exposed face up.

[0070] The first set of bonding leads 950 can connect to a pair of corresponding upward-facing external bonding pads of the upward-facing external bonding pad set (which may be memory-side external bonding pad 998 or logic-side external bonding pad 798). The second set of bonding leads 750 can connect to a pair of corresponding downward-facing external bonding pads of the downward-facing external bonding pad set (which may be memory-side external bonding pad 998 or logic-side external bonding pad 798).

[0071] In one embodiment, the plurality of bonding units (900, 700) may be staggered such that each upper bonding unit (900, 700) is laterally offset relative to the lower bonding unit (900, 700) along a first horizontal direction hd1. The first horizontal direction hd1 is the direction in which the logic die outer pad region of the logic die 700 is laterally spaced from the memory side outer pad region of the memory die 900.

[0072] The vertical stack of multiple bonding units (900, 700) can be electrically connected to the mounting substrate 300 by attaching additional bonding leads (950, 750) to bonding pads 398 located on the mounting side of the mounting substrate 300 and to the outer bonding pads (998, 798) of the nearest end bonding units (900, 700) of the vertical stack of multiple bonding units (900, 700).

[0073] In one embodiment, multiple bonding units (900, 700) may be attached to each other such that each upper-facing outer bonding pad within the stacked die assembly does not have area overlap with any upper bonding unit within the stacked die assembly in a plan view along the direction (such as the vertical direction) along which the bonding units are stacked, and each lower-facing outer bonding pad within the stacked die assembly does not have area overlap with any lower bonding unit within the stacked die assembly in a plan view.

[0074] refer to Figures 1A to 7 Furthermore, according to various embodiments of this disclosure, a structure including a stacked die assembly (900, 700, 300, 950, 750) is included. The stacked die assembly (900, 700, 300, 950, 750) comprises a vertically stacked plurality of bonding units (900, 700). Each bonding unit (900, 700) includes a memory die 900, which includes a memory-side die-to-die bonding pad 988 and a memory-side external bonding pad 998 located on opposite main surfaces of the memory die 900. Each bonding unit (900, 700) also includes a logic die 700, which includes logic circuitry configured to control the operation of the memory die 900 and includes a logic-side die-to-die bonding pad 788 and a logic-side external bonding pad 798 located on opposite main surfaces of the logic die 700. A logic-side die-to-die bonding pad 788 is bonded to a corresponding memory-side die-to-die bonding pad in a memory-side die-to-die bonding pad 988. The memory-side external bonding pad 998 and the logic-side external bonding pad 798 include an upward-facing set of external bonding pads and a downward-facing set of external bonding pads, the upward-facing set having an upward-facing physical exposed surface and the downward-facing set having a downward-facing physical exposed surface. A first set of bonding leads 950 connects to the upward-facing external bonding pads, and a second set of bonding leads 750 connects to the downward-facing external bonding pads.

[0075] As used herein, the main surfaces of the dies are opposite each other, one main surface containing an external bonding pad, and the other main surface containing a die-to-die bonding pad that bonds to the die-to-die bonding pads of the other dies in the bonding unit (900, 700). If one main surface points “down” toward the mounting substrate 3000, it can be considered a “lower” main surface, and if the other main surface points “up” away from the mounting substrate 3000, it can be considered an “upper” main surface. However, it should be noted that “up” and “down” do not necessarily align with “away” and “toward” directions relative to the ground, because the bonding units can be positioned laterally or “inverted” in the electronics (with the mounting substrate 3000 above the bonding units). Similarly, the electronics can be positioned relative to the ground in any orientation.

[0076] In one embodiment, each pair of vertically adjacent bonding units (900, 700) relative to the mounting substrate 3000 includes an overlay bonding unit (i.e., the upper bonding unit of the memory die 900 and the logic die 700) and a lower bonding unit (i.e., the additional bonding unit of the additional memory die 900 and the additional logic die 700). The overlay bonding unit is laterally offset relative to the lower bonding unit along a first horizontal direction hd1. The horizontal direction is parallel to the main surface of the die. In one embodiment, a memory-side external bonding pad 998 within each memory die 900 is laterally offset from the edge of the memory die 900 along the first horizontal direction hd1 by a uniform lateral offset distance, and the edge of the memory die 900 extends laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, a logic-side external bonding pad 798 within each logic die 700 is laterally offset from the edge of the logic die 700 by a uniform lateral offset distance, and the edge of the logic die 700 extends laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0077] In one embodiment, each upward-facing outer bonding pad (998 or 798) within the stacked die assembly (900, 700, 300, 950, 750) does not overlap in area with any overlying bonding unit (900, 700) within the stacked die assembly in a plan view along the direction along which the bonding units (900, 700) are stacked; and each downward-facing outer bonding pad (998 or 798) within the stacked die assembly (900, 700, 300, 950, 750) does not overlap in area with any lower bonding unit (900, 700) within the stacked die assembly (900, 700, 300, 950, 750) in a plan view.

[0078] In one embodiment, the set of external bonding pads (998 or 798) facing upward includes memory-side external bonding pads 998, and the set of external bonding pads facing downward includes logic-side external bonding pads 798, or the set of external bonding pads (998 or 798) facing downward includes logic-side external bonding pads 798, and the set of external bonding pads (998 or 798) facing downward includes memory-side external bonding pads 998.

[0079] In one embodiment, each pair of vertically adjacent bonding units (900, 700) is attached to each other via a respective adhesive layer 550. A vertical stack of multiple bonding units (900, 700) can be mounted to a mounting substrate 300 via additional adhesive layers 550. Additional bonding leads (950, 750) can provide electrical connection between the outer bonding pads (998, 798) of the nearest bonding unit (900, 700) among the multiple bonding units (900, 700) and the bonding pads located on the mounting substrate 300.

[0080] In one embodiment, the logic-side die-to-die bonding pad 788 is bonded to a corresponding memory-side die-to-die bonding pad in the memory-side die-to-die bonding pad 988 within each bonding unit (900, 700) via a metal-to-metal bonding.

[0081] In one embodiment, at least one memory die in the memory die 900 includes: a three-dimensional memory array located above a memory die substrate 908; a memory die metal interconnect structure 980 embedded in a memory die dielectric material layer 960; and a through-substrate via structure 916 extending vertically through the memory die substrate 908 and electrically connected to a corresponding memory-side external bonding pad in a memory-side external bonding pad 998. In one embodiment, the three-dimensional memory array includes: a vertically alternating stack of insulating layer 32 and conductive layer 46; a plurality of memory opening-fill structures 58, each including a vertical semiconductor channel and a vertically stacked memory element (e.g., a portion of a memory film) located at a level of conductive layer 46; bit lines 982 electrically connected to corresponding subsets of the plurality of memory opening-fill structures 58; stepped dielectric material portions 65 located on stepped surfaces of the alternating stack (32, 46); and layer contact via structures 86 extending vertically through the stepped dielectric material portions 65 and contacting corresponding conductive layers in conductive layer 46.

[0082] In one embodiment, at least one logic die in the logic die 700, which is bonded to a corresponding memory die in the memory die 900, includes: a sense amplifier region 702, which includes a sense amplifier electrically connected to a corresponding bit line in the bit line 982; and a peripheral device region 706, which includes charge pump circuitry. In one embodiment, the peripheral device region is located between the sense amplifier region 702 and the logic-side external bonding pad 798.

[0083] In one embodiment, at least one logic die in the logic die 700 includes: a through-substrate via structure 716 that extends vertically through the logic die substrate 708 and is electrically connected to a corresponding logic-side external bonding pad in the logic-side external bonding pad 798; and a logic die metal interconnect structure 780 that is embedded in the logic die dielectric material layer 760 and electrically connects a corresponding logic device 720 on the logic die substrate 708 to a corresponding logic-side inter-die bonding pad in the logic-side inter-die bonding pad 788.

[0084] refer to Figure 8A and Figure 8B This illustration shows a semiconductor die 600 according to a second embodiment of the present disclosure. The semiconductor die 600 of the second embodiment includes a substrate 608, also referred to as a first substrate. The semiconductor die 600 further includes a semiconductor device 620 overlying the substrate 608, a dielectric material layer 660 overlying the semiconductor device 620, and a metal interconnect structure 680 embedded in the dielectric material layer 660. The metal interconnect structure 680 includes bit lines 682. In one embodiment, the substrate 608 may be a commercially available silicon wafer with a thickness ranging from 500 micrometers to 1 mm. The semiconductor die 600 may be disposed in a wafer comprising a two-dimensional array of memory dies 600. For example, the substrate may be a semiconductor wafer, such as a silicon wafer.

[0085] Generally, semiconductor device 620 includes memory devices and optionally includes logic devices. Semiconductor die 600 may include at least one memory array region 100 and at least one auxiliary region 202. Auxiliary region 202 includes connection region 200 (which may be as described above). Figure 1A The described area 200) and optionally includes at least one logic device area 800. Each memory array area 100 includes a corresponding memory array (e.g., the memory die semiconductor device 920 described above). If present, each logic device area 800 includes the aforementioned logic device 720 for supporting the operation of memory elements in the corresponding memory array area 100. In one embodiment, as Figure 8A As shown, the logic device region 800 may be located adjacent to the contact region 200 (e.g., in a CMOS located adjacent to a memory array configuration). In an alternative embodiment, the logic device region 800 may be located below the memory array region 100 and below the contact region 200 (e.g., in a CMOS located below a memory array configuration). In another alternative embodiment, the logic device region 800 is not present on or above the substrate 608. Instead, the logic device region is present on a separate substrate, such as the mounting substrate 3000 described above with respect to the first embodiment (e.g., in a CMOS bonded to a memory array configuration).

[0086] Each plane may include a memory array region 100 and at least one auxiliary region 202. For example, Figure 8B A die comprising two memory planes is shown, each memory plane containing two auxiliary regions 202. However, other configurations may be used. Each memory array region 100 may include memory devices 920 that can be disposed in the memory die 900 of the first embodiment. Each logic device region 800 (if present) may include logic devices 720 that can be disposed in the logic die 700 of the first embodiment. For example, each memory array region 100 may include a three-dimensional memory array, such as a three-dimensional NAND memory array. The three-dimensional memory devices may include various device regions that contain various subsets of semiconductor devices 620.

[0087] In one embodiment, the semiconductor device 620 may include a vertically alternating stack of insulating layer 32 and conductive layer 46, and a two-dimensional array of memory openings extending vertically through the vertically alternating stack (32, 46). Conductive layer 46 may contain word lines of a three-dimensional NAND memory device. Memory opening fill structures 58 may be formed within each memory opening. Each memory opening fill structure 58 may include a memory film and a vertical semiconductor channel contacting the memory film. The memory film may include a barrier dielectric, a tunneling dielectric, and a charge storage material located between the barrier dielectric and the tunneling dielectric. The charge storage material may include a charge trapping layer, such as a silicon nitride layer; or multiple discrete charge trapping regions, such as floating gates or discrete portions of a charge trapping layer. In this case, each memory opening fill structure 58 and adjacent portions of the conductive layer 46 constitute a vertical NAND string. Alternatively, the memory opening fill structure 58 may include any type of non-volatile memory element, such as a resistive memory element, a ferroelectric memory element, a phase-change memory element, etc.

[0088] The memory aperture filling structure 58 can be formed within the corresponding memory array region. Multiple vertical NAND strings can be provided. Each vertical NAND string may include a vertical stack of vertical semiconductor channels and memory elements (e.g., portions of memory films or floating gates) located at the level of conductive layer 46.

[0089] The conductive layers 46 can be patterned to provide each overlying conductive layer 46 with a stepped region (i.e., contact region 200) having a smaller lateral extent than any underlying conductive layer 46. Stepped dielectric portions 65 can be formed around each vertical alternating stack (32, 46) to provide electrical isolation between adjacent vertical alternating stacks (32, 46). The stepped dielectric portions 65 can be formed on the stepped surfaces of the respective vertical alternating stacks (32, 46). Layer contact via structures 86 can be formed on the conductive layers 46 in the stepped regions to provide electrical connection to the conductive layers 46. The layer contact via structures 86 can extend vertically through the respective stepped dielectric portions 65 and can contact the respective conductive layers in the conductive layers 46.

[0090] A dielectric layer 660 and a metal interconnect structure 680 may be formed over the semiconductor device 620 and the stepped dielectric portion 65. The metal interconnect structure 680 includes bit lines 682. Each bit line 682 electrically contacts a corresponding subset of the drain region within the memory opening filling structure 58. The drain region may contact the top of a corresponding vertical semiconductor channel in the vertical semiconductor channel 60. Therefore, the bit lines may be electrically connected to corresponding subsets of a plurality of vertical NAND strings. The metal interconnect structure 680 includes interconnect metal lines and interconnect metal via structures.

[0091] Each dielectric layer in dielectric layer 660 may include a corresponding dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, silicon nitride, dielectric metal oxide, or a combination thereof. A pad-level dielectric layer (not shown) may be disposed on top of dielectric layer 660. The pad-level dielectric layer (if present) may include a dielectric diffusion barrier layer (such as a silicon nitride layer) or a first dielectric bonding layer (such as a silicon oxide layer) that can subsequently be bonded to another dielectric bonding material layer of a logic die to be supplied.

[0092] An external pad cavity may be formed in an external pad region located at the edge of the semiconductor die 600. The edge of the semiconductor die 600 may be perpendicular to a first horizontal direction hd2 and parallel to a second horizontal direction hd2. The external pad cavities may be arranged in one or more rows along the second horizontal direction. Each row of external pad cavities extends laterally along the second horizontal direction hd2.

[0093] At least one conductive material may then be deposited in the outer liner cavity. The at least one conductive material may include an optional metal liner and an under-bump metal (UBM) layer or stack. The metal liner includes materials such as TiN, TaN, and / or WN, and may have a thickness ranging from 10 nm to 100 nm, but smaller and larger thicknesses are also possible. The UBM layer or stack may include any UBM layer or stack that can be used in the first embodiment. The thickness of the UBM layer or stack may range from 1 micrometer to 30 micrometers, such as 3 micrometers to 10 micrometers, but smaller and larger thicknesses are also possible.

[0094] Excess portions of at least one conductive material can be removed from above the topmost horizontal surface of the dielectric material layer 660. The remaining portion of the at least one conductive material includes an outer bonding pad 698. Alternatively, the outer bonding pad 698 may be formed above the dielectric material layer 660, and an additional dielectric material layer may be deposited around the outer bonding pad 698 and subsequently planarized, such that the top surface of the outer bonding pad 698 is physically exposed.

[0095] In one embodiment, the memory die 900 includes logic circuitry in region 800 and a metal interconnect structure 680. The logic circuitry includes semiconductor devices 720 located on a substrate 608 and is configured to control the operation of memory elements within a memory array. The metal interconnect structure is embedded in a dielectric layer 660 and provides electrical connections between the semiconductor devices of the logic circuitry and the memory elements within the memory array. In one embodiment, the memory array may include: a vertically alternating stack of insulating layer 32 and conductive layer 46; a plurality of vertical NAND strings, each comprising a corresponding vertical semiconductor channel and a corresponding vertical stack of memory elements located at a level of conductive layer 46; a bit line 682 electrically connected to a corresponding subset of the plurality of vertical NAND strings; a stepped dielectric portion 65 located on a stepped surface of the alternating stack (32, 46); and a layer contact via structure 86 extending vertically through the stepped dielectric portion 65 and contacting a corresponding conductive layer in conductive layer 46.

[0096] The processing substrate 400 may be attached, for example, to the side of the semiconductor die 600, including the external bonding pad 698, using a temporary adhesive layer (not shown). The processing substrate 400 may include a dielectric material, a conductive material, or a semiconductor material, and may have a thickness in the range of 500 micrometers to 10 mm, but may also have smaller and larger thicknesses.

[0097] refer to Figures 9A to 9CThis provides two instances: an assembly of semiconductor die 600 and a processing substrate 400. Each semiconductor die 600 can be thinned from the back side. Specifically, each substrate 608 can be thinned from the back side. Each substrate 608 can be thinned by grinding, chemical etching, dry etching, and / or polishing. The processing substrate 400 can provide structural support to both the first and second wafers during the thinning process.

[0098] Generally, a first semiconductor die 600 and a second semiconductor die 600 may be provided. The first semiconductor die 600 may be disposed within a first wafer including a first plurality of memory dies 600, and the second semiconductor die 600 may be disposed within a second wafer including a second plurality of memory dies 600. The first semiconductor die 600 is referred to herein as a front semiconductor die 600F, and the second semiconductor die 600 is referred to herein as a back semiconductor die 600B.

[0099] Thinned substrates 608B of the back semiconductor die 600B and thinned substrates 608F of the front semiconductor die 600F are contacted to each other and then bonded to each other using wafer-to-wafer bonding. The bonding assembly of semiconductor dies 600F and the back semiconductor die 600B includes bonding units (600F, 600B). Multiple bonding units (600F, 600B) can be formed. In one embodiment, the front semiconductor die 600F may be disposed in a first wafer, and the back semiconductor die 600B may be disposed in a second wafer. In this case, multiple bonding units (600F, 600B) can be formed when the second wafer is bonded to the first wafer.

[0100] In one embodiment, no through-substrate via structure extends through either of the thinned substrates (608B, 608F), and the bonding pairs of the back semiconductor die 600B and the front semiconductor die 600F are electrically connected to each other through their respective thinned substrates (608B, 608F). In other embodiments, the bonding pairs of the back semiconductor die 600B and the front semiconductor die 600F are directly electrically connected to each other without any wire bonding or bonding pads. However, the back semiconductor die and the front semiconductor die are indirectly electrically connected to each other through a common mounting substrate 300, as will be described in more detail below.

[0101] The bonding assemblies of the first and second wafers can then be diced along the dicing channels to provide a plurality of bonding units (600F, 600B). In one embodiment, each bonding unit (600F, 600B) includes a corresponding front semiconductor die 600F and a corresponding back semiconductor die 600B. The corresponding front semiconductor die includes a front memory array and a front external bonding pad 698F, and the corresponding back semiconductor die includes a back memory array and a back external bonding pad 698B and is bonded to the corresponding front semiconductor die 600F.

[0102] According to aspects of this disclosure, the front semiconductor die 600F and the back semiconductor die 600B are oriented during bonding such that the outer bonding pad 698 of the front semiconductor die 600F (hereinafter referred to as the front outer bonding pad 698F) is located on opposite sides (i.e., opposite main surfaces of the bonding units (600F, 600B) of the outer bonding pad 698 of the back semiconductor die 600B (hereinafter referred to as the back outer bonding pad 698B) in a plan view. The plan view is a view along the vertical direction, i.e., a view along the direction perpendicular to the interface between the front semiconductor die 600F and the back semiconductor die 600B.

[0103] The front semiconductor die 600F and the back semiconductor die 600B may be located on opposite edges of the bonding units (600F, 600B). For example, the bonding units (600F, 600B) may have a first pair of straight edges that are parallel to each other and laterally spaced apart by a second pair of straight edges, with the front external bonding pad 698F located near one of the straight edges of the first pair of straight edges and the back external bonding pad 698B located near the other straight edge of the first pair of straight edges. The front external bonding pad 698F and the back external bonding pad 698B may be laterally spaced along a first horizontal direction hd2, and each of the front external bonding pad 698F and the back external bonding pad 698B may be arranged in a corresponding row (or multiple rows) extending laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0104] refer to Figure 10This illustration shows a second exemplary structure including a stacked die assembly according to a second embodiment of the present disclosure. The stacked die assembly includes a vertical stack of a plurality of bonding units (600F, 600B) formed by attaching vertically adjacent bonding unit pairs to each other. Attachment can be formed using adhesive layers, mechanical clamps, and / or packages that compress the vertically stacked bonding units together. In one embodiment, the stacked die assembly includes a vertical stack of a plurality of bonding units (600F, 600B) and a mounting substrate 300 connected to each other via an adhesive layer 550. Each pair of vertically adjacent bonding units (600F, 600B) can be attached to each other via a respective adhesive layer 550. The mounting substrate 300 may be attached to the vertical stack of the plurality of bonding units (600F, 600B) using an additional adhesive layer 550.

[0105] Generally, a vertical stack of multiple bonding cells (600F, 600B) can be formed by the following steps: attaching the multiple bonding cells (600F, 600B) to each other such that the outer bonding pads (698F, 698B) of the multiple bonding cells (600F, 600B) form an upward-facing outer bonding pad set and a downward-facing outer bonding pad set, the upward-facing outer bonding pad set having an upward-facing physically exposed surface, and the downward-facing outer bonding pad set having a downward-facing physically exposed surface. For example, the bonding cells (600F, 600B) can be staggered such that the outer bonding pads (698F, 698B) are physically exposed. The front outer bonding pad 698F of the front semiconductor die 600F can be physically exposed upwards, and the back outer bonding pad 698B of the back semiconductor die 600B can be physically exposed downwards.

[0106] The first set of bonding leads 950 can connect a pair of corresponding upward-facing external bonding pads between sets of upward-facing external bonding pads (which may be front external bonding pads 698F). The second set of bonding leads 750 can connect a pair of corresponding downward-facing external bonding pads between sets of downward-facing external bonding pads (which may be back external bonding pads 698F).

[0107] In one embodiment, a plurality of bonding units (600F, 600B) may be staggered such that each upper bonding unit (600F, 600B) is laterally offset relative to the lower bonding unit (600F, 600B) along a first horizontal direction hd1. The first horizontal direction hd1 is the direction in which the front outer padding area of ​​each bonding unit (600F, 600B) is laterally spaced from the back outer padding area of ​​each bonding unit (600F, 600B).

[0108] The vertical stack of multiple bonding units (600F, 600B) can be electrically connected to the mounting substrate 700 by attaching additional bonding leads (950, 750) to bonding pads 398 located on the mounting substrate 300 and to the outer bonding pads (698F, 698B) of the nearest bonding unit (600F, 600B) between the vertical stack of multiple bonding units (600F, 600B).

[0109] In one embodiment, multiple bonding units (600F, 600B) may be attached to each other such that each upper-facing outer bonding pad within the stacked die assembly does not have area overlap with any upper bonding unit within the stacked die assembly in a plan view along the direction (such as the vertical direction) along which the bonding units are stacked, and each lower-facing outer bonding pad within the stacked die assembly does not have area overlap with any lower bonding unit within the stacked die assembly in a plan view.

[0110] Although Figure 10 An embodiment is shown in which sixteen bonding units (600F, 600B) comprising thirty-two semiconductor dies 600 are attached to a mounting substrate 300, but embodiments in which any number of bonding units (600F, 600B) are attached to the mounting substrate 300 are explicitly considered herein. The mounting substrate 300 can be any package substrate. If the semiconductor dies 600 do not contain corresponding dedicated logic device regions 800, then logic devices 720 may be located on the mounting substrate 300. In the illustrated example, each front-side semiconductor die 600F is designated as an even-numbered die, and each back-side semiconductor die 600B is designated as an odd-numbered die. The number assigned to each semiconductor die 600 can be arbitrary.

[0111] refer to Figures 8A to 10With reference to the accompanying drawings and various embodiments of the present disclosure, a structure including a stacked die assembly (600F, 600B, 300, 950, 750, 550) is provided. The stacked die assembly (600F, 600B, 300, 950, 750, 550) comprises: a vertically stacked plurality of bonding units (600F, 600B), wherein each bonding unit (600F, 600B) includes a corresponding front-side semiconductor die 600F and a corresponding back-side semiconductor die 600B, the corresponding front-side semiconductor die including a front-side external bonding pad 698F, and the corresponding back-side semiconductor die including a back-side external bonding pad 698B, wherein the corresponding back-side semiconductor die 600B is bonded to a front-side external bonding pad 698F. The device comprises a front-side semiconductor die 600F, wherein each bonding unit (600F, 600B) has a front-side external bonding pad 698F with an upward-facing physical exposed surface, and each bonding unit (600F, 600B) has a rear-side external bonding pad 698B with a downward-facing physical exposed surface; a first bonding lead set 950 connected to the front-side external bonding pad 698F; and a second bonding lead set 750 connected to the rear-side external bonding pad 698B.

[0112] In one embodiment, the front semiconductor die 600F further includes a front memory array 620, and the back semiconductor die further includes a back memory array 620.

[0113] In one embodiment, the front semiconductor die 600F within each bonding unit (600F, 600B) includes a front metal interconnect structure 680 embedded in a front dielectric layer 660, wherein a subset of the front metal interconnect structure 680 is connected to a front external bonding pad 698F within each bonding unit (600F, 600B); and the back semiconductor die 600B within each bonding unit (600F, 600B) includes a back metal interconnect structure 680 embedded in a back dielectric layer 660, wherein a subset of the back metal interconnect structure 680 is connected to a back external bonding pad 698B within each bonding unit (600F, 600B).

[0114] In one embodiment, the front semiconductor die 600F in each bonding unit includes a front substrate 608F; the back semiconductor die 600B in each bonding unit includes a back substrate 608B; and the front substrate is bonded to the back substrate. In one embodiment, the back semiconductor die 600B and the front semiconductor die 600F in the same bonding unit are not directly electrically connected to each other.

[0115] In one embodiment, each pair of vertically adjacent bonding units (600F, 600B) includes an overlay bonding unit (600F, 600B) and a lower bonding unit (600F, 600B); and the overlay bonding unit (600F, 600B) is laterally offset relative to the lower bonding unit (600F, 600B) along a first horizontal direction hd1. In one embodiment, a front external bonding pad 698F within each front semiconductor die 600F is laterally offset from the edge of the front semiconductor die 600F along the first horizontal direction hd1 by a uniform lateral offset distance; and the edge of the front semiconductor die 600F extends laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, a back external bonding pad 698B within a back semiconductor die 600B is laterally offset from the edge of the back semiconductor die 600B by a uniform lateral offset distance; and the edge of the back semiconductor die 600B extends laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0116] In one embodiment, each front external bonding pad 698F within the stacked die assembly (600F, 600B, 300, 950, 750, 550) does not overlap in area with any overlying bonding unit (600F, 600B) within the stacked die assembly (600F, 600B, 300, 950, 750, 550) in a plan view along the direction along which the bonding units (600F, 600B) are stacked; and each back external bonding pad 698B within the stacked die assembly (600F, 600B, 300, 950, 750, 550) does not overlap in area with any lower bonding unit (600F, 600B) within the stacked die assembly (600F, 600B, 300, 950, 750, 550) in a plan view.

[0117] In one embodiment, each pair of vertically adjacent bonding units (600F, 600B) is attached to each other via a respective adhesive layer 550. In one embodiment, a vertical stack of multiple bonding units (600F, 600B) can be mounted on a mounting substrate 300 via additional adhesive layers 550; and additional bonding leads (950, 750) can provide electrical connection between bonding pads 398 located on the mounting substrate 300 and the front outer bonding pad 698F and the back outer bonding pad 698B of the nearest bonding unit (600F, 600B) between the bonding units (600F, 600B) of the stacked die assembly (600F, 600B).

[0118] In one embodiment, each of the front semiconductor die 600F and the back semiconductor die 600B includes: a corresponding logic circuit including a semiconductor device located on a corresponding substrate 608 and configured to control the operation of memory elements within the corresponding memory array; and a corresponding metal interconnect structure 680 embedded in a corresponding dielectric material layer 660 and providing electrical connection between the semiconductor device of the corresponding logic circuit and the memory elements within the corresponding memory array. In one embodiment, the corresponding memory array includes: vertically alternating stacks of insulating layer 32 and conductive layer 46; a plurality of memory aperture filling structures 58, each of the plurality of memory aperture filling structures including a corresponding vertical semiconductor channel and a corresponding vertical stack of memory elements located at a level of conductive layer 46; bit lines electrically connected to corresponding subsets of the plurality of memory aperture filling structures 58; stepped dielectric material portions 65 located on stepped surfaces of the alternating stacks (32, 46); and layer contact via structures 86 extending vertically through the stepped dielectric material portions 65 and contacting corresponding conductive layers in conductive layer 46.

[0119] Various embodiments of this disclosure simultaneously provide multi-level die stacking by placing front-side lead bonding on a front-side external bonding pad and back-side lead bonding on a back-side external bonding pad across an unlimited number of stacked bonding units. The double-sided bonding configuration increases the total external pad area available for lead bonding without sacrificing valuable device space for attaching lead bonding pads.

[0120] Although specific embodiments have been mentioned for the foregoing, it should be understood that this disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “substantially constitute…” or “consist of…” replace all embodiments in which the words “comprising” or “including” are used. While embodiments using specific structures and / or configurations are shown in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A structure including a stacked die assembly, wherein the stacked die assembly comprises: A vertical stack of multiple joining units, wherein each joining unit comprises: A memory die, the memory die including a memory-side die-in bonding pad and a memory-side external bonding pad located on opposite main surfaces of the memory die; and A logic die, the logic die including logic circuitry configured to control the operation of the memory die and including logic-side die-to-die bonding pads and logic-side external bonding pads located on opposite main surfaces of the logic die. in: The logic-side die-in bonding pad is coupled to the corresponding memory-side die-in bonding pad in the memory-side die-in bonding pad; and The memory-side external bonding pad and the logic-side external bonding pad include an upward-facing set of external bonding pads and a downward-facing set of external bonding pads, the upward-facing set of external bonding pads having an upward-facing physical exposed surface and the downward-facing set of external bonding pads having a downward-facing physical exposed surface. A first bonding lead assembly, wherein the first bonding lead assembly connects to an external bonding pad facing upwards; and The second bonding lead assembly has a downward-facing outer bonding pad.

2. The structure according to claim 1, wherein: Each pair of vertically adjacent joining units includes an upper joining unit and a lower joining unit; and The upper bonding unit is laterally offset relative to the lower bonding unit along a first horizontal direction.

3. The structure according to claim 2, wherein: The memory-side external bonding pad within each memory die is laterally offset from the edge of the memory die along the first horizontal direction by a uniform lateral offset distance; and The edge of the memory die extends laterally along a second horizontal direction perpendicular to the first horizontal direction.

4. The structure according to claim 3, wherein: The logic-side external bonding pads within each logic die are laterally offset from the edge of the logic die by a uniform lateral offset distance; and The edge of the logic die extends laterally along a second horizontal direction that is perpendicular to the first horizontal direction.

5. The structure according to claim 1, wherein: Each face-up external bonding pad within the stacked die assembly does not overlap in area with any overlying bonding unit within the stacked die assembly in a plan view along the direction along which the bonding units are stacked. and Each face-down external bonding pad within the stacked die assembly does not overlap in area with any lower bonding unit within the stacked die assembly in the plan view.

6. The structure according to claim 1, wherein: The upward-facing external bonding pad set includes the memory-side external bonding pads, and the downward-facing external bonding pad set includes the logic-side external bonding pads; or The face-down external bonding pad set includes the logic-side external bonding pad, and the face-down external bonding pad set includes the memory-side external bonding pad.

7. The structure according to claim 1, further comprising: Mounting substrate, the vertical stack of multiple bonding units is mounted on the mounting substrate by an additional adhesive layer; and Additional bonding leads provide an electrical connection between the outer bonding pad of the nearest bonding unit among the plurality of bonding units and the bonding pad located on the mounting substrate, wherein each pair of vertically adjacent bonding units is attached to each other by a corresponding adhesive layer.

8. The structure of claim 1, wherein the logic-side die-to-die bonding pad is bonded to the corresponding memory-side die-to-die bonding pad in the memory-side die-to-die bonding pad within each bonding unit by metal-to-metal bonding.

9. The structure according to claim 1, wherein one of the memory dies comprises: A three-dimensional memory array, wherein the three-dimensional memory array is located above the memory die substrate; A memory die metal interconnect structure, wherein the memory die metal interconnect structure is embedded in the dielectric material layer of the memory die; and A through-substrate via structure that extends vertically through the memory die substrate and is electrically connected to a corresponding memory-side external bonding pad in the memory-side external bonding pad.

10. The structure according to claim 9, wherein the three-dimensional memory array comprises: Alternating stacking of insulating and conductive layers; Multiple memory opening-filled structures, the multiple memory opening-filled structures extending vertically through the alternating stack; Bit lines, which are electrically connected to a corresponding subset of the plurality of memory aperture-filled structures; A stepped dielectric material portion, wherein the stepped dielectric material portion is located on the alternately stacked stepped surface; and A layer contact via structure that extends vertically through the stepped dielectric material portion and contacts a corresponding conductive layer in the conductive layer.

11. The structure of claim 10, wherein the logic die of the one memory die coupled to the memory die comprises: Sensing amplifier region, the sensing amplifier region including sensing amplifiers electrically connected to corresponding bit lines in the bit lines; and The peripheral device area includes a charge pump circuit.

12. The structure of claim 11, wherein the peripheral device region is located between the sense amplifier region and the logic side external bonding pad.

13. The structure according to claim 1, wherein at least one logic die comprises: A through-substrate via structure, the through-substrate via structure extending vertically through the logic die substrate and electrically connected to a corresponding logic-side external bonding pad in the logic-side external bonding pad; and A logic die metal interconnect structure is embedded in a logic die dielectric material layer and electrically connects the corresponding logic devices on the logic die substrate to the corresponding logic-side die-to-die interconnect pads in the logic-side die-to-die interconnect pads.

14. A method of forming a structure including a stacked die assembly, the method comprising: A plurality of bonding units are provided, wherein each bonding unit includes a memory die and a logic die, the memory die including a memory-side die-in bonding pad and a memory-side external bonding pad located on opposite main surfaces of the memory die, and the logic die including logic circuitry configured to control the operation of the memory die and including a logic-side die-in bonding pad and a logic-side external bonding pad located on opposite main surfaces of the logic die. The plurality of bonding units are vertically stacked by attaching them to each other, such that the memory-side external bonding pads and the logic-side external bonding pads of the plurality of bonding units form an upward-facing external bonding pad set and a downward-facing external bonding pad set, the upward-facing external bonding pad set having an upward-facing physical exposed surface and the downward-facing external bonding pad set having a downward-facing physical exposed surface. A first set of bonding leads is formed, which connects a pair of corresponding upward-facing external bonding pads in the set of upward-facing external bonding pads; as well as A second set of bonding leads is formed, which connects a pair of corresponding face-down outer bonding pads in the set of face-down outer bonding pads.

15. The method of claim 14, wherein each bonding unit is provided by bonding a corresponding logic die and a corresponding memory die such that the logic-side die-to-die bonding pad of the corresponding logic die is bonded to the corresponding memory-side die-to-die bonding pad in the memory-side die-to-die bonding pad of the corresponding memory die.

16. The method of claim 14, wherein the plurality of bonding units are staggered such that each overlay bonding unit is laterally offset relative to the underlay bonding unit along a first horizontal direction.

17. The method of claim 14, further comprising forming the vertical stack of the plurality of bonding units by attaching vertically adjacent bonding unit pairs using an adhesive layer.

18. The method according to claim 17, further comprising: An additional adhesive layer is used to attach the mounting substrate to the vertical stack of the plurality of bonding units; as well as The vertical stack of the plurality of bonding units is electrically connected to the mounting substrate by attaching additional bonding leads to the bonding pads located on the mounting substrate and the outer bonding pads of the nearest bonding unit between the vertical stack of the plurality of bonding units.

19. The method of claim 14, wherein providing the plurality of bonding units comprises forming each of the plurality of bonding units by bonding respective memory dies and respective logic dies to each other.

20. The method of claim 14, further comprising attaching the plurality of engaging units to each other such that: Each upward-facing outer bonding pad within the stacked die assembly does not overlap in area with any overlying bonding unit within the stacked die assembly in a plan view along the direction in which the bonding units are stacked; and Each face-down external bonding pad within the stacked die assembly does not overlap in area with any lower bonding unit within the stacked die assembly in the plan view.

21. A structure comprising a stacked die assembly, wherein the stacked die assembly comprises: A vertically stacked bonding unit, wherein each bonding unit comprises a corresponding front semiconductor die and a corresponding back semiconductor die, the corresponding front semiconductor die including a front external bonding pad, the corresponding back semiconductor die including a back external bonding pad, wherein the corresponding back semiconductor die is bonded to the corresponding front semiconductor die, and wherein the front external bonding pad of each bonding unit has an upward-facing physical exposed surface, and the back external bonding pad of each bonding unit has a downward-facing physical exposed surface; A first bonding lead assembly is connected to the front external bonding pad; and The second bonding lead assembly is connected to the back outer bonding pad.

22. The structure of claim 21, wherein each front semiconductor die further comprises a front memory array, and each back semiconductor die further comprises a back memory array.

23. The structure according to claim 22, wherein: The front semiconductor die within each bonding unit includes a front metal interconnect structure embedded in a front dielectric material layer, wherein a subset of the front metal interconnect structure is connected to the front external bonding pad within each bonding unit. and The back semiconductor die within each bonding unit includes a back metal interconnect structure embedded in a back dielectric material layer, wherein a subset of the back metal interconnect structure is connected to the back external bonding pad within each bonding unit.

24. The structure according to claim 21, wherein: The front semiconductor die within each bonding unit includes a front substrate; The back-side semiconductor die within each bonding unit includes a back-side substrate; and The front substrate is bonded to the back substrate.

25. The structure of claim 24, wherein the back semiconductor die and the front semiconductor die in the same bonding unit are not directly electrically connected to each other.

26. The structure according to claim 21, wherein: Each pair of vertically adjacent joining units includes an upper joining unit and a lower joining unit; and The upper bonding unit is laterally offset relative to the lower bonding unit along a first horizontal direction.

27. The structure according to claim 26, wherein: The front external bonding pad within each front semiconductor die is uniformly offset laterally from the edge of the front semiconductor die along the first horizontal direction by a distance; and The edge of the corresponding front semiconductor die extends laterally along a second horizontal direction perpendicular to the first horizontal direction.

28. The structure according to claim 26, wherein: The back external bonding pad within each back semiconductor die is laterally offset from the edge of the back semiconductor die by a uniform lateral offset distance. and The edge of the back semiconductor die extends laterally along a second horizontal direction perpendicular to the first horizontal direction.

29. The structure according to claim 21, wherein: Each frontal external bonding pad within the stacked die assembly does not have area overlap with any overlying bonding unit within the stacked die assembly in a plan view along the direction along which the bonding units are stacked. and Each back-side external bonding pad within the stacked die assembly does not overlap in area with any lower bonding unit within the stacked die assembly in the plan view.

30. The structure of claim 21, wherein each pair of vertically adjacent joining units is attached to each other by a corresponding adhesive layer.

31. The structure according to claim 30, further comprising: The mounting substrate, wherein the vertically stacked bonding units are mounted on the mounting substrate via an additional adhesive layer; and An additional bonding lead provides an electrical connection between the bonding pads located on the mounting substrate and the front and back outer bonding pads of the nearest bonding unit of the stacked die assembly.

32. The structure of claim 21, wherein each of the front semiconductor die and the back semiconductor die further comprises: Corresponding logic circuitry, the corresponding logic circuitry comprising semiconductor devices located on a corresponding substrate and configured to control the operation of memory elements within a corresponding memory array; and A corresponding metal interconnect structure is embedded in a corresponding dielectric material layer and provides an electrical connection between the semiconductor device of the corresponding logic circuit and the memory element in the corresponding memory array.

33. The structure of claim 32, wherein the corresponding memory array comprises: Insulating and conductive layers are stacked vertically in alternations; Multiple memory aperture filling structures, each of the multiple memory aperture filling structures including a corresponding vertical semiconductor channel and a corresponding vertical stack of memory elements located at the level of the conductive layer; Bit lines, which are electrically connected to a corresponding subset of the plurality of memory aperture-filled structures; A stepped dielectric material portion, wherein the stepped dielectric material portion is located on the alternately stacked stepped surface; and A layer contact via structure that extends vertically through the stepped dielectric material portion and contacts a corresponding conductive layer in the conductive layer.

34. A method of forming a structure including a stacked die assembly, the method comprising: A plurality of bonding units are provided, wherein each bonding unit includes a corresponding front semiconductor die and a corresponding back semiconductor die, the corresponding front semiconductor die including a front external bonding pad, the corresponding back semiconductor die including a back external bonding pad, wherein the corresponding back semiconductor die is bonded to the corresponding front semiconductor die. The plurality of bonding units are formed by attaching them to each other to form a vertical stack of the plurality of bonding units, such that the front outer bonding pad of each bonding unit has an upward-facing physical exposed surface, and the back outer bonding pad of each bonding unit has a downward-facing physical exposed surface. Form a first set of bonding leads connecting a pair of corresponding frontal external bonding pads; as well as A second set of bonding leads is formed to connect a pair of corresponding backside external bonding pads.

35. The method of claim 34, wherein the front semiconductor die further comprises a front memory array, and the back semiconductor die further comprises a back memory array.

36. The method of claim 35, wherein: The front semiconductor die within each bonding unit includes a front substrate; The back-side semiconductor die within each bonding unit includes a back-side substrate; and The front substrate is bonded to the back substrate.

37. The method of claim 36, wherein the back semiconductor die and the front semiconductor die in the same bonding unit are not directly electrically connected to each other.

38. The method of claim 34, wherein the plurality of bonding units are staggered such that each overlay bonding unit is laterally offset relative to the underlay bonding unit along a first horizontal direction.

39. The method of claim 34, further comprising forming the vertical stack of the plurality of bonding units by attaching vertically adjacent bonding unit pairs using an adhesive layer.

40. The method according to claim 39, further comprising: An additional adhesive layer is used to attach the mounting substrate to the vertical stack of the plurality of bonding units; as well as The vertical stack of the plurality of bonding units is electrically connected to the mounting substrate by attaching additional bonding leads to the bonding pads located on the mounting substrate and the front or back outer bonding pads of the nearest bonding unit between the vertical stack of the plurality of bonding units.

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