Imaging device and electronic device

Abstract

In this invention, the stacked imaging element can simultaneously ensure a wide sensitive area and a large amount of accumulated charge. The imaging element includes a pixel comprising: a photoelectric conversion layer (15); a first electrode (11) located on a first surface of the photoelectric conversion layer and electrically connected to the photoelectric conversion layer; a second electrode (16) located on a second surface of the photoelectric conversion layer opposite to the first surface; a charge accumulation electrode (12) located on the first surface of the photoelectric conversion layer and spaced apart from the first electrode in a direction parallel to the first surface; and a third electrode (200) located at a position overlapping the gap between the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface.

Description

Technical Field

[0001] This disclosure relates to an imaging device and an electronic device. Background Technology

[0002] A multilayer imaging device has been proposed in which multiple photoelectric conversion units with different absorption coefficients for different wavelengths of light are stacked together. In this multilayer imaging device, for example, a first photoelectric conversion unit made of an organic film is formed on a semiconductor layer, and second and third photoelectric conversion units are formed within the semiconductor layer. The first photoelectric conversion unit performs photoelectric conversion on light in a first wavelength region received on the organic film, which serves as a light-receiving surface, to generate a charge. Furthermore, the second and third photoelectric conversion units perform photoelectric conversion on light in second and third wavelength regions, respectively, received through layers higher than the second and third photoelectric conversion units, to generate charges.

[0003] In this configuration, the charge generated by photoelectric conversion in the second and third photoelectric conversion units is temporarily accumulated in the second and third photoelectric conversion units, and then transferred to the second and third floating diffusion regions formed in the semiconductor layer at predetermined times. Conversely, the charge generated in the first photoelectric conversion unit formed of the organic film is transferred through contact holes and wiring layers to the first floating diffusion region formed in the semiconductor layer and accumulates there. As described above, if the charge is directly transferred from the first photoelectric conversion unit to the first floating diffusion region, causing the transferred charge to accumulate there, there is a concern that kTC noise may increase and random noise may degrade, resulting in a decrease in the quality of the captured image.

[0004] In this regard, it has been disclosed that a charge accumulation electrode, serving as a transparent electrode, and a readout electrode spaced apart from the charge accumulation electrode are provided on the surface of the first photoelectric conversion unit opposite to the light receiving surface, and a common electrode shared by the charge accumulation electrode and the readout electrode is provided on the light receiving surface (e.g., Patent Document 1). In this configuration, a potential barrier is generated between the charge accumulation electrode and the readout electrode by applying a bias voltage from the common electrode. By controlling the voltage applied to the charge accumulation electrode and the readout electrode, the charge generated by photoelectric conversion can be accumulated between the charge accumulation electrode and the common electrode, and the accumulated charge can be read out by the readout electrode and transferred to the first floating diffusion region. According to this configuration, the occurrence of the aforementioned phenomena (e.g., the increase of kTC noise and the degradation of random noise) can be suppressed.

[0005] Reference List

[0006] Patent documents

[0007] Patent Document 1: JP 2017-157816 A Summary of the Invention

[0008] Technical issues

[0009] In the construction of Patent Document 1, the amount of signal charge accumulated by the charge accumulation electrode (accumulated charge) is ensured by the potential barrier between the charge accumulation electrode and the readout electrode. In this case, by increasing the distance between the charge accumulation electrode and the readout electrode, a high potential barrier can be generated and the amount of accumulated charge can be increased, but the sensitive area is reduced, resulting in a decrease in sensitivity.

[0010] The purpose of this disclosure is to provide an imaging device and electronic device that can simultaneously ensure a wide sensitive area and ensure the amount of accumulated charge.

[0011] Technical solutions to the problem

[0012] To address the aforementioned problems, an imaging apparatus according to one aspect of this disclosure includes a pixel comprising: a photoelectric conversion layer; a first electrode located on a first surface side of the photoelectric conversion layer and electrically connected to the photoelectric conversion layer; a second electrode located on a second surface of the photoelectric conversion layer opposite to the first surface; a charge accumulation electrode disposed on the first surface side of the photoelectric conversion layer and spaced apart from the first electrode in a direction parallel to the first surface; and a third electrode disposed at a position having an overlap portion with the gap between the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface. Attached Figure Description

[0013] Figure 1 This is a block diagram illustrating the construction of an example of an electronic device to which the technology is applicable according to various embodiments of the present disclosure.

[0014] Figure 2 This is a block diagram illustrating the construction of an example imaging element to which various embodiments of the present disclosure are applicable.

[0015] Figure 3 This is a schematic partial cross-sectional view of pixels in the prior art.

[0016] Figure 4 This is a diagram showing the equivalent circuit of a pixel in the prior art.

[0017] Figure 5 This is a diagram showing an example of the arrangement of the first electrode and the charge accumulation electrode in a pixel.

[0018] Figure 6 This is a schematic diagram showing an example of the arrangement of the second electrode in an imaging element.

[0019] Figure 7 This is a diagram used to illustrate the operation of the first photoelectric conversion unit.

[0020] Figure 8 This is a schematic diagram used to illustrate the relationship between electrode construction and accumulated charge according to the prior art.

[0021] Figure 9 This is a schematic diagram illustrating the electrode structure and operation in a pixel according to the first embodiment.

[0022] Figure 10 This is a schematic partial cross-sectional view of the pixels according to the first embodiment.

[0023] Figure 11 This is a diagram illustrating another example of the arrangement of the barrier forming electrode to which the first embodiment applies.

[0024] Figure 12A This is a schematic diagram illustrating an example arrangement of the first electrode, charge accumulation electrode, and barrier forming electrode applicable to the first embodiment.

[0025] Figure 12B This is a schematic diagram illustrating an example arrangement of the first electrode, charge accumulation electrode, and barrier forming electrode applicable to the first embodiment.

[0026] Figure 13A This is a schematic diagram illustrating an example arrangement of the first electrode, charge accumulation electrode, and barrier forming electrode applicable to the first embodiment.

[0027] Figure 13B This is a schematic diagram illustrating an example arrangement of the first electrode, charge accumulation electrode, and barrier forming electrode applicable to the first embodiment.

[0028] Figure 14A This is a schematic diagram illustrating an example arrangement of the first electrode, charge accumulation electrode, and barrier forming electrode applicable to the first embodiment.

[0029] Figure 14B This is a schematic diagram illustrating an example arrangement of the first electrode, charge accumulation electrode, and barrier forming electrode applicable to the first embodiment.

[0030] Figure 15A This is a schematic diagram illustrating an example arrangement of the first electrode, charge accumulation electrode, and barrier forming electrode applicable to the first embodiment.

[0031] Figure 15B This is a schematic diagram illustrating an example arrangement of the first electrode, charge accumulation electrode, and barrier forming electrode applicable to the first embodiment.

[0032] Figure 16AThis is a schematic diagram illustrating a first example of a method for applying a voltage to a barrier forming electrode to which the first embodiment applies.

[0033] Figure 16B This is a schematic diagram illustrating a second example of a method for applying a voltage to a barrier forming electrode, applicable to the first embodiment.

[0034] Figure 16C This is a schematic diagram illustrating a third example of a method for applying a voltage to a barrier forming electrode to which the first embodiment applies.

[0035] Figure 17 This is a schematic diagram illustrating a fourth example of a method for applying a voltage to a barrier forming electrode to which the first embodiment applies.

[0036] Figure 18A This is a schematic diagram illustrating a first example of pixel construction according to a first variation of the first embodiment.

[0037] Figure 18B This is a schematic diagram illustrating a second example of pixel construction according to a first variation of the first embodiment.

[0038] Figure 18C This is a schematic diagram illustrating a third example of pixel construction according to a first variation of the first embodiment.

[0039] Figure 19 This is a diagram illustrating an example of the electrode arrangement according to a second variation of the first embodiment.

[0040] Figure 20A This is a schematic diagram illustrating the state of the potential barrier under the charge accumulation state according to the second embodiment.

[0041] Figure 20B This is a schematic diagram showing the state of the potential barrier under the charge transport state according to the second embodiment.

[0042] Figure 21 This is a diagram illustrating an example arrangement of barrier-forming electrodes applicable to the second embodiment.

[0043] Figure 22 This is a schematic diagram showing the state of the barrier in the accumulated state according to the second embodiment.

[0044] Figure 23 This is a diagram illustrating an example of the use of an imaging device employing the technology disclosed herein.

[0045] Figure 24 This is a diagram illustrating a schematic example of the construction of an endoscopic surgical system.

[0046] Figure 25 This is a block diagram illustrating an example of the functional structure between the camera head and the CCU.

[0047] Figure 26 This is a block diagram illustrating a schematic example of the construction of a vehicle control system.

[0048] Figure 27 This is an explanatory diagram showing an example of the placement of the vehicle exterior information detection unit and the imaging unit. Detailed Implementation

[0049] In the following description, embodiments of the present disclosure will be detailed with reference to the accompanying drawings. Note that in the following embodiments, the same parts are indicated by the same reference numerals, and repeated descriptions will be omitted.

[0050] In the following description, embodiments of the present disclosure will be described in the following order.

[0051] 1. Applicable technologies for each embodiment

[0052] 1-0-1. Applicable Electronic Devices for Each Embodiment

[0053] 1-0-2. Prior Art Related to Each Embodiment

[0054] 1-0-3. Relationship between electrode structure and accumulated charge based on existing technology

[0055] 2. First Embodiment

[0056] 2-0-1. Overview of the imaging element according to the first embodiment

[0057] 2-0-2. A more specific example of the construction of the imaging element according to the first embodiment.

[0058] 2-0-3. Example of electrode construction according to the first embodiment

[0059] 2-0-4. Method for applying voltage to barrier forming electrode according to the first embodiment

[0060] 2-1. First variation of the first embodiment

[0061] 2-2. Second variation of the first embodiment

[0062] 3. Second Embodiment

[0063] 4. Third embodiment

[0064] 5. Fourth Embodiment

[0065] 5-1. Examples of application of the technology according to this disclosure

[0066] 5-2. Examples of the application of endoscopic surgical systems

[0067] 5-3. Examples of applications of moving bodies

[0068] [1. Applicable Technologies for Each Embodiment]

[0069] Before describing the various embodiments of this disclosure, the techniques applicable to each embodiment will be illustrated schematically for ease of understanding.

[0070] (1-0-1. Applicable Electronic Devices for Each Embodiment)

[0071] First, an electronic device to which the technology is applicable according to the various embodiments of this disclosure will be described. Figure 1 This is a block diagram illustrating the construction of an example of an electronic device to which the technology is applicable according to various embodiments of the present disclosure.

[0072] exist Figure 1 In this context, the electronic device 1000 includes an optical unit 1010, an imaging device 1011, a signal processing circuit 1012, a display device 1013, and a storage medium 1014. Figure 1 In this embodiment, the imaging device 1011 utilizes an imaging element, which will be described in detail later according to this disclosure. The imaging element includes multiple pixels and a driving circuit. Each pixel converts incident light into an electrical signal via photoelectric conversion, and the driving circuit drives the multiple pixels. Here, the electronic device 1000 can be applied to include digital cameras, digital video cameras, mobile phones with imaging capabilities, or smartphones, etc.

[0073] The optical unit 1010 includes one or more lenses, an aperture mechanism, a focusing mechanism, etc., and forms an image of the image light (incident light) from the subject on the imaging surface of the imaging device 1011. As a result, signal charge accumulates in the imaging device 1011 for a certain period of time. The signal processing circuit 1012 performs various signal processing, including image processing, on the pixel signals output from the imaging device 1011. The processed image signal can be stored in a non-volatile storage medium 1014, such as flash memory or a hard disk drive. Furthermore, the image based on the pixel signals can also be output to the display device 1013.

[0074] (1-0-2. Prior Art Related to Each Embodiment)

[0075] The prior art associated with each embodiment will now be illustrated schematically. Figure 2 This is a block diagram illustrating the construction of an example imaging element to which various embodiments of the present disclosure are applicable. Figure 2In the imaging element 100, there are: a pixel array unit 111, wherein pixels 101 are arranged in a matrix array; and a driving circuit as peripheral circuitry of the pixel array unit 111, the driving circuit being used to drive each pixel 101 included in the pixel array unit 111. More specifically, the driving circuit includes a vertical driving circuit 112, a column signal processing circuit 113, a horizontal driving circuit 114, an output circuit 115, and a driving control circuit 116.

[0076] The drive control circuit 116 generates clock and control signals based on the vertical synchronization signal, horizontal synchronization signal, and master clock provided externally to the imaging element 100, which serve as references for the operation of the vertical drive circuit 112, column signal processing circuit 113, and horizontal drive circuit 114. The drive control circuit 116 provides the generated clock and control signals to the vertical drive circuit 112, column signal processing circuit 113, and horizontal drive circuit 114.

[0077] For example, the vertical drive circuit 112 includes a shift register and sequentially and selectively scans the pixels 101 of the pixel array unit 111 in the vertical direction, row by row. Then, a pixel signal (image signal) based on the current (signal) generated according to the amount of light received in each pixel 101 is sent to the column signal processing circuit 113 via a vertical signal line 117, which serves as a data output line. Note that the vertical signal line 117 will also be referred to as VSL.

[0078] For example, column signal processing circuits 113 are arranged for each column of pixels 101, and the column signal processing circuits 113 perform noise removal and signal amplification on the image signal output from a row of pixels 101 using the signal from the black reference pixel. Note that the black reference pixel is a pixel 101 (not shown) arranged around the effective pixel area in the pixel array unit 111. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 113, and the horizontal selection switch is connected between the column signal processing circuit 113 and the horizontal signal line 118.

[0079] For example, the horizontal drive circuit 114 includes a shift register and sequentially selects the column signal processing circuits 113 by sequentially outputting horizontal scan pulses, such that each column signal processing circuit 113 outputs a signal to the horizontal signal line 118. After signal processing, the output circuit 115 outputs the signals sequentially provided from each column signal processing circuit 113 via the horizontal signal line 118.

[0080] Figure 3 This is a schematic partial cross-sectional view of pixel 101 in the prior art. Additionally, Figure 4 It shows Figure 3The diagram shows the equivalent circuit of pixel 101. Pixel 101 is a multilayer photoelectric conversion element consisting of multiple photoelectric conversion units stacked together. Reference will be made below to... Figure 3 and Figure 4 Explain the construction of pixel 101.

[0081] Figure 3 The pixel 101 shown includes multiple stacked photoelectric conversion units, each performing photoelectric conversion. In the following text, the photoelectric conversion unit closest to the light-receiving surface in pixel 101 will be referred to as the first photoelectric conversion unit, and it will be referred to as the uppermost photoelectric conversion unit among the multiple photoelectric conversion units. Figure 3 In the example, the second photoelectric conversion unit is arranged in a layer below the first photoelectric conversion unit, and the third photoelectric conversion unit is further arranged in a layer below the second photoelectric conversion unit.

[0082] The first photoelectric conversion unit includes a photoelectric conversion layer 15, a first electrode 11 located on a first surface side of the photoelectric conversion layer 15 and electrically connected to the photoelectric conversion layer 15, a second electrode 16 located on a second surface of the photoelectric conversion layer 15 opposite to the first surface, and a charge accumulation electrode 12 disposed on the first surface side of the photoelectric conversion layer 15 and spaced apart from the first electrode 11 in a direction parallel to the first surface. As described above, the first electrode 11 and the charge accumulation electrode 12 are arranged to be spaced apart from each other by a gap.

[0083] Pixel 101 also includes a semiconductor substrate (more specifically, a silicon semiconductor layer) 70, and a first photoelectric conversion unit is disposed above the semiconductor substrate 70. The pixel also includes a control unit disposed in the semiconductor substrate 70 and including a drive circuit connected to the first electrode 11. Here, the light incident surface of the semiconductor substrate 70 is defined as the upper side, and the surface of the semiconductor substrate 70 opposite to the light incident surface is defined as the lower side. A wiring layer 62 including multiple wirings is disposed below the semiconductor substrate 70.

[0084] Furthermore, the semiconductor substrate 70 is provided with at least a first floating diffusion layer FD1 constituting the control unit (see Figure 4 ) and amplifying transistor TR1 amp (see Figure 3 and Figure 4 The first electrode 11 is connected to the first floating diffusion layer FD1 and the amplifying transistor TR1. amp The gate portion. The semiconductor substrate 70 also includes a reset transistor TR1 constituting the control unit. rst and select transistor TR1 sel (see Figure 3 and Figure 4 ).

[0085] The first floating diffusion layer FD1 is connected to the reset transistor TR1. rst A source / drain region, amplifying transistor TR1 amp One source / drain region is connected to the select transistor TR1 sel A source / drain region, and select transistor TR1 sel Another source / drain region is connected to signal line VSL1 (see Figure 4 Amplifying transistor TR1 amp Reset transistor TR1 rst and select transistor TR1 sel It forms the driving circuit.

[0086] Specifically, Figure 3 The pixel 101 shown is a back-illuminated photoelectric conversion element, which is also a multilayer photoelectric conversion element. This multilayer photoelectric conversion element has a structure in which three photoelectric conversion units are stacked. These three photoelectric conversion units are: a first type of green photoelectric conversion unit (hereinafter referred to as the first photoelectric conversion unit), which is sensitive to green and has a first type of green photoelectric conversion layer that absorbs green light; a second type of blue photoelectric conversion unit (hereinafter referred to as the second photoelectric conversion unit), which is sensitive to blue and has a second type of blue photoelectric conversion layer that absorbs blue light; and a second type of red photoelectric conversion unit (hereinafter referred to as the third photoelectric conversion unit), which is sensitive to red and has a second type of red photoelectric conversion layer that absorbs red light.

[0087] Here, a red photoelectric conversion unit (third photoelectric conversion unit) and a blue photoelectric conversion unit (second photoelectric conversion unit) are disposed in the semiconductor substrate 70, with the second photoelectric conversion unit closer to the light incident side than the third photoelectric conversion unit. A green photoelectric conversion unit (first photoelectric conversion unit) is disposed above the blue photoelectric conversion unit (second photoelectric conversion unit). A pixel is configured with a structure in which the first, second, and third photoelectric conversion units are stacked. No color filter is provided.

[0088] In the first photoelectric conversion unit, the first electrode 11 and the charge accumulation electrode 12 are formed separately on the interlayer insulating layer 81. The interlayer insulating layer 81 and the charge accumulation electrode 12 are covered by the insulating layer 82. The photoelectric conversion layer 15 is formed on the insulating layer 82, and the second electrode 16 is formed on the photoelectric conversion layer 15. A protective layer 83 is formed on the entire surface including the second electrode 16, and an on-chip microlens 90 is disposed on the protective layer 83.

[0089] For example, the first electrode 11, the charge accumulation electrode 12, and the second electrode 16 are made of transparent electrodes made of indium tin oxide (ITO). The photoelectric conversion layer 15 is composed of a layer (organic film) containing at least a known organic photoelectric conversion material sensitive to green (e.g., organic materials such as rhodamine dye, cyanide dye, or quinacridone). Furthermore, the photoelectric conversion layer 15 may also be composed of a material layer suitable for charge accumulation. That is, a material layer suitable for charge accumulation may also be formed between the photoelectric conversion layer 15 and the first electrode 11 (e.g., in the connection portion 67).

[0090] Interlayer insulating layer 81, insulating layer 82, and protective layer 83 are made of known insulating materials (SiO2 or SiN). The photoelectric conversion layer 15 and the first electrode 11 are connected via a connection portion 67 provided in the insulating layer 82. The photoelectric conversion layer 15 extends through the connection portion 67. That is, the photoelectric conversion layer 15 is connected to the first electrode 11 by extending through an opening 84 provided in the insulating layer 82.

[0091] The charge accumulation electrode 12 is connected to the drive circuit. Specifically, the charge accumulation electrode 12 is connected via a connection hole 66, a pad 64, and a wiring V provided in the interlayer insulating layer 81. OA (Not shown) Connected to the vertical drive circuit 112 that constitutes the drive circuit.

[0092] The charge accumulation electrode 12 has a larger size (area) than the first electrode 11. When the size of the charge accumulation electrode 12 is defined as area S2 and the size of the first electrode 11 is defined as area S1, the relationship between areas S1 and S2 preferably satisfies the following equation (1).

[0093] 4≤S2 / S1 (1)

[0094] Figure 5 This is a schematic diagram showing an example of the arrangement of the first electrode 11 and the charge accumulation electrode 12 in pixel 101. Figure 5 The diagram schematically illustrates the state of pixel 101 as viewed from above the light-receiving surface. Figure 5 In the example, the first electrode 11 is arranged along one side of the pixel 101, which has a rectangular shape, and the charge accumulation electrode 12 is arranged spaced apart from the first electrode 11, i.e., there is a gap of a predetermined width between them. Figure 5 In the example, the first electrode 11 and the charge accumulation electrode 12 are formed and arranged such that the area S1 of the first electrode 11 and the area S2 of the charge accumulation electrode 12 have a relationship that satisfies the following equation (2).

[0095] S2 / S1=8 (2)

[0096] Note that the relationship between areas S1 and S2 is not limited to the relationship expressed by formulas (1) and (2) above.

[0097] Figure 6 This is a schematic diagram showing an example of the arrangement of the second electrode 16 in the imaging element 100. Figure 6 The diagram schematically shows a portion of the pixel array unit 111 as viewed from an obliquely above the light-receiving surface. (Example) Figure 6 As shown, the second electrode 16 is a common electrode shared by pixels 101. Furthermore, wiring V is provided for each row of pixel array units 111 in the layer below the charge accumulation electrode 12. OA Charge accumulation electrodes 12 are connected to each pixel 101 arranged in the row.

[0098] By controlling the voltage applied to the first electrode 11, the charge accumulation electrode 12, and the second electrode 16 to a predetermined value, the charge generated by photoelectric conversion in the first photoelectric conversion unit can be accumulated and transferred.

[0099] For example, when the first photoelectric conversion unit is exposed, a negative bias voltage is applied to the second electrode 16, and from the wiring V OA A positive bias voltage is applied to the charge accumulation electrode 12. Additionally, a predetermined positive bias voltage is also applied to the first electrode 11. As a result, a potential barrier is generated in the gap between the first electrode 11 and the charge accumulation electrode 12, and the charge generated by photoelectric conversion accumulates between the charge accumulation electrode 12 and the second electrode 16.

[0100] With the exposure over, from wiring V OA A negative bias voltage is applied to the charge accumulation electrode 12, such that the potential corresponding to the charge accumulation electrode 12 is higher than the potential barrier in the gap between the first electrode 11 and the charge accumulation electrode 12. As a result, the charge accumulated between the charge accumulation electrode 12 and the second electrode 16 flows over the potential barrier into the first electrode 11. The charge flowing into the first electrode 11 is supplied as a current to the predetermined wiring of the wiring layer 62 via the contact hole 61, which will be described later.

[0101] Next, the structure of the semiconductor substrate 70 will be described in more detail. A pixel isolation region 71 is formed on the first surface (front surface) 70A side of the semiconductor substrate 70, and an oxide film 72 is formed on the first surface 70A of the semiconductor substrate 70. Furthermore, a reset transistor TR1 constituting the control unit of the first photoelectric conversion unit is disposed on the first surface side of the semiconductor substrate 70. rst Amplifying transistor TR1 amp and select transistor TR1 sel It also has a first floating diffusion layer FD1.

[0102] Reset transistor TR1 rstIt includes a gate portion 51, a channel forming region 51A, and source / drain regions 51B and 51C. Reset transistor TR1 rst The gate portion 51 is connected to the reset line RST1, and the reset transistor TR1 rst One source / drain region 51C also serves as the first floating diffusion layer FD1, and the other source / drain region 51B is connected to the power supply V. DD (see Figure 4 ).

[0103] The first electrode 11 is connected to the reset transistor TR1 via a connection hole 65 and a pad 63 disposed in the interlayer insulating layer 81, a contact hole 61 formed in the semiconductor substrate 70 and the interlayer insulating layer 76, and a wiring layer 62 formed in the interlayer insulating layer 76. rst A source / drain region 51C (first floating diffusion layer FD1).

[0104] Amplifying transistor TR1 amp It includes a gate portion 52, a channel forming region 52A, and source / drain regions 52B and 52C. The gate portion 52 is connected to the first electrode 11 and the reset transistor TR1 via a wiring layer 62. rst A source / drain region 51C (first floating diffusion layer FD1). Additionally, a source / drain region 52B is present in conjunction with the reset transistor TR1. rst Another source / drain region, 51B, shares a region and is simultaneously connected to the power supply V. DD .

[0105] Select transistor TR1 sel It includes a gate portion 53, a channel forming region 53A, and source / drain regions 53B and 53C. The gate portion 53 is connected to the select line SEL1 (see [link to relevant documentation]). Figure 4 In addition, a source / drain region 53B forms the amplifying transistor TR1. amp Another source / drain region 52C shares a region, and another source / drain region 53C is connected to the vertical signal line 117 (see [link]). Figure 2 In this case, vertical signal line 117 corresponds to... Figure 4 VSL1 in the middle.

[0106] The second photoelectric conversion unit includes an n-type semiconductor region 41 disposed in the semiconductor substrate 70 as a photoelectric conversion layer 400. A transmission transistor TR2 formed by a vertical transistor is also included. trs The gate portion 45 extends into the n-type semiconductor region 41 and is connected to the transfer gate line TG2 (see [reference]). Figure 4 Additionally, in the transmission transistor TR2 trsA second floating diffusion layer FD2 is disposed in region 45C of the semiconductor substrate 70 near the gate portion 45 (see Figure 4 The charge accumulated in the n-type semiconductor region 41 is read out to the second floating diffusion layer FD2 via a transport channel formed along the gate portion 45.

[0107] In the second photoelectric conversion unit, a reset transistor TR2 constituting the control unit of the second photoelectric conversion unit is also provided on the first surface side of the semiconductor substrate 70. rst Amplifying transistor TR2 amp and select transistor TR2 sel .

[0108] Reset transistor TR2 rst This includes the gate region, the channel formation region, and the source / drain region. Reset transistor TR2 rst The gate of the reset transistor TR2 is connected to the reset line RST2. rst One source / drain region is connected to the power supply V. DD Furthermore, another source / drain region also serves as the second floating diffusion layer FD2 (see [reference]). Figure 4 ).

[0109] Amplifying transistor TR2 amp It includes the gate portion, the channel formation region, and the source / drain region. The gate portion is connected to the reset transistor TR2. rst Another source / drain region (second floating diffusion layer FD2, see...) Figure 4 Furthermore, a source / drain region is located in relation to the reset transistor TR2. rst A source / drain region shares a region and is simultaneously connected to the power supply V. DD (see Figure 4 ).

[0110] Select transistor TR2 sel This includes the gate portion, the channel formation region, and the source / drain region. The gate portion is connected to the select line SEL2 (see [link]). Figure 4 In addition, a source / drain region forms the amplifying transistor TR2. amp Another source / drain region shares a region, and another source / drain region is connected to vertical signal line 117 (see [link]). Figure 2 In this case, vertical signal line 117 corresponds to... Figure 4 VSL2 in the middle.

[0111] The third photoelectric conversion unit includes an n-type semiconductor region 43 disposed in the semiconductor substrate 70 as a photoelectric conversion layer 401. Transmission transistor TR3 trs Gate portion 46 is connected to transmission gate line TG3 (see Figure 4 Additionally, in the transmission transistor TR3... trs A third floating diffusion layer FD3 is disposed in region 46C of the semiconductor substrate 70 near the gate portion 46 (see Figure 4 The charge accumulated in the n-type semiconductor region 43 is read out to the third floating diffusion layer FD3 via the transport channel 46A formed along the gate portion 46.

[0112] In the third photoelectric conversion unit, a reset transistor TR3 constituting the control unit of the third photoelectric conversion unit is also provided on the first surface side of the semiconductor substrate 70. rst Amplifying transistor TR3 amp and select transistor TR3 sel .

[0113] Reset transistor TR3 rst This includes the gate region, the channel formation region, and the source / drain region. Reset transistor TR3 rst The gate of the transistor is connected to the reset line RST3, and the reset transistor TR3 is used. rst One source / drain region is connected to the power supply V. DD Furthermore, another source / drain region also serves as the third floating diffusion layer FD3 (see [link]). Figure 4 ).

[0114] Amplifying transistor TR3 amp It includes the gate portion, the channel formation region, and the source / drain region. The gate portion is connected to the reset transistor TR3. rst Another source / drain region (third floating diffusion layer FD3). Furthermore, a source / drain region is located in conjunction with the reset transistor TR3. rst A source / drain region shares a region and is simultaneously connected to the power supply V. DD (see Figure 4 ).

[0115] Select transistor TR3 sel This includes the gate portion, the channel formation region, and the source / drain region. The gate portion is connected to the select line SEL3 (see [link]). Figure 4 In addition, a source / drain region forms the amplifying transistor TR3. amp Another source / drain region shares a region, and another source / drain region is connected to vertical signal line 117 (see [link]). Figure 2 In this case, vertical signal line 117 corresponds to... Figure 4 VSL3 in the middle.

[0116] The aforementioned reset lines RST1, RST2, and RST3, select lines SEL1, SEL2, and SEL3, and transmission gate lines TG2 and TG3 are connected to the vertical drive circuit 112 that constitutes the drive circuit. Additionally, each of the vertical signal lines 117 (VSL1, VSL2, and VSL3) of the first, second, and third photoelectric conversion units is connected to the column signal processing circuit 113 that constitutes the drive circuit.

[0117] A p-type semiconductor region 43 is disposed between the n-type semiconductor region 43 and the front surface 70A of the semiconductor substrate 70. + Layer 44 is used to suppress the generation of dark current. A p-type semiconductor region is formed between n-type semiconductor region 41 and n-type semiconductor region 43. + Layer 42, and the sides of the n-type semiconductor region 43 are partially covered by p + Layer 42 surrounds the semiconductor substrate 70. p is formed on the back side 70B of the semiconductor substrate 70. + Layer 73, and from p + In the portion of layer 73 where contact holes 61 are formed within the semiconductor substrate 70, an HfO2 film 74 and an insulating film 75 are formed. The HfO2 film 74 is a film with a negative fixed charge. Note that in the interlayer insulating layer 76, wiring is formed on multiple layers, but in... Figure 3 The text is omitted.

[0118] Next, we will refer to Figure 7 The operation of the first photoelectric conversion unit described above will now be explained. Here, the first electrode 11 is set to have a higher potential than the second electrode 16. That is, for example, the first electrode 11 is set to have a positive potential and the second electrode 16 is set to have a negative potential, such that electrons after photoelectric conversion in the photoelectric conversion layer 15 are read out to the floating diffusion layer. Note that in the mode where the first electrode 11 is set to have a negative potential and the second electrode 16 is set to have a positive potential, such that holes generated in the photoelectric conversion layer 15 based on photoelectric conversion are read out to the floating diffusion layer, simply inverting the potential levels described below is sufficient.

[0119] Figure 7 The meanings of the reference numerals used in the accompanying drawings are as follows.

[0120] (1) PA: The potential at point PA in the region of the photoelectric conversion layer 15 facing the charge accumulation electrode 12 (see Figure 7 (The image in the lower left corner).

[0121] (2) PB: The potential of point PB in the region of the photoelectric conversion layer 15 facing the area between the charge accumulation electrode 12 and the first electrode 11 (see [reference]). Figure 7 (The image in the lower left corner).

[0122] (3) FD: Potential of the first floating diffusion layer FD1.

[0123] (4)VOA: Potential of charge accumulation electrode 12.

[0124] (5) RST: Reset transistor TR1 rst The potential of the gate portion 51.

[0125] (6) VDD: Power supply V DD The potential.

[0126] Reference Figure 7 The upper left figure illustrates the charge accumulation period. During the charge accumulation period, a potential V is applied to the first electrode 11 from the driving circuit. 11 A potential V is applied to the charge accumulation electrode 12. 12 Light incident on the photoelectric conversion layer 15 undergoes photoelectric conversion within the layer 15. Holes generated by the photoelectric conversion travel from the second electrode 16 through wiring V. OU (Not shown) is sent to the drive circuit.

[0127] On the other hand, since the first electrode 11 is configured to have a higher potential than the second electrode 16—in other words, for example, a positive potential is applied to the first electrode 11 and a negative potential is applied to the second electrode 16—V 12 ≥V 11 Preferably V 12 >V 11 As a result, electrons (charges) generated through photoelectric conversion are attracted to the charge accumulation electrode 12, and the electrons remain in the region of the photoelectric conversion layer 15 facing the charge accumulation electrode 12. That is, charge accumulates in the photoelectric conversion layer 15. Due to V 12 >V 11 Therefore, electrons generated inside the photoelectric conversion layer 15 do not move toward the first electrode 11. As the photoelectric conversion time passes, the potential in the region of the photoelectric conversion layer 15 facing the charge accumulation electrode 12 becomes more negative.

[0128] A reset operation is performed later in the charge accumulation period. Figure 7 The upper middle diagram schematically illustrates an example of the state of each unit during a reset operation. Through the reset operation, the potential FD of the first floating diffusion layer FD1 is reset, and the potential of the first floating diffusion layer FD1 becomes the power supply V. DD The potential VDD.

[0129] After the reset operation is completed, the charge is read out. Figure 7 The upper right figure schematically illustrates the state of each unit during charge readout, i.e., when charge is transferred from the charge accumulation electrode 12 to the first electrode 11. During the charge transfer period, a potential V is applied to the first electrode 11 from the drive circuit. 21And apply a potential V to the charge accumulation electrode 12 22 Here, the potential is set to V. 22 <V 21 As a result, the charge retained in the region of the photoelectric conversion layer 15 facing the charge accumulation electrode 12 is read out to the first electrode 11, and further read out from the first electrode 11 to the first floating diffusion layer FD1 via the contact hole 61. That is, the charge accumulated in the photoelectric conversion layer 15 is read out to the control unit.

[0130] Then, a series of operations of the first photoelectric conversion unit were completed, such as charge accumulation, reset operation and charge transfer. Figure 7 The lower right figure shows examples of the changes in potentials VOA, PA, PB, FD, and RST during various operations.

[0131] After electrons are read out into the first floating diffusion layer FD1, the amplifying transistor TR1 amp and select transistor TR1 sel The operation is the same as that of conventional amplifying transistors and selecting transistors. Furthermore, a series of operations of the second and third photoelectric conversion units, such as charge accumulation, reset operation, and charge transport, are the same as conventional operations such as charge accumulation, reset operation, and charge transport. In addition, the reset noise of the first floating diffusion layer FD1 can be removed through correlated double sampling (CDS) processing in a manner similar to existing technologies.

[0132] (1-0-3. Relationship between electrode structure and accumulated charge based on existing technology)

[0133] Next, we will refer to Figure 8 This schematically illustrates the relationship between electrode construction and accumulated charge according to the prior art. Figure 8 In part (a), it corresponds to the reference. Figure 5 In the electrode configuration, the first electrode 11 is disposed along one side of the pixel 101 having a rectangular shape, and the charge accumulation electrode 12 is disposed with a predetermined gap between it and the first electrode 11.

[0134] In the configuration of this part (a), as described above, when a gap 14 is provided between the first electrode 11 and the charge accumulation electrode 12, a bias voltage is applied through the second electrode 16 to generate a potential barrier corresponding to the position of the gap 14. At this time, by making the gap 14 wider, the amount of accumulated charge Qs accumulated by the charge accumulation electrode 12 increases. On the other hand, when the gap 14 is made wider, the area of ​​the charge accumulation electrode 12 decreases, that is, the sensitive area decreases, thereby resulting in a decrease in sensitivity.

[0135] Figure 8 Part (b) is an example in which a transfer gate electrode 13 is disposed between the first electrode 11 and the charge accumulation electrode 12. In this case, a potential barrier is generated between the first electrode 11 and the charge accumulation electrode 12 by applying a voltage to the transfer gate electrode 13. In the configuration of this part (b), since a potential barrier is formed by applying a voltage to the transfer gate electrode 13, a higher potential barrier can be generated, and the amount of accumulated charge Qs accumulated by the charge accumulation electrode 12 can be easily increased. On the other hand, by providing the transfer gate electrode 13, the area of ​​the charge accumulation electrode 12 is reduced, thereby resulting in a decrease in sensitivity.

[0136] [2. First Embodiment]

[0137] (2-0-1. Overview of the imaging element according to the first embodiment)

[0138] Next, the first embodiment will be described. First, the imaging element according to the first embodiment will be described schematically. Figure 9 This is a schematic diagram illustrating the electrode structure and operation in pixel 101 according to the first embodiment. Figure 9 In the diagram, part (a) is a schematic diagram showing the pixel according to the first embodiment as viewed from above the upper surface (light-receiving surface), and part (b) is a schematic diagram showing a cross-section of the pixel. Furthermore, part (c) is a diagram schematically showing the state of the potential Pot corresponding to parts (a) and (b).

[0139] like Figure 9 As shown in part (b), in pixel 101 according to the first embodiment, first electrode 11 and charge accumulation electrode 12 are spaced apart from each other by a gap 14, and a barrier forming electrode 200, serving as a third electrode, is arranged on the lower surface side (the surface opposite to the light receiving surface) of first electrode 11 and charge accumulation electrode 12. In other words, barrier forming electrode 200 is arranged between first electrode 11 and charge accumulation electrode 12 and semiconductor substrate 70. In this case, barrier forming electrode 200 is arranged not to be electrically connected to first electrode 11 and charge accumulation electrode 12. In addition, barrier forming electrode 200 is arranged at a position where the gap 14 between first electrode 11 and charge accumulation electrode 12 in the vertical direction overlaps with the first surface of photoelectric conversion layer 15.

[0140] exist Figure 9In the example shown in section (b), the width of the barrier forming electrode 200 is greater than the width 14a of the gap 14, and the barrier forming electrode 200 is arranged to have an overlapping portion over the entire width of the gap 14. The barrier forming electrode 200 is not limited to this example and may also be arranged to have an overlapping portion with a portion of the gap 14. Alternatively, the width of the barrier forming electrode 200 may be less than the width 14a of the gap 14, such that the overlapping portion is arranged within the gap 14. In this case, the barrier forming electrode 200 does not have any portion overlapping with the first electrode 11 and the charge accumulation electrode 12.

[0141] In pixel 101 with this configuration, a bias voltage is applied to the barrier forming electrode 200 to raise the barrier in gap 14. Figure 9 As schematically shown in part (c), a predetermined bias voltage is applied to the barrier forming electrode 200, causing the potential Pot in the gap 14 portion to become a higher potential Pot(b) than the potential Pot(a) of the gap 14 portion when no bias voltage is applied to the barrier forming electrode 200, and a barrier is generated according to the potential Pot(b). In this case, the bias voltage applied to the barrier forming electrode 200 is a negative bias voltage lower than the voltage applied to the first electrode 11 and the charge accumulation electrode 12.

[0142] In the first embodiment, as described above, the barrier forming electrode 200 is arranged to have a portion that overlaps with the gap 14 in the downward direction between the first electrode 11 and the charge accumulation electrode 12. Then, by applying a negative bias voltage to the barrier forming electrode 200, a higher barrier can be generated at the location corresponding to the gap 14. The gap 14 has a width 14a such that at least the first electrode 11 and the charge accumulation electrode 12 do not contact each other.

[0143] In a photoelectric conversion unit that includes a layer (organic film) containing organic photoelectric conversion material, the pixel 101 with this structure in the first embodiment is able to ensure the accumulated charge Qs while maintaining a wide sensitive area.

[0144] (2-0-2. A more specific example of the construction of the imaging element according to the first embodiment)

[0145] Next, a more specific construction example of the imaging element according to the first embodiment will be described. Figure 10 This is a schematic partial cross-sectional view of pixel 101 according to the first embodiment.

[0146] Figure 10 It corresponds to the above. Figure 3 The image, and will Figure 3 The HfO2 film 74 and the insulating film 75 are collectively shown as insulating film 700. Furthermore, in Figure 10In this text, the individual transistors and the like arranged on the first surface 70A of the semiconductor substrate 70 are omitted. Furthermore, in... Figure 10 In the photoelectric conversion layer 15, on the surface opposite to the surface where the second electrode 16 is arranged, an accumulation transport layer 800 is arranged, which is made of a material suitable for charge accumulation.

[0147] exist Figure 10 In the example, the barrier forming electrode 200 has a portion that overlaps with the gap 14 between the first electrode 11 and the charge accumulation electrode 12 in the direction toward the semiconductor substrate 70, and the barrier forming electrode 200 is disposed in the same layer as the pads 63 and 64. The barrier forming electrode 200 has a width such that the portion overlapping with the gap 14 is within the gap 14. That is, in Figure 10 In the example, the barrier forming electrode 200 is formed and arranged so that it does not have any portion overlapping with the first electrode 11 and the charge accumulation electrode 12 in the direction toward the semiconductor substrate 70. For example, similar to the pad 64, the barrier forming electrode 200 is connected to wiring in the interlayer insulating layer 81, and a fixed bias voltage is applied to the barrier forming electrode 200 via the wiring.

[0148] As described above, the arrangement of the barrier forming electrode 200 is not limited to an arrangement in which the barrier forming electrode 200 is completely included in the gap 14 or an arrangement in which the barrier forming electrode 200 completely includes the gap 14. That is, the barrier forming electrode 200 only needs to have a portion that overlaps with the gap 14 in the direction toward the semiconductor substrate 70, for example, as shown in the figure. Figure 11 Another arrangement example shows that the barrier forming electrode 200 can be arranged to extend partially from the gap 14.

[0149] Note that, in the following text, to avoid complications, the portion that overlaps with the gap 14 (or the first electrode 11 and the charge accumulation electrode 12) in the direction toward the semiconductor substrate 70 will be described as the portion that overlaps with the gap 14 (or the first electrode 11 and the charge accumulation electrode 12), etc.

[0150] (2-0-3. Example of electrode construction according to the first embodiment)

[0151] Next, we will refer to Figures 12A to 16B Some arrangement examples of the first electrode 11, charge accumulation electrode 12 and barrier forming electrode 200 applicable to the first embodiment are described.

[0152] and Figure 9 Similar examples are shown, such as pattern 300a on the far left. Figure 12AThe pixel 101a shown is an example of a pixel 101a in which a first electrode 11 is arranged along one side of the pixel 101a having a rectangular shape, and a charge accumulation electrode 12 is arranged such that a gap 14 exists between it and the first electrode 11. In this case, the gap 14 is formed between the side of the first electrode 11 opposite to the side that contacts one side of the pixel 101a and the side of the charge accumulation electrode 12 closest to that side.

[0153] In the following text, the pattern in which the first electrode 11 is arranged along one side of pixel 101a, similar to pattern 300a, will be referred to as a straight line pattern.

[0154] Figure 12A Pattern 300b is an example in which the barrier forming electrode 200 is arranged to have portions 210 that overlap with the first electrode 11 and the charge accumulation electrode 12, respectively, relative to the arrangement of pattern 300a. In pattern 300b, the barrier forming electrode 200 has overlapping portions over the entire width of the gap 14.

[0155] Figure 12A Pattern 300c is an example in which the barrier forming electrode 200 is arranged to have a portion 210 overlapping with the charge accumulation electrode 12, relative to the arrangement of pattern 300a. In pattern 300c, the barrier forming electrode 200 has a portion overlapping with the gap 14 on the side of the charge accumulation electrode 12, but not a portion overlapping with the gap 14 on the side of the first electrode 11. Figure 12A Pattern 300d is an example in which the barrier forming electrode 200 is arranged to have a portion 210 overlapping with the first electrode 11, relative to the arrangement of pattern 300a. In pattern 300d, the barrier forming electrode 200 has a portion overlapping with the gap 14 on the side of the first electrode 11, but not a portion overlapping with the gap 14 on the side of the charge accumulation electrode 12.

[0156] Figure 12A Pattern 300e is an example in which the barrier forming electrode 200 is arranged so as not to have a portion overlapping with the first electrode 11 and the charge accumulation electrode 12, relative to the arrangement of pattern 300a. In pattern 300e, the barrier forming electrode 200 has a portion overlapping with the gap 14 within the gap 14.

[0157] like Figure 12B As shown in the leftmost pattern 301a, Figure 12B An example of pixel 101b is shown, where, relative to the above... Figure 12APattern 300a has a pixel separation electrode 220. The pixel separation electrode 220 is arranged on the outer edge of pixel 101b and electrically separates pixel 101b from adjacent pixels 101b by applying a predetermined voltage (e.g., negative bias voltage). In the linear pattern, the pixel separation electrode 220 is not arranged on the side where the first electrode 11 is arranged.

[0158] Figure 12B Patterns 301b, 301c, 301d, and 301e in the reference numerals correspond to the reference numerals 301b, 301c, 301d, and 301e, respectively. Figure 12A Patterns 300b, 300c, 300d, and 300e are described below. Specifically, pattern 301b is an example where, relative to the arrangement of pattern 301a, the barrier forming electrode 200 is arranged to have portions 210 overlapping with the first electrode 11 and the charge accumulation electrode 12, respectively. Pattern 301c is an example where, relative to the arrangement of pattern 301a, the barrier forming electrode 200 is arranged to have a portion 210 overlapping with the charge accumulation electrode 12. Pattern 301d is an example where, relative to the arrangement of pattern 301a, the barrier forming electrode 200 is arranged to have a portion 210 overlapping with the first electrode 11. Pattern 301e is an example where, relative to the arrangement of pattern 301a, the barrier forming electrode 200 is arranged without portions overlapping with the first electrode 11 and the charge accumulation electrode 12.

[0159] like Figure 13A As shown in the leftmost pattern 302a, Figure 13A Here is an example of pixel 101c, in which a first electrode 11 is arranged at one corner of pixel 101c, which has a rectangular shape, and a charge accumulation electrode 12 is arranged with a gap 14 between it and the first electrode 11. In this case, the gap 14 is formed between the corner of the first electrode 11 opposite the corner that contacts the corner of pixel 101c and the corner of the charge accumulation electrode 12 closest to that corner. That is, in this case, the gap 14 is formed in an inclined direction relative to the rectangular shape of pixel 101c.

[0160] In the following text, the pattern in which the first electrode 11 is arranged at the corner of pixel 101c, similar to pattern 302a, will be referred to as the corner arrangement pattern.

[0161] Figure 13A Pattern 302b is an example in which the barrier forming electrode 200 is arranged to have portions 210 that overlap with the first electrode 11 and the charge accumulation electrode 12, respectively, relative to the arrangement of pattern 302a. In pattern 302b, the barrier forming electrode 200 has overlapping portions over the entire width of the gap 14.

[0162] Figure 13APattern 302c is an example in which the barrier forming electrode 200 is arranged to have a portion 210 overlapping with the charge accumulation electrode 12, relative to the arrangement of pattern 302a. In pattern 302c, the barrier forming electrode 200 has a portion overlapping with the gap 14 on the side of the charge accumulation electrode 12, but not a portion overlapping with the gap 14 on the side of the first electrode 11. Figure 13A Pattern 302d is an example in which the barrier forming electrode 200 is arranged to have a portion 210 overlapping with the first electrode 11, relative to the arrangement of pattern 302a. In pattern 302d, the barrier forming electrode 200 has a portion overlapping with the gap 14 on the side of the first electrode 11, but not a portion overlapping with the gap 14 on the side of the charge accumulation electrode 12.

[0163] Figure 13A Pattern 302e is an example in which the barrier forming electrode 200 is arranged so as not to have a portion overlapping with the first electrode 11 and the charge accumulation electrode 12, relative to the arrangement of pattern 302a. In pattern 302e, the barrier forming electrode 200 has a portion overlapping with the gap 14 within the gap 14.

[0164] like Figure 13B As shown in the leftmost pattern 303a, Figure 13B An example of pixel 101d is shown, where, relative to the above... Figure 13A The pattern 302a has pixel separation electrodes 220 arranged thereon. In the corner arrangement pattern, pixel separation electrodes 220 are not arranged around the corner where the first electrode 11 is arranged.

[0165] Figure 13B Patterns 303b, 303c, 303d, and 303e in the reference numerals correspond to the reference numerals 303b, 303c, 303d, and 303e, respectively. Figure 13A Patterns 302b, 302c, 302d, and 302e are described above. Specifically, pattern 303b is an example of pixel 101d, wherein, relative to the arrangement of pattern 303a, the barrier forming electrode 200 is arranged to have portions 210 overlapping with the first electrode 11 and the charge accumulation electrode 12, respectively. Pattern 303c is an example where, relative to the arrangement of pattern 303a, the barrier forming electrode 200 is arranged to have a portion 210 overlapping with the charge accumulation electrode 12. Pattern 303d is an example where, relative to the arrangement of pattern 303a, the barrier forming electrode 200 is arranged to have a portion 210 overlapping with the first electrode 11. Pattern 303e is an example where, relative to the arrangement of pattern 303a, the barrier forming electrode 200 is arranged without portions overlapping with the first electrode 11 and the charge accumulation electrode 12.

[0166] Figure 14AThis diagram illustrates an example arrangement of the barrier forming electrode 200 when a first electrode 11 is shared by multiple pixels 101 in a linear pattern. Note that in Figure 14A And what will be said later Figure 14B , Figure 15A , Figure 15B , Figure 16A and Figure 16B In the diagram, the horizontal direction is the row direction in pixel array unit 111, and the vertical direction is the column direction in pixel array unit 111.

[0167] like Figure 14A As shown in the upper left pattern 304a, a first electrode 11a consists of four pixels 101e that are in contact with each other at a point. 11 101e 12 101e 13 and 101e 14 Shared. Similarly, a first electrode 11b consists of four pixels 101e that are in contact with each other at a single point. 21 101e 22 101e 23 and 101e 24 Sharing. That is, in pattern 304a, four pixels 101 that are in contact with each other at a point are treated as shared units and share a first electrode 11. As described above, in the case where multiple pixels 101 share a first electrode 11, for example, for each pixel 101, charge is read from the charge accumulation electrode 12 of each pixel 101 at different times.

[0168] In pattern 304a, in this case, all pixels 101e are arranged in a row of pixel array unit 111. 11 101e 12 101e 21 102e 22 ...Shared barrier forming electrode 200 row(a) Similarly, pixel 101e 13 101e 14 101e 23 102e 24 ...shared barrier forming electrode 200 row(b) .

[0169] Due to the barrier forming electrode 200 according to the first embodiment row(a) and 200 row(b) A fixed voltage is applied to each of the pixels, thus enabling the barrier-forming electrode to be shared among pixels 101. For example, regarding pixel 101e 11 up to 101e 14 Electrode 200 is formed at a fixed potential barrierrow(a) and 200 row(b) While controlling the potential, selectively control pixel 101e 11 101e 12 101e 13 and 101e 14 The target pixel's charge accumulation electrode 12 is used to read the charge from the charge accumulation electrode 12.

[0170] Note the barrier forming electrode 200 in pattern 304a. row(a) and 200 row(b) The electrode is shown as not having a portion overlapping with each of the first electrodes 11 and each of the charge accumulation electrodes 12, but is not limited to this example. That is, the barrier forming electrode 200 row(a) and 200 row(b) It may have a portion that overlaps with both the first electrode 11 and the charge accumulation electrode 12, or it may have a portion that overlaps with only one of the first electrode 11 and the charge accumulation electrode 12.

[0171] exist Figure 14A In pattern 304b, pattern 304b is a straight line pattern shared by four pixels 101 that are in contact with each other at a point on the first electrode 11. All pixels arranged in two adjacent rows of pixel array unit 111, i.e., pixels 101e 11 101e 12 101e 21 102e 22 ... and 101e pixels 13 101e 14 101e 23 102e 24 ...sharing a barrier forming electrode 200 row(2) That is, in pattern 304b, every two rows of pixel array units 111 share a barrier forming electrode 200. row(2) .

[0172] Note the barrier forming electrode 200 in pattern 304b. row(2) The electrode is shown as not having a portion overlapping with each of the first electrodes 11 and each of the charge accumulation electrodes 12, but is not limited to this example. That is, the barrier forming electrode 200 row(2) It may have a portion that overlaps with both the first electrode 11 and the charge accumulation electrode 12, or it may have a portion that overlaps with only one of the first electrode 11 and the charge accumulation electrode 12.

[0173] exist Figure 14AIn pattern 304c, pattern 304c is a straight line pattern in which four pixels 101 that are in contact with each other at a point share a first electrode 11 as a shared unit. Multiple pixels 101 across pixel sharing units share a barrier forming electrode 200. For example, a first shared unit sharing a first electrode 11a includes pixel 101e. 11 up to 101e 14 Similarly, the second shared unit sharing a first electrode 11b includes pixel 101e. 21 up to 101e 24 In this case, pixels 101e that are in contact with each other at a point across the first and second shared units. 12 101e 21 101e 14 and 101e 23 Sharing a barrier forming electrode 200 cen .

[0174] Similarly, although not shown, pixel 101e 11 and 101e 13 Also, the two pixels 101 adjacent to each other on the left side of the shared cell and in contact with each other at one point share a barrier to form an electrode 200. rht Additionally, although not shown, pixel 101e 22 and 101e 24 Also, the two pixels 101 adjacent to each other on the right side of the shared cell and in contact with each other at one point share a barrier to form an electrode 200. lft .

[0175] Note, as an example, the barrier forming electrode 200 in pattern 304c cen The electrode is shown having portions overlapping with the first electrodes 11a and 11b but not portions overlapping with the upper and lower charge accumulation electrodes 12, but is not limited to this example. For example, barrier forming electrode 200 cen It may have portions that overlap with both the first electrodes 11a and 11b and the charge accumulation electrodes 12 on the upper and lower sides.

[0176] exist Figure 14A In pattern 304d, pattern 304d is a straight line pattern in which four pixels 101 that are in contact with each other at a point share the first electrode 11. All pixels arranged in two adjacent columns of pixel array unit 111, i.e., pixels 101e 12 101e 14 101e 21 102e 23 ...sharing a barrier forming electrode 200 col(a)That is, in pattern 304d, every two columns of pixel array units 111 share a barrier forming electrode 200. col(a) .

[0177] In this case, barrier forming electrode 200 col(a) It has a vertical portion arranged in the column direction between adjacent charge accumulation electrodes 12 and a protruding portion arranged in the gap 14 between the first electrode 11 and the charge accumulation electrode 12 in a pixel 101 and extending from the vertical portion. The protruding portion is the portion that helps to generate a potential barrier at the position corresponding to the gap 14 between the first electrode 11 and the charge accumulation electrode 12.

[0178] Similarly, pixels 101e arranged in a column 11 101e 13 ... and arranged in relation to pixel 101e 11 101e 13 Pixel 101 in the left adjacent column of ... shares a barrier to form electrode 200 col(c) Additionally, pixels 101e arranged in a column 22 101e 24 ...and arranged in relation to pixel 101e 22 101e 24 Pixel 101 in the column adjacent to the right of ... shares a barrier to form electrode 200 col(b) .

[0179] Note, for example, the barrier forming electrode 200 in pattern 304d col(a) Each protruding portion is shown as not having a portion overlapping with the respective first electrode 11 and the respective charge accumulation electrode 12, but is not limited to this example. That is, the barrier forming electrode 200 col(a) Each protrusion may have a portion that overlaps with both the respective first electrode 11 and the respective charge accumulation electrode 12, or may have a portion that overlaps with one of the respective first electrode 11 and the respective charge accumulation electrode 12.

[0180] Figure 14B This shows the above. Figure 14A Each of the patterns 304a to 304d is in pixel 101f 11 Up to 101f 14 and 101f pixels 21 Up to 101f 24 The diagram shows an example of a pixel separation electrode 220 arranged in the middle. That is, in Figure 14BIn the diagram, pattern 305a is an example of a pixel separation electrode 220 arranged in pattern 304a, pattern 305b is an example of a pixel separation electrode 220 arranged in pattern 304b, pattern 305c is an example of a pixel separation electrode 220 arranged in pattern 304c, and pattern 305d is an example of a pixel separation electrode 220 arranged in pattern 304d. The arrangement of the barrier forming electrode 200 in each of patterns 305a to 305d is similar to the example in each of patterns 304a to 304d described above, therefore its description is omitted here.

[0181] Note that in Figure 14B In the patterns 305a to 305d shown, the barrier forming electrode 200 row(a) 200 row(b) 200 row(2) 200 cen 200 rht 200 lft 200 col(a) 200 col(b) and 200 col(c) Each of them has a portion that overlaps with the pixel separation electrode 220. Since the pixel separation electrode 220 does not contribute to creating a potential barrier between the first electrode 11 and the charge accumulation electrode 12, this overlapping portion can be ignored.

[0182] Figure 15A This diagram illustrates an example arrangement of the barrier forming electrode 200 when a first electrode 11 is shared by multiple pixels 101 in a corner arrangement pattern. Figure 15A In the middle, pattern 306a is a four-pixel 101g corner arrangement pattern. 11 101g 12 101g 13 and 101g 14 An example of sharing a first electrode 11. In pattern 306a, four pixels 101g are in contact with each other at a single point. 11 Up to 101g 14 The unit that constitutes the shared first electrode 11, and the first electrode 11 is arranged to include four pixels 101g. 11 Up to 101g 14 The points where they come into contact.

[0183] exist Figure 15A In the example, in pattern 306a, which is a corner arrangement pattern, the barrier forming electrode 200 is formed by arranging the first electrode 11 and the pixel 101g respectively. 11 Up to 101g 14 The potential barrier forming electrodes in the gap 14 between the charge accumulation electrodes 12 of each electrode are connected to each other and have a rhomboid shape.

[0184] Note that the barrier forming electrode 200 in pattern 306a is shown without overlapping portions with the respective first electrodes 11 and the respective charge accumulation electrodes 12, but is not limited to this example. That is, the barrier forming electrode 200 may have portions overlapping with both the respective first electrodes 11 and the respective charge accumulation electrodes 12, or may have portions overlapping with only one of the respective first electrodes 11 and the respective charge accumulation electrodes 12.

[0185] exist Figure 15A In pattern 306b, pattern 306b is a corner arrangement pattern in which four pixels 101 that are in contact with each other at one point share the first electrode 11. All pixels arranged in two adjacent rows of pixel array unit 111, i.e., pixels 101g 11 101g 12 101g 21 101g 22 ...and 101g pixels 13 101g 14 101g 23 101g 24 ...sharing a barrier forming electrode 200 row That is, in pattern 306b, every two rows of pixel array units 111 share a barrier forming electrode 200. row .

[0186] Here, in pattern 306b, multiple barrier forming electrodes 200 arranged in a row constitute pixels 101g of a unit sharing the first electrode 11. 11 Up to 101g 14 Shared barrier forming electrode 200, and pixel 101g 21 Up to 101g 24 Shared barrier forming electrodes 200, ... are interconnected by wiring, etc., to form a row of barrier forming electrodes 200. row The barrier forming electrodes 200 arranged in a row are not limited to this, and can be connected to each other by extending the individual barrier forming electrodes 200.

[0187] exist Figure 15A In pattern 306c, pattern 306c is a corner arrangement pattern in which four pixels 101 that are in contact with each other at one point share the first electrode 11. All pixels arranged in two adjacent columns of pixel array unit 111, i.e., pixels 101g 11 101g 13 101g 31 101g 33 ...and 101g pixels 12 101g 14 101g32 101g 34 ...sharing a barrier forming electrode 200 col That is, in pattern 306c, every two columns of pixel array units 111 share a barrier forming electrode 200. col .

[0188] Here, in pattern 306c, multiple barrier forming electrodes 200 arranged along the column direction constitute pixels 101g of units sharing the first electrode 11. 11 Up to 101g 14 Shared barrier forming electrode 200, and pixel 101g 31 Up to 101g 34 Shared barrier forming electrodes 200, ... are interconnected by wiring, etc., to form a row of barrier forming electrodes 200. col The barrier forming electrodes 200 arranged in a row are not limited to this, and can be connected to each other by extending the individual barrier forming electrodes 200.

[0189] Note that the barrier forming electrode 200 in each of the above patterns 306a, 306b, and 306c is shown without overlapping portions with the respective first electrode 11 and the respective charge accumulation electrode 12, but this is not a limitation. That is, the barrier forming electrode 200 may have portions overlapping with both the respective first electrode 11 and the respective charge accumulation electrode 12, or it may have portions overlapping with only one of the respective first electrode 11 and the respective charge accumulation electrode 12.

[0190] Figure 15B This shows the above. Figure 15A Each of the patterns 306a to 306c is in pixel 101h 11 Up to 101h 14 and 101h pixels 21 Up to 101h 24 The diagram shows an example of a pixel separation electrode 220 arranged in the middle. That is, in Figure 15B In the diagram, pattern 307a is an example of arranging the pixel separation electrode 220 in pattern 306a, pattern 307b is an example of arranging the pixel separation electrode 220 in pattern 306b, and pattern 307c is an example of arranging the pixel separation electrode 220 in pattern 306c. The arrangement of the barrier forming electrode 200 in each of patterns 307a to 307c is similar to the example in each of patterns 306a to 306c described above, and therefore its description is omitted here.

[0191] exist Figure 15BIn the patterns 307b and 307c shown, the wiring connecting the barrier forming electrodes 200 to each other has a portion that overlaps with the pixel separation electrode 220. Since the pixel separation electrode 220 does not contribute to creating a barrier between the first electrode 11 and the charge accumulation electrode 12, this overlap can be ignored.

[0192] Here, in each of patterns 307a to 307c, the area surrounding the first electrode 11 is a region where the pixel separation electrode 220 is not disposed. That is, in each of patterns 307a to 307c, the pixel 101h arranged sharing the first electrode 11... 11 Up to 101h 14 The pixel separation electrode 220 in the middle has such a shape as that of pixel 101h 11 Up to 101h 14 The central portion between the lattice formed by the outer periphery is cut off.

[0193] (2-0-4. Method for applying voltage to barrier forming electrode according to the first embodiment)

[0194] Next, a method for applying a voltage to the barrier forming electrode 200 according to the first embodiment will be described. For example, in reference... Figure 12A and Figure 12B In each of the patterns 300b to 300e and patterns 301b to 301e (which are linear patterns), reference is made to, for example, reference to Figure 14A The patterns 304a, 304b and 304d and the reference Figure 14B The patterns 305a, 305b, and 305d, etc., allow voltage to be applied to the barrier forming electrode 200 from the outer periphery of the pixel array unit 111 by having pixels 101 in each row or column of the pixel array unit 111 share the barrier forming electrode 200 or by connecting the barrier forming electrodes 200 to each other. This also applies to the reference... Figure 14A The patterns 304a, 304b and 304d and the reference Figure 14B The patterns 305a, 305b and 305d are described.

[0195] Furthermore, in each of patterns 300b to 300e and patterns 301b to 301e, a through electrode is provided that penetrates the semiconductor substrate 70 and is connected to the wiring layer 62, enabling the application of a voltage to the barrier forming electrode 200. This also applies to the reference electrode. Figure 13A and Figure 13B The patterns 302b to 302e and 303b to 303e are angular arrangement patterns.

[0196] Here, we will explain the voltage application method when multiple pixels share a barrier to form an electrode in a corner arrangement pattern. For example, as Figure 15B As in pattern 307a, in a corner arrangement pattern, in four pixels 101h 11 Up to 101h 14 In the arrangement of the shared first electrode 11, it may be difficult to directly set a through electrode relative to the barrier forming electrode 200. (Refer to...) Figures 16A to 16C An example illustrating the method of applying voltage to the barrier forming electrode 200 under such circumstances.

[0197] Figure 16A This is a schematic diagram illustrating a first example of a method for applying a voltage to a barrier forming electrode 200 suitable for a first embodiment. In the first example of the voltage application method, the barrier forming electrode 200 and the pixel separation electrode 220 are connected to each other, and a voltage is applied from the pixel separation electrode 220 to the barrier forming electrode 200.

[0198] According to Figure 16A The left side shown Figure 15B In the arrangement of pattern 307a, the barrier forming electrode 200 is arranged below the pixel separation electrode 220. Therefore, as Figure 16A As shown on the right, the pixel separation electrode 220 and the barrier forming electrode 200 are connected to each other via a vertical via 221. Figure 16A In the example, the end of the pixel separation electrode 220 cut out according to the arrangement of the first electrode 11 and the end of the barrier forming electrode 200, which is obliquely arranged between the first electrode 11 and the charge accumulation electrode 12, are connected to each other via a vertical via 221. A predetermined negative bias voltage is applied to the pixel separation electrode 220 to electrically isolate it from adjacent pixels. Therefore, a negative bias voltage can be applied to the barrier forming electrode 200 connected to the pixel separation electrode 220 via the vertical via 221.

[0199] Figure 16B This is a schematic diagram illustrating a second example of a method for applying a voltage to the barrier forming electrode 200 applicable to the first embodiment. In this second example of the voltage application method, a wiring 230 is provided above the semiconductor substrate 70, and a voltage is applied to the barrier forming electrode 200 via the wiring 230. This second example can be applied to, for example, the methods described above. Figure 15B Patterns 307b and 307c.

[0200] Figure 16CThis is a schematic diagram illustrating a third example of a method for applying a voltage to a barrier forming electrode 200 suitable for the first embodiment. In this third example of the voltage application method, a voltage is applied from the wiring layer 62 to the barrier forming electrode 200 via a through electrode 240 connected to the wiring layer 62. In this case, the through electrode 240 is provided, for example, for pixels 101h sharing the first electrode 11. 11 Up to 101h 14 The operation of each component has minimal impact at the location, and the barrier forming electrode 200 and the through electrode 240 are connected to each other via wiring 231. Figure 16C In the example, the through electrode 240 is set in pixel 101h 11 Up to 101h 14 At a predetermined position outside the charge accumulation electrode 12 of each of them.

[0201] Among the first to third examples of the voltage application method described above, the first example is more advantageous than the second and third examples because the barrier forming electrode 200 does not occupy the plane in which the first electrode 11, the charge accumulation electrode 12 and the pixel separation electrode 220 are arranged, and has little impact on other electrodes.

[0202] Furthermore, a voltage application method will be described in the case where multiple pixels across a unit sharing a first electrode in a linear pattern share a barrier to form an electrode. In the above... Figure 14B In pattern 305c, for example, the first shared unit (pixel 101f) across the shared first electrode 11a 11 Up to 101f 14 ) and the second shared unit (pixel 101f) sharing the first electrode 11b. 21 Up to 101f 24 Shared barrier forming electrode 200 cen In this case, for example, with Figure 14B As in patterns 305a, 305b, and 305d, it is difficult to move from the outer periphery of pixel array unit 111 towards the barrier forming electrode 200. cen Apply voltage.

[0203] Figure 17 This illustrates a barrier forming electrode 200 suitable for the first embodiment. cen A schematic diagram of a fourth example of a method for applying voltage. Figure 17 In the pattern 305c' shown, relative to Figure 14B Pattern 305c is provided with a vertical through-hole 232, which is used to pass the barrier forming electrode 200. cen And the pixel separation electrode 220 are connected to each other. For example, Figure 17The schematically shown vertical through-hole 232 is actually configured to arrange the pixel separation electrode 220 in pixel 101f 12 and 101f 14 With pixel 101f 21 and 101f 23 The portion between them forms an electrode 200 with the potential barrier. cen Connection. By configuring the vertical via 232 in this manner, the voltage applied to the pixel separation electrode 220 can be applied to the barrier forming electrode 200. cen .

[0204] (2-1. First variation of the first embodiment)

[0205] Next, a first variation of the first embodiment will be described. In the first embodiment described above, pixel 101 has a structure in which a first photoelectric conversion unit serving as a green photoelectric conversion unit, a second photoelectric conversion unit serving as a blue photoelectric conversion unit, and a third photoelectric conversion unit serving as a red photoelectric conversion unit are stacked. The technology according to this disclosure is not limited to this example, and can also be applied to pixels 101 having other structures, as long as pixel 101 includes a first electrode 11 and a charge accumulation electrode 12 and a potential barrier is generated in the gap 14 between the first electrode 11 and the charge accumulation electrode 12 to accumulate charge.

[0206] Reference 18A to 18C A pixel 101 is illustrated schematically, which is capable of having other constructions that can be applied according to the technology of this disclosure.

[0207] Figure 18A This is a schematic diagram illustrating a first example of a pixel structure according to a first variation of the first embodiment. The first example is one in which the first photoelectric conversion unit corresponds to a panchromatic photoelectric conversion unit. That is, in Figure 18A In the example, the first photoelectric conversion unit includes a photoelectric conversion layer 15pan using an organic photoelectric conversion material sensitive to light with wavelengths in the visible light region. Furthermore, the semiconductor substrate 70 does not have the photoelectric conversion layer 400 constituting the second photoelectric conversion unit and the photoelectric conversion layer 401 constituting the third photoelectric conversion unit. For example, by providing color filters such as red, green, and blue on the light-receiving surface, pixel signals corresponding to the colors of the color filters can be output. Color filters may not be provided, and in this case, monochrome (grayscale) pixel signals can be output.

[0208] Also in Figure 18A In the construction, by arranging the barrier forming electrode 200 to have a portion overlapping with the gap 14 between the first electrode 11 and the charge accumulation electrode 12, the accumulated charge Qs can be ensured while maintaining a wide sensitive area.

[0209] Figure 18B This is a schematic diagram illustrating a second example of the pixel structure according to a first variation of the first embodiment. The second example is one in which the first photoelectric conversion unit remains a green photoelectric conversion unit and the second photoelectric conversion unit is a red photoelectric conversion unit. In this case, a color filter CF(RED) that allows light in the red wavelength region to pass through is arranged above the semiconductor substrate 70. As a result, both green pixel signals and red pixel signals can be output. Furthermore, Figure 18C This is a schematic diagram illustrating a third example of a pixel structure according to a first variation of the first embodiment. The third example is in which the first photoelectric conversion unit and... Figure 18B Similarly, the example maintains a green photoelectric conversion unit and a blue photoelectric conversion unit. In this case, a color filter CF (BLUE) that allows light in the blue wavelength region to pass through is arranged above the semiconductor substrate 70. As a result, both green pixel signals and blue pixel signals can be output.

[0210] In pixel array unit 111, for example by having Figure 18B The pixel 101 shown has the following structure and has Figure 18C The pixel 101 in the structure shown is arranged in a grid pattern, which enables panchromatic imaging.

[0211] Also in Figure 18B and Figure 18C In the construction, by arranging the barrier forming electrode 200 to have a portion overlapping with the gap 14 between the first electrode 11 and the charge accumulation electrode 12, the accumulated charge Qs can be ensured while maintaining a wide sensitive area.

[0212] (2-2. Second variation of the first embodiment)

[0213] Next, a second variation of the first embodiment will be described. In the first embodiment and the first variation thereof, the barrier forming electrode 200 is disposed below the layer on which the first electrode 11 and the charge accumulation electrode 12 are disposed. In contrast, in the second variation of the first embodiment, as... Figure 19 As shown, the barrier forming electrode 200 is arranged in the same layer as the first electrode 11 and the charge accumulation electrode 12, that is, in the gap 14 between the first electrode 11 and the charge accumulation electrode 12. Similarly, in Figure 19 In this arrangement, by applying a negative bias voltage to the barrier forming electrode 200, a higher potential barrier can be generated between the first electrode 11 and the charge accumulation electrode 12. On the other hand, in Figure 19 In the construction, since the barrier forming electrode 200 is arranged in the same layer as the first electrode 11 and the charge accumulation electrode 12, the sensitive region is reduced by the same amount as the width of the barrier forming electrode 200.

[0214] [3. Second Embodiment]

[0215] Next, a second embodiment of this disclosure will be described. In the first embodiment and its variations described above, a fixed voltage is applied to the barrier forming electrode 200. In contrast, in the second embodiment, the barrier forming electrode 200 is driven to change the voltage applied to the barrier forming electrode 200.

[0216] Figure 20A This is a schematic diagram illustrating the state of the potential barrier in the charge accumulation state of the charge accumulation electrode 12 according to the second embodiment. Additionally, Figure 20B This is a schematic diagram showing the state of the potential barrier in the transfer state of the charge accumulated in the charge accumulation electrode 12 according to the second embodiment being transferred to the first electrode 11.

[0217] exist Figure 20A In this context, potential Pot(a) is, for example, the potential in a state where no voltage is applied to the barrier forming electrode 200. For example, potential Pot(a) is generated based on the voltage applied to the second electrode 16. In the accumulation state, a negative bias voltage is applied to the barrier forming electrode 200 as an accumulation voltage. As a result, the potential at the position corresponding to the gap 14 rises from potential Pot(a) to potential Pot(b), and the barrier becomes higher.

[0218] In the transfer state where the charge accumulated in the charge accumulation electrode 12 is transferred to the first electrode 11, such as Figure 20B As shown, a positive bias voltage is applied to the barrier forming electrode 200 as the transmission voltage. That is, during transmission, a higher voltage is applied to the barrier forming electrode 200 than during accumulation. As a result, the potential at the position corresponding to the gap 14 drops to a potential Pot(c) that is lower than the potential Pot(b), and the barrier becomes lower. At this time, the voltage applied to the barrier forming electrode 200 is preferably a voltage that can make the potential Pot(c) lower than the potential Pot(a).

[0219] During transmission, when a transmission voltage is applied to the barrier forming electrode 200, a voltage lower than the voltage at accumulation is applied to the charge accumulation electrode 12. More specifically, a voltage that causes the potential corresponding to the charge accumulation electrode 12 to be higher than the potential Pot(c) is applied to the charge accumulation electrode 12. As a result, the potential corresponding to the charge accumulation electrode 12 becomes higher than the potential Pot(c) at the position corresponding to the gap 14, and the charge accumulated in the charge accumulation electrode 12 flows across the barrier into the first electrode 11. At this time, since the voltage applied to the barrier forming electrode 200 is controlled to lower the barrier, the voltage applied to the charge accumulation electrode 12 for transmission can be reduced.

[0220] Note that the second embodiment is not preferably applied to electrode arrangements in which multiple pixels 101 share a barrier forming electrode 200. As an example, the second embodiment can be considered for application to… Figure 15B The case shown is that of pattern 307a. In this case, due to pixel 101h... 11 Up to 101h 14 A shared barrier forming electrode 200 is used, therefore, when a transmission voltage is applied to the barrier forming electrode 200, at pixel 101h... 11 Up to 101h 14 In each of the pixels 101h, the potential barrier is lowered at the location corresponding to the gap 14 between the charge accumulation electrode 12 and the first electrode 11. Therefore, in the plurality of pixels 101h sharing the potential barrier forming electrode 200... 11 Up to 101h 14 In addition to the pixel from which the charge is expected to be read (let's assume it's pixel 101h) 11 Pixels other than 101h 12 Up to 101h 14 In the process, charge is also transferred from their charge accumulation electrodes 12 to the first electrode 11.

[0221] [4. Third Embodiment]

[0222] Next, a third embodiment of this disclosure will be described. In the first embodiment and its variations, as well as the second embodiment, it has been shown that the barrier forming electrode 200 is not connected to the first electrode 11 and the charge accumulation electrode 12. In contrast, in the third embodiment, the barrier forming electrode 200 is connected to the first electrode 11.

[0223] Figure 21 This is a diagram illustrating an example arrangement of the barrier forming electrode 200 suitable for the third embodiment. Figure 21 As shown, in the third embodiment, the barrier forming electrode 11ex is connected to the connection portion for connecting the first electrode 11 to the wiring layer 22. More specifically, the pad 63 constituting the connection portion for connecting the first electrode 11 to the wiring layer 22 extends to the location of the gap 14, such that the pad 63 serves as the barrier forming electrode 11ex. The barrier forming electrode 11ex only needs to have a portion overlapping the gap 14, but preferably does not reach the location of the charge accumulation electrode 12.

[0224] Figure 22 This is a schematic diagram illustrating the state of the potential barrier in the charge accumulation state of the charge accumulation electrode 12 according to the second embodiment. In the accumulation state, for example, a voltage of 2.7 [V] is applied to the charge accumulation electrode 12, and a voltage of 0 [V] is applied to the first electrode 11. At this time, the voltage applied to the second electrode 16 can make the potential at the position corresponding to the gap 14 higher than the potential of the first electrode 11.

[0225] As a result, compared to the case where no barrier forming electrode 11ex is provided, a higher potential barrier is generated at the position corresponding to the gap 14 between the first electrode 11 and the charge accumulation electrode 12. Therefore, compared to the case where no barrier forming electrode 11ex is provided, the amount of accumulated charge Qs accumulated by the charge accumulation electrode 12 increases.

[0226] When transferring the charge accumulated in the charge accumulation electrode 12 to the first electrode 11, a voltage of 2.7V is applied to the first electrode 11, and a voltage of 0V is applied to the charge accumulation electrode 12. As a result, the potential of the charge accumulation electrode 12 increases, and the potential of the first electrode 11 decreases. Furthermore, depending on the voltage applied to the second electrode 16, the potential of the barrier forming electrode 11ex becomes, for example, an intermediate potential between the potential of the charge accumulation electrode 12 and the potential of the first electrode 11. Therefore, the charge accumulated in the charge accumulation electrode 12 flows across the barrier into the first electrode 11.

[0227] According to the third embodiment, since the barrier forming electrode 11ex is formed by extending the existing pad 63, the accumulated charge Qs can be ensured while maintaining a wide sensitive area, without adding new construction.

[0228] Note that, for the same reasons as in the second embodiment, the third embodiment is not preferably applied to an electrode arrangement in which multiple pixels 101 share a barrier forming electrode 200.

[0229] [5. Fourth Embodiment]

[0230] (5-1. Examples of application of the technology according to this disclosure)

[0231] Next, as a fourth embodiment, examples of the application of the imaging element according to the first embodiment and its variations, as well as the second and third embodiments, will be described. Figure 23 This is a diagram illustrating examples of using imaging elements according to the first embodiment described above, its variations, and the second and third embodiments.

[0232] For example, the imaging element according to the first embodiment and its variations, as well as the second and third embodiments described above, can be used to sense various types of light, such as visible light, infrared light, ultraviolet light, and X-rays, as described below.

[0233] A device for taking pictures for viewing, such as a digital camera or a portable device with camera functionality.

[0234] Equipment used in transportation, such as onboard sensors used to image the front, rear, surroundings, and interior of a car for safe driving or to identify driver status, for example, for automatic parking or to monitor vehicles and roads; or range sensors used to measure distances between vehicles.

[0235] Devices used in household appliances such as televisions, refrigerators, or air conditioners are used to image user gestures and operate the device based on those gestures.

[0236] Devices used for medical or healthcare purposes, such as endoscopes or devices that perform angiography by receiving infrared light.

[0237] Security equipment, such as surveillance cameras used for crime prevention or cameras used for personal authentication.

[0238] Devices used for beauty purposes, such as skin measurement instruments for imaging the skin or microscopes for imaging the scalp.

[0239] Devices used for sports, such as action cameras or wearable cameras for sports activities.

[0240] Equipment used in agriculture, such as cameras used to monitor the condition of fields or crops.

[0241] (5-2. Examples of the application of endoscopic surgical systems)

[0242] The technology disclosed herein (the technology) can be applied to a variety of products. For example, the technology disclosed herein can be applied to endoscopic surgical systems.

[0243] Figure 24 This is a diagram illustrating a schematic example of the construction of an endoscopic surgical system capable of applying the technology (the present technology) according to this disclosure.

[0244] exist Figure 24 The image shows a surgeon (physician) 11131 performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgical system 11000. As shown, the endoscopic surgical system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy therapy device 11112, a support arm assembly 11120 supporting the endoscope 11100, and a trolley 11200 on which various devices for endoscopic surgery are mounted.

[0245] Endoscope 11100 includes a lens barrel 11101 and a camera head 11102, the portion of the lens barrel extending a predetermined length from its front end being inserted into the body cavity of a patient 11132, and the camera head being connected to the rear end of the lens barrel 11101. In the illustrated example, an endoscope 11100 is shown constructed as a so-called rigid endoscope including a rigid lens barrel 11101; however, endoscope 11100 can also be constructed as a so-called flexible endoscope including a flexible lens barrel.

[0246] An opening for mounting an objective lens is provided at the front end of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the front end of the lens barrel through a light guide extending into the lens barrel 11101, and then illuminated by the objective lens onto the object being observed within the body cavity of the patient 11132. Note that the endoscope 11100 can be a forward-looking endoscope, an oblique-looking endoscope, or a lateral-looking endoscope.

[0247] An optical system and imaging element are housed inside the camera head 11102, and reflected light from the observed object (observation light) is converged onto the imaging element by the optical system. The imaging element performs photoelectric conversion on the observation light and generates an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is transmitted as raw (RAW) data to the camera control unit (CCU) 11201.

[0248] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, for example, the CCU 11201 receives image signals from the camera head 11102 and performs various image processing operations on the image signals, such as developing processing (de-mosaic processing), to display an image based on the image signals.

[0249] The display device 11202 displays an image based on the image signal processed by the CCU 11201 under the control of the CCU 11201.

[0250] For example, the light source device 11203 includes a light source such as a light-emitting diode (LED) and provides illumination light to the endoscope 11100 when imaging the surgical site, etc.

[0251] Input device 11204 is the input interface of endoscopic surgery system 11000. Users can input various types of information or commands into endoscopic surgery system 11000 via input device 11204. For example, users can input commands to change the imaging conditions of endoscope 11100 (type of illumination light, magnification, focal length, etc.).

[0252] The treatment tool control device 11205 controls the drive of the energy treatment tool 11112 to burn or cut tissue, close blood vessels, etc. The pneumoperitoneum device 11206 supplies gas into the patient's body cavity 11132 through the pneumoperitoneum tube 11111 to inflate the patient's body cavity, thereby ensuring the field of vision of the endoscope 11100 and ensuring the surgeon's working space. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various forms such as text, images, or graphics.

[0253] Note that the light source device 11203 that provides illumination light to the endoscope 11100 when imaging the surgical site can include, for example, an LED, a laser light source, or a white light source composed of a combination of LEDs and laser light sources. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (wavelength) can be controlled with high precision, thereby adjusting the white balance of the captured image in the light source device 11203. Furthermore, in this case, by illuminating the object of observation with lasers from each RGB laser light source in a time-division manner, and controlling the driving of the imaging element of the camera head 11102 in sync with the illumination timing, images corresponding to RGB can be captured in a time-division manner. According to this method, color images can be obtained even without setting a color filter on the imaging element.

[0254] Furthermore, the drive of the light source device 11203 can be controlled to change the intensity of the light to be output at predetermined intervals. By controlling the drive of the imaging element of the camera head 11102 in sync with the change in light intensity, images are acquired and synthesized in a time-division manner, enabling the production of high dynamic range images without underexposure or overexposure.

[0255] Furthermore, the light source device 11203 can be configured to provide light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, utilizing the fact that the absorption of light by human tissue depends on the wavelength of light, so-called narrowband imaging is performed by irradiating a wavelength band narrower than that of the irradiation light used in ordinary observation (i.e., white light). This means imaging a predetermined tissue, such as blood vessels in the mucosal surface, with high contrast. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image by irradiating fluorescence generated by excitation light. In fluorescence observation, fluorescence from human tissue can be observed by irradiating the tissue with excitation light (autofluorescence observation), or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into the human tissue and irradiating the tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to provide narrowband light and / or excitation light corresponding to this special light observation.

[0256] Figure 25 It shows Figure 24 A block diagram illustrating an example of the functional configuration of the camera head 11102 and CCU 11201.

[0257] Camera head 11102 includes lens unit 11401, imaging unit 11402, drive unit 11403, communication unit 11404, and camera head control unit 11405. CCU 11201 includes communication unit 11411, image processing unit 11412, and control unit 11413. Camera head 11102 and CCU 11201 are communicatively connected to each other via transmission cable 11400.

[0258] Lens unit 11401 is an optical system disposed at the connection portion with lens barrel 11101. Observation light entering from the front end of lens barrel 11101 is guided to camera head 11102 and incident on lens unit 11401. Lens unit 11401 is constructed by combining multiple lenses, including zoom lenses and focusing lenses.

[0259] Imaging unit 11402 includes imaging elements. Imaging unit 11402 may include one imaging element (so-called single-plate type) or multiple imaging elements (so-called multi-plate type). For example, when imaging unit 11402 is configured as multi-plate type, image signals corresponding to R, G, and B respectively can be generated by each imaging element, and the generated image signals can be combined to obtain a color image. Alternatively, imaging unit 11402 may also include a pair of imaging elements for acquiring right-eye and left-eye image signals respectively corresponding to three-dimensional (3D) display. With 3D display, surgeon 11131 can more accurately grasp the depth of living tissue in the surgical site. Note that when imaging unit 11402 is configured as multi-plate type, multiple lens units 11401 can be arranged corresponding to each imaging element.

[0260] Furthermore, the imaging unit 11402 is not necessarily located on the camera head 11102. For example, the imaging unit 11402 may be located directly behind the objective lens inside the lens barrel 11101.

[0261] The drive unit 11403 includes an actuator, and, under the control of the camera head control unit 11405, moves the zoom lens and focusing lens of the lens unit 11401 a predetermined distance along the optical axis. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0262] The communication unit 11404 includes communication means for sending and receiving various information to and from the CCU 11201. The communication unit 11404 transmits image signals acquired from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0263] In addition, the communication unit 11404 receives control signals from the CCU 11201 for controlling the drive of the camera head 11102 and provides them to the camera head control unit 11405. For example, the control signals include information related to imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value when capturing the image, and / or information specifying the magnification and focus of the captured image.

[0264] Note that imaging conditions such as frame rate, exposure value, magnification, or focus can be appropriately specified by the user or can be automatically set by the control unit 11413 of CCU 11201 based on the acquired image signal. In the latter case, endoscope 11100 has so-called automatic exposure (AE), automatic focus (AF), and automatic white balance (AWB) functions.

[0265] The camera head control unit 11405 controls the driving of the camera head 11102 based on the control signals received from the CCU 11201 via the communication unit 11404.

[0266] The communication unit 11411 includes communication means for transmitting and receiving various types of information to and from the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0267] In addition, the communication unit 11411 transmits control signals for controlling the camera head 11102 to the camera head 11102. Image signals and control signals can be transmitted via electrical communication, optical communication, etc.

[0268] The image processing unit 11412 performs various image processing operations on the image signal transmitted from the camera head 11102 as RAW data.

[0269] The control unit 11413 performs various controls related to imaging the surgical site, etc., through the endoscope 11100 and displaying the images obtained by imaging the surgical site, etc. For example, the control unit 11413 generates control signals for controlling the drive of the camera head 11102.

[0270] Furthermore, the control unit 11413 causes the display device 11202 to display an image of the surgical site, etc., based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 can utilize various image recognition technologies to identify various objects in the captured image. For example, the control unit 11413 can identify surgical instruments such as surgical forceps, specific living areas, bleeding, and mist when using the energy therapy tool 11112 by detecting the shape and color of the edges of objects included in the captured image. When the captured image is displayed on the display device 11202, the control unit 11413 can overlay various surgical assistance information onto the image of the surgical site using the recognition results. Since the surgical assistance information is displayed in an overlay manner and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery reliably.

[0271] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for handling electrical signal communication, an optical fiber for handling optical communication, or a composite cable thereof.

[0272] Here, in the example shown, communication is conducted via a wired connection using transmission cable 11400, but communication between camera head 11102 and CCU 11201 can be conducted wirelessly.

[0273] Examples of endoscopic surgical systems to which the technology according to this disclosure can be applied have been described above. For example, the technology according to this disclosure can be applied to the imaging unit 11402 of the endoscope 11100 or camera head 11102 in the above-described components. Specifically, the imaging element described above can be applied to the imaging unit 11402. The imaging element according to this disclosure can simultaneously ensure a wide sensitive area (charge accumulation electrode 12) and the amount of accumulated charge Qs in each pixel 101, thereby obtaining higher quality images. As a result, for example, the surgeon 11131 can perform surgery more reliably.

[0274] Note that although an endoscopic surgical system has been used as an example here, the technology disclosed herein can also be applied to other microsurgical systems, for example.

[0275] (5-3. Examples of applications of moving bodies)

[0276] The technology disclosed herein can also be applied to devices mounted on any type of mobile body, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0277] Figure 26 This is a block diagram illustrating a schematic construction example of a vehicle control system, which is an example of a mobile body control system to which the technology according to this disclosure can be applied.

[0278] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 26 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as functional components of the comprehensive control unit 12050, a microcomputer 12051, an audio / visual output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0279] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for devices such as: drive force generating devices that generate driving force for the vehicle, such as internal combustion engines or drive motors; drive force transmission mechanisms that transmit driving force to the wheels; steering mechanisms that adjust the vehicle's steering angle; and braking devices that generate braking force for the vehicle.

[0280] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 acts as a control device for devices such as keyless entry systems, smart key systems, power windows, and various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves or signals from various switches transmitted from a portable device that replaces the key can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signal inputs and controls the vehicle's door locks, power windows, lights, etc.

[0281] The exterior information detection unit 12030 detects external information of the vehicle on which the vehicle control system 12000 is installed. For example, an imaging unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. The exterior information detection unit 12030 can perform object detection processing or distance detection processing for people, vehicles, obstacles, signs, or characters on the road surface based on the received images. For example, the exterior information detection unit 12030 performs image processing on the received images and performs object detection processing or distance detection processing based on the image processing results.

[0282] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can output an electrical signal as an image or as distance measurement information. Furthermore, the light received by imaging unit 12031 can be visible light or invisible light such as infrared light.

[0283] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041, which detects the driver's state, is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that captures images of the driver, and the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level based on the detection information input from the driver state detection unit 12041, or it can determine whether the driver is dozing off.

[0284] The microcomputer 12051 calculates control target values ​​for the drive force generating device, steering mechanism, or braking device based on information obtained from the external vehicle information detection unit 12030 or the internal vehicle information detection unit 12040, and outputs control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to realize the functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, following distance based on vehicle distance, speed maintenance, collision warning, and lane departure warning.

[0285] Furthermore, the microcomputer 12051 can control the driving force generating device, steering mechanism, or braking device, etc., based on the information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, to perform cooperative control aimed at achieving autonomous driving of the vehicle without relying on the driver's operation.

[0286] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the external environment of the vehicle obtained by the external information detection unit 12030. For example, the microcomputer 12051 can perform anti-glare coordinated control by controlling the headlights, such as switching the high beams to the low beams, based on the position of the vehicle ahead or oncoming vehicle detected by the external information detection unit 12030.

[0287] The audio-visual output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually and audibly notifying passengers of the vehicle or the outside of the vehicle. Figure 26 In the example, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0288] Figure 27 This is a diagram showing an example of the mounting location of the imaging unit 12031. Figure 27 In the process, as imaging unit 12031, vehicle 12100 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0289] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are disposed on the front nose, side mirrors, rear bumper or rear door, and upper part of the windshield of vehicle 12100. Imaging unit 12101 disposed on the front nose and imaging unit 12105 disposed on the upper part of the windshield mainly acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 disposed on the side mirrors mainly acquire images of the sides of vehicle 12100. Imaging unit 12104 disposed on the rear bumper or rear door mainly acquires images of the rear of vehicle 12100. The images of the vehicles in front acquired by imaging units 12101 and 12105 are mainly used to detect vehicles in front, pedestrians, obstacles, traffic lights, traffic signs, or lanes, etc.

[0290] Notice, Figure 27 An example of the imaging range of imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 represents the imaging range of imaging unit 12104 located on the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a top-down image of the vehicle 12100 can be obtained.

[0291] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0292] For example, the microcomputer 12051 can obtain the distance to each three-dimensional object in the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. This allows it to extract three-dimensional objects traveling on the driving path at a predetermined speed (e.g., equal to or greater than 0 km / h) in approximately the same direction as the vehicle 12100 (specifically, the three-dimensional object closest to the vehicle 12100) as the vehicle ahead. Furthermore, the microcomputer 12051 can pre-set the required vehicle-to-vehicle distance and perform automatic braking control (including stop-and-go control) and automatic acceleration control (including start-and-go control), etc. As described above, cooperative control, such as autonomous driving aimed at achieving autonomous driving without driver intervention, can be performed.

[0293] For example, based on distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles, and extract three-dimensional object data for automatic obstacle avoidance. For example, microcomputer 12051 distinguishes obstacles around vehicle 12100 into obstacles that are visually identifiable by the driver of vehicle 12100 and obstacles that are not visually identifiable by the driver of vehicle 12100. Then, microcomputer 12051 can determine the collision risk, which represents the degree of risk of colliding with each obstacle. When the collision risk is at or above a set value, indicating a possible collision, microcomputer 12051 can perform collision avoidance driving assistance by outputting a warning to the driver via audio speaker 12061 or display unit 12062, or by executing forced deceleration or evasive steering through drive system control unit 12010.

[0294] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and by performing pattern matching processing on a series of feature points representing the outline of an object and determining whether it is a pedestrian. For example, when the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the sound image output unit 12052 controls the display unit 12062 to overlay and display a square outline to emphasize the identified pedestrian. Furthermore, the sound image output unit 12052 can cause the display unit 12062 to display an icon representing a pedestrian light at a desired location.

[0295] Examples of vehicle control systems that can be applied according to the technology of this disclosure have been described above. For example, the technology of this disclosure can be applied to the imaging unit 12031 in the above-described components.

[0296] Specifically, the aforementioned imaging element can be applied to imaging unit 12031. The imaging element according to this disclosure can simultaneously ensure a wide sensitive area (charge accumulation electrode 12) and the amount of accumulated charge Qs in each pixel 101, thereby obtaining higher quality captured images. Therefore, pedestrians can be identified more accurately and vehicles can be controlled more effectively.

[0297] Note that the effects described in this specification are illustrative and not limiting, and other effects may also be present.

[0298] Note that this technology can also have the following configurations.

[0299] (1) An imaging device comprising pixels, wherein the pixels include:

[0300] Photoelectric conversion layer;

[0301] A first electrode is located on the first surface side of the photoelectric conversion layer and is electrically connected to the photoelectric conversion layer;

[0302] The second electrode is located on the second surface of the photoelectric conversion layer opposite to the first surface;

[0303] A charge accumulation electrode is disposed on the first surface side of the photoelectric conversion layer and spaced apart from the first electrode in a direction parallel to the first surface; and

[0304] The third electrode is arranged at a position where it overlaps with the gap between the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface.

[0305] (2) The imaging apparatus according to (1) above, wherein the third electrode is not connected to the first electrode and the charge accumulation electrode.

[0306] (3) The imaging apparatus according to (1) or (2) above, wherein the third electrode has a portion that overlaps with at least one of the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface.

[0307] (4) The imaging apparatus according to (1) or (2) above, wherein the third electrode does not have a portion that overlaps with the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface.

[0308] (5) The imaging apparatus according to any one of (1) to (4) above, wherein the third electrode is arranged at a location shared by the plurality of pixels.

[0309] (6) The imaging apparatus according to any one of (1) to (5) above, wherein the first electrode is shared by a plurality of said pixels as shared units, and

[0310] The third electrode is arranged at a location shared by the plurality of pixels across the shared unit.

[0311] (7) The imaging apparatus according to any one of (1) to (6) above, wherein the plurality of said pixels are arranged in a matrix array, and

[0312] The third electrode is positioned at a location shared by pixels arranged in a row or column of the matrix array.

[0313] (8) The imaging apparatus according to any one of (1) to (6) above, wherein the plurality of said pixels are arranged in a matrix array, and

[0314] The third electrode is positioned at a location shared by pixels arranged in adjacent rows or columns of the matrix array.

[0315] (9) The imaging apparatus according to any one of (1) to (8) above further includes a separation electrode for electrically separating the pixel from other pixels adjacent to the pixel.

[0316] The third electrode is connected to the separation electrode.

[0317] (10) The imaging apparatus according to (9) above, wherein the third electrode is connected to the separation electrode via a vertical through-hole.

[0318] (11) The imaging apparatus according to any one of (1) to (8) above, wherein the photoelectric conversion layer, the first electrode, the second electrode, the charge accumulation electrode and the third electrode are arranged on the third surface side of the semiconductor substrate, and

[0319] The third electrode is connected to wiring in a wiring layer arranged on a fourth surface of the semiconductor substrate opposite to the third surface by passing through the semiconductor substrate.

[0320] (12) The imaging apparatus according to any one of (1) to (11) above, wherein the pixel has a rectangular shape, and

[0321] The first electrode is arranged along any side of the rectangular shape.

[0322] (13) The imaging apparatus according to any one of (1) to (11) above, wherein the pixel has a rectangular shape, and

[0323] The first electrode is positioned at any corner of the rectangular shape.

[0324] (14) The imaging apparatus according to any one of (1) to (5) and (9) to (13) above, wherein, in a first state, a first voltage is applied to the third electrode, the first voltage being lower than the voltage applied to the charge accumulation electrode, and

[0325] In the second state, which transitions from the first state, a second voltage is applied to the third electrode, the second voltage being higher than the voltage applied to the charge accumulation electrode and higher than the first voltage.

[0326] (15) The imaging apparatus according to (1) or (3) or (4) or (12) or (13) above, wherein the third electrode is connected to the first electrode.

[0327] (16) According to the imaging apparatus described in (15) above, in the first state, a third voltage is applied to the third electrode, and a fourth voltage higher than the third voltage is applied to the charge accumulation electrode, and

[0328] In the second state transitioning from the first state, the fourth voltage is applied to the third electrode, and the third voltage is applied to the charge accumulation electrode.

[0329] (17) An electronic device comprising:

[0330] An imaging device comprising a pixel, wherein the pixel comprises: a photoelectric conversion layer; a first electrode located on a first surface side of the photoelectric conversion layer and electrically connected to the photoelectric conversion layer; a second electrode located on a second surface of the photoelectric conversion layer opposite to the first surface; a charge accumulation electrode disposed on the first surface side of the photoelectric conversion layer and spaced apart from the first electrode in a direction parallel to the first surface; and a third electrode disposed at a position having an overlap portion with the gap between the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface.

[0331] An image processing unit performs image processing on pixel signals based on the charge generated by the photoelectric conversion layer to generate image data; and

[0332] A storage unit that stores the image data generated by the image processing unit.

[0333] List of reference numerals

[0334] 11,11a,11b First Electrode

[0335] 11ex,200,200 cen 200 col 200 col(a) 200 col(b) 200 col(c) 200 lft 200 rht 200 row 200 row(2) 200 row(a)200 row(b) Barrier forming electrode

[0336] 12 Charge accumulation electrodes

[0337] 14 gaps

[0338] 15,15pan photoelectric conversion layer

[0339] 16 Second electrode

[0340] 61 Contact Hole

[0341] 63 pads

[0342] 70 Semiconductor substrate

[0343] 101, 101a, 101b, 101c, 101d, 101e 11 ,101e 12 ,101e 13 ,101e 14 ,101e 21 ,101e 22 ,101e 23 ,101e 24 ,101f 11 ,101f 12 ,101f 13 ,101f 14 ,101f 21 ,101f 22 ,101f 23 ,101f 24 101g 11 101g 12 101g 13 101g 14 101g 21 101g 22 101g 23 101g 24 ,101h 11 ,101h 12 ,101h 13 ,101h 14 ,101h 21 ,101h 22 ,101h 23 ,101h 24 Pixels

[0344] 221 Vertical through hole

[0345] 220 pixel separate electrode

[0346] 240 through electrode

Claims

1. An imaging device comprising pixels, wherein, The pixels include: Photoelectric conversion layer; A first electrode is located on the first surface side of the photoelectric conversion layer and is electrically connected to the photoelectric conversion layer; The second electrode is located on the second surface of the photoelectric conversion layer opposite to the first surface; A charge accumulation electrode is disposed on the first surface side of the photoelectric conversion layer and spaced apart from the first electrode in a direction parallel to the first surface; and The third electrode is positioned at a location that overlaps with the gap between the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface. The third electrode is not connected to the first electrode and the charge accumulation electrode, and is arranged at a certain distance from the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface.

2. The imaging device according to claim 1, wherein, The third electrode has a portion that overlaps with at least one of the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface.

3. The imaging device according to claim 1, wherein, The third electrode does not have a portion that overlaps with the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface.

4. The imaging device according to claim 1, wherein, The third electrode is positioned at a location shared by the multiple pixels.

5. The imaging apparatus according to claim 1, wherein, The first electrode is shared by a plurality of pixels that act as shared units, and The third electrode is arranged at a location shared by the plurality of pixels across the shared unit.

6. The imaging apparatus according to claim 1, wherein, The plurality of said pixels are arranged in a matrix array, and The third electrode is positioned at a location shared by pixels arranged in a row or column of the matrix array.

7. The imaging apparatus according to claim 1, wherein, The plurality of said pixels are arranged in a matrix array, and The third electrode is positioned at a location shared by pixels arranged in adjacent rows or columns of the matrix array.

8. The imaging apparatus of claim 1, further comprising a separation electrode, the separation electrode being used to electrically separate the pixel from other pixels adjacent to the pixel. in, The third electrode is connected to the separating electrode.

9. The imaging apparatus according to claim 8, wherein, The third electrode is connected to the separating electrode via a vertical through-hole.

10. The imaging apparatus according to claim 1, wherein, The photoelectric conversion layer, the first electrode, the second electrode, the charge accumulation electrode, and the third electrode are arranged on the third surface side of the semiconductor substrate, and The third electrode is connected to wiring in a wiring layer arranged on a fourth surface of the semiconductor substrate opposite to the third surface by passing through the semiconductor substrate.

11. The imaging apparatus according to claim 1, wherein, The pixel has a rectangular shape, and The first electrode is arranged along any side of the rectangular shape.

12. The imaging apparatus according to claim 1, wherein, The pixel has a rectangular shape, and The first electrode is positioned at any corner of the rectangular shape.

13. The imaging apparatus according to claim 1, wherein, In the first state, a first voltage is applied to the third electrode, the first voltage being lower than the voltage applied to the charge accumulation electrode, and In the second state, which transitions from the first state, a second voltage is applied to the third electrode, the second voltage being higher than the voltage applied to the charge accumulation electrode and higher than the first voltage.

14. An electronic device comprising: The imaging apparatus according to any one of claims 1-13; An image processing unit performs image processing on pixel signals based on the charge generated by the photoelectric conversion layer to generate image data; and A storage unit that stores the image data generated by the image processing unit.

Images