Lateral diffused metal oxide semiconductor transistor and method of manufacture
By employing passivation layers and a second modulation gate structure with alternating dielectric dielectrics of different dielectric constants in LDMOS devices, the problem of insufficient breakdown voltage under high voltage is solved, thereby improving the device's breakdown resistance and switching speed, and reducing power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2019-12-27
- Publication Date
- 2026-07-31
AI Technical Summary
If the breakdown voltage of a high-voltage LDMOS device is too low, the device will break down and fail under high voltage.
A passivation layer structure with alternating first and second insulating media of different dielectric constants is adopted. The breakdown resistance of the passivation layer is enhanced by the alternating coverage of the first and second insulating media, and the parasitic capacitance is reduced by setting a second modulation gate.
This improves the breakdown voltage of laterally diffused metal-oxide-semiconductor transistors, enhances their breakdown resistance, reduces parasitic capacitance, increases switching speed, and lowers switching power consumption.
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Figure CN114830352B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the semiconductor field, and more particularly to a laterally diffused metal-oxide-semiconductor transistor and its manufacturing method. Background Technology
[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) is frequently used in microwave / RF circuits.
[0003] LDMOS is commonly used in the fabrication of RF power amplifiers for base stations because it can meet the requirements of high output power and a gate-source breakdown voltage greater than 60 volts. Compared to other devices, LDMOS power amplifiers have a relatively low maximum frequency and are frequently used in microwave / RF circuits to fabricate RF power amplifiers for base stations.
[0004] Breakdown voltage is a critical parameter for high-voltage LDMOS devices. If the breakdown voltage is too low, the LDMOS will break down under high voltage, leading to device failure. Therefore, it is necessary to increase the breakdown voltage of high-voltage LDMOS devices. Summary of the Invention
[0005] This application provides a laterally diffused metal-oxide-semiconductor transistor and its manufacturing method, which solves the problem of device failure caused by excessively low breakdown voltage in high-voltage LDMOS devices.
[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:
[0007] A first aspect of this application provides a laterally diffused metal-oxide-semiconductor transistor, comprising: a substrate including a source region, a body region, a drift region, and a drain region disposed along a first direction, wherein the first direction is parallel to a first surface of the substrate; a first modulation gate disposed near the surface of the body region; and a passivation layer disposed near the surface of the drift region. The passivation layer includes: a first insulating medium and a second insulating medium alternately disposed along the first direction; the dielectric constant of the second insulating medium is different from that of the first insulating medium. Therefore, by alternating the first insulating medium and the second insulating medium with different dielectric constants, additional current can be avoided forming on the first insulating medium or the second insulating medium, making the passivation layer more resistant to breakdown, increasing the breakdown voltage between the first modulation gate and the drain region, and improving the breakdown resistance of the laterally diffused metal-oxide-semiconductor transistor.
[0008] In one alternative implementation, the widths of the first insulating medium and the second insulating medium in the passivation layer are equal along the first direction. This results in a uniform distribution of the first and second insulating media, improving the breakdown resistance of the laterally diffused metal-oxide-semiconductor transistor.
[0009] In one optional implementation, the width of each layer of the second insulating medium along the first direction is 0.1 μm to 0.8 μm. This results in a smaller width for each layer of the second insulating medium, preventing the formation of current on the second insulating medium.
[0010] In one alternative implementation, the passivation layer has a thickness of 0.1 μm to 0.3 μm. This results in a thin passivation layer, reducing production costs.
[0011] In one alternative implementation, the first insulating medium is silicon dioxide, and the second insulating medium is silicon oxynitride. This reduces the cost of both the first and second insulating media, allowing them to be used in the passivation layer, thereby improving the breakdown voltage of the laterally diffused metal-oxide-semiconductor transistor while simultaneously lowering production costs.
[0012] In one optional implementation, the laterally diffused metal-oxide-semiconductor transistor further includes a second modulation gate, a portion of which is disposed on the surface of the drift region and another portion on the surface of the first modulation gate. The second modulation gate is connected to the passivation layer. A first insulating dielectric is provided between the second modulation gate and the first surface of the substrate, between the second modulation gate and the first modulation gate, and between the first modulation gate and the first surface of the substrate. Thus, the second modulation gate acts as a shield between the drain region and the first modulation gate, significantly reducing the parasitic capacitance between the first modulation gate and the drain region. Consequently, the switching speed of the device is greatly improved, and the switching power consumption is significantly reduced.
[0013] In one optional implementation, the passivation layer is disposed on the surface of the first modulation gate and the surface of the drain region, wherein a first insulating dielectric is disposed between the passivation layer and the first modulation gate, between the passivation layer and the first surface of the substrate, and between the first modulation gate and the first surface of the substrate. This expands the coverage area of the passivation layer, further increases the breakdown voltage between the first modulation gate and the drain region, and improves the breakdown resistance of the laterally diffused metal-oxide semiconductor.
[0014] A second aspect of this application provides a method for manufacturing a laterally diffused metal-oxide-semiconductor transistor, comprising: depositing a first modulation gate on a first surface of a substrate, wherein the substrate includes a source region, a body region, a drift region, and a drain region disposed along a first direction, wherein the first direction is a direction parallel to the first surface, and the first modulation gate is opposite to the body region; depositing a passivation layer on the first modulation gate, wherein the passivation layer is opposite to the drift region; wherein the passivation layer includes: a first insulating medium and a second insulating medium alternately disposed along the first direction, wherein the dielectric constant of the second insulating medium is greater than that of the first insulating medium but different from that of the first insulating medium.
[0015] In one optional implementation, depositing the passivation layer on the first insulating medium includes: depositing a second insulating medium on the first insulating medium; etching the second insulating medium to expose it; and depositing the first insulating medium at the etched locations, such that the first insulating medium and the second insulating medium are alternately disposed along a first direction.
[0016] In one alternative implementation, the widths of the first insulating medium and the second insulating medium in the first direction are equal.
[0017] In one alternative implementation, the width of the second insulating medium in the first direction is 0.1 μm to 0.8 μm.
[0018] In one alternative implementation, the thickness of the passivation layer is 0.1 μm to 0.3 μm.
[0019] In one alternative implementation, the first insulating medium is silicon dioxide, and the second insulating medium is silicon oxynitride.
[0020] In one alternative implementation, the widths of the first insulating medium and the second insulating medium in the passivation layer are equal along the first direction.
[0021] In one alternative implementation, before depositing the first modulation gate on the first insulating medium, the method further includes depositing the first insulating medium on a first surface of the substrate.
[0022] In one alternative implementation, before depositing a passivation layer on the first insulating medium, the method further includes: depositing a second modulation gate on the first modulation gate and a first surface of the substrate, such that a portion of the second modulation gate is disposed near the surface of the drift region and another portion is disposed on the surface of the first modulation gate, wherein the second modulation gate is connected to the passivation layer.
[0023] In one alternative implementation, before depositing the second modulation gate on the first modulation gate and the first surface of the substrate, the method further includes depositing the first insulating medium on the first modulation gate and the first surface of the substrate.
[0024] In one optional implementation, the passivation layer is disposed on the surface of the first modulation gate and the surface of the drain region, wherein the first insulating medium is disposed between the passivation layer and the first modulation gate, the passivation layer and the first surface of the substrate, and the first modulation gate and the first surface of the substrate. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of the structure of a laterally diffused metal-oxide transistor provided in an embodiment of this application;
[0026] Figure 2 A schematic diagram of another laterally diffused metal-oxide transistor provided in this application embodiment;
[0027] Figure 3 A schematic diagram of another laterally diffused metal-oxide transistor provided in this application embodiment;
[0028] Figure 4 A schematic diagram of another laterally diffused metal-oxide transistor provided in this application embodiment;
[0029] Figure 4A for Figure 4 A graph showing the breakdown voltage of a laterally diffused metal-oxide transistor as a function of time.
[0030] Figure 5 A schematic diagram of another laterally diffused metal-oxide transistor provided in this application embodiment;
[0031] Figure 5A for Figure 5 A graph showing the breakdown voltage of a laterally diffused metal-oxide transistor as a function of time.
[0032] Figure 6A A top view of a laterally diffused metal-oxide transistor provided in an embodiment of this application;
[0033] Figure 6B A top view of another laterally diffused metal-oxide transistor provided in an embodiment of this application;
[0034] Figure 6C A top view of another laterally diffused metal-oxide transistor provided in an embodiment of this application;
[0035] Figure 7A flowchart illustrating a method for manufacturing a laterally diffused metal-oxide transistor, as provided in an embodiment of this application;
[0036] Figure 8A , Figure 8B , Figure 8C , Figure 8D To execute Figure 7 A schematic diagram of the product structure obtained from each step;
[0037] Figure 9 A flowchart illustrating another method for manufacturing a laterally diffused metal-oxide transistor provided in this application embodiment;
[0038] Figure 10A To execute Figure 9 A schematic diagram of the product structure obtained in the intermediate steps;
[0039] Figure 11 A flowchart illustrating another method for manufacturing a laterally diffused metal-oxide transistor provided in this application embodiment;
[0040] Figure 12A , Figure 12B , Figure 12C To execute Figure 11 A schematic diagram of the product structure obtained from each step. Detailed Implementation
[0041] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.
[0042] In the following description, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0043] Furthermore, in this application, directional terms such as "upper" and "lower" are defined relative to the indicated placement of the components in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the placement of the components in the accompanying drawings.
[0044] The following explains the terminology that may appear in the embodiments of this application.
[0045] Dielectric constant: When a dielectric material is subjected to an applied electric field, it generates induced charges that weaken the electric field. The ratio of the original applied electric field (in vacuum) to the final electric field in the dielectric is the dielectric constant, which is frequency-dependent. The dielectric constant ε can be defined as the ratio of electric displacement D to electric field strength E, ε = D / E.
[0046] Breakdown voltage: The voltage at which a dielectric material breaks down. When a dielectric material is subjected to a sufficiently strong electric field, it loses its dielectric properties and becomes a conductor; this is called dielectric breakdown, and the corresponding voltage is called the breakdown voltage.
[0047] The Miller effect, or parasitic capacitance, occurs in electronics, specifically in inverting amplifier circuits. Due to the amplifier's amplification, the distributed capacitance or parasitic capacitance between the input and output is amplified by a factor of 1+K, where K is the voltage gain of that amplifier stage. For MOSFETs, the overlay capacitance between the gate and drain is the Miller capacitance. This overlay capacitance spans the input (gate) and output (drain) terminals, thus the Miller effect increases the equivalent input capacitance, leading to a decrease in frequency response.
[0048] This application provides a laterally diffused metal-oxide transistor. Figure 1 This is a schematic diagram of the structure of a laterally diffused metal-oxide transistor provided in an embodiment of this application. Figure 1 As shown, the laterally diffused metal-oxide transistor includes a substrate 200, a first modulation gate 102 and a passivation layer 103 disposed above the substrate 200.
[0049] The substrate includes a source region 201, a body region 202, a drift region 203, and a drain region 204 disposed along a first direction. The substrate 200 is, for example, a silicon substrate doped with a first conductivity type. The first direction is parallel to the first surface of the substrate 200.
[0050] The substrate 200 is, for example, cubic in shape, and the first surface of the substrate 200 can be any surface of the substrate 200. The surfaces of the source region 201, the body region 202, the drift region 203, and the drain region 204 are all located on the first surface of the substrate 200 and extend from the first surface of the substrate 200 into the interior of the substrate 200.
[0051] Source region 201 and drain region 204 are located on opposite sides of substrate 200 in a first direction, and body region 202 and drift region 203 are located between source region 201 and drain region 204 in the first direction. The first direction is, for example, [missing information]. Figure 1 The direction of the X-axis in the diagram.
[0052] It should be noted that the first direction is... Figure 1 The X-axis direction may have errors, as long as the first direction is parallel to the first surface of the substrate, these are all within the protection scope of this application.
[0053] Drift region 203 is composed, for example, of an ion implantation region of the second conductivity type, and body region 202 is composed, for example, of an ion implantation region of the first conductivity type. Source region 201 and body region 202 have the same doping type but different doping concentrations. Drain region 204 and drift region 203 have the same doping type but different doping concentrations.
[0054] The first modulation gate 102 is disposed on the surface of the body region 202. The first modulation gate 102 is, for example, made of polysilicon. The first modulation gate 102 is used to control the source region 201 and the drain region 204 to be switched on and off according to the voltage. When a high voltage is input to the first modulation gate 102, the source region 201 and the drain region 204 can be connected through the body region 202 and the drift region 203.
[0055] A first insulating medium 101 is provided between the surface of the first modulation gate 102 and the body region 202, and the first insulating medium 101 can make the first modulation gate 102 insulated from the body region 202.
[0056] The first modulation gate 102 covers the surface of the body region 202, and the second side of the first modulation gate 102 extends to the surface of the drift region 203. The surface of the body region 202 covered by the first modulation gate 102 is used to form a channel.
[0057] Among them, the capacitance between the first modulation gate 102 and the drain region 204 becomes the most critical parasitic capacitance in the laterally diffused metal-oxide-semiconductor transistor device due to the Miller effect. The parasitic capacitance causes an electric field to be formed between the first modulation gate 102 and the drain region 204. When the electric field is strong enough, the dielectric between the first modulation gate 102 and the drain region 204 loses its dielectric properties and becomes a conductor under the influence of the electric field, causing the laterally diffused metal-oxide-semiconductor transistor device to fail.
[0058] This application embodiment does not limit the coverage area of the passivation layer 103. Among them, the drift region 203 has the largest electric field strength. In this embodiment, the passivation layer 103 is disposed, for example, on the surface of the drift region 203.
[0059] A first insulating medium 101 is provided between the passivation layer 103 and the drift region 203 to isolate the passivation layer 103 from the drift region 203 and the drain region 204.
[0060] This application does not limit the specific structure of the passivation layer 103. In this embodiment, the passivation layer 103 includes a second insulating medium 105, the dielectric constant of which is greater than that of the first insulating medium 101.
[0061] Therefore, the passivation layer 103 has a large dielectric constant. By setting the passivation layer 103, the dielectric properties between the first modulation gate and the drain can be improved, thereby increasing the breakdown voltage of the laterally diffused metal-oxide-semiconductor transistor.
[0062] This application does not limit the materials of the first insulating medium 101 and the second insulating medium 105. In this embodiment, the first insulating medium 101 is, for example, silicon dioxide, and the second insulating medium 105 is, for example, silicon oxynitride.
[0063] Silicon dioxide has a low dielectric constant of about 3.9, making it prone to breakdown in high-voltage LDMOS.
[0064] Silicon oxynitride has a high dielectric constant of about 7-8, good insulation, low leakage current, and oxidation resistance. As a passivation layer 103, it has a good isolation effect and can prevent the breakdown of laterally diffused metal oxide semiconductor transistors.
[0065] The laterally diffused metal-oxide-semiconductor transistor provided in this application embodiment can improve the breakdown voltage of the laterally diffused metal-oxide-semiconductor transistor by providing a passivation layer 103.
[0066] In pure silicon oxynitride, some electrons are captured, leading to atomic mismatch and more severe disorder. This creates an additional current within the silicon oxynitride. When electrons in silicon oxynitride generate current under the influence of an electric field, the breakdown voltage drops suddenly. Figure 4A As shown in the line graph, this makes the LDMOS breakdown voltage curve uneven, affecting the breakdown performance of the laterally diffused metal-oxide-semiconductor transistor.
[0067] Therefore, embodiments of this application also provide a laterally diffused metal-oxide-semiconductor transistor. Figure 2 This is a schematic diagram of another laterally diffused metal-oxide transistor provided in an embodiment of this application. Figure 2 As shown, the passivation layer 103 further includes a first insulating medium 101, and the first insulating medium 101 and the second insulating medium 105 are alternately disposed, for example, along a first direction.
[0068] By using a first insulating medium 101 to separate the second insulating medium 105, it is possible to avoid the formation of additional current on the second insulating medium 105, such as... Figure 5A As shown, the breakdown voltage curve of the laterally diffused metal-oxide-semiconductor transistor with passivation layer 103 is smoother, which improves the breakdown resistance of the device.
[0069] The laterally diffused metal-oxide-semiconductor transistor provided in this application has a high dielectric constant of the passivation layer. By setting the passivation layer, the breakdown voltage of the laterally diffused metal-oxide-semiconductor transistor can be improved.
[0070] Simultaneously, alternating the first and second insulating media, with the first insulating media separating the second insulating media, prevents the formation of additional current on the second insulating media, making the passivation layer more resistant to breakdown. This increases the breakdown voltage between the first modulation gate and the drain region 204, thereby improving the breakdown performance of the laterally diffused metal-oxide-semiconductor transistor. Furthermore, separating the second insulating media by the first insulating media eliminates the need to introduce new media, thus avoiding any impact on the performance of the laterally diffused metal-oxide-semiconductor transistor device.
[0071] In another implementation of this application, such as Figure 3 As shown, the passivation layer 103 is disposed close to the surface of the first modulation gate 102, the surface of the drift region 203 and the surface of the drain region 204, wherein a first insulating medium is provided between the passivation layer 103 and the surface of the first modulation gate 102, the surface of the passivation layer 103 and the surface of the drift region 203 and the surface of the passivation layer 103 and the surface of the drain region 204.
[0072] The passivation layer 103 is applied to the first modulation gate 102 in a portion that is approximately one-third the width of the first modulation gate 102 in the first direction. Other locations of the first modulation gate 102 and the source region 201 are used, for example, for connection to other parts of the power amplifier circuit.
[0073] This expands the coverage of the passivation layer 103, further improving the breakdown performance of the laterally diffused metal-oxide-semiconductor transistor.
[0074] The above-described passivation layer coverage method is only one implementation of the embodiments of this application. Those skilled in the art can make adjustments according to the specific structure of the laterally diffused metal-oxide-semiconductor transistor, and these adjustments all fall within the protection scope of this application.
[0075] Figure 4 This is a schematic diagram of another laterally diffused metal-oxide-semiconductor transistor provided in an embodiment of this application. Figure 5 This is a schematic diagram of another laterally diffused metal-oxide transistor provided in an embodiment of this application. Figure 4 , Figure 5 As shown, the laterally diffused metal-oxide-semiconductor transistor further includes a second modulation gate 104.
[0076] The second modulation gate 104 is partially disposed near the surface of the drift region 203 and partially disposed on the surface of the first modulation gate 102.
[0077] The distribution of the second modulation gate 104 described above is only one implementation of the embodiments of this application. Those skilled in the art can make adjustments according to the specific structure of the laterally diffused metal-oxide-semiconductor transistor, and these adjustments all fall within the protection scope of this application.
[0078] The second modulation gate 104 is, for example, made of polysilicon. The second modulation gate 104 acts as a shield between the drain region 204 and the first modulation gate 102. By adjusting the voltage of the second modulation gate 104, the parasitic capacitance between the first modulation gate 102 and the drain region 204 can be greatly reduced, thereby significantly improving the switching speed of the device and significantly reducing the switching power consumption.
[0079] A first insulating medium 101 is provided between the surface of the second modulation gate 104 and the drift region 203, and between the surface of the second modulation gate 104 and the first modulation gate 102. The first insulating medium 101 can isolate the second modulation gate 104 and the first modulation gate 102, and isolate the second modulation gate 104 and the drift region 203.
[0080] The second modulation gate 104 includes a first side surface, which is connected to the passivation layer 103.
[0081] The laterally diffused metal-oxide-semiconductor transistor provided in this application embodiment can reduce the parasitic capacitance between the first modulation gate and the drain region 204 by setting the second modulation gate 104, thereby increasing the breakdown voltage between the first modulation gate and the drain region 204, which is beneficial to improving the breakdown performance of the laterally diffused metal-oxide-semiconductor transistor.
[0082] This application embodiment does not limit the shape of the first insulating medium 101 and the second insulating medium 105 in the passivation layer 103. In this embodiment, as shown... Figure 6A As shown, the first insulating medium 101 and the second insulating medium 105 are, for example, a plurality of alternating strip structures, and the widths of the first insulating medium 101 and the second insulating medium 105 in the first direction are equal.
[0083] Thus, the uniform distribution of the first and second insulating media improves the breakdown resistance of the laterally diffused metal-oxide-semiconductor transistor.
[0084] In addition, such as Figure 6B , Figure 6C As shown, the shapes of the first insulating medium 101 and the second insulating medium 105 can also be polygonal or wave-shaped.
[0085] This application embodiment does not limit the dimensions of the first insulating medium 101 and the second insulating medium 105 in the passivation layer 103. In this embodiment, the width of each layer of the first insulating medium 101 and the second insulating medium 105 along the first direction is 0.1μm-0.8μm. Therefore, the width of each layer of the second insulating medium is small, avoiding the formation of current on the second insulating medium.
[0086] The thickness of each first insulating medium 101 and second insulating medium 105 is 0.1μm-0.3μm. As a result, the passivation layer thickness is small, saving production costs.
[0087] like Figure 7 As shown in the illustration, this application provides a method for manufacturing a laterally diffused metal-oxide transistor. The method includes:
[0088] S101, such as Figure 8A As shown, a first insulating medium 101 is deposited on the first surface of the substrate 200.
[0089] The substrate 200 includes a source region 201, a body region 202, a drift region 203 and a drain region 204 disposed along a first direction, and the first insulating medium 101 is in contact with the source region 201, the body region 202, the drift region 203 and the drain region 204 on the first surface.
[0090] In this step, ion doping and diffusion can be performed on substrate 200 to form body regions 202 and drift regions 203 with different doping types. Subsequently, ions are implanted at appropriate locations to form source and drain electrodes.
[0091] Specifically, if the laterally diffused metal-oxide transistor is an N-type device, then the first conductivity type is P-type, and the second conductivity type is N-type. Alternatively, if the laterally diffused metal-oxide transistor is a P-type device, then the first conductivity type is N-type, and the second conductivity type is P-type.
[0092] The substrate 200 includes, for example, a silicon substrate and an epitaxial layer, wherein the epitaxial layer is disposed on the silicon substrate, and a source region 201, a body region 202, a drift region 203 and a drain region 204 are formed on the epitaxial layer, for example. The first insulating medium 101 is, for example, silicon dioxide.
[0093] S102, such as Figure 8B As shown, a first modulation gate 102 is deposited on the first insulating medium 101.
[0094] The first modulation gate 102 is located on the surface of the body region 202. The first modulation gate 102 is, for example, made of polysilicon. The first modulation gate 102 is used to control the source region 201 and the drain region 204 to be switched on and off according to the voltage. When a high voltage is input to the first modulation gate 102, the source region 201 and the drain region 204 can be connected through the body region 202 and the drift region 203.
[0095] A first insulating medium 101 is provided between the surface of the first modulation gate 102 and the body region 202, and the first insulating medium 101 can make the first modulation gate 102 insulated from the body region 202.
[0096] S103, such as Figure 8CAs shown, a first insulating dielectric 101 is deposited on the first modulation gate 102.
[0097] The deposition of the first insulating medium 101 on the first modulation gate 102 includes: the first insulating medium 101 is disposed on the side of the first surface of the first modulation gate 102 away from the substrate 200 and on the side surface of the first modulation gate 102.
[0098] In this embodiment, a first insulating medium 101 can be deposited on the first modulation gate 102 and the first surface of the substrate provided with the first insulating medium 101.
[0099] S104, such as Figure 8D As shown, a passivation layer 103 is deposited on the first insulating medium 101.
[0100] In this embodiment, the passivation layer 103 is located on the surface of the drift region 203.
[0101] In another implementation of this application, the passivation layer is located on the first modulation gate 102, the drift region 203, and the drain region 204. Expanding the coverage of the passivation layer can improve the breakdown voltage of the laterally diffused metal-oxide-semiconductor transistor.
[0102] The passivation layer 103 includes a second insulating medium 105, the dielectric constant of which is greater than that of the first insulating medium 101.
[0103] The passivation layer 103 has a large dielectric constant. By setting the passivation layer 103, the dielectric properties between the first modulation gate and the drain can be improved, thereby increasing the breakdown voltage of the laterally diffused metal-oxide-semiconductor transistor.
[0104] A first insulating medium 101 is provided between the passivation layer 103 and the drift region 203, and between the passivation layer 103 and the drain region 204, to isolate the passivation layer 103 from the drift region 203 and the drain region 204.
[0105] The second insulating medium 105 is, for example, silicon oxynitride, which has a high dielectric constant of about 7-8, good insulation, low leakage current, and oxidation resistance. As a passivation layer 103, it has a better isolation effect and can prevent the laterally diffused metal oxide semiconductor transistor from being broken down.
[0106] In another implementation of this application, such as Figure 9 As shown, before depositing the passivation layer 103 on the first insulating medium 101, the method further includes:
[0107] S105, such as Figure 10AAs shown, a second modulation gate 104 is deposited on the first insulating medium 101, such that a portion of the second modulation gate 104 is disposed on the drift region 203 and another portion is disposed on the first modulation gate 102.
[0108] The second modulation gate 104 is connected to the passivation layer 103.
[0109] The second modulation gate 104 is a shielding gate. It can be energized so that the second modulation gate 104 acts as a shield between the drain region 204 and the first modulation gate 102, which greatly reduces the parasitic capacitance between the first modulation gate 102 and the drain region 204. Therefore, the switching speed of the device is greatly improved and the switching power consumption is greatly reduced.
[0110] A first insulating medium 101 is provided between the surface of the second modulation gate 104 and the drift region 203, and between the surface of the second modulation gate 104 and the first modulation gate 102. The first insulating medium 101 can isolate the second modulation gate 104 and the first modulation gate 102, and isolate the second modulation gate 104 and the drift region 203.
[0111] In another implementation of this application, such as Figure 11 As shown, a passivation layer 103 is deposited on the first insulating medium 101, comprising:
[0112] S1041, such as Figure 12A As shown, a second insulating medium 105 is deposited on the first insulating medium 101.
[0113] The second insulating medium 105 is located on the surfaces of the drift region 203 and the drain region 204. The second modulation gate 104 is partially located on the first modulation gate 102 and partially located on the drift region 203. The second insulating medium 105 is connected to the second side of the second modulation gate 104.
[0114] S1042, such as Figure 12B As shown, etching is performed on the second insulating medium 105 to expose the first insulating medium 101.
[0115] Specifically, a first groove 106 can be etched into the second insulating medium, with the bottom of the first groove 106 being the first insulating medium 101. After etching, the first insulating medium 101 is exposed.
[0116] S1043, such as Figure 12C As shown, a first insulating medium 101 is deposited at the etched location, such that the first insulating medium 101 and the second insulating medium 105 are alternately arranged along the first direction.
[0117] The first insulating medium 101 can be deposited in the first groove 106.
[0118] Thus, the first insulating medium 101 can separate the second insulating medium 105 along the first direction, and the two are alternately arranged to avoid the formation of additional current on the second insulating medium 105, making the passivation layer 103 more resistant to breakdown.
[0119] Meanwhile, the second insulating medium 105 is separated by the first insulating medium 101, eliminating the need to introduce a new medium and avoiding affecting the performance of the laterally diffused metal-oxide-semiconductor transistor device.
[0120] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A lateral diffused metal oxide semiconductor transistor, characterized by, include: The substrate includes a source region, a body region, a drift region, and a drain region disposed along a first direction, wherein the first direction is a direction parallel to the first surface of the substrate; A first modulation gate is disposed near the surface of the body region; A second modulation gate, a portion of which is disposed on the surface of the drift region, and another portion of which is disposed on the surface of the first modulation gate; A passivation layer is disposed on the surface near the drift region, and the passivation layer is connected to the second modulation gate; The passivation layer includes: a first insulating medium and a second insulating medium alternately disposed along the first direction; The dielectric constant of the second insulating medium is different from that of the first insulating medium; The first insulating medium is provided between the second modulation gate and the first surface of the substrate, between the second modulation gate and the first modulation gate, and between the first modulation gate and the first surface of the substrate.
2. The lateral diffused metal oxide semiconductor transistor of claim 1, wherein, The first insulating medium is silicon dioxide, and the second insulating medium is silicon oxynitride.
3. The lateral diffused metal oxide semiconductor transistor of claim 1 or 2, wherein, The width of each layer of the second insulating medium along the first direction is 0.1μm-0.8μm.
4. The lateral diffused metal oxide semiconductor transistor of claim 1 or 2, wherein, The thickness of the passivation layer is 0.1μm-0.3μm.
5. The lateral diffused metal oxide semiconductor transistor of claim 1 or 2, wherein, The widths of the first insulating medium and the second insulating medium in the passivation layer are equal along the first direction.
6. A method of manufacturing a lateral diffused metal oxide semiconductor transistor, characterized by, include: A first insulating medium is deposited on a first surface of a substrate, the substrate including a source region, a body region, a drift region and a drain region disposed along a first direction, wherein the first direction is a direction parallel to the first surface of the substrate; A first modulation gate is deposited on the first insulating medium, the first modulation gate being disposed near the surface of the body region; The first insulating dielectric is deposited on the first surface of the first modulation gate and the first surface of the substrate; A second modulation gate is deposited on the first insulating medium, such that a portion of the second modulation gate is disposed close to the surface of the drift region, and another portion is disposed on the surface of the first modulation gate; A passivation layer is deposited on the first insulating medium, wherein the passivation layer is disposed near the surface of the drift region, and the second modulation gate is connected to the passivation layer; The passivation layer includes a first insulating medium and a second insulating medium alternately disposed along the first direction, wherein the dielectric constant of the second insulating medium is different from that of the first insulating medium.
7. The method of manufacturing a lateral diffusion metal oxide semiconductor transistor according to claim 6, wherein Depositing the passivation layer on the first insulating medium includes: Deposit a second insulating medium on the first insulating medium; The second insulating medium is etched to expose it. A first insulating medium is deposited at the etched location, such that the first insulating medium and the second insulating medium are alternately arranged along a first direction.
8. The method of manufacturing a lateral diffusion metal oxide semiconductor transistor according to claim 6 or 7, wherein The first insulating medium is silicon dioxide, and the second insulating medium is silicon oxynitride.
9. The method for manufacturing a laterally diffused metal-oxide-semiconductor transistor according to claim 6 or 7, characterized in that, The width of the second insulating medium in the first direction is 0.1μm-0.8μm.
10. The method for manufacturing a laterally diffused metal-oxide-semiconductor transistor according to claim 6 or 7, characterized in that, The thickness of the passivation layer is 0.1μm-0.3μm.
11. The method for manufacturing a laterally diffused metal-oxide-semiconductor transistor according to claim 6 or 7, characterized in that, The widths of the first insulating medium and the second insulating medium in the passivation layer are equal along the first direction.