Power amplifier circuit, high frequency circuit, and communication device

Abstract

An improvement in power added efficiency is achieved. A second base of a second transistor (Q2) is connected to a first collector of a first transistor (Q1). A third base of a third transistor (Q3) is connected to the first collector of the first transistor (Q1), and a third collector is connected to a second collector of the second transistor (Q2). A second bias circuit (5) includes a fifth transistor (50) connected to the second base of the second transistor (Q2). A third bias circuit (6) includes a sixth transistor (60) connected to the third base of the third transistor (Q3). A first current limit circuit (7) has a seventh transistor (70), a first collector resistor (Rc1), and a first base resistor (Rb1). A second current limit circuit (8) has an eighth transistor (80), a second collector resistor (Rc2), and a second base resistor (Rb2).

Description

Technical Field

[0001] The present invention generally relates to power amplifier circuits, high-frequency circuits, and communication devices, and more specifically, to power amplifier circuits for amplifying high-frequency signals, high-frequency circuits having the power amplifier circuit, and communication devices having the high-frequency circuit. Background Technology

[0002] Previously, power amplifier circuits having a first amplifying transistor, a second amplifying transistor, a first variable voltage power supply, a second variable voltage power supply, a first bias circuit, a second bias circuit, and a current limiting circuit were known (for example, see Patent Document 1).

[0003] The first amplifying transistor is a pre-stage (driver stage) amplifying transistor having a base terminal, a collector terminal, and an emitter terminal. It amplifies a high-frequency signal input from the base terminal and outputs the amplified high-frequency signal from the collector terminal. The second amplifying transistor is a post-stage (power stage) amplifying transistor having a base terminal, a collector terminal, and an emitter terminal. It amplifies a high-frequency signal input from the base terminal and outputs the amplified high-frequency signal from the collector terminal. A first variable voltage power supply supplies a first variable voltage to the collector terminal of the first amplifying transistor. A second variable voltage power supply supplies a second variable voltage to the collector terminal of the second amplifying transistor. A first bias circuit outputs a DC bias current to the base terminal of the first amplifying transistor. A second bias circuit outputs a DC bias current to the base terminal of the second amplifying transistor. A current limiting circuit limits the DC bias current from the second bias circuit to the base terminal of the second amplifying transistor.

[0004] In the power amplifier circuit described in Patent Document 1, regarding the static characteristic (DC characteristic) of the collector current of the second variable voltage when the base-emitter voltage of the second amplifying transistor changes, the collector current decreases relative to the decrease of the second variable voltage. This is because, in the power amplifier circuit described in Patent Document 1, the current limiting circuit limits (reduces) the DC bias current output from the second bias circuit relative to the decrease of the second variable voltage. In other words, in the power amplifier circuit described in Patent Document 1, for example, if the second variable voltage is reduced in accordance with the power amplitude of the high-frequency signal by means of envelope tracking (ET), the DC bias current supplied from the second bias circuit to the base terminal of the second amplifying transistor is reduced by the current limiting circuit. Therefore, in the power amplifier circuit described in Patent Document 1, the collector current flowing depending on the DC bias current also decreases correspondingly to the decrease of the second variable voltage.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-176454

[0006] In the power amplifier circuit described in Patent Document 1, for example, there is a case where the power-added efficiency is lower when operating at medium output power (e.g., 16 dBm) compared to the power-added efficiency when operating at high output power (e.g., 22 dBm). Summary of the Invention

[0007] The purpose of this invention is to provide power amplifier circuits, high-frequency circuits, and communication devices that can achieve improved power-added efficiency.

[0008] According to one aspect of the present invention, a power amplifier circuit amplifies high-frequency signals. The power amplifier circuit includes a first transistor, a second transistor, a third transistor, a first bias circuit, a second bias circuit, a third bias circuit, a first current limiting circuit, and a second current limiting circuit. The first transistor has a first base, a first collector, and a first emitter. The second transistor has a second base, a second collector, and a second emitter. In the second transistor, the second base is connected to the first collector. The third transistor has a third base, a third collector, and a third emitter. In the third transistor, the third base is connected to the first collector, and the third collector is connected to the second collector. The first bias circuit includes a fourth transistor connected to the first base. The second bias circuit includes a fifth transistor connected to the second base. The third bias circuit includes a sixth transistor connected to the third base. The fourth transistor has a fourth base, a fourth collector, and a fourth emitter. The fifth transistor has a fifth base, a fifth collector, and a fifth emitter. The sixth transistor described above has a sixth base, a sixth collector, and a sixth emitter. The first current limiting circuit includes a seventh transistor, a first collector resistor, and a first base resistor. The seventh transistor has a seventh base, a seventh collector, and a seventh emitter. In the seventh transistor, the seventh emitter is connected to the fifth emitter. The first collector resistor has one end and another end. In the first collector resistor, one end is connected to the seventh collector, and the other end is connected to the first collector. The first base resistor has one end and another end. In the first base resistor, one end is connected to the seventh base, and the other end is connected to the fifth base. The second current limiting circuit includes an eighth transistor, a second collector resistor, and a second base resistor. The eighth transistor has an eighth base, an eighth collector, and an eighth emitter. In the eighth transistor, the eighth emitter is connected to the sixth emitter. The second collector resistor has one end and another end. In the second collector resistor, one end is connected to the eighth collector, and the other end is connected to the first collector. The second base resistor has one end and another end. In the second base resistor, one end is connected to the eighth base, and the other end is connected to the sixth base. The power amplifier circuit satisfies at least one of a first condition and a second condition. The first condition is that the resistance value of the first base resistor is different from the resistance value of the second base resistor. The second condition is that the resistance value of the first collector resistor is different from the resistance value of the second collector resistor.

[0009] According to one aspect of the present invention, a power amplifier circuit amplifies a high-frequency signal. The power amplifier circuit includes a first transistor, a second transistor, a third transistor, a first bias circuit, a second bias circuit, and a third bias circuit. The first transistor has a first base, a first collector, and a first emitter, amplifies the high-frequency signal input to the first base, and outputs it from the first collector. The second transistor has a second base, a second collector, and a second emitter. In the second transistor, the second base is connected to the first collector. The third transistor has a third base, a third collector, and a third emitter. In the third transistor, the third base is connected to the first collector, and the third collector is connected to the second collector. The first bias circuit supplies a first bias current to the first base of the first transistor. The second bias circuit supplies a second bias current to the second base of the second transistor. The third bias circuit supplies a third bias current to the third base of the third transistor. In the power amplifier circuit described above, the gain dispersion is greater when the first bias current is supplied to the first transistor, the second bias current is not supplied to the second transistor, and the third bias current is supplied to the third transistor than when the first bias current is supplied to the first transistor, the second bias current is supplied to the second transistor, and the third bias current is supplied to the third transistor.

[0010] One aspect of the high-frequency circuit of the present invention includes a power amplifier circuit and a control circuit of any of the above-described embodiments. The control circuit controls the power amplifier circuit.

[0011] A communication device according to one aspect of the present invention includes the aforementioned high-frequency circuit and signal processing circuit. The power amplifier circuit of the aforementioned high-frequency circuit amplifies the high-frequency signal input from the aforementioned signal processing circuit.

[0012] The power amplifier circuit, high-frequency circuit, and communication device of the present invention can achieve improved power-added efficiency. Attached Figure Description

[0013] Figure 1 This is a circuit diagram of the power amplifier circuit in the implementation method.

[0014] Figure 2 This is a circuit diagram of a communication device that includes a high-frequency circuit containing the aforementioned power amplifier circuit.

[0015] Figure 3 This refers to the second power supply voltage-collector current characteristics of the third transistor in the power amplifier circuit described above, where the resistance value of the second base resistor is kept constant and the resistance value of the second collector resistor is changed.

[0016] Figure 4 This refers to the second power supply voltage-collector current characteristics of the third transistor in the power amplifier circuit described above, where the resistance value of the second collector resistor is kept constant while the resistance value of the second base resistor is changed.

[0017] Figure 5 This refers to the second power supply voltage-collector current characteristics of the third transistor when the resistance values ​​of the second base resistor and the second collector resistor are changed in the power amplifier circuit described above.

[0018] Figure 6 A is an illustration of the gain dispersion in the high output power mode of the power amplifier circuit described above. Figure 6 B is an illustration of the gain dispersion in the output power mode of the power amplifier circuit described above.

[0019] Figure 7 This is an illustration of the operation of the power amplifier circuit in its high output power mode.

[0020] Figure 8 A is the operation diagram of the above power amplifier circuit in the output power mode. Figure 8 B is an operational illustration diagram of the power amplifier circuit in the output power mode of the comparative example. Detailed Implementation

[0021] (Implementation Method)

[0022] The following is for reference Figures 1-5 The power amplifier circuit 10 of the embodiment will be described using A of 6, B of 6, A of 7, B of 8, and B of 8.

[0023] (1) Power amplifier circuits, high-frequency circuits, and communication devices

[0024] (1.1) Circuit structure of a high-frequency circuit with a power amplifier circuit

[0025] High-frequency circuit 100 with power amplifier circuit 10 (see reference) Figure 2 For example, it can be used in communication device 300 (see reference). Figure 2 The communication device 300 is, for example, a mobile phone (e.g., a smartphone), but is not limited thereto; it could also be a wearable terminal (e.g., a smartwatch). The high-frequency circuit 100 is, for example, a circuit capable of supporting 4G (fourth-generation mobile communication) and 5G (fifth-generation mobile communication) standards. The 4G standard is, for example, the 3GPP LTE (Long Term Evolution) standard. The 5G standard is, for example, 5G NR (New Radio). The high-frequency circuit can also be a circuit capable of supporting carrier aggregation and dual connectivity.

[0026] The high-frequency circuit 100 is configured, for example, to amplify the transmitted signal input from the signal processing circuit 301 and output it to the antenna 310. The signal processing circuit 301 is not a component of the high-frequency circuit 100, but is a component of the communication device 300 equipped with the high-frequency circuit 100. The high-frequency circuit 100 is controlled, for example, by the signal processing circuit 301 equipped in the communication device 300.

[0027] The high-frequency circuit 100 includes a power amplifier circuit 10, an output matching circuit 101, a first switch 102, a filter 103, a second switch 104, an antenna terminal 105, a signal input terminal 106, a first power supply terminal 111, and a second power supply terminal 112.

[0028] The power amplifier circuit 10 includes a first amplifier 1, a second amplifier 2, and a third amplifier 3. The power amplifier circuit 10 amplifies, for example, an input signal from the signal processing circuit 301 and outputs it. The input signal is a high-frequency signal (transmit signal) within a defined frequency band. Here, the defined frequency band may include, for example, multiple communication frequency bands that are different from each other.

[0029] Output matching circuit 101 is disposed in the signal path between power amplifier circuit 10 and first switch 102. Output matching circuit 101 is a circuit used to achieve impedance matching between power amplifier circuit 10 and filter 103. Output matching circuit 101 is composed of an inductor, for example, but is not limited to this, and may also include multiple inductors and multiple capacitors.

[0030] A first switch 102 is disposed between the output matching circuit 101 and the filter 103. The first switch 102 has a common terminal and multiple selectable terminals. The common terminal of the first switch 102 is connected to the power amplifier circuit 10 via the output matching circuit 101. One of the multiple selectable terminals of the first switch 102 is connected to the filter 103. The first switch 102 is, for example, a switch capable of connecting at least one of the multiple selectable terminals to the common terminal. Here, the first switch 102 is, for example, a switch capable of one-to-one and one-to-many connections. The first switch 102 is a switch capable of switching signal paths for multiple transmitted signals in different communication frequency bands. The first switch 102, for example, conforms to the MIPI (Mobile Industry Processor Interface) standard. The first switch 102, for example, switches the connection state between the common terminal and the multiple selectable terminals according to a control signal input from the signal processing circuit 301. The first switch 102 is, for example, a switch IC (Integrated Circuit).

[0031] Filter 103 uses the transmission band of one of the multiple communication frequency bands (e.g., Band 3) as the passband. Filter 103 is, for example, a single-chip elastic wave filter, which is constructed by using elastic wave resonators to form each of multiple series-arm resonators and multiple parallel-arm resonators. The elastic wave filter is, for example, a surface elastic wave filter utilizing surface waves. In the surface elastic wave filter, each of the multiple series-arm resonators and multiple parallel-arm resonators is, for example, a SAW (Surface Acoustic Wave) resonator.

[0032] A second switch 104 is disposed between the filter 103 and the antenna terminal 105. The second switch 104 is a switch connected to the antenna terminal 105. The second switch 104 has a common terminal and multiple selectable terminals. In the second switch 104, the common terminal is connected to the antenna terminal 105. One of the multiple selectable terminals of the second switch 104 is connected to the filter 103. The second switch 104, for example, conforms to the MIPI standard. The second switch 104, for example, switches the connection state of the common terminal and the multiple selectable terminals according to a control signal input from the signal processing circuit 301. The second switch 104 is, for example, a switch IC.

[0033] Antenna terminal 105 is connected to antenna 310.

[0034] In the high-frequency circuit 100, the high-frequency signal (transmit signal) output from the power amplifier circuit 10 passes through the output matching circuit 101, the first switch 102, the filter 103, the second switch 104, and the antenna terminal 105 and is transmitted from the antenna 310.

[0035] In the high-frequency circuit 100, the first power supply terminal 111 is connected to the first amplifier 1. The second power supply terminal 112 is connected to the second amplifier 2 and the third amplifier 3. An envelope tracking modulator 321 (hereinafter referred to as ET modulator 321) and a constant voltage source 322 are selectively connected to the first power supply terminal 111 and the second power supply terminal 112 via a switch 304. The ET modulator 321, the constant voltage source 322, and the switch 304 are not components of the high-frequency circuit 100, but rather components of a communication device 300 equipped with the high-frequency circuit 100.

[0036] (1.2) Circuit structure of communication device with high frequency circuit

[0037] The communication device 300 includes a high-frequency circuit 100 and a signal processing circuit 301. The communication device 300 also includes an antenna 310. The signal processing circuit 301 includes, for example, an RF signal processing circuit 302 and a baseband signal processing circuit 303. The RF signal processing circuit 302 is, for example, an RFIC (Radio Frequency Integrated Circuit) that performs signal processing on the high-frequency signal (transmit signal) output from the baseband signal processing circuit 303, and outputs the processed high-frequency signal. The baseband signal processing circuit 303 is, for example, a BBIC (Baseband Integrated Circuit). The baseband signal processing circuit 303 generates I-phase and Q-phase signals based on the baseband signal. The baseband signal can be, for example, an externally input audio signal or image signal. The baseband signal processing circuit 303 performs IQ modulation processing by synthesizing the I-phase and Q-phase signals and outputs the transmit signal. At this time, the transmitted signal is generated as a modulated signal (IQ signal) after the amplitude of the carrier signal of the specified frequency is modulated with a period longer than the period of the carrier signal. The high-frequency circuit 100 transmits the high-frequency signal (transmitted signal) between the antenna 310 and the RF signal processing circuit 302 of the signal processing circuit 301.

[0038] In addition, the communication device 300 also includes the aforementioned ET modulator 321, constant voltage source 322, and switch 304.

[0039] The ET modulator 321 detects the envelope of the signal output from the baseband signal processing circuit 303. That is, the ET modulator 321 detects the waveform (envelope signal) of the amplitude modulation of the carrier signal that constitutes the transmitted signal. Specifically, the ET modulator 321 detects the envelope signal based on the I-phase signal and the Q-phase signal.

[0040] The ET modulator 321 uses the waveform of the envelope signal and a preset amplification rate to determine the power supply voltage (a first power supply voltage and a second power supply voltage). The period of the power supply voltage is the same as the period of the envelope signal. The amplitude variation of the power supply voltage is the same as the amplitude variation of the envelope signal. That is, the amplitude characteristics (period and amplitude variation) of the envelope signal and the power supply voltage are the same. The ET modulator 321 outputs the power supply voltage to the first power supply terminal 111 and the second power supply terminal 112.

[0041] The switch 304 has a common terminal 340 connected to both the first power supply terminal 111 and the second power supply terminal 112, a first selection terminal 341 connected to the ET modulator 321, and a second selection terminal 342 connected to the constant voltage source 322. The switch 304 is controlled, for example, by a signal processing circuit 301, to selectively connect either the first selection terminal 341 or the second selection terminal 342 to the common terminal 340.

[0042] When the communication device 300 operates the power amplifier circuit 10 in ET (Envelope Tracking) mode, the ET modulator 321 supplies a power supply voltage to the first power supply terminal 111 and the second power supply terminal 112, which is amplitude modulated according to the amplitude level of the high-frequency signal (transmit signal) input from the signal processing circuit 301 to the power amplifier circuit 10. When the communication device 300 does not operate the power amplifier circuit 10 in ET mode, it supplies a constant power supply voltage output from the constant voltage source 322 to the first power supply terminal 111 and the second power supply terminal 112. The power amplifier circuit 10 can operate in a high output power mode (first power mode), a medium output power mode (second power mode), and a low output power mode (third power mode). In the high output power mode, the power amplifier circuit 10 outputs a first predetermined power (e.g., 22 dBm). In the medium output power mode, the power amplifier circuit 10 outputs a second predetermined power (e.g., 16 dBm), which is lower than the first predetermined power. In addition, in the low output power mode, the power amplifier circuit 10 makes the output power a third specified power (e.g., 10dBm) that is lower than the second specified power.

[0043] In the power amplifier circuit 10, when operating in high output power mode, an amplitude-modulated power supply voltage is supplied to the first amplifier 1, the second amplifier 2, and the third amplifier 3 from the ET modulator 321. Furthermore, in the power amplifier circuit 10, when operating in medium output power mode, an amplitude-modulated power supply voltage is supplied to the first amplifier 1, the second amplifier 2, and the third amplifier 3 from the ET modulator 321. Additionally, in the power amplifier circuit 10, when operating in low output power mode, a constant power supply voltage is supplied to the first amplifier 1, the second amplifier 2, and the third amplifier 3 from the constant voltage source 322.

[0044] (1.3) Circuit structure of power amplifier circuit

[0045] In the power amplifier circuit 10, such as Figure 1As shown in Figure 2, the first amplifier 1, the second amplifier 2, and the third amplifier 3 respectively include a first transistor Q1, a second transistor Q2, and a third transistor Q3. The first transistor Q1, the second transistor Q2, and the third transistor Q3 are amplifying transistors that amplify the power of high-frequency signals.

[0046] The power amplifier circuit 10 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a first bias circuit 4, a second bias circuit 5, a third bias circuit 6, a first current limiting circuit 7, and a second current limiting circuit 8. The first transistor Q1 has a first base (base terminal), a first collector (collector terminal), and a first emitter (emitter terminal), amplifying the high-frequency signal input to the first base and outputting it from the first collector. The second transistor Q2 has a second base, a second collector, and a second emitter. In the second transistor Q2, the second base is connected to the first collector of the first transistor Q1. The third transistor Q3 has a third base, a third collector, and a third emitter. In the third transistor Q3, the third base is connected to the first collector of the first transistor Q1, and the third collector is connected to the second collector of the second transistor Q2. The first bias circuit 4 supplies a first bias current I1 to the first base of the first transistor Q1. The second bias circuit 5 supplies a second bias current I2 to the second base of the second transistor Q2. The third bias circuit 6 supplies a third bias current I3 to the third base of the third transistor Q3. The first current limiting circuit 7 limits the second bias current I2 based on the power supply voltage Vcc2 supplied to the second collector of the second transistor Q2. The second current limiting circuit 8 limits the third bias current I3 based on the power supply voltage Vcc2. Additionally, the power amplifier circuit 10 also includes a bypass circuit 170. The bypass circuit 170 includes a series circuit of a bypass switch SW1 and a capacitor 171, connected between the first base and the first collector of the first transistor Q1. Furthermore, in this specification, the base, emitter, and collector of the transistor are the base terminal, emitter terminal, and collector terminal, respectively.

[0047] The first transistor Q1, the second transistor Q2, and the third transistor Q3 are all bipolar transistors used for amplification. Here, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all npn-type bipolar transistors.

[0048] The first emitter of the first transistor Q1, the second emitter of the second transistor Q2, and the third emitter of the third transistor Q3 are connected to ground. In other words, the first emitter of the first transistor Q1, the second emitter of the second transistor Q2, and the third emitter of the third transistor Q3 are grounded. The first collector of the first transistor Q1 is connected to the first power supply terminal 111 of the high-frequency circuit 100 and is supplied with a power supply voltage Vcc1. The second collector of the second transistor Q2 and the third collector of the third transistor Q3 are connected to the second power supply terminal 112 of the high-frequency circuit 100 and are supplied with a power supply voltage Vcc2. The power supply voltages Vcc1 and Vcc2 change synchronously. In other words, when the power supply voltage Vcc1 increases, the power supply voltage Vcc2 also increases, and when the power supply voltage Vcc1 decreases, the power supply voltage Vcc2 also decreases. The power amplifier circuit 10 also includes an input terminal 11 and an output terminal 12 (see reference 12). Figure 2 In the power amplifier circuit 10, the first base of the first transistor Q1 is connected to the input terminal 11. Additionally, in the power amplifier circuit 10, the second collector of the second transistor Q2 and the third collector of the third transistor Q3 are connected to the output terminal 12. The third transistor Q3 is connected in parallel with the second transistor Q2. The first transistor Q1 is a driver stage transistor that amplifies the high-frequency signal input from the first base and outputs the amplified high-frequency signal from the first collector. The second transistor Q2 is an output stage transistor that amplifies the high-frequency signal input from the second base and outputs the amplified high-frequency signal from the second collector. The third transistor Q3 is an output stage transistor that amplifies the high-frequency signal input from the third base and outputs the amplified high-frequency signal from the third collector.

[0049] The power amplifier circuit 10 also includes a first capacitor 161, a second capacitor 162, and a third capacitor 163. The first capacitor 161, the second capacitor 162, and the third capacitor 163 are DC cutoff capacitors used to remove the DC component of high-frequency signals. The first capacitor 161 is located at the input terminal 11 (see reference 163). Figure 2 A first capacitor 162 is disposed between the first collector of the first transistor Q1 and the second base of the second transistor Q2. A second capacitor 163 is disposed between the first collector of the first transistor Q1 and the third base of the third transistor Q3. Figure 2As shown, the power amplifier circuit 10 also includes a first matching circuit 130, a second matching circuit 140, and a third matching circuit 150. The first matching circuit 130 is disposed between the input terminal 11 and the first amplifier 1. The second matching circuit 140 is disposed between the first amplifier 1 and the second amplifier 2. The third matching circuit 150 is disposed between the first amplifier 1 and the third amplifier 3. The first matching circuit 130 is used to achieve impedance matching between the first amplifier 1 and the signal processing circuit 301. The second matching circuit 140 is used to achieve impedance matching between the first amplifier 1 and the second amplifier 2 (interstage matching circuit). The third matching circuit 150 is used to achieve impedance matching between the first amplifier 1 and the third amplifier 3 (interstage matching circuit).

[0050] The first bias circuit 4 has a fourth transistor 40. The fourth transistor 40 has a fourth base, a fourth collector, and a fourth emitter. The fourth emitter of the fourth transistor 40 is connected to the first base of the first transistor Q1. More specifically, the fourth emitter of the fourth transistor 40 is connected to the first base of the first transistor Q1 via a first resistor 151. The fourth transistor 40 is an npn-type bipolar transistor. A first bias current I1 output from the first bias circuit 4 is supplied to the first base of the first transistor Q1 via the first resistor 151. The first bias current I1 is a DC current that determines the operating point of the first transistor Q1. In the first bias circuit 4, the fourth transistor 40 is used as an emitter follower transistor. The fourth transistor 40 is a current amplification transistor.

[0051] In addition to the fourth transistor 40 mentioned above, the first bias circuit 4 also includes two diodes 41 and 42, a capacitor 43, and a resistor 44. The two diodes 41 and 42 are formed by connecting the base and collector of the npn transistor, respectively.

[0052] In the first bias circuit 4, two diodes 41 and 42 are connected in series between the fourth base of the fourth transistor 40 and ground. Additionally, in the first bias circuit 4, the first constant current source 14 included in the control circuit 110 of the high-frequency circuit 100 is connected to the fourth base of the fourth transistor 40 via a resistor 44. Furthermore, in the first bias circuit 4, a capacitor 43 is connected between the fourth base of the fourth transistor 40 and ground.

[0053] In the first bias circuit 4, the constant current output from the first constant current source 14 is input to the fourth base of the fourth transistor 40, amplified into a first bias current I1, and output from the fourth emitter of the fourth transistor 40. The first bias current I1 output from the fourth emitter of the fourth transistor 40 is supplied to the first base of the first transistor Q1 via the first resistor 151.

[0054] The second bias circuit 5 includes a fifth transistor 50. The fifth transistor 50 has a fifth base, a fifth collector, and a fifth emitter. In the fifth transistor 50, the fifth emitter is connected to the second base of the second transistor Q2. More specifically, in the fifth transistor 50, the fifth emitter is connected to the second base of the second transistor Q2 via a second resistor 152. The fifth transistor 50 is an npn-type bipolar transistor. A second bias current I2 output from the second bias circuit 5 is supplied to the second base of the second transistor Q2 via the second resistor 152. The second bias current I2 is a DC current that determines the operating point of the second transistor Q2. In the second bias circuit 5, the fifth transistor 50 is used as an emitter follower transistor. The fifth transistor 50 is a current amplification transistor.

[0055] In addition to the fifth transistor 50 mentioned above, the second bias circuit 5 also includes two diodes 51 and 52, a capacitor 53, and a resistor 54. The two diodes 51 and 52 are formed by connecting the base and collector of the npn transistor, respectively.

[0056] In the second bias circuit 5, two diodes 51 and 52 are connected in series between the fifth base of the fifth transistor 50 and ground. Additionally, in the second bias circuit 5, the second constant current source 15 included in the control circuit 110 is connected to the fifth base of the fifth transistor 50 via a resistor 54. Furthermore, in the second bias circuit 5, a capacitor 53 is connected between the fifth base of the fifth transistor 50 and ground.

[0057] In the second bias circuit 5, the constant current output from the second constant current source 15 is input to the fifth base of the fifth transistor 50, amplified into a second bias current I2, and output from the fifth emitter of the fifth transistor 50. The second bias current I2 output from the fifth emitter of the fifth transistor 50 is supplied to the second base of the second transistor Q2 via the second resistor 152.

[0058] The third bias circuit 6 includes a sixth transistor 60. The sixth transistor 60 has a sixth base, a sixth collector, and a sixth emitter. The sixth emitter of the sixth transistor 60 is connected to the third base of the third transistor Q3. More specifically, the sixth emitter of the sixth transistor 60 is connected to the third base of the third transistor Q3 via a third resistor 153. The sixth transistor 60 is an npn-type bipolar transistor. The third bias current I3 output from the third bias circuit 6 is supplied to the third base of the third transistor Q3 via the third resistor 153. The third bias current I3 is the DC current that determines the operating point of the third transistor Q3. In the third bias circuit 6, the sixth transistor 60 is used as an emitter follower transistor. The sixth transistor 60 is a current amplification transistor.

[0059] In addition to the sixth transistor 60 mentioned above, the third bias circuit 6 also includes two diodes 61 and 62, a capacitor 63, and a resistor 64. The two diodes 61 and 62 are formed by connecting the base and collector of the npn transistor, respectively.

[0060] In the third bias circuit 6, two diodes 61 and 62 are connected in series between the sixth base of the sixth transistor 60 and ground. Additionally, in the third bias circuit 6, the third constant current source 16 included in the control circuit 110 is connected to the sixth base of the sixth transistor 60 via a resistor 64. Furthermore, in the third bias circuit 6, a capacitor 63 is connected between the sixth base of the sixth transistor 60 and ground.

[0061] In the third bias circuit 6, the constant current output from the third constant current source 16 is input to the sixth base of the sixth transistor 60, amplified into a third bias current I3, and output from the sixth emitter of the sixth transistor 60. The third bias current I3 output from the sixth emitter of the sixth transistor 60 is supplied to the third base of the third transistor Q3 via the third resistor 153.

[0062] The first current limiting circuit 7 is a circuit that limits the second bias current I2 output from the second bias circuit 5. More specifically, the first current limiting circuit 7 includes a seventh transistor 70, a first collector resistor Rc1, and a first base resistor Rb1. The seventh transistor 70 has a seventh base, a seventh collector, and a seventh emitter. In the seventh transistor 70, the seventh emitter is connected to the fifth emitter of the fifth transistor 50. In the first collector resistor Rc1, one end is connected to the seventh collector of the seventh transistor 70, and the other end is connected to the first collector of the first transistor Q1. Therefore, the other end of the first collector resistor Rc1 is connected to the first power supply terminal 111 (refer to the first power supply terminal 111 supplied with power supply voltage Vcc1) of the first power supply. Figure 2 The first base resistor Rb1 has one end and the other end. One end of the first base resistor Rb1 is connected to the seventh base of the seventh transistor 70, and the other end is connected to the fifth base of the fifth transistor 50. The seventh transistor 70 is a current-limiting transistor.

[0063] The first current limiting circuit 7 limits the current by comparing the power supply voltage Vcc1 (which is equal to the power supply voltage Vcc2) with the reference voltage (V). BE When the base-emitter voltage is small, the greater the potential difference between the power supply voltage Vcc1 (equal to the power supply voltage Vcc2) and the reference voltage, the greater the DC current flowing from the fifth base of the fifth transistor 50 of the second bias circuit 5 through the seventh base of the seventh transistor 70 to the seventh collector of the seventh transistor 70, which is also the DC limiting current.

[0064] The second current limiting circuit 8 is a circuit that limits the third bias current I3 output from the third bias circuit 6. More specifically, the second current limiting circuit 8 includes an eighth transistor 80, a second collector resistor Rc2, and a second base resistor Rb2. The eighth transistor 80 has an eighth base, an eighth collector, and an eighth emitter. In the eighth transistor 80, the eighth emitter is connected to the sixth emitter of the sixth transistor 60. The second collector resistor Rc2 has one end and another end. In the second collector resistor Rc2, one end is connected to the eighth collector of the eighth transistor 80, and the other end is connected to the first collector of the first transistor Q1. Therefore, the other end of the second collector resistor Rc2 is connected to the first power supply terminal 111 (refer to the first power supply terminal 111 supplied with power supply voltage Vcc1) of the first power supply. Figure 2 The second base resistor Rb2 has one end and the other end. One end of the second base resistor Rb2 is connected to the eighth base of the eighth transistor 80, and the other end is connected to the sixth base of the sixth transistor 60. The eighth transistor 80 is a current-limiting transistor.

[0065] The bypass circuit 170 includes a series circuit of bypass switch SW1 and capacitor 171. The bypass circuit 170 is connected between the first base and the first collector of the first transistor Q1.

[0066] The power amplifier circuit 10 is, for example, included in a single-chip IC chip. The IC chip including the power amplifier circuit 10 is, for example, a GaAs-based IC chip. In this case, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are, for example, HBTs (Heterojunction Bipolar Transistors).

[0067] The IC chip containing the power amplifier circuit 10 is not limited to GaAs-based IC chips. For example, it can also be a Si-based IC chip with the power amplifier circuit 10, or a SiGe-based IC chip with the power amplifier circuit 10.

[0068] The power amplifier circuit 10 is controlled, for example, by the control circuit 110 included in the high-frequency circuit 100. The control circuit 110 is, for example, a control IC (Integrated Circuit) that controls the power amplifier circuit 10. The control circuit 110 controls the first bias circuit 4, the second bias circuit 5, and the third bias circuit 6. As described above, the control circuit 110 is not a component of the power amplifier circuit 10, but rather a component of the high-frequency circuit 100. The control circuit 110 includes the first constant current source 14, the second constant current source 15, and the third constant current source 16 described above.

[0069] The control circuit 110 is, for example, contained in a single-chip IC that is different from the power amplifier circuit 10. The IC chip containing the control circuit 110 is, for example, a Si-based IC chip.

[0070] Control circuit 110 is connected to signal processing circuit 301, for example. Control circuit 110 controls power amplifier circuit 10 based on control signals obtained from signal processing circuit 301. Control circuit 110 conforms to MIPI standard, for example. Control circuit 110 controls power amplifier circuit 10 according to control signals from RF signal processing circuit 302 from signal processing circuit 301.

[0071] (2) Operation of the power amplifier circuit

[0072] The power amplifier circuit 10 amplifies, for example, the high-frequency signal (transmit signal) from the signal processing circuit 301 and outputs it. Here, the power amplifier circuit 10 amplifies the high-frequency signal input from the input terminal 11 and outputs the amplified high-frequency signal from the output terminal 12.

[0073] The power amplifier circuit 10 can operate in high output power mode, medium output power mode, and low output power mode. The power amplifier circuit 10 is controlled by the control circuit 110.

[0074] When the power amplifier circuit 10 operates in high output power mode, the control circuit 110 controls both the second bias circuit 5 and the third bias circuit 6 in addition to the first bias circuit 4. In other words, when the power amplifier circuit 10 operates in high output power mode, the control circuit 110 controls the first bias circuit 4, the second bias circuit 5, and the third bias circuit 6 to amplify and output the high-frequency signals input to each of the first transistor Q1, the second transistor Q2, and the third transistor Q3.

[0075] When the power amplifier circuit 10 operates in the medium output power mode, the control circuit 110 controls only the third bias circuit 6 of the second bias circuit 5 and the third bias circuit 6, in addition to the first bias circuit 4. In other words, when the control circuit 110 operates the power amplifier circuit 10 in the medium output power mode, it controls the first bias circuit 4 and the third bias circuit 6 to amplify the high-frequency signals input to each of the first transistors Q1 and the third transistor Q3 and output them.

[0076] When the power amplifier circuit 10 operates in low output power mode, the control circuit 110 only controls the third bias circuit 6 among the first bias circuit 4, the second bias circuit 5, and the third bias circuit 6. In other words, when the power amplifier circuit 10 operates in low output power mode, the control circuit 110 controls the third bias circuit 6 to amplify the high-frequency signal input to the third transistor Q3 and output it. When the power amplifier circuit 10 operates in low output power mode, the control circuit 110 controls the bypass switch SW1 of the bypass circuit 170 to be in the on state.

[0077] The power amplifier circuit 10 includes a first current limiting circuit 7. Therefore, the static characteristic of the second transistor Q2 in the power amplifier circuit 10 has a slope. Here, in the static characteristic of the second transistor Q2, the collector current flowing through the second transistor Q2 decreases as the power supply voltage Vcc2 decreases. This is because, in the power amplifier circuit 10, the first current limiting circuit 7 limits (reduces) the second bias current I2 output from the second bias circuit 5 in accordance with the decrease in the power supply voltage Vcc2. In other words, in the communication device 300 including the power amplifier circuit 10, for example, if the power supply voltage Vcc2 is reduced in accordance with the power amplitude of the high-frequency signal by the ET modulator 321, the second bias current I2 supplied from the second bias circuit 5 to the second base of the second transistor Q2 is limited and reduced by the first current limiting circuit 7. Therefore, in the second transistor Q2, the collector current flowing depending on the second bias current I2 decreases in accordance with the decrease in the power supply voltage Vcc2. The slope of the static characteristic of the second transistor Q2 can be changed by altering at least one of the resistance values ​​of the first collector resistor Rc1 and the first base resistor Rb1.

[0078] In the power amplifier circuit 10, the static characteristic of the third transistor Q3 has a slope due to the presence of the second current limiting circuit 8. Here, in the static characteristic of the third transistor Q3, the collector current flowing through the third transistor Q3 decreases as the power supply voltage Vcc2 decreases. This is because, in the power amplifier circuit 10, the second current limiting circuit 8 limits (reduces) the third bias current I3 output from the third bias circuit 6 in accordance with the decrease in the power supply voltage Vcc2. In other words, in the communication device 300 equipped with the power amplifier circuit 10, for example, if the power supply voltage Vcc2 is reduced in accordance with the power amplitude of the high-frequency signal by the ET modulator 321, the third bias current I3 supplied from the third bias circuit 6 to the third base of the third transistor Q3 is reduced by the second current limiting circuit 8. Therefore, in the third transistor Q3, the collector current flowing through it, dependent on the third bias current I3, decreases in accordance with the decrease in the power supply voltage Vcc2. The slope of the static characteristic of the third transistor Q3 can be changed by altering at least one of the resistance values ​​of the second collector resistor Rc2 and the second base resistor Rb2.

[0079] In the power amplifier circuit 10, for example, by satisfying a first condition and a second condition, the slope of the static characteristic of the second transistor Q2 is made different from the slope of the static characteristic of the third transistor Q3. The first condition is that the resistance value of the first base resistor Rb1 is different from the resistance value of the second base resistor Rb2. The second condition is that the resistance value of the first collector resistor Rc1 is different from the resistance value of the second collector resistor Rc2. In the power amplifier circuit 10, by making at least one of the first and second conditions different, the slope of the static characteristic of the second transistor Q2 is made different from the slope of the static characteristic of the third transistor Q3. The power amplifier circuit 10 is configured to make the slope of the static characteristic of the third transistor Q3 larger than the slope of the static characteristic of the second transistor Q2 by satisfying at least one of the first and second conditions.

[0080] Figure 3 The static characteristics of the third transistor Q3 are shown when the resistance of the second base resistor Rb2 is 100Ω and the resistance of the second collector resistor Rc2 is 3kΩ, 5kΩ and 7kΩ respectively. Figure 3 The horizontal axis represents the power supply voltage Vcc2 supplied to the third collector of the third transistor Q3. Figure 3 The vertical axis represents the collector current Iq flowing through the third collector of the third transistor Q3. Figure 3 In the diagram, solid lines are used to show the static characteristics when the resistance of the second collector resistor Rc2 is 3kΩ and the resistance of the second base resistor Rb2 is 100Ω. Additionally, in... Figure 3In the diagram, dashed lines show the static characteristics when the resistance of the second collector resistor Rc2 is 5kΩ and the resistance of the second base resistor Rb2 is 100Ω. Additionally, in... Figure 3 In the diagram, the static characteristics are shown with a dashed line, where the resistance of the second collector resistor Rc2 is 7kΩ and the resistance of the second base resistor Rb2 is 100Ω. According to... Figure 3 It can be seen that if the resistance value of the second base resistor Rb2 is the same, then if the resistance value of the second collector resistor Rc2 is decreased, the slope of the static characteristic of the third transistor Q3 tends to increase. This trend is also the same in the static characteristic of the second transistor Q2.

[0081] Figure 4 The static characteristics of the third transistor Q3 are shown when the resistance of the second collector resistor Rc2 is 5kΩ and the resistance of the second base resistor Rb2 is 50Ω, 100Ω and 200Ω respectively. Figure 4 The horizontal axis represents the power supply voltage Vcc2 supplied to the third collector of the third transistor Q3. Figure 4 The vertical axis represents the collector current Iq flowing through the third collector of the third transistor Q3. Figure 4 In the diagram, solid lines are used to show the static characteristics when the resistance of the second collector resistor Rc2 is 5kΩ and the resistance of the second base resistor Rb2 is 50Ω. Additionally, in... Figure 4 In the diagram, dashed lines show the static characteristics when the resistance of the second collector resistor Rc2 is 5kΩ and the resistance of the second base resistor Rb2 is 100Ω. Additionally, in... Figure 4 In the diagram, the static characteristics are shown with dashed lines when the resistance of the second collector resistor Rc2 is 5kΩ and the resistance of the second base resistor Rb2 is 200Ω. According to... Figure 4 It can be seen that if the resistance value of the second collector resistor Rc2 is the same, then the slope of the static characteristic of the third transistor Q3 increases if the resistance value of the second base resistor Rb2 is decreased. This trend is also the same in the static characteristic of the second transistor Q2.

[0082] exist Figure 5 In the diagram, the static characteristics of the third transistor Q3 are shown in solid lines when the resistance of the second collector resistor Rc2 is 3kΩ and the resistance of the second base resistor Rb2 is 50Ω. Additionally, in... Figure 5 In the diagram, the static characteristics of the third transistor Q3 are shown by dashed lines when the resistance of the second collector resistor Rc2 is 5kΩ and the resistance of the second base resistor Rb2 is 100Ω. Additionally, in... Figure 5 In the figure, the static characteristics are shown with a dashed line, where the resistance of the second collector resistor Rc2 is 7kΩ and the resistance of the second base resistor Rb2 is 200Ω. Figure 5The horizontal axis represents the power supply voltage Vcc2 supplied to the third collector of the third transistor Q3. Figure 5 The vertical axis represents the collector current Iq flowing through the third collector of the third transistor Q3. According to... Figures 3-5 It can be seen that, for the slope of the static characteristic of the third transistor Q3, the influence of the resistance value of the second collector resistor Rc2 is greater than the influence of the resistance value of the second base resistor Rb2. This trend is also the same in the static characteristic of the second transistor Q2.

[0083] In the power amplifier circuit 10, as described above, the slope of the static characteristic of the third transistor Q3 is greater than the slope of the static characteristic of the second transistor Q2. Therefore, in the power amplifier circuit 10, when a first bias current I1 is supplied to the first transistor Q1, a second bias current I2 is not supplied to the second transistor Q2, and a third bias current I3 is supplied to the third transistor Q3, the gain dispersion ΔGain (refer to...) Figure 6 B) is the gain dispersion ΔGain when the first bias current I1, the second bias current I2, and the third bias current I3 are supplied to the first transistor Q1, the second transistor Q2, and the third transistor Q3, respectively (refer to B). Figure 6 A) is large. In each Figure 6 A and Figure 6 In diagram B, the horizontal axis represents the output power Pout of the power amplifier circuit 10, and the vertical axis represents the gain of the power amplifier circuit 10. Additionally, in each... Figure 6 A and Figure 6 In section B, the gain-output power characteristics are illustrated for Vcc = 1.2V and Vcc = 3.4V. Furthermore, Figure 1 In this context, "Pin" refers to the input power of the high-frequency signal input to the power amplifier circuit 10.

[0084] In the power amplifier circuit 10, in the high output power mode, the second transistor Q2 and the third transistor Q3 respectively amplify the high-frequency signal that has been amplified by the first transistor Q1. In the medium output power mode, only the third transistor Q3 of the second transistor Q2 and the third transistor Q3 amplifies the high-frequency signal that has been amplified by the first transistor Q1. Therefore, the power amplifier circuit 10 can make the gain dispersion ΔGain different in the high output power mode and the medium output power mode. In other words, the medium output power amplifier circuit 10 can increase the gain dispersion ΔGain in the medium output power mode compared to the gain dispersion ΔGain in the high output power mode.

[0085] Figure 7 This is a diagram illustrating the operation of the power amplifier circuit 10 in its high output power mode. Additionally, Figure 8 A is an operational diagram illustrating the operation of the power amplifier circuit 10 in the output power mode. Figure 8 Figure B is an operational illustration of the comparative example power amplifier circuit in the output power mode. The comparative example power amplifier circuit is identical to that in Patent Document 1, using only two transistors—a first amplifying transistor and a second amplifying transistor—to amplify high-frequency signals. In each... Figure 7 , 8 In A and 8B, "Pout" represents the voltage component of the output power Pout, and "E1" represents the envelope signal detected in the ET modulator 321. Therefore, in Figure 7 , 8 In A and 8B, the smaller the difference between Pout and E1 (the area of ​​the part with the added dotted shadow), the higher the power-added efficiency; the larger the difference between Pout and E1, the lower the power-added efficiency.

[0086] Furthermore, the ET modulator 321 includes, for example, a DC-DC converter that generates a signal power supply voltage Vcc2 based on the envelope. In the ET modulator 321 that includes a DC-DC converter, considering the effects of noise generated by the DC-DC converter, the minimum voltage of the power supply voltage Vcc2 is set to, for example, 1.2V, so that the power supply voltage Vcc2 does not become 0V when performing ET operation. The maximum voltage of the power supply voltage Vcc2 is set to, for example, 3.5V.

[0087] In the power amplifier circuit 10, at a specified high-frequency output power, the more the power supply voltage Vcc2 (and power supply voltage Vcc1) is reduced, the higher the power-added efficiency becomes. Here, in the communication device 300 including the power amplifier circuit 10 and the ET modulator 321, the voltage component of the output power Pout of the high-frequency signal output from the power amplifier circuit 10 is expressed as a linear function of the power supply voltage Vcc2. However, in the power amplifier circuit of the comparative example, if the power supply voltage (equivalent to the power supply voltage Vcc2) supplied to the collector of the second amplifying transistor is set to 1.2V, and it is designed to obtain the same power-added efficiency as the power amplifier circuit 10 of the embodiment in the high output power mode, then when it is operated in the medium output power mode, as... Figure 8 As shown in B, the following performance of Pout relative to E1 decreases (the difference between Pout and E1 increases), while the power-added efficiency decreases. Conversely, in the power amplifier circuit 10 of the embodiment, when operating in a medium output power mode, the gain dispersion ΔGain can be increased compared to when operating in a high output power mode, so as... Figure 8 As shown in A, the following performance of Pout relative to E1 is improved (the difference between Pout and E1 decreases), while the power-added efficiency is improved.

[0088] When the power amplifier circuit 10 operates, for example, in a low output power mode, in the communication device 300, power supply voltages Vcc1 and Vcc2 are supplied from the constant voltage source 322 via switch 304 to the first power supply terminal 111 and the second power supply terminal 112, respectively, instead of from the ET modulator 321. Furthermore, in the low output power mode, the bypass switch SW1 is activated via the control circuit 110. In the low output power mode, the power amplifier circuit 10 amplifies high-frequency signals using only the third transistor Q3 of the first transistor Q1, the second transistor Q2, and the third transistor Q3.

[0089] (3) Summary

[0090] (3.1) Power amplifier circuit

[0091] The power amplifier circuit 10 of the embodiment includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a first bias circuit 4, a second bias circuit 5, a third bias circuit 6, a first current limiting circuit 7, and a second current limiting circuit 8. The first transistor Q1 has a first base, a first collector, and a first emitter. The second transistor Q2 has a second base, a second collector, and a second emitter. In the second transistor Q2, the second base is connected to the first collector of the first transistor Q1. The third transistor Q3 has a third base, a third collector, and a third emitter. In the third transistor Q3, the third base is connected to the first collector of the first transistor Q1, and the third collector is connected to the second collector of the second transistor Q2. The first bias circuit 4 includes a fourth transistor 40 connected to the first base. The second bias circuit 5 includes a fifth transistor 50 connected to the second base. The third bias circuit 6 includes a sixth transistor 60 connected to the third base. The fourth transistor 40 has a fourth base, a fourth collector, and a fourth emitter. The fifth transistor 50 has a fifth base, a fifth collector, and a fifth emitter. The sixth transistor 60 has a sixth base, a sixth collector, and a sixth emitter. The first current limiting circuit 7 includes a seventh transistor 70, a first collector resistor Rc1, and a first base resistor Rb1. The seventh transistor 70 has a seventh base, a seventh collector, and a seventh emitter. In the seventh transistor 70, the seventh emitter is connected to the fifth emitter of the fifth transistor 50. The first collector resistor Rc1 has one end and another end. In the first collector resistor Rc1, one end is connected to the seventh collector of the seventh transistor 70, and the other end is connected to the first collector of the first transistor Q1. The first base resistor Rb1 has one end and another end. In the first base resistor Rb1, one end is connected to the seventh base of the seventh transistor 70, and the other end is connected to the fifth base of the fifth transistor 50. The second current limiting circuit 8 includes an eighth transistor 80, a second collector resistor Rc2, and a second base resistor Rb2. The eighth transistor 80 has an eighth base, an eighth collector, and an eighth emitter. In the eighth transistor 80, the eighth emitter is connected to the sixth emitter of the sixth transistor 60. The second collector resistor Rc2 has one end and another end. One end of the second collector resistor Rc2 is connected to the eighth collector of the eighth transistor 80, and the other end is connected to the first collector of the first transistor Q1. The second base resistor Rb2 has one end and another end. One end of the second base resistor Rb2 is connected to the eighth base of the eighth transistor 80, and the other end is connected to the sixth base of the sixth transistor 60. The power amplifier circuit 10 satisfies at least one of a first condition and a second condition. The first condition is that the resistance value of the first base resistor Rb1 is different from the resistance value of the second base resistor Rb2. The second condition is that the resistance value of the first collector resistor Rc1 is different from the resistance value of the second collector resistor Rc2.

[0092] The power amplifier circuit 10 of the embodiment can improve power-added efficiency. Furthermore, the power amplifier circuit 10 of the embodiment can improve linearity. Here, the power amplifier circuit 10 of the embodiment can improve both power-added efficiency and linearity when operating in a medium-power output mode.

[0093] (3.2) High-frequency circuits

[0094] The high-frequency circuit 100 of the embodiment includes a power amplifier circuit 10 and a control circuit 110. The control circuit 110 controls the power amplifier circuit 10. Therefore, the high-frequency circuit 100 of the embodiment can improve the power-added efficiency of the power amplifier circuit 10. The high-frequency circuit 100 of the embodiment can also achieve a linear improvement in the power amplifier circuit 10.

[0095] (3.3) Communication device

[0096] The communication device 300 of the embodiment includes a high-frequency circuit 100 and a signal processing circuit 301. The power amplifier circuit 10 of the high-frequency circuit 100 amplifies the high-frequency signal input from the signal processing circuit 301. Therefore, the communication device 300 of the embodiment can improve the power-added efficiency of the power amplifier circuit 10. Furthermore, the communication device 300 of the embodiment can improve the linearity of the power amplifier circuit 10.

[0097] (Modified example)

[0098] The above-described embodiments are merely one of the various embodiments of the present invention. Various modifications can be made to the above-described embodiments based on design and other factors, as long as the objectives of the present invention are achieved.

[0099] For example, in the power amplifier circuit 10, if the gain dispersion ΔGain is greater when the first bias current I1 is supplied to the first transistor Q1, the second bias current I2 is not supplied to the second transistor Q2, and the third bias current I3 is supplied to the third transistor Q3 than when the first bias current I1 is supplied to the first transistor Q1, the second bias current I2 is supplied to the second transistor Q2, and the third bias current I3 is supplied to the third transistor Q3 (the third condition), then the first current limiting circuit 7 and the second current limiting circuit 8 may not necessarily be present. For example, the third condition can also be satisfied by making the parasitic capacitance between the third base and the third collector of the third transistor Q3 different from the parasitic capacitance between the second base and the second collector of the second transistor Q2. In transistors, there is a tendency for the larger the parasitic capacitance between the base and collector, the greater the slope of the static characteristic. For example, the parasitic capacitance between the third base and the third collector and the parasitic capacitance between the second base and the second collector of the second transistor Q2 can be made different based on the layout (including size and position within the chip) of the third transistor Q3 and the second transistor Q2 in the GaAs IC chip described above.

[0100] For example, in the power amplifier circuit 10, the number of amplifier stages is not limited to two stages, but can also be three or more stages. The power amplifier circuit 10 may also further include an amplifier preceding the first amplifier 1, which includes the first transistor Q1.

[0101] In the high-frequency circuit 100, the filter 103 is an elastic wave filter that utilizes elastic surface waves, but it is not limited to this. For example, it can also be an elastic wave filter that utilizes elastic boundary waves, plate waves, etc.

[0102] In elastic wave filters, the multiple series arm resonators and the multiple parallel arm resonators are not limited to SAW resonators; for example, they can also be BAW (Bulk Acoustic Wave) resonators.

[0103] The high-frequency circuit 100 may also include a receiving circuit that includes a low-noise amplifier that amplifies the received signal input from the antenna terminal 105 and a filter connected to the low-noise amplifier.

[0104] In addition, filter 103 is not limited to a transmitting filter, but can also be a duplexer.

[0105] In addition, in the high-frequency circuit 100, the first switch 102 and the second switch 104 may also be switch ICs corresponding to GPIO (General Purpose Input / Output).

[0106] (Way)

[0107] The following methods are disclosed in this specification.

[0108] The power amplifier circuit (10) of the first type amplifies the power of a high-frequency signal. The power amplifier circuit (10) includes a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), a first bias circuit (4), a second bias circuit (5), a third bias circuit (6), a first current limiting circuit (7), and a second current limiting circuit (8). The first transistor (Q1) has a first base, a first collector, and a first emitter. The second transistor (Q2) has a second base, a second collector, and a second emitter. In the second transistor (Q2), the second base is connected to the first collector of the first transistor (Q1). The third transistor (Q3) has a third base, a third collector, and a third emitter. In the third transistor (Q3), the third base is connected to the first collector of the first transistor (Q1), and the third collector is connected to the second collector of the second transistor (Q2). The first bias circuit (4) includes a fourth transistor (40) connected to the first base. The second bias circuit (5) includes a fifth transistor (50) connected to the second base. The third bias circuit (6) includes a sixth transistor (60) connected to a third base. The fourth transistor (40) has a fourth base, a fourth collector, and a fourth emitter. The fifth transistor (50) has a fifth base, a fifth collector, and a fifth emitter. The sixth transistor (60) has a sixth base, a sixth collector, and a sixth emitter. The first current limiting circuit (7) includes a seventh transistor (70), a first collector resistor (Rc1), and a first base resistor (Rb1). The seventh transistor (70) has a seventh base, a seventh collector, and a seventh emitter. In the seventh transistor (70), the seventh emitter is connected to the fifth emitter. The first collector resistor (Rc1) has one end and another end. In the first collector resistor (Rc1), one end is connected to the seventh collector, and the other end is connected to the first collector. The first base resistor (Rb1) has one end and another end. In the first base resistor (Rb1), one end is connected to the seventh base, and the other end is connected to the fifth base. The second current limiting circuit (8) includes an eighth transistor (80), a second collector resistor (Rc2), and a second base resistor (Rb2). The eighth transistor (80) has an eighth base, an eighth collector, and an eighth emitter. In the eighth transistor (80), the eighth emitter is connected to the sixth emitter. The second collector resistor (Rc2) has one end and another end. In the second collector resistor (Rc2), one end is connected to the eighth collector, and the other end is connected to the first collector. The second base resistor (Rb2) has one end and another end. In the second base resistor (Rb2), one end is connected to the eighth base, and the other end is connected to the sixth base. The power amplifier circuit (10) satisfies at least one of a first condition and a second condition. The first condition is that the resistance value of the first base resistor (Rb1) is different from the resistance value of the second base resistor (Rb2).The second condition is that the resistance value of the first collector resistor (Rc1) is different from the resistance value of the second collector resistor (Rc2).

[0109] The power amplifier circuit (10) of the first method can achieve an improvement in power-added efficiency.

[0110] The second power amplifier circuit (10) is based on the first method. In the first bias circuit (4), the fourth emitter is connected to the first base. In the second bias circuit (5), the fifth emitter is connected to the second base. In the third bias circuit (6), the sixth emitter is connected to the third base.

[0111] The power amplifier circuit (10) of the third mode satisfies both the first and second conditions in the first or second mode.

[0112] The third power amplifier circuit (10) can achieve improved power-added efficiency compared to the case where only the first and second conditions are satisfied.

[0113] The power amplifier circuit (10) of the fourth type, in any one of the first to third types, also includes a bypass circuit (170). The bypass circuit (170) is connected between the first base and the first collector of the first transistor (Q1). The bypass circuit (170) includes a series circuit of a bypass switch (SW1) and a capacitor (171).

[0114] In the power amplifier circuit (10) of the fourth method, high-frequency signals can be amplified without activating the first transistor (Q1).

[0115] The power amplifier circuit (10) of the fifth type amplifies the high-frequency signal. The power amplifier circuit (10) includes a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), a first bias circuit (4), a second bias circuit (5), and a third bias circuit (6). The first transistor (Q1) has a first base, a first collector, and a first emitter, amplifies the high-frequency signal input to the first base, and outputs it from the first collector. The second transistor (Q2) has a second base, a second collector, and a second emitter. In the second transistor (Q2), the second base is connected to the first collector of the first transistor (Q1). The third transistor (Q3) has a third base, a third collector, and a third emitter. In the third transistor (Q3), the third base is connected to the first collector of the first transistor (Q1), and the third collector is connected to the second collector of the second transistor (Q2). The first bias circuit (4) supplies a first bias current (I1) to the first base of the first transistor (Q1). The second bias circuit (5) supplies a second bias current (I2) to the second base of the second transistor (Q2). The third bias circuit (6) supplies a third bias current (I3) to the third base of the third transistor (Q3). In the power amplifier circuit (10), the gain dispersion (ΔGain) is greater when the first bias current (I1) is supplied to the first transistor (Q1), the second bias current (I2) is not supplied to the second transistor (Q2), and the third bias current (I3) is supplied to the third transistor (Q3) than when the first bias current (I1) is supplied to the first transistor (Q1), the second bias current (I2) is supplied to the second transistor (Q2), and the third bias current (I3) is supplied to the third transistor (Q3).

[0116] The fifth power amplifier circuit (10) can improve power-added efficiency.

[0117] The high-frequency circuit (100) of the sixth method includes any one of the power amplifier circuits (10) of the first to fifth methods and a control circuit (110). The control circuit (110) controls the power amplifier circuit (10).

[0118] The sixth type of high-frequency circuit (100) can achieve an improvement in power-added efficiency.

[0119] In the high-frequency circuit (100) of the seventh mode, in the sixth mode, the power amplifier circuit (10) can operate in a high output power mode and a medium output power mode with lower output power compared to the high output power mode. When the power amplifier circuit (10) operates in the high output power mode, the control circuit (110) controls the first bias circuit (4), the second bias circuit (5), and the third bias circuit (6) to activate the first transistor (Q1), the second transistor (Q2), and the third transistor (Q3), respectively. When the power amplifier circuit (10) operates in the medium output power mode, the control circuit (110) controls the first bias circuit (4) and the third bias circuit (6) to activate the first transistor (Q1) and the third transistor (Q3), respectively.

[0120] The communication device (300) of the eighth mode includes a high-frequency circuit (100) of the sixth or seventh mode and a signal processing circuit (301). The power amplifier circuit (10) of the high-frequency circuit (100) amplifies the high-frequency signal input from the signal processing circuit (301).

[0121] The communication device (300) of the eighth mode can achieve an increase in power-added efficiency in the power amplifier circuit (10).

[0122] Explanation of reference numerals in the attached figures

[0123] 1…First amplifier, 2…Second amplifier, 3…Third amplifier, 4…First bias circuit, 40…Fourth transistor, 41…Diode, 42…Diode, 43…Capacitor, 44…Resistor, 5…Second bias circuit, 50…Fifth transistor, 51…Diode, 52…Diode, 53…Capacitor, 54…Resistor, 6…Third bias circuit, 60…Sixth transistor, 61…Diode, 62…Diode, 63…Capacitor, 64…Resistor, 7…First current limiting circuit 70…Seventh transistor, 8…Second current limiting circuit, 80…Eighth transistor, 10…Power amplifier circuit, 14…First constant current source, 15…Second constant current source, 16…Third constant current source, 100…High frequency circuit, 101…Output matching circuit, 102…First switch, 103…Filter, 104…Second switch, 105…Antenna terminal, 111…First power supply terminal, 112…Second power supply terminal, 130…First matching circuit, 140…Second matching circuit, 1 50…Third matching circuit, 151…First resistor, 152…Second resistor, 153…Third resistor, 161…First capacitor, 162…Second capacitor, 163…Third capacitor, 170…Bypass circuit, 171…Capacitor, 300…Communication device, 301…Signal processing circuit, 302…RF signal processing circuit, 303…Baseband signal processing circuit, 304…Switch, 340…Common terminal, 341…First selection terminal, 342…Second selection terminal. 310… Antenna, 321… ET modulator, 322… Constant voltage source, I1… First bias current, I2… Second bias current, I3… Third bias current, Rb1… First base resistor, Rb2… Second base resistor, Rc1… First collector resistor, Rc2… Second collector resistor, Q1… First transistor, Q2… Second transistor, Q3… Third transistor, SW1… Bypass switch, Vcc1… Power supply voltage, Vcc2… Power supply voltage, ΔGain… Gain dispersion.

Claims

1. A power amplifier circuit, which amplifies the power of a high-frequency signal, wherein, have: The first transistor has a first base, a first collector, and a first emitter; The second transistor has a second base, a second collector, and a second emitter, wherein the second base is connected to the first collector. The third transistor has a third base, a third collector and a third emitter, wherein the third base is connected to the first collector and the third collector is connected to the second collector. The first bias circuit includes a fourth transistor connected to the first base; The second bias circuit includes a fifth transistor connected to the second base described above; The third bias circuit includes a sixth transistor connected to the aforementioned third base; First current limiting circuit; as well as Second current limiting circuit, The aforementioned fourth transistor has a fourth base, a fourth collector, and a fourth emitter. The aforementioned fifth transistor has a fifth base, a fifth collector, and a fifth emitter. The aforementioned sixth transistor has a sixth base, a sixth collector, and a sixth emitter. The aforementioned first current limiting circuit includes: The seventh transistor has a seventh base, a seventh collector, and a seventh emitter, wherein the seventh emitter is connected to the fifth emitter. A first collector resistor has one end and another end, wherein the one end of the first collector resistor is connected to the seventh collector, and the other end of the first collector resistor is connected to the first collector; and A first base resistor has one end and another end, the first end of the first base resistor being connected to the seventh base, and the other end of the first base resistor being connected to the fifth base. The aforementioned second current limiting circuit includes: The eighth transistor has an eighth base, an eighth collector, and an eighth emitter, wherein the eighth emitter is connected to the sixth emitter. A second collector resistor has one end and another end, the first end of the second collector resistor being connected to the eighth collector, and the other end of the second collector resistor being connected to the first collector; and The second base resistor has one end and another end, the first end of the second base resistor being connected to the eighth base, and the other end of the second base resistor being connected to the sixth base. The power amplifier circuit described above satisfies at least one of the first and second conditions. The first condition mentioned above is that the resistance value of the first base resistor is different from the resistance value of the second base resistor. The second condition mentioned above is that the resistance value of the first collector resistor is different from the resistance value of the second collector resistor.

2. The power amplifier circuit according to claim 1, wherein, In the first bias circuit described above, the fourth emitter is connected to the first base. In the second bias circuit described above, the fifth emitter is connected to the second base. In the third bias circuit described above, the sixth emitter is connected to the third base.

3. The power amplifier circuit according to claim 1 or 2, wherein, All of the above power amplifier circuits satisfy both the first condition and the second condition.

4. The power amplifier circuit according to claim 1 or 2, wherein, It also includes a bypass circuit connected between the first base and the first collector of the first transistor. The aforementioned bypass circuit includes a bypass switch and a capacitor connected in series.

5. The power amplifier circuit according to claim 3, wherein, It also includes a bypass circuit connected between the first base and the first collector of the first transistor. The aforementioned bypass circuit includes a bypass switch and a capacitor connected in series.

6. A power amplifier circuit, which amplifies the power of a high-frequency signal, wherein, have: The first transistor has a first base, a first collector, and a first emitter, amplifies the high-frequency signal input to the first base, and outputs it from the first collector; The second transistor has a second base, a second collector, and a second emitter, wherein the second base is connected to the first collector. The third transistor has a third base, a third collector and a third emitter, wherein the third base is connected to the first collector and the third collector is connected to the second collector. The first bias circuit supplies a first bias current to the first base of the first transistor. The second bias circuit supplies a second bias current to the second base of the second transistor. as well as The third bias circuit supplies a third bias current to the third base of the third transistor. In the power amplifier circuit described above, the gain dispersion is greater when the first bias current is supplied to the first transistor, the second bias current is not supplied to the second transistor, and the third bias current is supplied to the third transistor than when the first bias current is supplied to the first transistor, the second bias current is supplied to the second transistor, and the third bias current is supplied to the third transistor.

7. A high-frequency circuit, wherein, have: The power amplifier circuit according to any one of claims 1 to 6; and The control circuit controls the aforementioned power amplifier circuit.

8. The high-frequency circuit according to claim 7, wherein, The power amplifier circuit described above can operate in both high output power mode and medium output power mode. The medium output power mode has lower output power compared to the high output power mode. When the power amplifier circuit operates in the high output power mode, the control circuit controls the first bias circuit, the second bias circuit, and the third bias circuit to activate the first transistor, the second transistor, and the third transistor. When the power amplifier circuit operates in the output power mode described above, the control circuit controls the first bias circuit and the third bias circuit to activate the first transistor and the third transistor, respectively.

9. A communication device, wherein, have: The high-frequency circuit as described in claim 7 or 8; and Signal processing circuit, The power amplifier circuit of the aforementioned high-frequency circuit amplifies the high-frequency signal input from the aforementioned signal processing circuit.

Images