A handshake signal failure protection system and method for a car chip

Abstract

A handshake signal failure protection system of a car chip, a master, sends a request signal to a slave, and outputs a timeout interrupt signal if no response signal of the slave is received within a timeout threshold; the slave comprises: a request holding module with enable control, which receives and detects the request signal sent by the master, generates a request holding signal and sends it to a slave handshake module; the slave handshake module is used for receiving the request holding signal and sending a response signal to the master; the request holding module with enable control comprises: a synchronization module, which receives and detects the request signal, and sends a generated synchronization request rising edge signal or a synchronization request falling edge signal to a latch; the latch generates the request holding signal according to the synchronization request rising edge signal or the synchronization request falling edge signal. The application also provides a handshake signal failure protection method of a car chip, which can discover the abnormality of a handshake signal in time and give a prompt.

Description

Technical Field

[0001] This invention relates to the field of automotive-grade chip technology, and in particular to a failure protection system and method for handshake signals in automotive-grade chips. Background Technology

[0002] Automotive-grade chips provide a higher-performance and safer hardware foundation for future smart cars and autonomous driving. High performance is reflected in the ability to integrate more modules from traditional automotive-grade chips and to catch up with consumer processors in image and audio processing capabilities. High reliability is reflected in the ability to operate in a wider range of high and low temperatures and undergo more stringent functional safety design certification processes compared to consumer electronics, and in the longer lifespan required for consumer electronics.

[0003] In existing technologies, the protection against abnormal handshake connections between modules of automotive-grade chips typically employs watchdog timer (WDT) timeout protection. This protection method consumes a lot of resources and has a long waiting time. Furthermore, the loss of request signals due to abnormalities in the request signal sender is not easily detected. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this application is to provide a handshake signal failure protection system and method for automotive-grade chips, which can promptly and effectively detect potential handshake signal loss at both ends of the connection and reduce unnecessary system resource consumption due to handshake failure.

[0005] To achieve the above objectives, the automotive-grade chip handshake signal failure protection system provided in this application includes,

[0006] The master sends a request signal to the slave. If no response signal is received from the slave within the timeout threshold, a timeout interrupt signal is output.

[0007] The slave device includes: a request hold module with enable control, which receives and detects the request signal sent by the host, generates a request hold signal and sends it to the slave handshake module; and a slave handshake module, which receives the request hold signal and sends a response signal to the host.

[0008] The request hold module with enable control includes:

[0009] The synchronization module receives and detects the request signal, and sends the generated synchronization request rising edge signal or synchronization request falling edge signal to the latch;

[0010] The latch generates the request hold signal based on the rising edge signal or the falling edge signal of the synchronization request.

[0011] Furthermore, the host includes a host handshake module and a response monitoring module with enable control, wherein,

[0012] The response monitoring module with enable control enables response monitoring and sets a response timeout threshold; if no response signal is received from the slave device within the timeout threshold, a timeout interrupt signal is output.

[0013] The host handshake module is used to send a request signal to the slave device.

[0014] Furthermore, the response monitoring module with enable control starts timing after being enabled and calculates the timing duration, which is the time from when the host handshake module sends a request signal to when the response monitoring module receives the response signal sent by the slave handshake module; when the timing duration is greater than or equal to the timeout threshold, a timeout interrupt signal is issued.

[0015] Furthermore, the response monitoring module with enable control does not issue a timeout interrupt signal when the timing duration is less than the timeout threshold, and simultaneously resets the timer to zero.

[0016] Furthermore, the request holding module with enable control also includes:

[0017] The XOR gate circuit receives the synchronization shielding signal sent by the synchronization module and the request hold signal sent by the latch, respectively, and sends the generated set signal to the interrupt generation module.

[0018] The interrupt generation module receives the set signal from the XOR gate circuit and generates a hold interrupt signal output.

[0019] To achieve the above objectives, this application also provides a method for protecting automotive-grade chip handshake signal from failure, comprising:

[0020] The host enables response monitoring and sets a response timeout threshold, and sends a request signal to the slave device;

[0021] The slave device enables request holding and receives and detects the request signal sent by the master device.

[0022] If the slave device detects an abnormality in the request signal, it returns a response signal to the master device and outputs a hold interrupt signal.

[0023] If the host does not receive a response signal from the slave within the timeout threshold, it outputs a timeout interrupt signal.

[0024] Furthermore, the step of receiving and detecting the request signal sent by the host further includes,

[0025] The slave synchronization module receives and detects the request signal, and generates a synchronization request rising edge signal or a synchronization request falling edge signal.

[0026] The latch generates the request hold signal based on the rising edge signal or the falling edge signal of the synchronization request;

[0027] The slave handshake module receives the request hold signal and outputs a response signal.

[0028] To achieve the above objectives, this application also provides an automotive-grade chip, including the automotive-grade chip handshake signal failure protection system described above.

[0029] To achieve the above objectives, the electronic device provided in this application includes the automotive-grade chip described above.

[0030] To achieve the above objectives, the present application provides a computer-readable storage medium storing computer instructions that, when executed, perform the steps of the automotive-grade chip handshake signal failure protection method as described above.

[0031] This application discloses a handshake signal failure protection system and method for automotive-grade chips. The slave device can detect abnormal requests from the master device and report a request loss interrupt; the master device can detect abnormal responses from the slave device. Handshake failure protection is implemented on-chip with minimal resource consumption, and the safety logic switch is controllable, thereby ensuring both safety and timeliness.

[0032] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. Attached Figure Description

[0033] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings:

[0034] Figure 1 This is a schematic diagram of the structure of the automotive-grade chip handshake signal failure protection system according to this application;

[0035] Figure 2 This is a timing diagram of the normal handshake operation of the automotive-grade chip handshake signal failure protection system according to this application;

[0036] Figure 3 This is a timing diagram of the slave device in the automotive-grade chip handshake signal failure protection system according to this application when an abnormality occurs;

[0037] Figure 4 This is a timing diagram of the host computer of the automotive-grade chip handshake signal failure protection system according to this application when an abnormality occurs;

[0038] Figure 5 This is a schematic diagram of an embodiment of the automotive-grade chip handshake signal failure protection system according to this application;

[0039] Figure 6 This is a timing diagram of a normal handshake in Embodiment 1 of the automotive-grade chip handshake signal failure protection system according to this application;

[0040] Figure 7 This is a timing diagram of the slave device when an abnormality occurs in Embodiment 1 of the automotive-grade chip handshake signal failure protection system according to this application;

[0041] Figure 8 This is a schematic diagram of the structure of Embodiment 2 of the automotive-grade chip handshake signal failure protection system according to this application;

[0042] Figure 9 This is a timing diagram of the normal handshake operation in Embodiment 2 of the automotive-grade chip handshake signal failure protection system according to this application;

[0043] Figure 10 This is a timing diagram of the host computer when an abnormality occurs in Embodiment 2 of the automotive-grade chip handshake signal failure protection system according to this application;

[0044] Figure 11 This is a schematic diagram of the structure of Embodiment 3 of the automotive-grade chip handshake signal failure protection system according to this application;

[0045] Figure 12 A schematic diagram of the module structure for request retention with enable control according to this application;

[0046] Figure 13 A timing diagram showing the normal operation of the input request signal of the request holding module with enable control according to this application;

[0047] Figure 14 A timing diagram for an abnormal input request signal of the request holding module with enable control according to this application;

[0048] Figure 15 The following is a flowchart of the slave device operation of the automotive-grade chip handshake signal failure protection system according to this application;

[0049] Figure 16 This is a flowchart of the host computer operation of the automotive-grade chip handshake signal failure protection system according to this application. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0051] The steps illustrated in the flowchart in the accompanying drawings can be executed in a terminal device such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in a different order than that shown here.

[0052] Figure 1 The diagram below illustrates the structure of a failure protection system for handshake signals in automotive-grade chips according to this application. Figure 1 As shown, the automotive-grade chip handshake signal failure protection system 1' of this application includes a host 10' and a slave 20'. The host 10' includes a host handshake module 11', and the slave 20' includes a slave handshake module 21'. The handshake connection signal between the host handshake module 11' and the slave handshake module 21' consists of a set of request signals (req) and acknowledgment signals (ack). First, the host handshake module 11' of the host 10' sends a req to the slave 20'. Then, the slave handshake module 21' of the slave 20' receives the req and sends an ack to the host 10' based on its functional logic. After receiving the ack, the host handshake module 11' of the host 10' cancels the corresponding req. Finally, the slave handshake module 21' of the slave 20' cancels the ack corresponding to the req, thus completing one handshake. Normal handshakes support asynchronous processing between the host 10' and the slave 20'.

[0053] Figure 2 To illustrate the timing diagram of the normal handshake operation in the automotive-grade chip handshake signal failure protection system according to this application, as follows: Figure 2 As shown, clk_m represents the clock pulse of master 10', clk_s represents the clock pulse of slave 20', and Bn represents the nth pulse (i.e., time Bn). For example, in a normal handshake, at the beginning of the 3rd pulse of clk_m, the master handshake module 11' of master 10' sends req to slave 20'. Then, at the beginning of the 6th pulse of clk_s, the slave handshake module 21' of slave 20' sends ack to master. Then, at the beginning of the Bnth pulse of clk_m, the master handshake module 11' withdraws req. Finally, at the beginning of the Bnth pulse of clk_s, the slave handshake module 21' withdraws ack.

[0054] Figure 3 The following is a timing diagram of the slave device in the automotive-grade chip handshake signal failure protection system according to this application when an abnormality occurs, such as... Figure 3 As shown, if the slave device 20' malfunctions, the ACK that should be sent by the slave handshake module 21' cannot be generated in a timely manner or even cannot be generated at all. In this case, the handshake fails, and the system needs to report the malfunction.

[0055] Figure 4 The following is a timing diagram of the automotive-grade chip handshake signal failure protection system host when an abnormality occurs, according to this application: Figure 4 As shown, an abnormality occurs in host 10', causing the req sent by the host handshake module 21' to be briefly set to 1. Since the ack sent by the slave handshake module 21' is not received, the req is set to 0. At this time, the handshake fails, and the system also needs to report this abnormality.

[0056] Currently, the fault protection for slave device 20' is achieved through watchdog timer (WDT) timeout protection, which waits for the WDT to reset after a failure occurs. This protection method consumes significant resources and has a long waiting time. On the other hand, the loss of req caused by faults in master device 10' is not easily detected in previous designs.

[0057] Example 1

[0058] Figure 5 The diagram below shows the structure of an embodiment of the automotive-grade chip handshake signal failure protection system according to this application. Figure 5 As shown, in this embodiment, the automotive-grade chip handshake signal failure protection system 1A includes a host 10 and a slave 20. The host 10 includes a host handshake module 11 and an enable control response monitoring module 12. The slave 20 includes a slave handshake module 21. The host handshake module 11 of the host 10 sends a request (req) to the slave 20 and simultaneously sends an enable signal (default enable) to the enable control response monitoring module 12 to notify it that a request (req) has been sent to the slave 20. Upon receiving the enable signal, the enable control response monitoring module 12 starts timing and calculates the timing duration (i.e., the time from when the host handshake module 11 of the host 10 sends a request (req) to the slave 20 until it receives an ack (ack) from the slave 20). The enable control response monitoring module 12 has a pre-set timeout threshold Tth, which is used to compare with the timing duration to determine if a timeout has occurred. When the timeout duration is less than the timeout threshold Tth, the response monitoring module 12 with enable control does not issue a timeout interrupt signal (timeout_irq), resets the timer to zero, and sends a cancellation signal to the host handshake module 11. When the host handshake module 11 receives the cancellation signal from the response monitoring module 12 with enable control, it cancels req. When the timeout duration is greater than or equal to the timeout threshold Tth, the response monitoring module 12 with enable control issues a timeout interrupt signal.

[0059] Figure 6 The following is a timing diagram of the normal handshake process in Embodiment 1 of the automotive-grade chip handshake signal failure protection system according to this application, as follows: Figure 6As shown, at the start of the 3rd pulse of clk_m, the host handshake module 11 of host 10 sends a req to slave 20 and simultaneously sends an enable signal to the response monitoring module 12 with enable control, thereby enabling the response monitoring module 12 to start timing. When the timing duration is less than the timeout threshold Tth, if host 10 receives an ack (for example, if the timeout threshold Tth is set to 6 pulse cycles, slave handshake module 21 of slave 20 sends an ack to host at the end of the 6th pulse of clk_m, and host 10 receives an acknowledgment synchronization signal (ack_sync) at the start of the 8th pulse of clk_m), then the response monitoring module 12 with enable control does not issue a timeout interrupt signal (timeout_irq), and the timer is reset to zero. Then, at the start of the Bnth pulse of clk_m, host handshake module 11 cancels the req, and finally, at the end of the Bnth pulse of clk_m, slave handshake module 21 cancels the ack. In addition, in this embodiment, the timeout threshold Tth can also be set to be greater than 6 pulse cycles, such as 10 pulse cycles.

[0060] Figure 7 This is a timing diagram of the slave device when an anomaly occurs in Embodiment 1 of the automotive-grade chip handshake signal failure protection system according to this application, as follows: Figure 7 As shown, at the start of the third pulse of clk_m, the host handshake module 11 of the host 10 sends a req to the slave 20 and simultaneously sends an enable signal to the response monitoring module 12 with enable control, thereby enabling the response monitoring module 12 to start timing. If the host 10 does not receive an ack (i.e., the slave 20 does not send an ack, and ack_sync remains 0), when the timing duration is greater than or equal to the timeout threshold Tth, the response monitoring module 12 with enable control issues a timeout interrupt signal (timeout_irq), which is used to inform the user in a timely manner that the slave 20 has encountered an abnormality and to handle it promptly.

[0061] In this embodiment, the example of timing with a response monitoring module 12 having enable control is described, but it is also possible to set a separate timer on the host 10.

[0062] In this embodiment, the host 10 of the automotive-grade chip handshake signal failure protection system 1A includes a host handshake module 11 and an enable-controlled response monitoring module 12. Upon receiving an enable signal, the enable-controlled response monitoring module 12 starts timing and calculates the timing duration. A timeout threshold Tth is preset in the enable-controlled response monitoring module 12. When the timing duration is greater than or equal to the timeout threshold Tth, the enable-controlled response monitoring module 12 issues a timeout interrupt signal. This allows the host 10 to detect handshake anomalies in the slave device 20. The slave device 20 anomaly detection time is short and configurable. Furthermore, this embodiment features a simple design, supports controllable protection logic switches, consumes fewer resources, and thus ensures both safety and timeliness.

[0063] Example 2

[0064] Figure 8 This is a schematic diagram of the structure of Embodiment 2 of the automotive-grade chip handshake signal failure protection system according to this application, as shown below. Figure 8 As shown, in this embodiment, the automotive-grade chip handshake signal failure protection system 1B includes a master unit 10 and a slave unit 20. The master unit 10 includes a master handshake module 11; the slave unit 20 includes a slave handshake module 21 and a request-hold module 22 with enable control. The master handshake module 11 of the master unit 10 sends a `req` to the slave unit 20 and simultaneously sends an enable signal (default enabled) to the request-hold module 22 with enable control to notify that it has sent a `req` to the slave unit 20. After detecting the `req` sent by the master unit 10 (i.e., `req` is 1), the request-hold module 22 with enable control sets the received `req` to one, and only sets `req` to zero after the slave handshake module 21 of the slave unit 20 sends an `ack`. When it is detected that host 10 has revoked req, request hold module 22 with enable control issues request hold interrupt (kp_irq) signal.

[0065] Figure 9 The timing diagram for the normal handshake operation in Embodiment 2 of the automotive-grade chip handshake signal failure protection system according to this application is as follows: Figure 9As shown, at the end of the second pulse of clk_s, the host handshake module 11 of host 10 sends req to slave 20 and simultaneously sends an enable signal to the request hold module 22 with enable control. At the start of the fourth pulse of clk_s, the request hold module 22 keeps req constant until the end of the Bn-th pulse of clk_s. At the start of the eighth pulse of clk_s, the slave handshake module 21 of slave 20 sends ack, and this ack is withdrawn at the end of the Bn-th pulse of clk_s. At this time, the request hold module 22 with enable control does not issue a request hold interrupt (kp_irq) signal.

[0066] Figure 10 This is a timing diagram of the host computer malfunctioning according to Embodiment 2 of the automotive-grade chip handshake signal failure protection system of this application, as shown below. Figure 10 As shown, at the end of the second pulse of clk_s, the host handshake module 11 of host 10 sends req to slave 20 and simultaneously sends an enable signal to the request hold module 22 with enable control. At the start of the fourth pulse of clk_s, the request hold module 22 with enable control sets req until the end of the Bn-th pulse of clk_s. At the start of the fifth pulse of clk_s, the host handshake module 11 of host 10 cancels req (i.e., host 10 experiences an error causing req to be lost). At this time, since the host handshake module 11 of host 10 has canceled req, at the start of the sixth pulse of clk_s, the request hold module 22 with enable control issues a request hold interrupt (kp_irq) signal. At the start of the eighth pulse of clk_s, the slave handshake module 21 of slave 20 sends ack, and the slave handshake module 21 of slave 20 cancels ack until the end of the Bn-th pulse of clk_s.

[0067] The slave device 20 of the automotive-grade chip 1B according to this embodiment includes a slave handshake module 21 and an enable-controlled request-hold module 22. After detecting the request (req) sent by the master device 10, the enable-controlled request-hold module 22 sets the request (req) to one. When the master device 10 has revoked the request (req), the enable-controlled request-hold module 22 sends a request-hold interrupt signal. Thus, the slave device 20 can detect handshake anomalies of the master device 10, and master device 10 anomalies can be effectively detected. Furthermore, this embodiment features a simple design, supports controllable protection logic switches, consumes fewer resources, and thus ensures safety and timeliness.

[0068] Example 3

[0069] In the above embodiments, examples were described where the host separately includes a response monitoring module 12 with enable control, and the slave 20 separately includes a request holding module 22 with enable control. Figure 11 This is a schematic diagram of the structure of Embodiment 3 of the automotive-grade chip handshake signal failure protection system according to this application, as shown below. Figure 11 As shown, the automotive-grade chip handshake signal failure protection system in this embodiment can be composed of a host 10 including a response monitoring module 12 with enable control and a slave 20 including a request holding module 22 with enable control.

[0070] Figure 12 To maintain the module structure diagram according to the enable control request of this application, as shown below. Figure 12 As shown, this application has an enable control request holding module 22, including,

[0071] Synchronization module 220 receives the req signal sent from host 10, sends the generated synchronization request rising edge signal (sync_req pos) or synchronization request falling edge signal (sync_req neg) to latch 221, and sends the synchronization mask signal (req) to latch 221. ∧ The sync_mask is sent to the XOR gate circuit 222.

[0072] The latch 221 receives a synchronization request rising edge signal (sync_req pos) or a synchronization request falling edge signal (sync_req neg) from the synchronization module 220, as well as an ack signal, and sends a request hold signal (req_kp) to the XOR gate circuit 222 and the slave handshake module 21 respectively.

[0073] The XOR gate circuit 222 receives the synchronization shielding signal from the synchronization module 220 and the request hold signal from the latch 221, and sends the generated set signal to the interrupt generation module 223.

[0074] The interrupt generation module 223 generates a hold interrupt signal output based on the set signal from the XOR gate circuit 222.

[0075] Figure 13 This is a timing diagram showing the normal operation of the input request signal of the request holding module with enable control according to this application. Figure 14 For an abnormal timing diagram of the input request signal of the request holding module with enable control according to this application, as shown below... Figure 13 and 14As shown, the request hold module with enable control in this application, when the input request signal is normal, after receiving the request signal, the synchronization module 220 generates a rising edge signal of synchronization request to the latch 221 and sends the request signal to the XOR gate circuit 222; the latch 221 sends the request hold signal to the XOR gate circuit 222 and the slave handshake module 21 respectively, and the interrupt generation module 223 does not generate a hold interrupt signal output at this time. When the input request signal is abnormal, the synchronization module 220 outputs a synchronization shield signal to the XOR gate circuit 222 and simultaneously outputs a falling edge signal of synchronization request to the latch 221; after receiving the output falling edge signal of synchronization request, the latch 221 still sends the request hold signal to the XOR gate circuit 222 and the slave handshake module 21 respectively; after receiving the synchronization shield signal, the XOR gate circuit 222 sends a set signal to the interrupt generation module 223, causing the interrupt generation module 223 to generate a hold interrupt signal output. In this embodiment, regardless of whether the request signal detected by the synchronization module 220 is normal, the latch 221 will generate a request hold signal to the slave handshake module 21, causing the slave handshake module 21 to output an ack signal to the master. When the synchronization module 220 detects an abnormal request signal, it outputs a synchronization shield signal to the XOR gate circuit 222 to trigger the interrupt generation module 223 to generate a hold interrupt signal output, so that the user can know in time that the req sent by the master is abnormal and handle it.

[0076] In this embodiment, an XOR gate circuit 222 is used to receive the synchronization shielding signal output by the synchronization module 220 and the hold request signal output by the latch 221 to trigger the interrupt generation module 223 to generate a hold interrupt signal. The circuit is simple and can greatly reduce the size of the chip.

[0077] Example 4

[0078] Figure 13 The following is a flowchart of the slave device operation of the automotive-grade chip handshake signal failure protection system according to this application, with reference to... Figure 13 This paper provides a detailed description of the slave-side workflow of the automotive-grade chip handshake signal failure protection system.

[0079] In step 101, the host handshake module 11 of the host 10 sends a req to the slave 20, and at the same time sends an enable signal (enabled by default) to the response monitoring module 12 of the host 10 with enable control, so as to notify the response monitoring module 12 with enable control that it has sent a req to the slave 20.

[0080] In step 102, the response monitoring module 12 with enable control starts timing after receiving the enable signal (i.e., timing begins when the host handshake module 11 of the host 10 sends the req to the slave 20). The response monitoring module 12 with enable control has a preset timeout threshold Tth, which is used to compare with the timing duration to determine whether a timeout has occurred.

[0081] In step 103, after receiving the req from the host 10, the slave handshake module 21 of the slave 20 sends an ack to the response monitoring module 12 of the host 10, which has enable control.

[0082] In step 104, the response monitoring module 12 with enable control calculates the timing duration based on the time of receiving the ACK (i.e., the time from when the host handshake module 11 sends the req to when it receives the ACK sent by the slave 20).

[0083] In step 105, the response monitoring module 12 with enable control determines whether the timing duration is greater than or equal to the timeout threshold Tth. When the timing duration is greater than or equal to the timeout threshold Tth, step 105 is executed; when the timing duration is less than the timeout threshold Tth, step 106 is executed.

[0084] In step 106, the response monitoring module 12 with enable control issues a timeout interrupt signal (timeout_irq).

[0085] In step 107, the response monitoring module 12 with enable control does not issue a timeout interrupt signal, and the timer is reset to zero.

[0086] Example 5

[0087] Figure 14 The following is a flowchart of the host computer operation of the automotive-grade chip handshake signal failure protection system according to this application, with reference to... Figure 14 This paper provides a detailed description of the host workflow of the automotive-grade chip handshake signal failure protection system.

[0088] In step 201, the host handshake module 11 of the host 10 sends a req to the slave 20 and simultaneously sends an enable signal (enabled by default) to the request hold module 22 with enable control to notify the request hold module 22 with enable control that it has sent a req to the slave 20.

[0089] In step 202, after the slave device 20 detects the req sent by the master device 10, the slave device 20 starts the request hold module 22 with enable control and sets the received req to one.

[0090] In step 203, the request hold module 22 with enable control determines whether the request from host 10 has been withdrawn. If the request hold module 22 with enable control determines that the request from host 10 has been withdrawn, step 204 is executed; if the request hold module 22 with enable control determines that the request from host 10 has not been withdrawn, step 205 is executed.

[0091] In step 204, when it is detected that the req of host 10 has been withdrawn, the request hold module 22 with enable control issues a request hold interrupt (kp_irq) signal.

[0092] In step 205, after the slave handshake module 21 of slave 20 sends ack, the request holding module 22 with enable control sets req to zero.

[0093] Example 6

[0094] In this embodiment, an automotive-grade chip is also provided, including the automotive-grade chip handshake signal failure protection system described in the above embodiment.

[0095] Example 7

[0096] In this embodiment, an electronic device is also provided, including the automotive-grade chip described in the above embodiments.

[0097] Example 8

[0098] In this embodiment, a computer-readable storage medium is also provided, on which computer instructions are stored, which, when executed, perform the steps of the automotive-grade chip handshake signal failure protection method of the above embodiment.

[0099] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A failure protection system for handshake signals of automotive-grade chips, characterized in that, include, The master sends a request signal to the slave. If no response signal is received from the slave within the timeout threshold, a timeout interrupt signal is output. The slave device includes: a request hold module with enable control, which receives and detects the request signal sent by the master device, generates a request hold signal, and sends it to the slave handshake module; The slave handshake module is used to receive the request hold signal and send a response signal to the host; The request hold module with enable control includes: a synchronization module that receives and detects the request signal and sends a generated synchronization request rising edge signal or synchronization request falling edge signal to a latch; a latch that generates the request hold signal based on the synchronization request rising edge signal or the synchronization request falling edge signal; an XOR gate circuit that receives a synchronization mask signal sent by the synchronization module and a request hold signal sent by the latch, respectively, and sends a generated set signal to an interrupt generation module; and an interrupt generation module that receives the set signal from the XOR gate circuit and generates a hold interrupt signal output. The request holding module with enable control, When the input request signal is normal, after receiving the request signal, the synchronization module generates a synchronization request rising edge signal to the latch and sends the request signal to the XOR gate circuit; the latch sends the request hold signal to the XOR gate circuit and the slave handshake module respectively, and at this time the interrupt generation module does not generate a hold interrupt signal output; When the input request signal is abnormal, the synchronization module outputs a synchronization shield signal to the XOR gate circuit and simultaneously outputs a synchronization request falling edge signal to the latch. After receiving the output synchronization request falling edge signal, the latch still sends the request hold signal to the XOR gate circuit and the slave handshake module respectively. After receiving the synchronization shield signal, the XOR gate circuit sends a set signal to the interrupt generation module, causing the interrupt generation module to generate a hold interrupt signal output. Regardless of whether the request signal detected by the synchronization module is normal or not, the latch generates a request hold signal to the slave handshake module, causing the slave handshake module to output an ack signal to the master. When the synchronization module detects an abnormal request signal, it outputs a synchronization shield signal to the XOR gate circuit to trigger the interrupt generation module to generate a hold interrupt signal output, so that the user can be aware of the abnormal req sent by the master and handle it in a timely manner.

2. The automotive-grade chip handshake signal failure protection system according to claim 1, characterized in that, The host includes a host handshake module and a response monitoring module with enable control. The response monitoring module with enable control enables response monitoring and sets a response timeout threshold. If no response signal is received from the slave device within the timeout threshold, a timeout interrupt signal is output. The host handshake module is used to send a request signal to the slave device.

3. The automotive-grade chip handshake signal failure protection system according to claim 2, characterized in that, The response monitoring module with enable control starts timing after being enabled and calculates the timing duration, which is the time from when the host handshake module sends a request signal to when the response monitoring module receives the response signal sent by the slave handshake module; when the timing duration is greater than or equal to the timeout threshold, a timeout interrupt signal is issued.

4. The automotive-grade chip handshake signal failure protection system according to claim 2, characterized in that, The response monitoring module with enable control does not issue a timeout interrupt signal when the timing duration is less than the timeout threshold, and simultaneously resets the timer to zero.

5. A method for protecting automotive-grade chip handshake signal from failure, characterized in that, The automotive-grade chip handshake signal failure protection system according to any one of claims 1 to 4 includes: a host enabling response monitoring and setting a response timeout threshold, and sending a request signal to a slave device; the slave device enabling request hold, receiving and detecting the request signal sent by the host; the slave device detecting an abnormal request signal, returning a response signal to the host and outputting a hold interrupt signal; if the host does not receive a response signal from the slave device within the timeout threshold, it outputs a timeout interrupt signal.

6. The method for protecting automotive-grade chip handshake signal failure according to claim 5, characterized in that, The step of receiving and detecting the request signal sent by the host further includes: a synchronization module of the slave receiving and detecting the request signal and generating a synchronization request rising edge signal or a synchronization request falling edge signal; a latch generating a request hold signal based on the synchronization request rising edge signal or the synchronization request falling edge signal; and a slave handshake module receiving the request hold signal and outputting an acknowledgment signal.

7. An automotive-grade chip, characterized in that, The automotive-grade chip, Includes the automotive-grade chip handshake signal failure protection system according to any one of claims 1 to 4.

8. An electronic device, characterized in that, The electronic device includes the automotive-grade chip as described in claim 7.

9. A computer-readable storage medium, characterized in that, It stores computer instructions, which, when executed, perform the steps of the automotive-grade chip handshake signal failure protection method as described in claim 5 or 6.

Images