Display device

Abstract

A display device is provided. The display device includes a gate line and a data line in a display area; a pixel in the display area and electrically connected to the gate line, the data line, a first power line, and a second power line; a driving circuit supplying a gate signal and a data signal to the gate line and the data line, and including a first circuit element disposed between the pixels in the display area; and a conductive pattern disposed in the display area, superposed with the first circuit element and electrically connected to the second power line. Each pixel includes a first electrode electrically connected to the first power line, a second electrode electrically connected to the second power line, and at least one light emitting element between the first electrode and the second electrode. The conductive pattern, the first electrode, and the second electrode are on the same layer.

Description

[0001] The application claims priority and benefits to Korean Patent Application No. 10-2021-0014398, filed on February 1, 2021, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosed embodiments relate to a display device. Background Technology

[0003] In recent years, interest in information display has increased. Therefore, research and development in the technical fields related to display devices have been ongoing. Summary of the Invention

[0004] The publicly disclosed aspect will provide a display device that can reduce non-display areas and improve image quality.

[0005] The disclosed aspects are not limited to those described above, and those skilled in the art will clearly understand from the following description other aspects not mentioned.

[0006] A display device according to a disclosed embodiment may include: gate lines and data lines disposed in a display area; pixels disposed in the display area, the pixels being electrically connected to the gate lines, data lines, a first power line, and a second power line; a driving circuit supplying gate signals and data signals to the gate lines and data lines respectively, the driving circuit including a first circuit element disposed between the pixels in the display area; and a conductive pattern disposed in the display area and superimposed on the first circuit element, the conductive pattern being electrically connected to the second power line. Each pixel may include: a first electrode electrically connected to the first power line; a second electrode electrically connected to the second power line; and at least one light-emitting element disposed between the first electrode and the second electrode. The conductive pattern, the first electrode, and the second electrode may be disposed on the same layer.

[0007] In one embodiment, the display area may include a first clock line electrically connected to a first circuit element and transmitting a first clock signal, and a conductive pattern may be superimposed on the first clock line.

[0008] In one embodiment, the first clock line may extend in a first direction and pass through the area between the i-th pixel row and the (i+1)-th pixel row of the display area.

[0009] In an embodiment, the first circuit element may be disposed in a non-pixel region between two unit pixel regions disposed parallel to each other in the i-th pixel row, and the first clock line may be disposed between a second power line connected to a pixel in the i-th pixel row and a first power line connected to a pixel in the (i+1)-th pixel row.

[0010] In an embodiment, the conductive pattern may be a separate pattern on the first clock line and on the first circuit element that does not overlap with the pixel.

[0011] In one embodiment, the display area may include at least one gate line adjacent to the first circuit element, and the conductive pattern may be superimposed on the at least one gate line.

[0012] In an embodiment, the driving circuit may further include a second circuit element disposed in the display area adjacent to the first circuit element, and the conductive pattern may be superimposed on the first circuit element and the second circuit element.

[0013] In an embodiment, the conductive pattern may be adjacent to at least one pixel, and the conductive pattern and the second electrode of the at least one pixel may be integral with each other.

[0014] In an embodiment, the driving circuit may include: a gate driver, including circuit elements, the circuit elements may include a first circuit element and are disposed between pixels, the gate driver outputs a gate signal to a gate line; and a data driver, outputting a data signal to a data line.

[0015] In one embodiment, the data driver may be located only in a side region of the display panel adjacent to one side of the display area.

[0016] In one embodiment, the gate driver may include an i-th stage, which includes a first circuit element. The first circuit element may be a transistor connected to a first clock line that transmits a first clock signal and uses the first clock signal to output the i-th gate signal to the i-th gate line.

[0017] In an embodiment, the display area may include groups of pixels located in each unit pixel area. Gate lines may include a first scan line connected to even-numbered pixel groups in the i-th pixel row of the display area and a second scan line connected to odd-numbered pixel groups in the i-th pixel row.

[0018] In an embodiment, the i-th pixel row may include a first pixel group, a second pixel group, and a third pixel group. The first pixel group includes pixels connected to a first data line and a first scan line. The second pixel group is located on a first side of the first pixel group and includes pixels connected to a second data line and a second scan line. The third pixel group is located on a second side of the first pixel group and includes pixels connected to the first data line and the second scan line. The fourth pixel group is located on a first side of the second pixel group and includes pixels connected to the second data line and the first scan line.

[0019] In an embodiment, the first circuit element may be disposed between the first pixel group and the second pixel group, the first data line may be disposed between the first pixel group and the third pixel group, and the second data line may be disposed between the second pixel group and the fourth pixel group.

[0020] In an embodiment, the display area may include a first pixel group and a second pixel group, each comprising pixels, and a first circuit element may be disposed between a first unit pixel area in which the first pixel group may be disposed and a second unit pixel area in which the second pixel group may be disposed.

[0021] In an embodiment, the display area may further include a fifth pixel group and a sixth pixel group, each comprising pixels, and the driving circuit may further include a second circuit element disposed between a unit pixel area in which the fifth pixel group may be disposed and another unit pixel area in which the sixth pixel group may be disposed.

[0022] In an embodiment, each pixel may include a pixel circuit and an emitter. The pixel circuit is connected to each gate line, each data line and a first power line and includes a driving transistor. The emitter is electrically connected between the electrode of the driving transistor and a second power line. The emitter includes a first electrode, a second electrode and at least one light-emitting element.

[0023] In one embodiment, the first circuit element may include a first electrode connected to a first clock line. The first electrode of the first circuit element, the first clock line, and the electrode of the driving transistor may be disposed on the same layer.

[0024] In an embodiment, the display area may include a first pixel, a second pixel, and a third pixel disposed in the first unit pixel area. The emitting portions of the first pixel, the second pixel, and the third pixel may be disposed along a first direction in the first unit pixel area, and the pixel circuits of the first pixel, the second pixel, and the third pixel may be disposed along a second direction in the first unit pixel area.

[0025] In an embodiment, the emitting part of the first pixel may be superimposed on the pixel circuits of the first pixel, the second pixel, and the third pixel.

[0026] Details of other embodiments are included in the detailed description and the accompanying drawings. Attached Figure Description

[0027] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the disclosure.

[0028] Figure 1 This is a schematic plan view illustrating a display device according to an embodiment.

[0029] Figure 2 This is a schematic plan view illustrating a splicing display device according to an embodiment.

[0030] Figure 3 This is a schematic circuit diagram showing pixels according to an embodiment.

[0031] Figure 4 This is a schematic plan view showing the emission unit of a pixel according to an embodiment.

[0032] Figure 5 This is a schematic block diagram illustrating a gate driver according to an embodiment.

[0033] Figure 6 It is shown Figure 5 A schematic diagram of the i-th level.

[0034] Figure 7 This is a schematic plan view showing the display area of ​​a display device according to an embodiment.

[0035] Figures 8 to 10 Each is a schematic plan view showing the display area of ​​a display device according to an embodiment.

[0036] Figure 11 and Figure 12 Each is a schematic cross-sectional view showing the display area of ​​the display device according to an embodiment.

[0037] Figure 13 This is a schematic plan view showing components disposed in the display area of ​​a display device according to an embodiment. Detailed Implementation

[0038] The disclosure can be modified in various ways and can have various forms, and specific embodiments will be shown in the accompanying drawings and described in detail herein. In the following description, the singular form may also include the plural form unless the context clearly includes only the singular form, and vice versa.

[0039] The disclosure is not limited to the embodiments disclosed below, and can be modified and implemented in various forms. Each of the embodiments disclosed below can be implemented individually or in combination with at least one of the other embodiments.

[0040] In the specification and claims, for purposes of meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a combined or separate sense and can be understood as equivalent to "and / or".

[0041] In the specification and claims, for purposes of meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one selected from the group consisting of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0042] The term “overlay” or “overlaying” means that the first object may be above or below the second object or to one side of the second object, or vice versa. Additionally, the term “overlay” may include stacking, overlapping, facing or oriented towards, extending over, covering or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art.

[0043] In the accompanying drawings, some elements that may not be directly related to the disclosed features may be omitted to clearly focus on the disclosure. Elements in the drawings may be shown as exaggerated in size or scale. Throughout the drawings, even if the same or similar elements may be shown in different drawings, they will be given by the same reference numerals and symbols as much as possible, and repeated descriptions may be omitted.

[0044] It will be understood that the terms “connected to” or “integrated into” can include physical connection or electrical connection or physical integration or electrical integration.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which they pertain. It will also be understood that terms (such as those defined in general dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0046] Figure 1 This is a schematic plan view showing a display device DD according to an embodiment.

[0047] Reference Figure 1 The display device DD may include a gate line GL, a data line DL, a pixel PXL, and driving circuitry for driving the pixel PXL. The gate line GL, data line DL, and pixel PXL may be disposed (e.g., arranged) in the display area DA of the display panel PNL. The driving circuitry may supply gate signals and data signals to the gate line GL and data line DL, respectively. For this purpose, the driving circuitry may include a gate driver and a data driver DDR, and a timing controller TCON for controlling the gate driver and the data driver DDR. In an embodiment, at least a portion of the driving circuitry (e.g., the gate driver) may be disposed inside the display panel PNL.

[0048] Each gate line GL may extend along a first direction DR1 in the display area DA and may be connected to a pixel PXL arranged in at least one pixel row. The gate line GL may connect between the gate driver and the pixel PXL and may include scan lines. Scan lines may be signal lines to which a scan signal is applied to select the pixel PXL to which data signals will be supplied. For example, a scan signal output from the gate driver may be transmitted to the pixel PXL via a scan line. The gate line GL may also optionally include control lines for supplying other types of control signals for controlling the operation of the pixel PXL.

[0049] Each data line DL can extend along the second direction DR2 in the display area DA and can be connected to a pixel PXL arranged in at least one pixel column. For example, the data line DL can be arranged in the display area DA to intersect with the gate line GL. The data line DL can be connected between the data driver DDR and the pixel PXL, and the data signal output from the data driver DDR can be transmitted to the pixel PXL through the data line DL.

[0050] Each pixel PXL can be connected to at least one gate line GL and at least one data line DL. When a gate signal (particularly a scan signal) is supplied from the gate line GL, the pixel PXL can receive a data signal from the data line DL. The pixel PXL can emit light with a brightness corresponding to the data signal.

[0051] A gate driver can be connected to a pixel PXL via a gate line GL and can output a gate signal to the gate line GL in response to a gate control signal supplied from a timing controller TCON. The gate driver may include a scan driver that outputs scan signals to scan lines. The scan driver may include stages for sequentially outputting scan signals to scan lines.

[0052] In an embodiment, a gate driver (or a portion thereof) may be formed within the display region DA. For example, stages and circuit elements constituting the stages (e.g., transistors and capacitors for each stage) may be formed within the display region DA together with the pixels PXL. For example, the circuit elements of the gate driver may be distributed and disposed in non-pixel regions between the pixels PXL.

[0053] When the gate driver is formed inside the display panel PNL, the manufacturing cost of the display device DD can be reduced because a separate gate driver IC (integrated circuit) is not required. When the gate driver is formed inside the display area DA, the non-display area NDA of the display panel PNL can be reduced.

[0054] The data driver DDR can be connected to the pixel PXL via the data line DL, and can output data signals to the data line DL in response to image data and data control signals supplied from the timing controller TCON. To this end, the data driver DDR may include a data signal generator that generates data signals corresponding to the image signal for each frame, and an output buffer for outputting the data signals to the data line DL.

[0055] In this embodiment, the data driver DDR can be located in a non-display area NDA outside the display area DA. The non-display area NDA can be any area other than the display area DA.

[0056] For example, the data driver DDR may include one or more source driver ICs (SiCs), and the source driver ICs (SiCs) may be mounted on a flexible circuit board (e.g., chip-on-film (COF)) or mounted in the non-display area (NDA) of the display panel PNL using a chip-on-glass (COG) process. In other embodiments, at least a portion of the data driver DDR may be formed together with the pixel PXL inside the display panel PNL.

[0057] In this embodiment, the data driver DDR may be provided only on the display panel PNL and / or disposed adjacent to one side of the display area DA. For example, the data driver DDR may be disposed only in the upper (or lower) area of ​​the display area DA. In this case, in the non-display area NDA of the display panel PNL, the driving circuit (or the connection unit connected to the driving circuit) may not be located in an area other than the area in which the data driver DDR may be located (e.g., in the non-display area NDA located in the left, right, and lower areas of the display area DA).

[0058] The timing controller TCON can supply gate control signals to the gate driver to control the operation of the gate driver. The timing controller TCON can also supply image data and data control signals to the data driver DDR to control the operation of the data driver DDR. In an embodiment, the timing controller TCON can be mounted on a first printed circuit board PCB1 and can be connected to the source driver IC SIC via a flexible flat cable FFC and a second printed circuit board PCB2 (e.g., the source PCB).

[0059] Figure 2 This is a schematic plan view illustrating a TDD (Translation Display Device) according to an embodiment. For example, Figure 2 It shows the use of Figure 1 The display device DD splicing display device TDD.

[0060] Reference Figure 1 and Figure 2A larger screen can be constructed by using multiple display devices (DDs). For example, multiple display devices (DDs) can be arranged along a first direction (DR1) and / or a second direction (DR2) to construct a TDD that achieves an ultra-large screen.

[0061] In an embodiment, each display device DD constituting the splicing display device TDD may include drive circuitry disposed only within the display area DA and / or on a side corresponding to a specific side of the display panel PNL. For example, each display device DD may be manufactured such that the drive circuitry may be disposed only on and / or connected to a first surface corresponding to the upper (or lower) area of ​​the display area DA of the display panel PNL, and the drive circuitry may not be disposed on or connected to the second, third, and fourth surfaces corresponding to the left, right, and lower (or upper) areas of the display panel PNL. Therefore, the non-display area NDA of the second, third, and fourth surfaces of the display panel PNL may have a reduced and / or minimized width. In other embodiments, if the non-display area NDA of the second, third, and fourth surfaces of the display panel PNL has a narrow width that is difficult for the human eye to perceive, it can be considered that the second, third, and fourth surfaces of the display panel PNL substantially do not include the non-display area NDA.

[0062] When using display devices (DDs) to construct a tiled display device (TDD), it is possible to prevent or minimize the visual recognition of the boundaries between display devices (DDs). This allows for the construction of a seamless tiled display device (TDD).

[0063] Figure 3 This is a schematic circuit diagram illustrating pixel PXL according to an embodiment. For example, Figure 3 The pixel PXL shown can be Figure 1 and Figure 2 Any of the pixels PXL shown, and the pixels PXL arranged in each display area DA, can be constructed to be substantially the same or similar to each other.

[0064] Reference Figure 3 Pixel PXL can be connected to at least one gate line GL, at least one data line DL, a first power line PL1, and a second power line PL2. Additionally, pixel PXL can be selectively connected to at least one other power line and / or signal line.

[0065] The pixel PXL may include an emitting unit (or emitting section) EMU for generating light with a brightness corresponding to the data signal. Additionally, the pixel PXL may optionally include a pixel circuit PXC for driving the emitting unit EMU.

[0066] The pixel circuit PXC can be connected to the gate line GL and the data line DL, and can also be connected between the first power supply line PL1 and the transmitter unit EMU. For example, the pixel circuit PXC can be connected to the scan line SL to which the scan signal can be supplied, the data line DL to which the data signal can be supplied, the first power supply line PL1 to which the power of the first power supply VDD can be supplied, and the first electrode ELT1 of the transmitter unit EMU. The pixel circuit PXC can also be selectively connected to the control line CTL to which the control signal can be supplied, and the sensing line SENL to which the reference power supply (or initialization power supply) or sensing circuit is connected, in response to the display period or sensing period. In this case, the gate line GL can include the scan line SL and the control line CTL.

[0067] A pixel circuit (PXC) may include at least one transistor and a capacitor. For example, a pixel circuit (PXC) may include a first transistor M1, a second transistor M2, a third transistor M3, and a capacitor Cst.

[0068] A first transistor M1 can be connected between a first power line PL1 and a second node N2. The second node N2 can be a node to which pixel circuit PXC and emitter unit EMU can be connected. For example, the second node N2 can be a node to which the first electrode (e.g., source electrode) of the first transistor M1 and the first electrode ELT1 of the emitter unit EMU can be connected (also referred to as the source node of the first transistor M1 or the anode node of pixel PXL). The gate electrode of the first transistor M1 can be connected to the first node N1. The first transistor M1 can control the drive current supplied to the emitter unit EMU in response to the voltage of the first node N1. For example, the first transistor M1 can be a drive transistor for pixel PXL.

[0069] In an embodiment, the first transistor M1 may optionally include a bottom metal layer (or back gate electrode) BML. The gate electrode of the first transistor M1 and the bottom metal layer BML may be stacked on top of each other, with an insulating layer disposed between the gate electrode and the bottom metal layer BML of the first transistor M1. In an embodiment, the bottom metal layer BML may be connected to one electrode of the first transistor M1 (e.g., the source electrode).

[0070] In embodiments where the first transistor M1 includes a bottom metal layer BML, a reverse bias technique (or synchronization technique) can be applied. In this technique, the threshold voltage of the first transistor M1 can be shifted in the negative or positive direction by applying a reverse bias voltage to the bottom metal layer BML. When the bottom metal layer BML is disposed below the semiconductor pattern constituting the channel of the first transistor M1 to block light incident on the semiconductor pattern, the operating characteristics of the first transistor M1 can be stabilized.

[0071] The second transistor M2 can be connected between the data line DL and the first node N1. The gate electrode of the second transistor M2 can be connected to the scan line SL. When a scan signal with a gate on-state voltage (e.g., a high-level voltage) can be supplied from the scan line SL, the second transistor M2 can be turned on to connect the data line DL to the first node N1.

[0072] For each frame period, the data signal corresponding to the frame can be supplied to the data line DL. During the period when a scan signal with a gate on-voltage can be supplied, the data signal can be transmitted to the first node N1 via the second transistor M2. For example, the second transistor M2 can be a switching transistor inside the pixel PXL for transmitting each data signal.

[0073] One electrode of capacitor Cst can be connected to the first node N1, and the other electrode can be connected to the second node N2. Capacitor Cst can be charged with a voltage corresponding to the data signal supplied to the first node N1 during each frame period.

[0074] A third transistor M3 can be connected between the second node N2 and the sensing line SENL. The gate electrode of the third transistor M3 can be connected to the control line CTL. When a control signal with a gate on-state voltage (e.g., a high-level voltage) is supplied from the control line CTL, the third transistor M3 can be turned on to transfer the reference voltage (or initialization voltage) supplied to the sensing line SENL to the second node N2, or to transfer the voltage of the second node N2 to the sensing line SENL. The voltage transferred to the second node N2 of the sensing circuit via the sensing line SENL can be provided to external circuitry (e.g., a timing controller TCON) and can be used to compensate for deviations in the characteristics of pixel PXL.

[0075] exist Figure 3 In this embodiment, all transistors included in the pixel circuit PXC are shown as N-type transistors, but the embodiment is not limited to this. For example, at least one of the first transistor M1, the second transistor M2, and the third transistor M3 can be changed to a P-type transistor. The structure and driving method of the pixel PXL can be varied according to the embodiment.

[0076] The emitting unit (EMU) may include a first electrode ELT1, a second electrode ELT2, and at least one light-emitting element (LD) connected between a first power line PL1 and a second power line PL2. For example, the emitting unit EMU may include a first electrode ELT1 connected to the first power line PL1 via a first transistor M1, a second electrode ELT2 connected to the second power line PL2, and at least one light-emitting element (LD) connected between the first electrode ELT1 and the second electrode ELT2. In an embodiment, the emitting unit EMU may include multiple light-emitting elements (LDs) connected in parallel between the first electrode ELT1 and the second electrode ELT2.

[0077] The power supplied to the first power supply VDD on the first power line PL1 and the power supplied to the second power supply VSS on the second power line PL2 can have different potentials. For example, the first power supply VDD can be a high-potential pixel power supply, and the second power supply VSS can be a low-potential pixel power supply. The potential difference between the first power supply VDD and the second power supply VSS can be set to be greater than or equal to the threshold voltage of the light-emitting element LD. In this case, the first electrode ELT1 can be the anode electrode of the emitting unit EMU, and the second electrode ELT2 can be the cathode electrode of the emitting unit EMU.

[0078] Each light-emitting element (LD) can be connected in the forward direction between the first power supply VDD and the second power supply VSS to construct each effective light source. These effective light sources can be combined to form the emission unit (EMU) of the pixel PXL.

[0079] The light-emitting element (LD) can emit light with a brightness corresponding to the drive current supplied through the pixel circuit (PXC). During each frame period, the pixel circuit (PXC) can supply a drive current corresponding to the data signal to the transmitter unit (EMU). The drive current supplied to the transmitter unit (EMU) can be shunted and flow through the light-emitting element (LD). Therefore, when each light-emitting element (LD) emits light with a brightness corresponding to the current flowing through it, the transmitter unit (EMU) can emit light with a brightness corresponding to the drive current.

[0080] In an embodiment, the transmitting unit (EMU) may further include at least one invalid light source. For example, the transmitting unit (EMU) may also include an invalid light-emitting element, which may be aligned in opposite directions between the first electrode ELT1 and the second electrode ELT2, or may not be fully connected between the first electrode ELT1 and the second electrode ELT2.

[0081] Figure 3An embodiment in which pixel PXL includes a transmitting unit EMU with a parallel structure is shown, but the embodiment is not limited thereto. For example, in another embodiment, pixel PXL may include a transmitting unit EMU with a series structure or a series / parallel structure. In this case, the transmitting unit EMU may include a plurality of light-emitting elements LD connected in series or in series / parallel between the first electrode ELT1 and the second electrode ELT2. In yet another embodiment, pixel PXL may include only one light-emitting element LD connected between the first electrode ELT1 and the second electrode ELT2.

[0082] Figure 4 This is a schematic plan view illustrating the emission unit (EMU) of the pixel PXL according to a disclosed embodiment. For example, as in Figure 3 In the embodiments, Figure 4 The structure of the transmitting unit EMU is shown. The transmitting unit EMU includes a first electrode ELT1, a second electrode ELT2, and multiple light-emitting elements LD connected in parallel between the first electrode ELT1 and the second electrode ELT2.

[0083] Figure 4 An embodiment is shown in which the transmitting unit (EMU) can be connected to power lines (e.g., first power line PL1 and / or second power line PL2), circuit elements (e.g., at least one circuit element constituting the pixel circuit PXC of the corresponding pixel PXL), and / or signal lines (e.g., scan lines SL and / or data lines DL) via a first contact hole CH1 and a second contact hole CH2. However, the embodiment is not limited thereto. For example, in another embodiment, at least one of the first electrode ELT1 and the second electrode ELT2 of each pixel PXL can be directly connected to the power lines and / or signal lines without through contact holes and / or intermediate wiring.

[0084] Reference Figure 3 and Figure 4 The transmitting unit (EMU) may include a first electrode ELT1, a second electrode ELT2, and a light-emitting element (LD) disposed between and / or aligned between the first electrode ELT1 and the second electrode ELT2. The statement that the light-emitting element LD may be disposed between and / or aligned between the first electrode ELT1 and the second electrode ELT2 can mean that at least one region of each of the light-emitting elements LD may be located in the region between the first electrode ELT1 and the second electrode ELT2 in a plan view.

[0085] The emitting unit (EMU) may also include a first contact electrode CNE1 and a second contact electrode CNE2 connected to the light-emitting element (LD). The pixel PXL may also include at least one other electrode, a conductive pattern, and / or an insulating pattern.

[0086] The first electrode ELT1 and the second electrode ELT2 can be spaced apart from each other. For example, the first electrode ELT1 and the second electrode ELT2 can be arranged to be spaced apart from each other along a first direction DR1 in the same layer, and can extend along a second direction DR2 respectively. The first direction DR1 and the second direction DR2 can be directions that intersect each other (e.g., orthogonal to each other). In an embodiment, the first direction DR1 can be a horizontal direction (or a row direction), and the second direction DR2 can be a vertical direction (or a column direction). However, the shape, size, position, and / or arrangement of the first electrode ELT1 and the second electrode ELT2 can be varied according to different embodiments.

[0087] Figure 4 An embodiment is shown in which the transmitting unit EMU includes a first electrode ELT1 and a second electrode ELT2, but the embodiment is not limited thereto. For example, the number of first electrodes ELT1 and / or second electrodes ELT2 provided for each transmitting unit EMU can be varied. When multiple first electrodes ELT1 are provided in a transmitting unit EMU, the first electrodes ELT1 can be connected to each other integrally or non-integrally. Similarly, when multiple second electrodes ELT2 are provided in a transmitting unit EMU, the second electrodes ELT2 can be connected to each other integrally or non-integrally.

[0088] Each of the first electrode ELT1 and the second electrode ELT2 may have a separate pattern for each pixel PXL or a pattern that is connected together within multiple pixels PXL. For example, the first electrode ELT1 may have an independent pattern for each pixel PXL and may be separate from the first electrode ELT1 of adjacent pixels PXL. The second electrode ELT2 may have an independent pattern for each pixel PXL, or it may be integrally connected to the second electrode ELT2 of adjacent pixels PXL.

[0089] In the process of forming pixel PXL, specifically, before the alignment of the light-emitting element LD can be completed, the first electrodes ELT1 of pixel PXL can be connected to each other, and the second electrodes ELT2 of pixel PXL can be connected to each other. For example, before the alignment of the light-emitting element LD can be completed, the first electrodes ELT1 of pixel PXL can be integrally or non-integrally connected to each other to form a first alignment line, and the second electrodes ELT2 of pixel PXL can be integrally or non-integrally connected to each other to form a second alignment line.

[0090] In the step of aligning the light-emitting element (LD), the first alignment line and the second alignment line can respectively receive a first alignment signal and a second alignment signal. The first alignment signal and the second alignment signal can have different waveforms, potentials, and / or phases. Therefore, an electric field can be formed between the first alignment line and the second alignment line, allowing the LD to be aligned between the first alignment line and the second alignment line. After the alignment of the LD can be completed, the first electrodes ELT1 of the pixel PXL can be separated from each other by at least cutting the first alignment line. Therefore, the pixel PXL can be driven independently.

[0091] The first electrode ELT1 can be electrically connected via the first contact hole CH1 to circuit elements (e.g., at least one transistor constituting the pixel circuit PXC), power lines (e.g., the first power line PL1), and / or signal lines (e.g., scan line SL, data line DL, or control line). In another embodiment, the first electrode ELT1 can be directly connected to the power line or signal line.

[0092] In an embodiment, the first electrode ELT1 can be electrically connected to a circuit element (e.g., the first transistor M1 of the pixel circuit PXC) through the first contact hole CH1, and can also be electrically connected to a first wiring through the circuit element. The first wiring can be a first power line PL1.

[0093] The second electrode ELT2 can be electrically connected via the second contact hole CH2 to circuit elements (e.g., at least one transistor constituting the pixel circuit PXC), power lines (e.g., the second power line PL2), and / or signal lines (e.g., scan line SL, data line DL, or control line). In another embodiment, the second electrode ELT2 can be directly connected to the power line or signal line.

[0094] In this embodiment, the second electrode ELT2 can be electrically connected to the second wiring via the second contact hole CH2. The second wiring can be a second power line PL2.

[0095] Each of the first electrode ELT1 and the second electrode ELT2 may consist of a single layer or multiple layers. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one reflective electrode layer comprising a reflective conductive material, and may also selectively include at least one transparent electrode layer and / or a conductive capping layer. The reflective conductive material may be a metal with high reflectivity in the visible light wavelength band (e.g., at least one of aluminum (Al), gold (Au), and silver (Ag)), but the embodiments are not limited thereto.

[0096] The light-emitting element (LD) can be aligned between the first electrode ELT1 and the second electrode ELT2. For example, the light-emitting element (LD) can be aligned between the first electrode ELT1 and the second electrode ELT2 and / or connected in parallel with each other.

[0097] In an embodiment, each light-emitting element (LD) can be aligned in a first direction DR1 between the first electrode ELT1 and the second electrode ELT2, and can be electrically connected to the first electrode ELT1 and the second electrode ELT2. Figure 4 An embodiment in which all the light-emitting elements LD can be uniformly aligned in the first direction DR1 is shown, but the embodiment is not limited thereto. For example, at least one of the light-emitting elements LD can be arranged diagonally between the first electrode ELT1 and the second electrode ELT2 in a direction inclined relative to the first direction DR1 and the second direction DR2.

[0098] In embodiments, each light-emitting element (LD) can be an ultra-small inorganic light-emitting diode (e.g., having dimensions from nanometer to micrometer scale) using a material with an inorganic crystal structure. For example, each light-emitting element (LD) can be an ultra-small inorganic light-emitting diode manufactured by growing a nitride-based semiconductor and etching the nitride-based semiconductor into a rod shape. However, the type, size, shape, structure, and / or number of light-emitting elements (LDs) constituting each emission unit (EMU) can be varied.

[0099] Each light-emitting element (LD) may include a first terminal EP1 and a second terminal EP2. The first terminal EP1 may be configured to be adjacent to a first electrode ELT1, and the second terminal EP2 may be configured to be adjacent to a second electrode ELT2. The first terminal EP1 may be stacked with the first electrode ELT1, or it may not be stacked with the first electrode ELT1. The second terminal EP2 may be stacked with the second electrode ELT2, or it may not be stacked with the second electrode ELT2.

[0100] In one embodiment, the first end EP1 of each of the light-emitting elements (LDs) can be electrically connected to the first electrode ELT1 via the first contact electrode CNE1. In another embodiment, the first end EP1 of each of the light-emitting elements (LDs) can be directly connected to the first electrode ELT1. In yet another embodiment, the first end EP1 of each of the light-emitting elements (LDs) can be electrically connected only to the first contact electrode CNE1, and may not be connected to the first electrode ELT1. In this case, the first contact electrode CNE1 can constitute the anode electrode of the emission unit (EMU), and the light-emitting element (LD) can be connected to the corresponding pixel circuit (PXC) via the first contact electrode CNE1.

[0101] Similarly, the second end EP2 of each of the light-emitting elements (LDs) can be electrically connected to the second electrode ELT2 via the second contact electrode CNE2. In another embodiment, the second end EP2 of each of the light-emitting elements (LDs) can be directly connected to the second electrode ELT2. In yet another embodiment, the second end EP2 of each of the light-emitting elements (LDs) can be electrically connected only to the second contact electrode CNE2, and may not be connected to the second electrode ELT2. In this case, the second contact electrode CNE2 can constitute the cathode electrode of the emitting unit (EMU), and the light-emitting element (LD) can be connected to the second power line PL2 via the second contact electrode CNE2.

[0102] The light-emitting element (LD) can be fabricated in a dispersed form in a solution and supplied to the emitting region of each pixel PXL via inkjet printing or slot coating. With the LD supplied to each emitting region, and alignment signals applied to the first electrode ELT1 and the second electrode ELT2 (or the first alignment line and the second alignment line) of the pixel PXL, the LD can be aligned between the first electrode ELT1 and the second electrode ELT2. After the LD is aligned, the solvent can be removed via a drying process or similar method.

[0103] The first contact electrode CNE1 and the second contact electrode CNE2 can be selectively formed on the first end EP1 and the second end EP2 of the light-emitting element LD, respectively.

[0104] The first contact electrode CNE1 can be disposed on the first terminal EP1 and electrically connected to the first terminal EP1 of the light-emitting element LD. The first contact electrode CNE1 can also be disposed on the first electrode ELT1 and electrically connected to the first electrode ELT1. The first terminal EP1 of the light-emitting element LD can be electrically connected to the first electrode ELT1 through the first contact electrode CNE1.

[0105] The second contact electrode CNE2 can be disposed on the second terminal EP2 to be electrically connected to the second terminal EP2 of the light-emitting element LD. The second contact electrode CNE2 can also be disposed on the second electrode ELT2 to be electrically connected to the second electrode ELT2. The second terminal EP2 of the light-emitting element LD can be electrically connected to the second electrode ELT2 through the second contact electrode CNE2.

[0106] Figure 5 This is a schematic block diagram illustrating a gate driver GDR according to an embodiment. For example, Figure 5 An example of a scan driver SDR for sequentially outputting scan signals SS to scan lines SL is shown, the scan driver SDR being a component included in the gate driver GDR.

[0107] Reference Figures 1 to 5The gate driver GDR may include a stage ST for outputting the scan signal SS to the scan line SL. For ease of explanation, Figure 5 Only the i-th level STi and the (i+1)-th level STi+1 used to output the i-th scan line SLi and the (i+1)-th scan line SLi+1 to the display area DA are shown (where i can be a natural number greater than 0).

[0108] Stage ST can be independently connected to the input terminal of the start pulse STP. For example, the first stage of the gate driver GDR can be connected to the input terminal of the start pulse STP, and the second stage of the gate driver GDR can be connected to the second output terminal OUT2 of the first stage. In this way, the i-th stage of the scan driver SDR can be connected to the input terminal of the start pulse STP or the second output terminal OUT2 of the previous stage (e.g., the (i-1)-th stage). Stage ST may also include at least one power supply terminal and can be driven by drive power supplied from the power supply terminal. Stage ST may also include a reset terminal, etc., to which a reset signal can be input.

[0109] The ST stage can use the start pulse STP and the clock signal CLK to sequentially output the scan signal SS to the scan line SL.

[0110] In an embodiment, the clock signal CLK may include a first clock signal CLK1 and a second clock signal CLK2. The first clock signal CLK1 may be input to a first clock terminal CK1 for odd-numbered levels and a second clock terminal CK2 for even-numbered levels. The second clock signal CLK2 may be input to a second clock terminal CK2 for odd-numbered levels and a first clock terminal CK1 for even-numbered levels. However, the type, quantity, and / or supply method of the clock signal CLK may vary depending on the circuit configuration of the stage ST.

[0111] The first stage of the gate driver GDR can use a start pulse STP and a clock signal CLK to output a first scan signal and a first carry signal to a first output terminal OUT1 and a second output terminal OUT2, respectively. The first output terminal OUT1 of the first stage can be connected to a first scan line, and the second output terminal OUT2 can be connected to the next stage (e.g., the second stage). Therefore, the first scan signal can be supplied to the first scan line, and the first carry signal can be supplied to the next stage.

[0112] The second stage of the gate driver GDR can output a second scan signal to the first output terminal OUT1 using a first carry signal and a clock signal CLK, and can also output a second carry signal to the second output terminal OUT2. The first output terminal OUT1 of the second stage can be connected to the second scan line, and the second output terminal OUT2 can be connected to the next stage (e.g., the third stage). Therefore, the second scan signal can be supplied to the second scan line, and the second carry signal can be supplied to the next stage.

[0113] In this way, the i-th stage of the gate driver GDR can output the i-th scan signal SSi to the i-th scan line SLi using the (i-1)-th carry signal CRi-1 (or start pulse STP) output from the (i-1)-th stage STi-1 and the clock signal CLK, and can also output the i-th carry signal CRi to the (i+1)-th stage STi+1. Similarly, the (i+1)-th stage STi+1 of the gate driver GDR can output the (i+1)-th scan signal SSi+1 to the (i+1)-th scan line SLi+1 using the i-th carry signal CRi and the clock signal CLK, and can also output the (i+1)-th carry signal CRi+1 to the (i+2)-th stage.

[0114] Figure 6 This is a schematic diagram illustrating a stage ST according to an embodiment, and is shown as an example. Figure 5 The i-th stage ST. According to an embodiment, the stages ST disposed in each gate driver GDR can be configured to be substantially the same or similar.

[0115] In the disclosure, the circuit construction of each ST stage is not particularly limited and can be modified in various ways depending on the embodiment. Therefore, in Figure 6 In each stage ST shown, the circuit elements used to control the voltage of the Q node and the voltage of the QB node in response to the carry signal CRp or the start pulse STP of the previous stage can be omitted, and the construction including the circuit elements is simplified and shown in block diagram form as the control circuit CCR.

[0116] Figure 6 The diagram illustrates the construction of a first output circuit OCR1 and a second output circuit OCR2 for outputting each scan signal SS (e.g., the i-th scan signal SSi) and each carry signal CR (e.g., the i-th carry signal CRi) based on the voltages of the Q-node and QB-node. However, the construction of the first output circuit OCR1 and the second output circuit OCR2 can also be modified in various ways according to embodiments.

[0117] Reference Figure 5 and Figure 6The stage ST may include a control circuit CCR, a first output circuit OCR1, and a second output circuit OCR2. The clock terminal CK (or clock line) of the stage ST may include a first clock terminal CK1 (or a first clock line) and a second clock terminal CK2 (or a second clock line). A first clock signal CLK1 (the scan clock signal of the stage ST) can be input to the first clock terminal CK1, and a second clock signal CLK2 (the carry clock signal of the stage ST) can be input to the second clock terminal CK2. A start pulse STP or a carry signal CRp from the previous stage (e.g., the (i-1)th carry signal CRi-1 or the ikth carry signal CRi-k) can be input to the control circuit CCR of the stage ST (where k can be a natural number of 2 or greater).

[0118] In this embodiment, the first clock signal CLK1 and the second clock signal CLK2 can be the same signal, and only the first clock terminal CK1 and the second clock terminal CK2 can be constructed separately. In this case, each stage ST can simultaneously output the scan signal SSi and the carry signal CR to the first output terminal OUT1 and the second output terminal OUT2, respectively, in response to the first clock signal CLK1 and the second clock signal CLK2 (or a substantially identical clock signal CLK).

[0119] The control circuit CCR can receive a start pulse STP or a previous carry signal CRp and at least one clock signal CLK (e.g., a first clock signal CLK1, a second clock signal CLK2, and / or at least one other clock signal), and can control the voltages of the Q nodes and QB nodes based on these signals. For example, when the previous carry signal CRp is at a logic low level (e.g., a gate cutoff voltage or a cutoff voltage level), the control circuit CCR can control the voltage of the QB node to become a logic high level (e.g., a gate on-voltage or an on-voltage level), and can maintain the voltage of the Q node at the gate cutoff voltage. When the previous carry signal CRp is at a logic high level, the control circuit CCR can control the voltage of the Q node to become a logic high level, and can maintain the voltage of the QB node at a logic low level.

[0120] In an embodiment, the control circuit CCR can initialize the voltage of the Q node based on the next carry signal CRq (or initialization signal) input from the next stage (e.g., stage i+1 STi+1 or stage i+k). For example, the control circuit CCR can use the next carry signal CRq to initialize the voltage of the Q node such that each stage ST outputs a carry signal CR and a scan signal SS with logic high level during the corresponding horizontal period, and does not output a carry signal CR and a scan signal SS with logic high level after the corresponding horizontal period (e.g., outputs a carry signal CR and a scan signal SS with logic low level).

[0121] The first output circuit OCR1 can output the first clock signal CLK1 as a scan signal SS to the first output terminal OUT1 in response to the voltage of the Q node, and can pull down the scan signal SS to a first logic low level or maintain it at a first logic low level in response to the voltage of the QB node. For example, when the voltage of the Q node is at a logic high level and the voltage of the QB node is at a logic low level, the first output circuit OCR1 can output the first clock signal CLK1 to the first output terminal OUT1. Conversely, when the voltage of the Q node is at a logic low level and the voltage at the QB node is at a logic high level, the first output circuit OCR1 can pull down the voltage of the scan signal SS output to the first output terminal OUT1 to a first cutoff voltage VOFF1 input from the first power supply terminal VIN1, or can maintain the voltage of the scan signal SS at the first cutoff voltage VOFF1. The first cutoff voltage VOFF1 can be a switching transistor capable of enabling the pixel PXL (e.g., Figure 3 The voltage at which the second transistor M2 is turned off.

[0122] The first output circuit OCR1 may include a first transistor T1 and a second transistor T2. The first output circuit OCR1 may also include a first capacitor C1.

[0123] The first transistor T1 can be connected between the first clock terminal CK1 and the first output terminal OUT1, and the gate electrode of the first transistor T1 can be connected to the Q node. The first transistor T1 can be turned on when the voltage of the Q node is at a logic high level (e.g., gate on-state voltage) to electrically connect the first clock terminal CK1 and the first output terminal OUT1. Therefore, when the first transistor T1 is turned on, the first clock signal CLK1 can be output as a scan signal SS.

[0124] The second transistor T2 can be connected between the first output terminal OUT1 and the first power supply terminal VIN1, and the gate electrode of the second transistor T2 can be connected to the QB node. The second transistor T2 can be turned on when the voltage of the QB node is at a logic high level (e.g., gate on-state voltage) to electrically connect the first power supply terminal VIN1 to the first output terminal OUT1. Therefore, when the second transistor T2 is turned on, the voltage of the scan signal SS can be maintained at the first cutoff voltage VOFF1.

[0125] The first capacitor C1 can be connected between the gate electrode of the first transistor T1 and the first output terminal OUT1. The first capacitor C1 can be a boost capacitor disposed in the first output circuit OCR1 to stably output a scan signal SS with a logic high level.

[0126] The second output circuit OCR2 can output the second clock signal CLK2 as a carry signal CR to the second output terminal OUT2 in response to the voltage of the Q node, and can pull down the carry signal CR to a second logic low level or maintain it at a second logic low level in response to the voltage of the QB node. For example, when the voltage of the Q node is at a logic high level and the voltage of the QB node is at a logic low level, the second output circuit OCR2 can output the second clock signal CLK2 to the second output terminal OUT2. Conversely, when the voltage of the Q node is at a logic low level and the voltage at the QB node is at a logic high level, the second output circuit OCR2 can pull down the voltage of the carry signal CR output to the second output terminal OUT2 to the second cutoff voltage VOFF2 input from the second power supply terminal VIN2, or can maintain the voltage of the carry signal CR at the second cutoff voltage VOFF2. The second cutoff voltage VOFF2 can be a voltage level capable of turning off at least one transistor included in the control circuit CCR, and can be the same as or different from the first cutoff voltage VOFF1.

[0127] The second output circuit OCR2 may include a third transistor T3 and a fourth transistor T4. The second output circuit OCR2 may also include a second capacitor C2.

[0128] The third transistor T3 can be connected between the second clock terminal CK2 and the second output terminal OUT2, and the gate electrode of the third transistor T3 can be connected to the Q node. The third transistor T3 can be turned on when the voltage of the Q node is at a logic high level to electrically connect the second clock terminal CK2 and the second output terminal OUT2. Therefore, when the third transistor T3 is turned on, the second clock signal CLK2 can be output as a carry signal CR.

[0129] The fourth transistor T4 can be connected between the second output terminal OUT2 and the second power supply terminal VIN2, and the gate electrode of the fourth transistor T4 can be connected to the QB node. The fourth transistor T4 can be turned on when the voltage of the QB node is at a logic high level to electrically connect the second power supply terminal VIN2 and the second output terminal OUT2. Therefore, when the fourth transistor T4 is turned on, the voltage of the carry signal CR can be maintained at the second cutoff voltage VOFF2.

[0130] The second capacitor C2 can be connected between the gate electrode of the third transistor T3 and the second output terminal OUT2. The second capacitor C2 can be a boost capacitor set in the second output circuit OCR2 to stably output a carry signal CR with a logic high level.

[0131] In this embodiment, the waveforms of the scan signal SS and the carry signal CR can be different from each other. In this case, the stage ST may include a second output circuit OCR2, which is different from the first output circuit OCR1, and a second clock terminal CK2, which is different from the first clock terminal CK1. To prevent interference between the output of the first output circuit OCR1 (e.g., the scan signal SS) and the output of the second output circuit OCR2 (e.g., the carry signal CR), the stage ST may include a first power supply terminal VIN1 and a second power supply terminal VIN2.

[0132] However, the embodiments are not limited thereto. For example, in another embodiment, the scan signal SS of the next stage (e.g., the (i+1)th scan signal SSi+1) can be generated by using the scan signal SS output from each stage ST (e.g., the i-th scan signal SSi). The construction of the stage ST, the waveforms of the input / output signals, and the operation methods can be varied according to the embodiments.

[0133] Figure 7 This is a schematic plan view showing the display area DA of the display device DD according to an embodiment. For example, Figure 7 It shows Figure 1 and Figure 2 The area DA shown in the diagram specifically illustrates the area where the first circuit element CRE1 and the second circuit element CRE2 of the drive circuit can be set.

[0134] Reference Figures 1 to 7 The display area DA may include pixel groups PXG, each pixel group PXG including pixels PXL and located in each unit pixel area UPA. For example, each of the pixels PXL in the display area DA may form a pair with at least one adjacent pixel PXL to form each pixel group PXG.

[0135] Furthermore, the display area DA may include at least one circuit element disposed within the display area DA and located between pixels PXL and / or pixel groups PXG. The at least one circuit element may be a circuit element constituting a driving circuit. For example, the driving circuit may include circuit elements distributed and arranged in non-pixel regions between pixels PXL (e.g., regions located within the display area DA and between adjacent pixels PXL and / or adjacent pixel groups PXG), as well as a first circuit element CRE1 and a second circuit element CRE2.

[0136] The display area DA may also include at least a conductive pattern CDP superimposed on the first circuit element CRE1.

[0137] First, the arrangement of pixel PXL and pixel group PXG including pixel PXL will be described. Figure 7 The structure of the embodiment shown is illustrated. In this embodiment, pixel groups PXG of two adjacent pixel columns can share a data line DL. In this case, scan lines SL can be formed in each pixel row, and scan lines SL can be connected to different pixels PXL. For example, scan lines SL may include a first scan line SL1 formed in the i-th pixel row of the display area DA and connected to the even-numbered pixel group (or odd-numbered pixel group) of the i-th pixel row, and a second scan line SL2 formed in the i-th pixel row and connected to the odd-numbered pixel group (or even-numbered pixel group) of the i-th pixel row. Furthermore, scan lines SL may include a third scan line SL3 formed in the (i+1)-th pixel row of the display area DA and connected to the even-numbered pixel group (or odd-numbered pixel group) of the (i+1)-th pixel row, and a fourth scan line SL4 formed in the (i+1)-th pixel row and connected to the odd-numbered pixel group (or even-numbered pixel group) of the (i+1)-th pixel row. Scan lines SL can receive scan signals SS with gate on-state voltage at different time points.

[0138] In an embodiment, the scan lines SL formed in each pixel row can be spaced apart from each other, and the pixels PXL of the corresponding pixel row are placed between them. For example, the first scan line SL1 and the second scan line SL2 can be respectively set in the upper and lower regions of the i-th pixel row, and the third scan line SL3 and the fourth scan line SL4 can be respectively set in the upper and lower regions of the (i+1)-th pixel row.

[0139] In an embodiment, the first power line PL1 may be formed for each pixel row or for each of a plurality of rows, and may extend along a first direction DR1 between adjacent pixel rows. The first power line (or first sub-power line) PL1 formed along the first direction DR1 between pixel rows may be integrally or non-integrally connected in the region between pixels PXL and / or in the outer region of the display region DA to form the first power line PL1.

[0140] Similarly, the second power line PL2 can be formed for each pixel row or for each of multiple rows, and can extend along the first direction DR1 between adjacent pixel rows. The second power line (or second sub-power line) PL2 formed along the first direction DR1 between pixel rows can be integrally or non-integrally connected in the region between pixels PXL and / or the outer region of the display region DA to form a second power line PL2.

[0141] In an embodiment, each pixel group PXG may include a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 located in each unit pixel region UPA. For example, the first pixel group PXG1 located in the i-th pixel row may include the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 located in the first unit pixel region UPA1 of the i-th pixel row. Similarly, the second pixel group PXG2 located in the i-th pixel row may include the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 located in the second unit pixel region UPA2 of the i-th pixel row.

[0142] In this embodiment, the first pixel group PXG1 and the second pixel group PXG2 can be connected to different data lines DL and scan lines SL. For example, the first pixel group PXG1 can be connected to the first scan line SL1 and multiple first data lines DL1, and the second pixel group PXG2 can be connected to the second scan line SL2 and multiple second data lines DL2.

[0143] For example, the first pixel circuits PXC1, PXC2, and PXC3 of the first pixel PXL1, second pixel PXL2, and third pixel PXL3 of the first pixel group PXG1 can be connected to the first scan line SL1 and the first power line PL1 to be driven simultaneously, and can be connected to the first data line DL1_1 (the first sub-data line of the first pixel column), the first data line DL1_2 (the second sub-data line of the first pixel column), and the first data line DL1_3 (the third sub-data line of the first pixel column) to receive different data signals. The first pixel circuit PXC1, the second pixel circuit PXC2, and / or the third pixel circuit PXC3 can also be selectively connected to at least one signal line and / or power line.

[0144] The pixel circuits PXC of the first pixel PXL1, second pixel PXL2, and third pixel PXL3 of the first pixel group PXG1 can be electrically connected to the transmitting unit EMU through the first contact hole CH1. For example, the first pixel circuit PXC1 of the first pixel group PXG1 can be connected to the first transmitting unit EMU1 of the first pixel group PXG1 to construct the first pixel PXL1 of the first pixel group PXG1 together with the first transmitting unit EMU1. Similarly, the second pixel circuit PXC2 of the first pixel group PXG1 can be connected to the second transmitting unit EMU2 of the first pixel group PXG1 to construct the second pixel PXL2 of the first pixel group PXG1 together with the second transmitting unit EMU2, and the third pixel circuit PXC3 of the first pixel group PXG1 can be connected to the third transmitting unit EMU3 of the first pixel group PXG1 to construct the third pixel PXL3 of the first pixel group PXG1 together with the third transmitting unit EMU3. The transmitting unit EMU of the first pixel group PXG1 can be individually connected to each pixel circuit PXC, and can be collectively connected to the second power line PL2.

[0145] The first pixel circuits PXC1, PXC2, and PXC3 of the first pixel PXL1, second pixel PXL2, and third pixel PXL3 of the second pixel group PXG2 can be connected to the second scan line SL2 and the first power line PL1 to be driven simultaneously. They can also be connected to the 2_1 data line (the first sub-data line of the second pixel column) DL2_1, the 2_2 data line (the second sub-data line of the second pixel column) DL2_2, and the 2_3 data line (the third sub-data line of the second pixel column) DL2_3 respectively to receive different data signals. The first pixel circuit PXC1, the second pixel circuit PXC2, and / or the third pixel circuit PXC3 can also be selectively connected to at least one signal line and / or power line.

[0146] The pixel circuits PXC of the first pixel PXL1, second pixel PXL2, and third pixel PXL3 of the second pixel group PXG2 can be electrically connected to the transmitting unit EMU through the first contact hole CH1. For example, the first pixel circuit PXC1 of the second pixel group PXG2 can be connected to the first transmitting unit EMU1 of the second pixel group PXG2 to construct the first pixel PXL1 of the second pixel group PXG2 together with the first transmitting unit EMU1. Similarly, the second pixel circuit PXC2 of the second pixel group PXG2 can be connected to the second transmitting unit EMU2 of the second pixel group PXG2 to construct the second pixel PXL2 of the second pixel group PXG2 together with the second transmitting unit EMU2, and the third pixel circuit PXC3 of the second pixel group PXG2 can be connected to the third transmitting unit EMU3 of the second pixel group PXG2 to construct the third pixel PXL3 of the second pixel group PXG2 together with the third transmitting unit EMU3. The transmitting unit EMU of the second pixel group PXG2 can be individually connected to each pixel circuit PXC, and can be collectively connected to the second power line PL2.

[0147] In an embodiment, in each unit pixel region UPA, the pixel circuit PXC and the emitter unit EMU can be arranged along different directions and can be stacked on top of each other. For example, in each unit pixel region UPA, the pixel circuit PXC can be arranged along the second direction DR2, and the emitter unit EMU can be arranged along the first direction DR1. Each emitter unit EMU can be stacked with a plurality of pixel circuits PXC including the pixel circuit PXC of the corresponding pixel PXL, and can be electrically connected to the pixel circuit PXC in the region stacked with the pixel circuit PXC of the corresponding pixel PXL. For example, the first emitter unit EMU1 of the first pixel group PXG1 can be stacked with the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 of the first pixel group PXG1, and can be connected to the first pixel circuit PXC1 through the first contact hole CH1 in the region stacked with the first pixel circuit PXC1 of the first pixel group PXG1.

[0148] For example, pixel circuits (PXCs) and emitter units (EMUs) can be formed on different layers and can be stacked on top of each other. Therefore, the position and arrangement order of pixel circuits (PXCs) and emitter units (EMUs) in each unit pixel area (UPA) and / or display area (DA) can be designed with greater freedom.

[0149] Furthermore, adjacent pixel groups PXG (e.g., first pixel group PXG1 and second pixel group PXG2) can have the same or different arrangement structures. For example, in the first unit pixel region UPA1 and the second unit pixel region UPA2, the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 can be arranged in different orders, while the first transmitting unit EMU1, the second transmitting unit EMU2, and the third transmitting unit EMU3 can be arranged in the same order. The arrangement structure of pixel PXL and / or pixel group PXG can be varied according to different embodiments.

[0150] In this embodiment, the first pixel group PXG1 and the second pixel group PXG2 can share the data line DL with the third pixel group PXG3 and the fourth pixel group PXG4, respectively. For example, the third pixel group PXG3 can be located to the left of the first pixel group PXG1 and can share the first data line DL1 located between the first unit pixel region UPA1 and the third unit pixel region UPA3 with the first pixel group PXG1. For example, the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 of the third pixel group PXG3 can be connected to the first data line DL1 and the second scan line SL2.

[0151] The second pixel group PXG2 can be located to the right of the first pixel group PXG1. The first pixel group PXG1 and the second pixel group PXG2 do not need to share the data line DL.

[0152] The fourth pixel group PXG4 can be located to the right of the second pixel group PXG2, and can share the second data line DL2 located between the second unit pixel region UPA2 and the fourth unit pixel region UPA4 with the second pixel group PXG2. For example, the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 of the fourth pixel group PXG4 can be connected to the second data line DL2 and the first scan line SL1. Each of the third pixel group PXG3 and the fourth pixel group PXG4 can have a structure substantially similar to that of the first pixel group PXG1 and / or the second pixel group PXG2.

[0153] The arrangement structure of the pixel PXL is not limited to Figure 7 Examples include, for instance, data lines DL can be arranged for each pixel column. In this case, adjacent pixel columns may not share data lines DL and may be connected to different data lines DL. Furthermore, pixels PXL arranged in the same pixel row may be connected to the same scan line SL to receive data signals simultaneously.

[0154] The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 formed in each unit pixel region UPA can be sub-pixels that emit light of different colors. For example, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, the type, number, and / or arrangement of the pixels PXL constituting each pixel group PXG can be varied depending on the embodiment.

[0155] The driving circuit may include at least one circuit element disposed in the display area DA between pixels PXL and / or between pixel groups PXG. For example, the driving circuit may include circuit elements distributed and disposed in non-pixel areas between pixels PXL (e.g., areas located in the display area DA and between adjacent pixels PXL and / or adjacent pixel groups PXG), as well as a first circuit element CRE1 and a second circuit element CRE2.

[0156] In this embodiment, the first circuit element CRE1 and the second circuit element CRE2 can be circuit elements constituting the gate driver GDR. For example, the first circuit element CRE1 can be the first transistor T1 of the i-th stage STi, and the second circuit element CRE2 can be the first capacitor C1 of the i-th stage STi (or another stage). The remaining circuit elements of the i-th stage STi and the circuit elements constituting the remaining stages of the gate driver GDR can also be distributed and arranged in the non-pixel area of ​​the display area DA.

[0157] When the first circuit element CRE1 is the first transistor T1 of the gate driver GDR, the display area DA may include a first clock line CL1 connected to the first transistor T1 to transmit a first clock signal CLK1. The display area DA may also include signal lines and / or power lines for transmitting drive signals and / or power to circuit elements formed in the display area DA.

[0158] For example, the first circuit element CRE1 can be a transistor connected to the first clock line CL1 and outputting the i-th gate signal to the i-th gate line using the first clock signal CLK1 input through the first clock line CL1. For example, the first circuit element CRE1 can be the first transistor T1 of the i-th stage STi that outputs the i-th scan signal SSi to the i-th scan line SLi using the first clock signal CLK1. In this case, the first circuit element CRE1 can also be connected to the Q node of the i-th stage STi and the first output terminal OUT1 (or the i-th scan line SLi).

[0159] In an embodiment, the first circuit element CRE1 may be disposed in the i-th pixel row. For example, the first circuit element CRE1 may be disposed between a first pixel group PXG1 and a second pixel group PXG2 disposed adjacent to each other in the i-th pixel row. The first circuit element CRE1 may be configured not to overlap with pixel PXL. For example, the first circuit element CRE1 may be disposed between a first unit pixel region UPA1 in which the first pixel group PXG1 can be positioned and a second unit pixel region UPA2 in which the second pixel group PXG2 can be positioned. The first circuit element CRE1 may be formed together with the circuit elements of the pixel circuit PXC during the process of forming the pixel circuit PXC.

[0160] In an embodiment, the first clock line CL1 may pass through the non-pixel region between two adjacent pixel rows and may extend in the display area DA along the first direction DR1. For example, the first clock line CL1 may extend in the display area DA along the first direction DR1 to pass through the region between the i-th pixel row and the (i+1)-th pixel row, and the end of the first clock line CL1 may be connected to the first circuit element CRE1.

[0161] In an embodiment, the first clock line CL1 may be located between two power lines formed between pixels PXL in two adjacent pixel rows. For example, the first circuit element CRE1 may be located in the non-pixel region between a first unit pixel region UPA1 and a second unit pixel region UPA2 arranged in parallel in the i-th pixel row, and the first clock line CL1 may be provided between the second power line PL2 connected to the pixel PXL in the i-th pixel row and the first power line PL1 connected to the pixel PXL in the (i+1)-th pixel row. The second power line PL2 connected to the pixel PXL in the i-th pixel row and the first power line PL1 connected to the pixel PXL in the (i+1)-th pixel row may be formed between the pixels PXL in the i-th pixel row and the pixel PXL in the (i+1)-th pixel row. When the first clock line CL1 is provided between two adjacent power lines, the problem of the first clock signal CLK1 affecting the operation of surrounding pixels PXL due to coupling or the like can be reduced or minimized. Therefore, the operating characteristics of the pixel PXL can be uniform and / or stable.

[0162] The second circuit element CRE2 can be located in the same or a different pixel row as the first circuit element CRE1. When the second circuit element CRE2 is directly connected to the first circuit element CRE1, it can be located around the first circuit element CRE1. For example, if the first circuit element CRE1 is located between the first pixel group PXG1 and the second pixel group PXG2 in the i-th pixel row, the second circuit element CRE2 can be located between the fifth pixel group PXG5 and the sixth pixel group PXG6 in the (i+1)-th pixel row. As an example, the second circuit element CRE2 can be located in a non-pixel region between the fifth unit pixel region UPA5, where the fifth pixel group PXG5 can be located, and the sixth unit pixel region UPA6, where the sixth pixel group PXG6 can be located.

[0163] The fifth pixel group PXG5 and the sixth pixel group PXG6 can be positioned around the first pixel group PXG1 and the second pixel group PXG2. For example, the first pixel group PXG1 and the fifth pixel group PXG5 can be arranged sequentially in the j-th pixel column, and the second pixel group PXG2 and the sixth pixel group PXG6 can be arranged sequentially in the (j+1)-th pixel column (where j can be a natural number greater than 0).

[0164] Figure 7 An embodiment is shown in which each of the first circuit element CRE1 and the second circuit element CRE2 can be disposed in a non-pixel region between adjacent unit pixel regions UPA, but the embodiment is not limited thereto. For example, in another embodiment, the first circuit element CRE1 and / or the second circuit element CRE2 can be disposed in a non-pixel region located between multiple pixels PXL in any one of the unit pixel regions UPA.

[0165] In an embodiment, the first circuit element CRE1 and the second circuit element CRE2 can be formed together with the circuit elements of the pixel circuit PXC. For example, in the transistors forming the pixel circuit PXC (e.g., Figure 3 The first transistor M1, the second transistor M2, and the third transistor M3 shown in the figure) and the capacitor (e.g., Figure 3 In the process of the capacitor Cst shown, the circuit elements of stage ST (including the first transistor T1 and the first capacitor C1 of stage ST) can be formed simultaneously. Therefore, the manufacturing cost of the display device DD can be reduced and the manufacturing efficiency can be improved.

[0166] A conductive pattern CDP may be disposed in the display area DA to be superimposed on the first circuit element CRE1. In an embodiment, where multiple first circuit elements CRE1 (e.g., multiple first transistors T1 included in multiple stages ST) are distributed and disposed in the display area DA, the display area DA may include multiple conductive patterns CDP superimposed on each of the first transistors T1, and each conductive pattern CDP has a separate pattern. In addition to the first circuit elements CRE1, the display area DA may also include at least one circuit element constituting a driving circuit, signal lines, and / or another conductive pattern (not shown) superimposed on a power supply line.

[0167] The conductive pattern CDP can also be superimposed on a portion of the first clock line CL1 connected to the first circuit element CRE1. For example, the conductive pattern CDP can be superimposed on the first clock line CL1 surrounding the first circuit element CRE1.

[0168] In an embodiment, where at least one signal line and / or power line is disposed around the first circuit element CRE1 and the first clock line CL1 (e.g., between the first circuit element CRE1 and the first clock line CL1), the conductive pattern CDP may also be superimposed on a portion of the at least one signal line and / or a portion of the power line. For example, the conductive pattern CDP may also be superimposed on a portion of the second scan line SL2 and a portion of the second power line PL2.

[0169] The conductive pattern CDP can be connected to a power line to which power can be supplied. For example, the conductive pattern CDP can be connected to an adjacent second power line PL2 to receive a second power supply VSS with a constant potential. In this case, the portions of the first circuit element CRE1 and the first clock line CL1 connected to the first circuit element CRE1 can be covered by the conductive pattern CDP connected to the second power supply VSS. Therefore, deviations in the size and / or parasitic capacitance formed between the first circuit element CRE1 and the first clock line CL1 and the pixels PXL surrounding the first circuit element CRE1 and the first clock line CL1 can be reduced or prevented. Thus, deviations in the characteristics of the pixel PXL can be reduced or prevented, and the image quality of the display device DD can be improved.

[0170] In an embodiment, the conductive pattern CDP can be formed without overlapping with the pixel PXL. For example, the conductive pattern CDP can be formed as a separate pattern (e.g., an island pattern) on a portion of the first clock line CL1 and the first circuit element CRE1, and can be separate from the adjacent pixel PXL.

[0171] The conductive pattern CDP can be formed together with the electrodes of the emitter unit EMU. For example, in the process of forming the first electrode ELT1 and the second electrode ELT2 of the emitter unit EMU, the conductive pattern CDP can be formed on the same layer as the first electrode ELT1 and the second electrode ELT2, and can be formed to at least cover the first circuit element CRE1. Therefore, the conductive pattern CDP can be easily formed in the process of forming the emitter unit EMU of the pixel PXL.

[0172] Figures 8 to 10 Each is a schematic plan view showing the display area DA of the display device DD according to an embodiment. For example, Figures 8 to 10 It shows the relationship with Figure 7 Different modified embodiments are described. Figures 8 to 10 In the implementation of the example, the terms that can be used with Figure 7 The construction of the embodiments is substantially similar to or the same as the description of the construction.

[0173] Reference Figures 1 to 8 At least one gate line GL can be disposed around the first circuit element CRE1 and / or the first clock line CL1, and a conductive pattern CDP can be superimposed on at least one gate line GL. For example, a first scan line SL1 and a second scan line SL2 can be disposed around the first circuit element CRE1, and the conductive pattern CDP can be superimposed on the portion of each of the first scan line SL1 and the second scan line SL2 around the first circuit element CRE1. Therefore, voltage variations in the gate signal (e.g., scan signal SS) caused by voltage variations in the first clock signal CLK1 input to the first clock line CL1 can be prevented, and pixel PXL can be driven stably.

[0174] Reference Figures 1 to 9 The conductive pattern CDP can be superimposed on the first circuit element CRE1 and the second circuit element CRE2 located around the first circuit element CRE1. For example, the conductive pattern CDP can have a wider area by extending from the area where the first circuit element CRE1 can be formed to the area where the second circuit element CRE2 can be formed. Therefore, the problem of the second circuit element CRE2 affecting the operation of the surrounding pixel PXL can be reduced or minimized.

[0175] Reference Figures 1 to 10The conductive pattern CDP can extend toward at least one adjacent pixel PXL and can be integrally connected to an electrode of at least one adjacent pixel PXL. For example, when the conductive pattern CDP is electrically connected to the second power line PL2, the conductive pattern CDP can extend to the region where the emitter unit EMU of at least one adjacent pixel PXL can be formed, and can be integrally formed with the second electrode ELT2 of the emitter unit EMU. For example, the conductive pattern CDP can extend to the region where the first emitter unit EMU1 of the second pixel group PXG2 can be formed, and can be integrally formed with the second electrode ELT2 of the first emitter unit EMU1. In this case, the conductive pattern CDP can be connected through the second contact hole CH2 formed in the first pixel PXL1 of the second pixel group PXG2. Figure 4 (as shown in the diagram) is connected to the second power line PL2 without forming a contact hole for connecting the conductive pattern CDP to the second power line PL2.

[0176] Figure 11 and Figure 12 These are schematic cross-sectional views showing the display area DA of the display device DD according to an embodiment. For example, Figure 11 and Figure 12 Different embodiments of the conductive pattern CDP are shown.

[0177] Figure 11 and Figure 12 A schematic cross-section of the display area DA, based on the first circuit element CRE1 and the conductive pattern CDP, and the third pixel PXL3 of the first pixel group PXG1 and the first pixel PXL1 of the second pixel group PXG2 located on both sides of the first circuit element CRE1, is shown. Figure 11 and Figure 12 The present invention discloses, as an example of a circuit element that can be disposed in a unit pixel region UPA of the circuit layer PCL, a first transistor M1 disposed in each pixel PXL, a first transistor T1 disposed in each stage ST as an example of a first circuit element CRE1, and a second power line PL2 disposed as an example of wiring that can be disposed on the circuit layer PCL. Pixels PXL of the display region DA may have substantially similar cross-sectional structures, but the size and / or shape of the circuit elements constituting each pixel PXL and the electrodes included in the circuit elements may vary depending on the embodiment.

[0178] Reference Figures 1 to 12 The display device DD may include a base layer BSL, a circuit layer PCL, and a display layer DPL. The circuit layer PCL and the display layer DPL may be stacked on top of each other on the base layer BSL. For example, the circuit layer PCL and the display layer DPL may be sequentially disposed on the surface of the base layer BSL.

[0179] Furthermore, the display device DD may also include a color filter layer CFL disposed on the display layer DPL. In an embodiment, the color filter layer CFL may be formed directly on the surface of the layer on which the circuit layer PCL and the display layer DPL may be formed, but the embodiment is not limited thereto. The display device DD may also include an encapsulation layer ENC that seals the surface of the base layer BSL on which the circuit layer PCL, the display layer DPL, and / or the color filter layer CFL may be formed.

[0180] The pixel circuit PXC constituting the pixel PXL of each pixel group PXG can be formed in each unit pixel region UPA of the circuit layer PCL. For example, circuit elements including a first transistor M1 can be formed in the region where each pixel circuit PXC is located. In embodiments, the circuit layer PCL may also optionally include a bottom metal layer BML of the first transistor M1, etc.

[0181] The circuit elements of the driving circuit can be formed in the non-pixel regions between the unit pixel regions UPA of the circuit layer PCL. For example, the first circuit element CRE1 can be formed between the first unit pixel region UPA1 and the second unit pixel region UPA2. In an embodiment, the first circuit element CRE1 can be the first transistor T1 of the i-th level STi. The first transistor T1 of the i-th level STi can be formed together with the first transistor M1 of the pixel circuit PXC on the base layer BSL.

[0182] The wiring (signal lines and power lines) connecting the circuit elements of the driving circuit and the pixel PXL can be formed in the circuit layer PCL. For example, scan lines SL, data lines DL, first power lines PL1, second power lines PL2, first clock lines CL1, etc., can be formed in the circuit layer PCL.

[0183] The circuit layer PCL may include insulating layers. For example, the circuit layer PCL may include a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, and / or a fourth insulating layer INS4 sequentially disposed on the surface of the base layer BSL.

[0184] The circuit layer PCL can be disposed on the base layer BSL and may optionally include a first conductive layer, which includes the bottom metal layer BML of the first transistor M1, etc. The first conductive layer can be disposed between the base layer BSL and the first insulating layer INS1, and may include the bottom metal layer BML superimposed on the gate electrode GE and / or semiconductor pattern SCP of each of the first transistors M1 in the pixel PXL. In an embodiment, the bottom metal layer BML may be connected to one electrode of the first transistor M1 (e.g., the source electrode or the drain electrode).

[0185] The first insulating layer INS1 can be disposed on the surface of the base layer BSL on which the first conductive layer is formed. The first insulating layer INS1 can prevent impurities from diffusing into each circuit element.

[0186] A semiconductor layer may be disposed on the first insulating layer INS1. The semiconductor layer may include a semiconductor pattern SCP for each transistor, etc. For example, the semiconductor layer may include a semiconductor pattern SCP for the first transistor M1 of pixel PXL and a semiconductor pattern SCP for the first transistor T1 of stage ST. Each semiconductor pattern SCP may include a channel region superimposed with the gate electrode GE of the corresponding transistor, and a first conductive region and a second conductive region (e.g., source region and drain region) disposed on the side of the channel region.

[0187] A semiconductor pattern (SCP) can be a semiconductor pattern made of polycrystalline silicon, amorphous silicon, oxide semiconductor, or a combination thereof. The first and second conductive regions of the semiconductor pattern (SCP) can be doped with dopants of different conductivity types.

[0188] In an embodiment, the first transistor M1 of pixel PXL and the first transistor T1 of stage ST may include a semiconductor pattern SCP formed of oxide semiconductor. The oxide semiconductor may include oxides of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), and / or oxides of combinations of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti). For example, the oxide semiconductor may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO). When the semiconductor pattern SCP of the first transistor M1 of pixel PXL and the semiconductor pattern SCP of the first transistor T1 of stage ST are formed of oxide semiconductor, the mobility of the first transistor M1 of pixel PXL and the mobility of the first transistor T1 of stage ST can be improved.

[0189] The second insulating layer INS2 can be disposed on the semiconductor layer. The second conductive layer can be disposed on the second insulating layer INS2.

[0190] The second conductive layer may include the gate electrode GE of each transistor, etc. The second conductive layer may also include capacitors disposed in the pixel circuit PXC and the stage ST (e.g., Figure 3 capacitor Cst and Figure 6 The electrodes, wiring, and / or bridging patterns of each of the first capacitor C1 and the second capacitor C2.

[0191] The third insulating layer INS3 can be disposed on the second conductive layer. The third conductive layer can be disposed on the third insulating layer INS3.

[0192] The third conductive layer may include the source electrode SE and drain electrode DE of each transistor. The third conductive layer may also include capacitors disposed in the pixel circuit PXC and stage ST (e.g., Figure 3 capacitor Cst and Figure 6 The electrodes, wiring, and / or bridging patterns of each of the first capacitor C1 and the second capacitor C2. As an example, the third conductive layer may include signal lines (such as scan lines SL or data lines DL), a first power line PL1, and / or a second power line PL2.

[0193] Each of the conductive patterns, electrodes, and wiring constituting the first to third conductive layers can be conductive by including at least one conductive material, and there are no particular limitations on the materials constituting them. For example, each of the conductive patterns, electrodes, and wiring constituting the first to third conductive layers may include at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), and may also include various conductive materials other than those listed above.

[0194] A fourth insulating layer INS4 may be disposed on the third conductive layer. In an embodiment, the fourth insulating layer INS4 may be a first planarization layer for planarizing the surface of the circuit layer PCL. For example, the fourth insulating layer INS4 may comprise at least an organic insulating layer and may substantially planarize the surface of the circuit layer PCL.

[0195] The display layer DPL can be set on the fourth insulating layer INS4.

[0196] Each of the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may consist of a single layer or multiple layers, and may include at least one inorganic insulating material and / or an organic insulating material. For example, each of the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may include various organic / inorganic insulating materials (including silicon nitride (SiN)). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y (or a combination thereof).

[0197] The display layer DPL may include an emission unit (EMU) for each pixel PXL. For example, the display layer DPL may include a first electrode ELT1, a second electrode ELT2, a light-emitting element (LD), a first contact electrode CNE1, and a second contact electrode CNE2 disposed in the emission region of each pixel PXL.

[0198] In addition, the display layer DPL may also include a fifth insulating layer INS5, a sixth insulating layer INS6, a dam BNK, an insulating pattern INP, a light conversion layer CCL, and / or a seventh insulating layer INS7. The fifth insulating layer INS5, the sixth insulating layer INS6, the dam BNK, the insulating pattern INP, the light conversion layer CCL, and / or the seventh insulating layer INS7 may be sequentially disposed on a surface on which the circuit layer PCL may be formed.

[0199] A fifth insulating layer INS5 may be disposed and / or formed on the fourth insulating layer INS4. In an embodiment, the fifth insulating layer INS5 may have an opening or groove corresponding to the emission region of each pixel PXL. For example, the fifth insulating layer INS5 may have an opening or groove corresponding to the emission region to surround the light-emitting element LD disposed in the emission region of each pixel PXL. In another embodiment, the fifth insulating layer INS5 may be formed by a separate pattern disposed separately under each of the first electrode ELT1 and the second electrode ELT2.

[0200] The first electrode ELT1 and the second electrode ELT2 can protrude upwards (e.g., towards the third direction DR3) from the periphery of the light-emitting element LD on the fifth insulating layer INS5. The fifth insulating layer INS5 and the first electrode ELT1 and the second electrode ELT2 on the fifth insulating layer INS5 can form a reflective protrusion pattern around the light-emitting element LD. Therefore, since the light emitted from the light-emitting element LD can be further guided towards the upper part of the pixel PXL, the light efficiency of the pixel PXL can be improved.

[0201] The fifth insulating layer INS5 may comprise an inorganic insulating layer made of inorganic materials or an organic insulating layer made of organic materials, or a combination thereof. The fifth insulating layer INS5 may be formed as a single layer or multiple layers, and its cross-sectional structure is not particularly limited.

[0202] The first electrode ELT1 and the second electrode ELT2 of the emitter unit EMU, as well as the conductive pattern CDP, can be formed on the fifth insulating layer INS5. For example, in each unit pixel region UPA, the first electrode ELT1 and the second electrode ELT2 of the emitter unit EMU constituting the corresponding pixel PXL can be formed on the fifth insulating layer INS5. In the region where the first circuit element CRE1, etc., can be formed, the conductive pattern CDP can be formed on the fifth insulating layer INS5.

[0203] In an embodiment, the conductive pattern CDP can be formed simultaneously with the first electrode ELT1 and the second electrode ELT2 of the pixel PXL. In this case, the conductive pattern CDP can be disposed on the same layer as the first electrode ELT1 and the second electrode ELT2 of the pixel PXL, and can include the same conductive material as the conductive material of the first electrode ELT1 and the second electrode ELT2.

[0204] The conductive pattern CDP may have an area larger than that of the first circuit element CRE1, so as to at least cover the first circuit element CRE1. For example, the conductive pattern CDP may cover the upper part of the first circuit element CRE1, and may also cover a portion of the first clock line CL1 and / or a portion of at least one scan line SL around the first circuit element CRE1.

[0205] In an embodiment, the conductive pattern CDP may have, for example... Figure 11 The diagram shows separate, individual patterns. In this case, the conductive pattern CDP can be connected to the second power line PL2 via the third contact hole CH3.

[0206] In another embodiment, such as Figure 12 As shown, the conductive pattern CDP can be connected to the second electrode ELT2 disposed in an adjacent pixel PXL (e.g., the first pixel PXL1 of the second pixel group PXG2), and can be integrally formed with the second electrode ELT2. In this case, the conductive pattern CDP can share the second contact hole CH2 with the second electrode ELT2, and can be connected to the second power line PL2 through the second contact hole CH2.

[0207] The first electrode ELT1 and the second electrode ELT2 can be disposed on the fifth insulating layer INS5 to have a surface profile corresponding to the shape of the fifth insulating layer INS5. Each first electrode ELT1 can be connected to the first transistor M1 of the corresponding pixel PXL through the first contact hole CH1, and each second electrode ELT2 can be connected to the second power line PL2 through the second contact hole CH2.

[0208] The first electrode ELT1 and the second electrode ELT2 may comprise at least one conductive material. For example, the first electrode ELT1 and the second electrode ELT2 may comprise at least one metal selected from various metallic materials (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), and copper (Cu), and alloys thereof). The first electrode ELT1 and the second electrode ELT2 may comprise at least one conductive material selected from conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO)) and conductive polymers (such as PEDOT). However, the embodiments are not limited thereto. For example, the first electrode ELT1 and the second electrode ELT2 may comprise other conductive materials (such as carbon nanotubes or graphene). For example, the first electrode ELT1 and the second electrode ELT2 can be conductive by including at least one of a variety of conductive materials. The first electrode ELT1 and the second electrode ELT2 can include conductive materials that may be the same as or different from each other.

[0209] Each of the first electrode ELT1 and the second electrode ELT2 may consist of a single layer or multiple layers. For example, the first electrode ELT1 and the second electrode ELT2 may include a reflective electrode layer comprising a reflective conductive material (e.g., a metal). The first electrode ELT1 and the second electrode ELT2 may also optionally include at least one of a transparent electrode layer disposed above and / or below the reflective electrode layer and a conductive capping layer covering the upper part of the reflective electrode layer and / or the transparent electrode layer.

[0210] A sixth insulating layer INS6 may be disposed on the first electrode ELT1, the second electrode ELT2, and the conductive pattern CDP. In one embodiment, the sixth insulating layer INS6 may be formed on the entire upper surface of the display area DA in which the first electrode ELT1, the second electrode ELT2, and the conductive pattern CDP may be formed, and may include openings that expose portions of the first electrode ELT1 and the second electrode ELT2, respectively. In another embodiment, the sixth insulating layer INS6 may include a plurality of contact holes for connecting the first electrode ELT1 and the second electrode ELT2 to the first contact electrode CNE1 and the second contact electrode CNE2, respectively. In the area where the sixth insulating layer INS6 may be exposed (or in the area where contact holes may be formed in the sixth insulating layer INS6), the first electrode ELT1 and the second electrode ELT2 may be connected to the first contact electrode CNE1 and the second contact electrode CNE2, respectively.

[0211] The sixth insulating layer INS6 may consist of a single layer or multiple layers and may include at least one inorganic insulating material and / or an organic insulating material. In embodiments, the sixth insulating layer INS6 may include at least one inorganic insulating material (such as silicon nitride (SiN)). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y (or a combination thereof).

[0212] Since the first electrode ELT1, the second electrode ELT2, and the conductive pattern CDP can be covered by the sixth insulating layer INS6, damage to the first electrode ELT1, the second electrode ELT2, and the conductive pattern CDP in subsequent processes can be prevented. Short-circuit defects that might result in incorrect connection between the first electrode ELT1, the second electrode ELT2, and the light-emitting element LD can also be prevented.

[0213] In the emission region corresponding to the emission unit EMU of pixel PXL, a light-emitting element LD can be supplied on the sixth insulating layer INS6 and aligned on the sixth insulating layer INS6. The light-emitting element LD can be aligned between the first electrode ELT1 and the second electrode ELT2 of the corresponding emission unit EMU.

[0214] Each light-emitting element (LD) may include a first semiconductor layer SCL1 (e.g., a P-type semiconductor layer), an active layer ACT, and a second semiconductor layer SCL2 (e.g., an N-type semiconductor layer) sequentially disposed in any direction (e.g., from the first end EP1 to the second end EP2). Each light-emitting element (LD) may also include an insulating film surrounding the outer peripheral surfaces (e.g., the side surfaces of a cylinder) of the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2.

[0215] The first semiconductor layer SCL1 may include a semiconductor layer of a first conductivity type. For example, the first semiconductor layer SCL1 may include at least one P-type semiconductor layer. For example, the first semiconductor layer SCL1 may include a P-type semiconductor layer comprising at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first conductivity type dopant (or P-type dopant) such as Mg.

[0216] The active layer ACT can be formed in a single quantum well structure or a multi-quantum well structure. According to embodiments, materials such as AlGaN and AlInGaN can be used to form the active layer ACT, and in addition to these, the active layer ACT can be formed from a variety of other materials. The location of the active layer ACT can vary depending on the type of light-emitting element LD. The active layer ACT can emit light with a wavelength of approximately 400 nm to approximately 900 nm, and a dual heterostructure can be used.

[0217] The second semiconductor layer SCL2 may include a semiconductor layer of a different type from the first semiconductor layer SCL1. For example, the second semiconductor layer SCL2 may include at least one N-type semiconductor layer. As an example, the second semiconductor layer SCL2 may be an N-type semiconductor layer comprising at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductivity type dopant (or N-type dopant) such as Si, Ge, Sn, etc.

[0218] Before supplying the light-emitting element LD, a dam BNK can be formed around the emitting region of pixel PXL. For example, the dam BNK can be formed on the sixth insulating layer INS6 to surround the emitting region of pixel PXL. Therefore, each emitting region to which the light-emitting element LD will be supplied can be defined. For example, the dam BNK can be a pixel defining layer including multiple openings corresponding to the emitting region of pixel PXL. The dam BNK can be formed to cover the outer region of pixel PXL, the region where circuit elements of driving circuitry can be formed, and / or the non-pixel regions between pixels PXL. The dam BNK can include a black matrix material and light-shielding and / or reflective materials. This prevents optical interference between pixels PXL.

[0219] An insulating pattern INP can be formed on a portion of the light-emitting element LD. For example, each insulating pattern INP can be locally formed on a portion of the light-emitting element LD including the central portion, exposing the first end EP1 and the second end EP2 of the light-emitting element LD aligned with the corresponding emission region. When the insulating pattern INP can be formed on the light-emitting element LD, the light-emitting element LD can be stably fixed.

[0220] An insulating pattern INP can consist of a single layer or multiple layers and can include at least one inorganic insulating material and / or an organic insulating material. For example, an insulating pattern INP can include various organic / inorganic insulating materials (such as silicon nitride (SiN)). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (Al) x O y( ), photoresist (PR) materials, etc.) or combinations thereof.

[0221] The first contact electrode CNE1 and the second contact electrode CNE2 can be formed on both ends (e.g., the first end EP1 and the second end EP2 of the light-emitting element LD that are not covered by the insulating pattern INP).

[0222] The first contact electrode CNE1 and the second contact electrode CNE2 can be formed separately from each other. For example, the first contact electrode CNE1 and the second contact electrode CNE2 of each pixel PXL can be configured to be spaced apart from each other on the first end EP1 and the second end EP2 of the light-emitting element LD, with an insulating pattern INP placed between the first contact electrode CNE1 and the second contact electrode CNE2. Therefore, the first contact electrode CNE1 can be connected to the first end EP1 of the light-emitting element LD disposed in the corresponding pixel PXL, and the second contact electrode CNE2 can be connected to the second end EP2 of the light-emitting element LD.

[0223] The first contact electrode CNE1 can be disposed above the first electrode ELT1 to connect to the first electrode ELT1 of the corresponding pixel PXL, and the second contact electrode CNE2 can be disposed above the second electrode ELT2 to connect to the second electrode ELT2 of the corresponding pixel PXL. Therefore, the first end EP1 of the light-emitting element LD can be connected to the first electrode ELT1 of the corresponding pixel PXL, and the second end EP2 of the light-emitting element LD can be connected to the second electrode ELT2 of the corresponding pixel PXL.

[0224] The first contact electrode CNE1 and the second contact electrode CNE2 may comprise at least one conductive material. In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may comprise a transparent conductive material, allowing light emitted from the light-emitting element LD to be transmitted.

[0225] In an embodiment, the display device DD may further include a light conversion layer CCL disposed on the light-emitting element LD. For example, the light conversion layer CCL may be selectively disposed on each emitting unit (EMU) on which the light-emitting element LD may be arranged.

[0226] The light conversion layer (CCL) may include wavelength conversion particles (or color conversion particles) that convert the wavelength and / or color of light emitted from the light-emitting element (LD) and / or light scattering particles (SCTs) that increase luminous efficiency by scattering light emitted from the LD. For example, each CCL comprising wavelength conversion particles and / or light scattering particles (SCTs) may be provided on each emission unit (EMU), wherein the wavelength conversion particles comprise at least one quantum dot (QD) (e.g., red quantum dot, green quantum dot, and / or blue quantum dot). For example, if any pixel PXL is set as a red (or green) pixel and a blue light-emitting element (LD) may be provided in the emission unit (EMU) of pixel PXL, a CCL comprising red (or green) quantum dot (QD) particles for converting blue light into red (or green) light may be provided on the emission unit (EMU) of pixel PXL. The CCL may also include light scattering particles (SCTs).

[0227] The seventh insulating layer INS7 can be formed on the surface of the light conversion layer CCL and the embankment BNK.

[0228] In an embodiment, the seventh insulating layer INS7 may be a second planarization layer for protecting the transmitting unit EMU and / or the light conversion layer CCL and substantially planarizing the surface of the display layer DPL. For example, the seventh insulating layer INS7 may include at least an organic insulating layer.

[0229] The color filter layer CFL can be set on the seventh insulating layer INS7.

[0230] The color filter layer CFL may include a color filter CF corresponding to the color of each pixel PXL. For example, the color filter layer CFL may include a first color filter CF1 disposed on a first emission unit EMU1 of the first pixel PXL1, a second color filter CF2 disposed on a second emission unit EMU2 of the second pixel PXL2, and a third color filter CF3 disposed on a third emission unit EMU3 of the third pixel PXL3. In an embodiment, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be configured to overlap each other in a non-emission region in which a dam BNK may be formed to block optical interference between pixels PXL. In another embodiment, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be separate patterns formed individually on the emission regions of the first emission unit EMU1, the second emission unit EMU2, and the third emission unit EMU3 (specifically, the emission regions of each of the first emission unit EMU1, the second emission unit EMU2, and the third emission unit EMU3). A light-blocking pattern (not shown) may be disposed between the first transmitting unit EMU1, the second transmitting unit EMU2, and the third transmitting unit EMU3.

[0231] The encapsulation layer ENC may be disposed on the color filter layer CFL. The encapsulation layer ENC may include at least one insulating layer containing an eighth insulating layer INS8. The eighth insulating layer INS8 may be formed on the entire surface of the display area DA to cover the circuit layer PCL, the display layer DPL, and / or the color filter layer CFL.

[0232] The eighth insulating layer INS8 may include at least one of an inorganic layer and an organic layer. For example, the eighth insulating layer INS8 may consist of a single layer or multiple layers and may include at least one inorganic insulating material and / or an organic insulating material. For example, the eighth insulating layer INS8 may include various organic / inorganic insulating materials (such as silicon nitride (SiN)). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (Al) x O y (or a combination thereof).

[0233] In embodiments, the eighth insulating layer INS8 can be formed in a multilayer structure. For example, the eighth insulating layer INS8 can be formed of a multilayer thin-film encapsulation layer comprising at least two inorganic insulating layers and at least one organic insulating layer disposed between the at least two inorganic insulating layers. However, the material and / or structure of the eighth insulating layer INS8 can be varied. According to embodiments, at least one outer coating layer, a filler layer, and / or an upper substrate can also be provided on the eighth insulating layer INS8.

[0234] Figure 13 This is a schematic plan view illustrating components arranged in the display area DA of the display device DD according to an embodiment. For example, Figure 13 This shows that it can form Figure 7 A plan view of an example of the regions of the first pixel group PXG1, the second pixel group PXG2, the first circuit element CRE1, and the conductive pattern CDP. Some configurations of the first pixel group PXG1, the second pixel group PXG2, the first circuit element CRE1, and the conductive pattern CDP are shown.

[0235] For example, Figure 13The diagram shows some electrodes of the first circuit element CRE1 (e.g., the source electrode T1_SE and drain electrode T1_DE of the first transistor T1), the first clock line CL1, and some configurations of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 located around the first circuit element CRE1 and the first clock line CL1 and formed on the same layer as the electrodes, the first scan line SL1, the second scan line SL2, the first power line PL1, and the second power line PL2 (e.g., the source electrode M1_SE of the first transistor M1 of each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, and the capacitor Cst are integrally connected to an electrode CE of the source electrode M1_SE). Figure 13 The conductive pattern CDP and the first electrode ELT1 and the second electrode ELT2 of each of the first pixel PXL1, the second pixel PXL2 and the third pixel PXL3, which are formed on the same layer as the conductive pattern CDP, are shown.

[0236] Reference Figures 7 to 13 The source electrode T1_SE and drain electrode T1_DE of the first transistor T1 constituting the first circuit element CRE1, as well as the first clock line CL1, can be disposed on the same layer. The drain electrode T1_DE and the first clock line CL1 of the first transistor T1 can be electrically connected to each other through a bridging pattern BRP disposed on a different layer than the drain electrode T1_DE and the first clock line CL1.

[0237] Each of the first pixel PXL1, second pixel PXL2, and third pixel PXL3 in the first pixel group PXG1 and the second pixel group PXG2 may include a first transistor M1 and a capacitor Cst. The source electrode M1_SE of the first transistor M1 and one electrode CE of the capacitor Cst may be disposed on the same layer as the first circuit element CRE1 and the first clock line CL1, so as to be adjacent to the first circuit element CRE1 and the first clock line CL1. Therefore, it is possible that the source electrode M1_SE of the first transistor M1 and one electrode CE of the capacitor Cst may be connected to the second node N2 of its pixel PXL (…). Figure 3 Parasitic capacitance is generated between the first circuit element CRE1 (specifically, the source electrode T1_SE and drain electrode T1_DE of the first transistor T1) and the first clock line CL1.

[0238] In the embodiments, the magnitude of the parasitic capacitance formed in the second node N2 of each pixel PXL due to the first circuit element CRE1 and the first clock line CL1 may be different for each pixel PXL. For example, in the first pixel group PXG1, since the source electrode M1_SE of the first transistor M1 included in the third pixel PXL3 can be set closest to the source electrode T1_SE and drain electrode T1_DE of the first circuit element CRE1, the parasitic capacitance formed in the second node N2 of the third pixel PXL3 can be greater than the parasitic capacitance formed in the second node N2 of each of the first pixel PXL1 and the second pixel PXL2. In the second pixel group PXG2, since the source electrode M1_SE of the first transistor M1 included in the first pixel PXL1 can be set closest to the source electrode T1_SE and drain electrode T1_DE of the first circuit element CRE1, the parasitic capacitance formed in the second node N2 of the first pixel PXL1 can be greater than the parasitic capacitance formed in the second node N2 of each of the second pixel PXL2 and the third pixel PXL3.

[0239] For example, the parasitic capacitances formed in pixel PXL due to the first circuit element CRE1 and the first clock line CL1 can be different from each other. Deviations in parasitic capacitance can lead to image quality defects by altering the operating characteristics of pixel PXL.

[0240] To prevent such image quality defects, in the disclosed embodiments, a conductive pattern CDP can be formed on the first circuit element CRE1 and / or the first clock line CL1, and the conductive pattern CDP can be connected to an adjacent power line (e.g., a second power line PL2). Therefore, the magnitude and / or deviation of the parasitic capacitance formed between the source electrode T1_SE and drain electrode T1_DE of the first circuit element CRE1 and between the first clock line CL1 and the second node N2 of the pixel PXL can be reduced. Thus, according to the disclosed embodiments, deviations in the characteristics of the pixel PXL can be reduced or prevented, and the image quality of the display device DD can be improved.

[0241] In the above embodiments, the conductive pattern CDP can be formed simultaneously on the same layer as the first electrode ELT1 and the second electrode ELT2, but the embodiments are not limited to this. For example, the conductive pattern CDP can be formed with other electrodes of the transmitting unit EMU (e.g., Figure 4 , Figure 11 and Figure 12 The first contact electrode CNE1 and the second contact electrode CNE2 shown are formed simultaneously on the same layer. For example, the conductive pattern CDP can be formed simultaneously with the electrode disposed on the transmitter unit EMU of the display layer DPL, and can be formed as the first circuit element CRE1 and / or the first clock line CL1 of the shielding circuit layer PCL.

[0242] According to an embodiment, the circuit elements of the driving circuit can be arranged between pixels in the display area. This reduces the manufacturing cost of the display device and decreases the size of the non-display area.

[0243] Furthermore, according to an embodiment, the conductive pattern superimposed on the circuit elements of the driving circuit can be disposed on the same layer as the first and second electrodes of the pixel, and the conductive pattern can be connected to the second power line. Therefore, deviations in pixel characteristics caused by parasitic capacitance formed between the circuit elements of the driving circuit and the signal lines connected to the circuit elements of the driving circuit and the pixel can be reduced or prevented, thereby improving the image quality of the display device. The conductive pattern can be easily formed in the process of forming the emitting unit of the pixel.

[0244] The effects of the embodiments are not limited to the foregoing, and the additional effects are at least inherent in the disclosure.

[0245] Although the disclosed technical spirit has been described in detail through the above embodiments, it should be noted that the above embodiments are for illustrative purposes only and are not intended to limit the disclosure. Those skilled in the art will understand that various modifications are possible within the scope of the disclosed technical spirit.

[0246] The scope of the disclosure is not limited to the specific embodiments described in the specification, but should be defined by the appended claims, including their equivalents. Furthermore, all changes or modifications to the disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included within the scope of the disclosure.

Claims

1. A display device, the display device comprising: Gate lines and data lines are located in the display area; A pixel is disposed in the display area, and the pixel is electrically connected to the gate line, the data line, the first power line and the second power line; A driving circuit supplies gate signals and data signals to the gate line and the data line respectively, and the driving circuit includes a first circuit element disposed between the pixels in the display area; as well as A conductive pattern is disposed in the display area and superimposed on the first circuit element, the conductive pattern being electrically connected to the second power line, wherein... Each of the pixels includes: a first electrode electrically connected to the first power line; a second electrode electrically connected to the second power line; and at least one light-emitting element disposed between the first electrode and the second electrode. The conductive pattern, the first electrode, and the second electrode are disposed on the same layer. The driving circuit includes a gate driver, which includes an i-th stage. The i-th stage includes the first circuit element, which is a transistor connected to a first clock line that transmits a first clock signal and uses the first clock signal to output the i-th gate signal to the i-th gate line.

2. The display device as claimed in claim 1, wherein, The display area includes a first clock line electrically connected to the first circuit element and transmitting a first clock signal, and The conductive pattern is superimposed on the first clock line.

3. The display device as claimed in claim 2, wherein, The first clock line extends in a first direction and passes through the area between the i-th pixel row and the (i+1)-th pixel row of the display area.

4. The display device as claimed in claim 3, wherein, The first circuit element is disposed in a non-pixel region between two unit pixel regions arranged parallel to each other in the i-th pixel row, and The first clock line is positioned between the second power line connected to the pixel in the i-th pixel row and the first power line connected to the pixel in the (i+1)-th pixel row.

5. The display device as claimed in claim 2, wherein, The conductive pattern is a separate pattern on the first clock line and on the first circuit element that does not overlap with the pixel.

6. The display device as claimed in claim 1, wherein, The display area includes at least one gate line adjacent to the first circuit element, and The conductive pattern is superimposed on the at least one gate line.

7. The display device as claimed in claim 1, wherein, The driving circuit further includes a second circuit element disposed adjacent to the first circuit element in the display area, and The conductive pattern is superimposed on the first circuit element and the second circuit element.

8. The display device as claimed in claim 1, wherein, The conductive pattern is adjacent to at least one pixel, and The conductive pattern and the second electrode of the at least one pixel are integral with each other.

9. The display device as claimed in claim 1, wherein, The gate driver includes a circuit element, the circuit element including the first circuit element and disposed between the pixels, and The data driver outputs the data signal to the data line.

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