Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a substrate, including a substrate and a fin protruding from the substrate, wherein a dummy gate structure spanning the fin is formed on the substrate; cutting the dummy gate structure to form an isolation opening, the isolation opening dividing the dummy gate structure in the extending direction of the dummy gate structure; and smoothing the dummy gate structure exposed on the sidewall of the isolation opening. By smoothing the dummy gate structure exposed on the sidewall of the isolation opening, the surface smoothness of the sidewall of the isolation opening is improved. Therefore, the uniformity of the opening size of the isolation opening is improved. In the subsequent process of removing the dummy gate structure, it is beneficial to clean the dummy gate structure between the sidewall of the isolation opening and the adjacent fin, reducing residue residue. At the same time, obtaining an isolation opening with higher sidewall smoothness helps to reduce the stress when filling the isolation opening with material, and correspondingly reduces the probability of bending of the fin adjacent to the sidewall of the isolation opening, thereby improving the working performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the gate size of planar transistors is becoming shorter and shorter. Traditional planar transistors have a weaker ability to control channel current, resulting in short-channel effects, leakage current, and ultimately affecting the electrical performance of semiconductor devices.

[0003] To better accommodate the shrinking feature size, semiconductor manufacturing processes are gradually transitioning from planar MOSFETs to more efficient three-dimensional transistors, such as FinFETs. Currently, the gate fabrication process typically employs a polycut technique to cut the strip-shaped gate. The cut gate corresponds to different transistors, improving transistor integration. Furthermore, when multiple gates are arranged in a row along the extension direction, the polycut technique allows for highly precise reduction of the spacing in the mating direction between the disconnected gates (PolyCut CD). Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby improving the working performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a fin protruding from the substrate, wherein a pseudo-gate structure is formed on the substrate spanning the fin, the pseudo-gate structure covering a portion of the top and a portion of the sidewalls of the fin; cutting the pseudo-gate structure to form a partition opening, the partition opening dividing the pseudo-gate structure in the extending direction of the pseudo-gate structure; and smoothing the pseudo-gate structure exposed on the sidewalls of the partition opening.

[0006] Optionally, the smoothing process includes: forming a reaction layer within the partition opening, the reaction layer conformally covering the sidewall of the partition opening, and the reaction layer and the pseudo-gate structure being made of the same material; after forming the reaction layer, performing an annealing process to re-bond the materials of the reaction layer and the pseudo-gate structure exposed at the interface between the reaction layer and the sidewall of the partition opening, thereby transforming the reaction layer into a smooth layer.

[0007] Optionally, a rapid thermal annealing process can be used to perform the annealing treatment.

[0008] Optionally, the annealing process may be performed in a nitrogen-containing gas atmosphere.

[0009] Optionally, after forming the smoothing layer, the process further includes removing the smoothing layer.

[0010] Optionally, the step of removing the smoothing layer includes: modifying the smoothing layer to convert it into a sacrificial layer, wherein the etch resistance of the sacrificial layer is less than that of the smoothing layer; and removing the sacrificial layer.

[0011] Optionally, in the modification process, the smoothing layer is oxidized to transform it into a sacrificial layer.

[0012] Optionally, after smoothing the exposed pseudo-gate structure on the sidewall of the partition opening, the method further includes: forming a partition structure within the partition opening.

[0013] Optionally, the partition opening can be formed using a dry etching process.

[0014] Optionally, the dry etching process includes inductively coupled plasma etching.

[0015] Optionally, the reaction layer may be formed using a chemical vapor deposition process.

[0016] Optionally, the process parameters of the chemical vapor deposition process include: a process temperature of 250°C to 450°C and a process time of 8 to 12 hours.

[0017] Optionally, the process parameters of the rapid thermal annealing process include: the annealing gas is nitrogen, the gas flow rate of the annealing gas is 300 standard milliliters per minute to 500 standard milliliters per minute, the process temperature is 600°C to 800°C, and the process time is 10 seconds to 30 seconds.

[0018] Optionally, the process parameters for oxidizing the smooth layer include: the oxidizing gas is oxygen, the process pressure is 5mT to 20mT, the gas flow rate of the oxidizing gas is 200 standard milliliters per minute to 500 standard milliliters per minute, the source power is 500W to 1000W, and the process time is 15 seconds to 60 seconds.

[0019] Optionally, the sacrificial layer can be removed using a wet etching process.

[0020] Optionally, the etching solution in the wet etching process includes a mixture of diluted hydrofluoric acid solution, sulfuric acid and hydrogen peroxide solution, and standard cleaning solution No. 1.

[0021] Optionally, the material of the sacrificial layer includes silicon oxide.

[0022] Optionally, the thickness of the reaction layer is to

[0023] Optionally, the material of the pseudo-gate structure includes one or both of amorphous silicon and polycrystalline silicon.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0025] In the forming method provided by this embodiment of the invention, the dummy gate structure is cut to form an opening, and then the exposed dummy gate structure on the sidewall of the opening is smoothed. By smoothing the exposed dummy gate structure on the sidewall of the opening, this embodiment of the invention improves the surface smoothness of the sidewall of the opening, resulting in an opening with higher sidewall smoothness. This also improves the uniformity of the opening size and reduces the probability that the distance between the sidewall of the opening and the adjacent fin is too small. Therefore, in the subsequent process of removing the dummy gate structure, it is beneficial to clean the dummy gate structure between the sidewall of the opening and the adjacent fin, reducing residue. Simultaneously, obtaining an opening with higher sidewall smoothness helps reduce stress when filling the opening with material, thus reducing the probability of bending of the fin adjacent to the sidewall of the opening. This also reduces the probability of the distance between the sidewall of the opening and the adjacent fin being too small, and consequently, it also helps to clean the dummy gate structure between the sidewall of the opening and the adjacent fin, thereby improving the working performance of the semiconductor structure. Attached Figure Description

[0026] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0027] Figures 4 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0028] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons for this need to improve performance using a semiconductor structure formation method as an example.

[0029] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0030] refer to Figure 1A substrate (not shown) is provided, including a substrate 10 and a fin 12 protruding from the substrate 10, wherein a pseudo-gate structure 20 is formed on the substrate 10 across the fin 12, the pseudo-gate structure 20 covering a portion of the top and a portion of the sidewalls of the fin 12.

[0031] Specifically, a hard mask layer 30 is also formed on the pseudo gate structure 20, and an opening 33 is formed in the hard mask layer 30. The hard mask layer 30 is used as an etching mask for subsequent cutting of the pseudo gate structure 20.

[0032] refer to Figure 2 Remove opening 33 (e.g.) Figure 1 The pseudo-gate structure 20 exposed (as shown) is cut off to form a partition opening 21, which divides the pseudo-gate structure 20 in the extending direction of the pseudo-gate structure 20.

[0033] refer to Figure 3 In the partition opening 21 (e.g. Figure 2 As shown, a partition structure 50 is formed in the partition structure.

[0034] It should be noted that in the actual process, the pseudo-gate structure 20 is first subjected to a dry etching process to remove the pseudo-gate structure 20 exposed by the opening 33, forming a separation opening 21. During the dry etching process, the sidewall 22 of the separation opening 21 (i.e. the end of the pseudo-gate structure 20 exposed by the separation opening 21) will be oxidized, and an oxide layer will be formed on the sidewall 22. Then, a wet etching process is required to remove the oxide layer and clean the residue from the separation opening 21.

[0035] The dry etching process creates a poorly smooth and excessively rough sidewall 22 of the partition opening 21, which can easily lead to uneven grain size in the microstructure of the sidewall 22. When wet etching is then performed on the partition opening 21, the etching rate varies depending on the grain size of the pseudo-gate structure 20. The etching solution has a faster etching rate for pseudo-gate structures 20 with smaller grain sizes, further worsening the roughness of the sidewall and the uniformity of the opening size of the partition opening 21. Consequently, the uniformity of the distance between the sidewall 22 of the partition opening 21 and the adjacent fin 12 also deteriorates, potentially resulting in an excessively small distance between the sidewall 22 of the partition opening 21 and the adjacent fin 12. In the subsequent process of removing the pseudo-gate structure 20, it becomes difficult to completely remove the pseudo-gate structure 20 between the sidewall 22 of the partition opening 21 and the adjacent fin 12, leaving residue that affects the performance of the semiconductor structure. Furthermore, due to the poor smoothness of the sidewall 22 of the partition opening 21 and the poor uniformity of the opening size of the partition opening 21, the stress during the formation of the partition structure 50 is easily increased, which can easily lead to bending of the fin 12 adjacent to the sidewall 22 of the partition opening 21. The bending of the fin 12 not only easily has an adverse effect on the performance of the transistor, but also easily leads to an excessively small distance between the sidewall 22 of the partition opening 21 and the adjacent fin 12, making it difficult to completely remove the pseudo-gate structure 20 between the sidewall 22 of the partition opening 21 and the adjacent fin 12, thereby affecting the working performance of the semiconductor structure.

[0036] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a fin protruding from the substrate, wherein a pseudo-gate structure is formed on the substrate spanning the fin, the pseudo-gate structure covering a portion of the top and a portion of the sidewalls of the fin; cutting the pseudo-gate structure to form a partition opening, the partition opening dividing the pseudo-gate structure in the extending direction of the pseudo-gate structure; and smoothing the pseudo-gate structure exposed on the sidewalls of the partition opening.

[0037] In the forming method provided by this embodiment of the invention, the pseudo-gate structure is cut to form a partition opening, and then the pseudo-gate structure exposed on the sidewall of the partition opening is smoothed. This embodiment of the invention improves the surface smoothness of the sidewall of the partition opening by smoothing the exposed pseudo-gate structure, resulting in a partition opening with higher sidewall smoothness. This also improves the sidewall smoothness of the partition opening, enhances the uniformity of the opening size, and reduces the probability of the distance between the sidewall of the partition opening and adjacent fins being too small. Therefore, in subsequent removal of the pseudo-gate structure... In the fabrication process of the pseudo-gate structure, it is beneficial to thoroughly remove the pseudo-gate structure between the partition opening sidewall and the adjacent fin, reducing residue residue. At the same time, obtaining a partition opening with a high sidewall smoothness helps to reduce the stress when filling the partition opening with material later, thereby reducing the probability of bending of the fin adjacent to the partition opening sidewall. This also reduces the probability that the distance between the partition opening sidewall and the adjacent fin is too small, which in turn helps to thoroughly remove the pseudo-gate structure between the partition opening sidewall and the adjacent fin, thereby improving the working performance of the semiconductor structure.

[0038] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figures 4 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0040] refer to Figure 4 A substrate (not shown) is provided, including a substrate 100 and a fin 120 protruding from the substrate 100, wherein a pseudo-gate structure 200 is formed on the substrate 100 across the fin 120, the pseudo-gate structure 200 covering a portion of the top and a portion of the sidewalls of the fin 120.

[0041] The substrate provides the basis for the process operation of forming the semiconductor structure.

[0042] In this embodiment, the substrate includes a substrate 100, and the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The material of the substrate 100 may be a material suitable for process requirements or easy to integrate.

[0043] The fin 120 is used to provide a channel for the fin field-effect transistor.

[0044] In this embodiment, the fin 120 and the substrate 100 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving precise control over the height of the fin.

[0045] In this embodiment, the material of the fin 120 is the same as the material of the substrate 100, and the material of the fin 120 is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin may also be different from the material of the substrate.

[0046] In this embodiment, the substrate further includes an isolation layer 110, which covers a portion of the sidewall of the fin 120.

[0047] The isolation layer 110 is used to achieve insulation between different devices.

[0048] The insulating layer 110 is made of an insulating material. As an example, the insulating layer 110 is made of silicon oxide.

[0049] The pseudo-gate structure 200 occupies space for the subsequent formation of the metal gate structure.

[0050] The pseudo-gate structure 200 can be a single-layer structure or a stacked structure. In this embodiment, the pseudo-gate structure 200 is a single-layer structure.

[0051] In this embodiment, the material of the pseudo-gate structure 200 includes one or both of amorphous silicon and polycrystalline silicon. As an example, the material of the pseudo-gate structure 200 is amorphous silicon.

[0052] In this embodiment, a hard mask layer 300 is also formed on the pseudo gate structure 200.

[0053] The hard mask layer 300 is used as an etching mask in the subsequent process of forming the isolation opening.

[0054] In this embodiment, the hard mask layer 300 is a non-metallic mask layer, and the material of the hard mask layer 300 includes one or more of silicon oxide and silicon nitride, that is, the mask layer 300 can be a single-layer structure or a multilayer structure. In this embodiment, the material of the mask layer 300 includes silicon oxide and silicon nitride, that is, the mask layer 300 is a multilayer structure, including a silicon nitride layer 310 and a silicon oxide layer 320 covering the silicon nitride layer 310.

[0055] In this embodiment, a pattern transfer layer (not shown) is also formed on the hard mask layer 300. The pattern transfer layer includes a planarization layer 400, an anti-reflection coating 410 on the planarization layer 400, and a photoresist layer 420 on the anti-reflection coating 410. An opening 430 is formed in the pattern transfer layer.

[0056] The graphics transfer layer with opening 430 is used to transfer graphics, which are then used to pattern the hard mask layer 300.

[0057] In this embodiment, the planarization layer 400 is made of spin-on carbon (SOC). Spin-on carbon is formed by a spin coating process, which has a low processing cost. Moreover, by using spin-on carbon, the flatness of the top surface of the planarization layer 400 is improved, thereby providing a good interface for the formation of the opening 430.

[0058] In this embodiment, the material of the anti-reflective layer 410 is Si-ARC (silicon-containing anti-reflective coating) material.

[0059] In this embodiment, the photoresist layer 420 serves as a mask for forming the opening 430. After patterning the photoresist layer 420, the anti-reflection coating 410 and the planarization layer 400 are sequentially etched using the photoresist layer 420 as a mask to form the opening 430.

[0060] Reference Figure 5 and Figure 6 The pseudo-gate structure 200 is polycut to form a partition opening 210, which divides the pseudo-gate structure 200 in the extending direction of the pseudo-gate structure 200.

[0061] By cutting off the transistor, the integration density can be improved, and the distance of the line end of the disconnected pseudo-gate structure 200 can be reduced with high precision in the extension direction of the pseudo-gate structure 200.

[0062] The partition opening 210 is used to provide space for the subsequent formation of the partition structure.

[0063] In this embodiment, before forming the metal gate structure, the pseudo gate structure 200 is cut off, so that the partition opening 210 can be smoothed in advance, forming a partition structure with high sidewall smoothness, thereby making the contact surface between the metal gate structure and the partition structure of high quality.

[0064] In this embodiment, the partition opening 210 is formed using a dry etching process.

[0065] The dry etching process has the characteristics of anisotropic etching. Therefore, by selecting the dry etching process, the etching is more directional, which is beneficial to improving the opening size accuracy of the partition opening 210.

[0066] In this embodiment, the dry etching process includes inductively coupled plasma (ICP) etching.

[0067] The inductively coupled plasma etching process has a high plasma density and high etching rate, which reduces the influence of the etching loading effect during the etching process.

[0068] In this embodiment, the process parameters of the inductively coupled plasma etching process include: source power of 400W to 600W and bias voltage of 1000V to 1300V.

[0069] It should be noted that the surface smoothness of the sidewall 220 of the partition opening 210 formed by the dry etching is poor, too rough, and it is easy to cause uneven grain size of the microstructure of the sidewall 220.

[0070] Meanwhile, the dry etching process employs a cyclic process of etching followed by passivation, then etching again and passivation again. Therefore, during the dry etching process, the sidewall 220 of the partition opening 210 is easily oxidized, and an oxide layer is easily formed on the sidewall 220.

[0071] Therefore, the forming method further includes: performing a wet etching process on the partition opening 210 to remove the oxide layer and cleaning the partition opening 210 for residue.

[0072] The wet etching process includes: oxidizing the sidewall 220 of the partition opening 210 with a sulfuric acid-hydrogen peroxide mixture to form an oxide layer, removing the oxide layer with a diluted hydrofluoric acid solution, and finally cleaning the residue on the sidewall 220 of the partition opening 210 with standard cleaning solution No. 1.

[0073] Because the crystallization uniformity of the sidewall 220 is poor, the ammonia in the No. 1 standard cleaning solution in the wet etching process has different etching rates for pseudo-gate structures 200 with different grain sizes. The ammonia has a faster etching rate for pseudo-gate structures 200 with smaller grain sizes, which further worsens the sidewall roughness and opening size uniformity of the partition opening 210. Therefore, the sidewall 220 needs to be smoothed in the subsequent process.

[0074] Specifically, refer to Figure 5 Before forming the partition opening 210, the method further includes: patterning the hard mask layer 300 to form a mask opening 330.

[0075] The mask opening 330 exposes the pseudo-gate structure 200 at the position to be cut, which is used to prepare for the subsequent cutting process of the pseudo-gate structure 200 to form the isolation opening 210.

[0076] Specifically, along the opening 430 (e.g.) Figure 4 (As shown) Etch the hard mask layer 300 to remove the hard mask layer 300 exposed by the opening 430, forming the mask opening 330.

[0077] In this embodiment, after forming the mask opening 330, the remaining pattern transfer layer is removed.

[0078] Therefore, refer to Figure 6 Using the graphical hard mask layer 300 as a mask, the pseudo gate structure 200 is etched along the mask opening 330 to form the isolation opening 210.

[0079] It should be noted that when the pseudo-gate structure 200 is cut off, a portion of the isolation layer 110 below the pseudo-gate structure 200 at the cut-off position is also removed to form the isolation opening 210, which helps to ensure that the pseudo-gate structure 200 is completely divided by the isolation opening 210.

[0080] Reference Figure 7 and Figure 8 The pseudo-gate structure 200 exposed on the sidewall of the partition opening 210 is smoothed.

[0081] This embodiment of the invention improves the surface smoothness of the sidewall of the partition opening 210 by smoothing the exposed pseudo-gate structure 200 on the sidewall. This results in a partition opening 210 with higher sidewall smoothness, which in turn improves the uniformity of the opening size and reduces the probability of the distance between the sidewall of the partition opening 210 and the adjacent fin 120 being too small. Therefore, in the subsequent process of removing the pseudo-gate structure 200, it is beneficial to ensure that the sidewall of the partition opening 210 and the adjacent fin 120 are properly aligned. The pseudo-gate structure 200 between the two is completely removed, reducing residue residue. At the same time, the partition opening 210 with a high sidewall smoothness is obtained, which helps to reduce the stress when filling the partition opening 210 with material later. This reduces the probability of bending of the fin 120 adjacent to the sidewall of the partition opening 210. This also reduces the probability that the distance between the sidewall of the partition opening 210 and the adjacent fin 120 is too small. Correspondingly, it also helps to completely remove the pseudo-gate structure 200 between the sidewall of the partition opening 210 and the adjacent fin 120, thereby improving the working performance of the semiconductor structure.

[0082] Specifically, refer to Figure 7 The smoothing method includes: forming a reaction layer 230 within the partition opening 210, the reaction layer 230 conformally covering the sidewall 220 of the partition opening 210 (e.g., Figure 6 As shown in the figure, the reaction layer 230 and the pseudo-gate structure 200 are made of the same material.

[0083] The reaction layer 230 is formed to fill the rough surface of the sidewall 220 and to recrystallize in combination with the pseudo-gate structure 200 of the sidewall 220 at the interface. The reaction layer 230 is made of the same material as the pseudo-gate structure 200, which is beneficial for subsequent fusion and recrystallization with the pseudo-gate structure 200 of the sidewall 220.

[0084] In this embodiment, the material of the pseudo-gate structure 200 is amorphous silicon, therefore, the material of the reaction layer 230 is also amorphous silicon.

[0085] In this embodiment, the reaction layer 230 is formed using a chemical vapor deposition process.

[0086] The chemical vapor deposition process has a good deposition effect, can form a high-quality film structure, and can reduce the porosity in the film.

[0087] In this embodiment, the process parameters of the chemical vapor deposition process include: a process temperature of 250°C to 450°C and a process time of 8 to 12 hours.

[0088] The process temperature of the chemical vapor deposition (CVD) process cannot be too high or too low. If the process temperature is too low, the CVD process will be slow, resulting in a low deposition rate, which is detrimental to the deposition of the reaction layer 230. Conversely, the deposition rate of the CVD process initially increases and then decreases as the process temperature rises; therefore, if the process temperature is too high, it is also detrimental to the deposition of the reaction layer 230. Therefore, in this embodiment, the process temperature of the CVD process is between 250°C and 450°C. For example, the process temperature of the CVD process is 350°C.

[0089] The chemical vapor deposition (CVD) process time must be neither too long nor too short. If the CVD process time is too long, an excessively thick reaction layer 230 may form, leading to material waste. Furthermore, retaining the reaction layer 230 subsequently affects the opening size of the partition opening 210. Conversely, if the CVD process time is too short, an excessively thin reaction layer 230 may form, making it difficult to form a sufficiently thick layer that can subsequently fuse with the pseudo-gate structure 200 of the sidewall 220, thus hindering the improvement of the surface smoothness of the partition opening 210 sidewall. Therefore, in this embodiment, the CVD process time is 8 to 12 hours. For example, the CVD process time is 10 hours.

[0090] In this embodiment, the thickness of the reaction layer 230 is to

[0091] The thickness of the reaction layer 230 cannot be too large or too small. If the reaction layer 230 is too thick, it will easily lead to material waste, and if the reaction layer 230 is retained later, it will affect the opening size of the partition opening 210. If the reaction layer 230 is too thin, it will be difficult to form a sufficiently thick reaction layer 230 to subsequently fuse with the pseudo-gate structure 200 of the sidewall 220, resulting in poor effect on improving the surface smoothness of the sidewall of the partition opening 210. Therefore, in this embodiment, the thickness of the reaction layer 230 is... to For example, the thickness of the reaction layer 230 is

[0092] refer to Figure 8 Forming the reaction layer 230 (e.g.) Figure 7 After (as shown), annealing is performed at the interface between the reaction layer 230 and the pseudo-gate structure 200 exposed on the sidewall of the partition opening 210, so that the materials of the reaction layer 230 and the pseudo-gate structure 200 are fused together, and the reaction layer 230 is transformed into a smooth layer 240.

[0093] At the interface between the reaction layer 230 and the pseudo-gate structure 200 exposed on the sidewall of the partition opening 210, the reaction layer 230 and the pseudo-gate structure 200 exposed on the sidewall of the partition opening 210 combine and recrystallize, realizing grain recrystallization and filling the rough surface of the sidewall 220, which is beneficial to forming the partition opening 210 with a higher sidewall smoothness.

[0094] In this embodiment, the material of the pseudo-gate structure 200 is amorphous silicon. Therefore, the material of the reaction layer 230 is also amorphous silicon. Amorphous silicon is formed on the surface of the pseudo-gate structure 200 on the sidewall of the partition opening 210. Then, the amorphous silicon formed and the amorphous silicon of the pseudo-gate structure 200 are nucleated and crystallized by high-temperature rapid heat treatment. The nucleation and crystallization time is controlled to produce polycrystalline silicon with uniform grain size on the surface of the pseudo-gate structure 200 on the sidewall of the partition opening 210.

[0095] In this embodiment, a rapid thermal annealing process is used to perform the annealing treatment.

[0096] The rapid thermal annealing process can rearrange the crystal lattice and eliminate stress concentration, which is beneficial to improving the material fusion effect between the reaction layer 230 and the pseudo-gate structure 200. In addition, the rapid thermal annealing process has high efficiency and the film quality of the smooth layer 240 formed is high. At the same time, the rapid thermal annealing process has the advantages of short annealing time and small thermal budget.

[0097] In this embodiment, the annealing process is performed in a nitrogen-containing gas atmosphere.

[0098] In subsequent processes, a partition structure needs to be formed in the partition opening 210. In order to improve the density and etching resistance of the partition structure, the partition structure is made of nitrogen-containing material. Therefore, the annealing treatment of the pseudo gate structure 200 on the sidewall of the partition opening 210 under a nitrogen-containing gas atmosphere can reduce the problems caused by the doping of different elements.

[0099] In this embodiment, the process parameters of the rapid thermal annealing process include: the annealing gas is nitrogen, the gas flow rate of the annealing gas is 300 standard milliliters per minute to 500 standard milliliters per minute, the process temperature is 600°C to 800°C, and the process time is 10 seconds to 30 seconds.

[0100] The annealing gas in the rapid thermal annealing process is nitrogen, which is an inert gas and helps to reduce the impact of the annealing gas during the annealing process.

[0101] The flow rate of the annealing gas must not be too high or too low. If the flow rate is too high, it can easily lead to unnecessary process waste; if the flow rate is too low, the annealing gas will be difficult to distribute evenly, resulting in uneven temperature distribution during the annealing process and consequently poor temperature control. Therefore, in this embodiment, the flow rate of the annealing gas is between 300 and 500 standard milliliters per minute. For example, the flow rate is 400 standard milliliters per minute.

[0102] The process temperature cannot be too high or too low. If the process temperature is too high, it may affect other components of the semiconductor structure; if the process temperature is too low, it will hinder the grain recrystallization during the smoothing process, making it difficult to form the smooth layer 240 with a high surface smoothness. Therefore, in this embodiment, the process temperature is 600°C to 800°C. For example, the process temperature is 700°C.

[0103] The process time cannot be too long or too short. If the process time is too long, the semiconductor structure will be exposed to a high temperature for an extended period, which may damage other components of the semiconductor structure. If the process time is too short, it will be difficult to form the smooth layer 240 with a high surface smoothness. Therefore, in this embodiment, the process time is 10 to 30 seconds. For example, the process time is 20 seconds.

[0104] Reference Figure 9 and Figure 10 Forming the smooth layer 240 (e.g.) Figure 8 Following (as shown), the process also includes: removing the smoothing layer 240.

[0105] Since a partition structure needs to be formed in the partition opening 210, the smoothing layer 240 occupies part of the space of the partition opening, which has a certain impact on the formation of the partition structure. Therefore, the smoothing layer 240 needs to be removed to provide sufficient space for the formation of the partition structure.

[0106] Specifically, refer to Figure 9 The step of removing the smoothing layer 240 includes: modifying the smoothing layer 240 to transform it into a sacrificial layer 250, wherein the etching resistance of the sacrificial layer 250 is less than that of the smoothing layer 240.

[0107] By modifying the smooth layer 240 to transform it into a sacrificial layer 250, the etching resistance of the sacrificial layer 250 is reduced, making it easier to remove the sacrificial layer 250 by subsequent etching. At the same time, the probability of the process of removing the smooth layer 240 causing damage to the sidewall of the partition opening 210 is reduced.

[0108] In this embodiment, the smoothing layer 240 is oxidized, transforming the smoothing layer 240 into a sacrificial layer 250.

[0109] Oxidizing the smooth layer 240 is beneficial for obtaining the sacrificial layer 250 with lower etch resistance.

[0110] In this embodiment, the sacrificial layer 250 is made of silicon oxide. The silicon oxide material is easily etched away and causes minimal damage to the dummy gate structure 200.

[0111] Specifically, the material of the reaction layer 230 is amorphous silicon. Therefore, by oxidizing the smoothing layer 240, the sacrificial layer 250 of silicon oxide material can be easily obtained.

[0112] In this embodiment, the process of oxidizing the smooth layer 240 is beneficial for removing the polymer on the sidewall of the partition opening 210 and oxidizing the smooth layer 240 completely, which in turn facilitates the subsequent removal of the smooth layer 240.

[0113] In this embodiment, the process parameters for oxidizing the smooth layer include: the oxidizing gas is oxygen, the process pressure is 5mT to 20mT, the gas flow rate of the oxidizing gas is 200 standard milliliters per minute to 500 standard milliliters per minute, the source power is 500W to 1000W, and the process time is 15 seconds to 60 seconds.

[0114] Oxygen is used as the oxidizing gas, thereby obtaining a sacrificial layer 250 of silicon oxide material, so as to avoid introducing other elements into the sacrificial layer 250 and ensure that the etching resistance of the sacrificial layer 250 is reduced.

[0115] The process pressure must not be too high or too low. If the process pressure is too high, it can easily lead to unnecessary process waste; if the process pressure is too low, insufficient oxidizing gas will enter, affecting the process efficiency of the oxidation process. Therefore, in this embodiment, the process pressure is between 5 mT and 20 mT. For example, the process pressure is 10 mT.

[0116] The flow rate of the oxidizing gas cannot be too high or too low. If the flow rate is too high, the pseudo-gate structure 200 on the sidewall of the partition opening 210 will be excessively oxidized within the same time frame while oxidizing the reaction layer 240, forming an excessive amount of the sacrificial layer 250. This sacrificial layer 250 will then need to be removed, potentially resulting in an insufficient distance between the sidewall of the partition opening 210 and the adjacent fin 120. This increases the difficulty of thoroughly removing the pseudo-gate structure 200 between the sidewall of the partition opening 210 and the adjacent fin 120 during the subsequent removal process. Conversely, if the flow rate is too low, the reaction layer 240 will be difficult to completely oxidize within the same time frame. This will leave residual reaction layer after the removal of the sacrificial layer 250, affecting the opening size of the partition opening 210. Therefore, in this embodiment, the flow rate of the oxidizing gas is between 200 standard milliliters per minute and 500 standard milliliters per minute. For example, the flow rate of the oxidizing gas is 350 standard milliliters per minute.

[0117] The source power cannot be too high or too low. If the source power is too high, it can easily lead to unnecessary process waste; if the source power is too low, too little oxidizing gas will be introduced, affecting the heat conduction of the oxidation process and thus affecting the process effect. Therefore, in this embodiment, the source power is 500W to 1000W. For example, the source power is 750W.

[0118] The process time cannot be too long or too short. If the process time is too long, it is easy to oxidize too much of the pseudo-gate structure 200 on the sidewall of the partition opening 210 while oxidizing the reaction layer 240, forming too much of the sacrificial layer 250. Subsequent removal of the sacrificial layer 250 will result in an excessively small distance between the sidewall of the partition opening 210 and the adjacent fin 120, increasing the difficulty of completely removing the pseudo-gate structure 200 between the sidewall of the partition opening 210 and the adjacent fin 120. If the process time is too short, it is difficult to completely oxidize the reaction layer 240, leaving some of the reaction layer after removing the sacrificial layer 250, affecting the opening size of the partition opening 210. Therefore, in this embodiment, the process time is 15 to 60 seconds. For example, the process time is 40 seconds.

[0119] refer to Figure 10 Remove the sacrificial layer 250 (e.g.) Figure 9 (As shown).

[0120] Remove the sacrificial layer 250 to restore the opening size of the partition opening 210.

[0121] In this embodiment, the sacrificial layer 250 is removed using a wet etching process.

[0122] The wet etching process is isotropic, which is beneficial for completely removing the sacrificial layer 250.

[0123] In this embodiment, the etching solution for the wet etching process includes a diluted hydrofluoric acid solution, a sulfuric acid-hydrogen peroxide mixture (SPM), and a standard cleaning solution (SC1). The standard cleaning solution (SC1) is a mixture of ammonia, hydrogen peroxide, and water.

[0124] The diluted hydrofluoric acid solution is typically used for etching to remove oxide films. The low concentration of the diluted hydrofluoric acid solution results in a stable etching rate and reduces damage to other film layers during the etching process.

[0125] The sulfuric acid and hydrogen peroxide mixture is used to remove organic particle impurities from the etched surface, which helps to remove the residue left during the etching process.

[0126] The No. 1 standard cleaning solution is used to remove particulate impurities from the etched surface, which helps to further remove the particulate residues from the etching process.

[0127] In this embodiment, the solution parameters of the diluted hydrofluoric acid solution include: a volume ratio of water to hydrofluoric acid of 90:1 to 110:1, and a solution temperature of 23°C to 27°C; the solution parameters of the sulfuric acid and hydrogen peroxide mixed solution include: a volume ratio of sulfuric acid to hydrogen peroxide of 5:1 to 8:1, and a solution temperature of 110°C to 130°C; the solution parameters of the No. 1 standard cleaning solution include: a volume ratio of ammonia, hydrogen peroxide, and water of 1:2:40 to 1:3:60, and a solution temperature of 40°C to 70°C.

[0128] refer to Figure 11 For the partition opening 210 (e.g. Figure 10 After the exposed pseudo-gate structure 200 on the sidewall (as shown) is smoothed, the method further includes: forming a partition structure 500 within the partition opening 210.

[0129] The isolation structure 500 is used to insulate the pseudo-gate structures 200 from each other, thereby achieving mutual insulation between subsequent metal gate structures. The isolation structure 500 is also used to provide a process platform for the subsequent formation of metal gate structures.

[0130] In this embodiment, the aforementioned smoothing process results in a partition opening 210 with a high degree of sidewall smoothness. Therefore, during the process of forming the partition structure 500 within the partition opening 210, it is beneficial to reduce the stress when filling the partition structure 500 with material in the partition opening 210, thereby reducing the probability of bending of the fin 120 adjacent to the sidewall of the partition opening 210. This also reduces the probability that the distance between the sidewall of the partition opening 210 and the adjacent fin 120 is too small, which also helps to completely remove the pseudo-gate structure 200 between the sidewall of the partition opening 210 and the adjacent fin 120, thereby improving the working performance of the semiconductor structure.

[0131] The material of the partition structure 500 has high hardness and density, thereby reducing the probability of the partition structure 500 being damaged during the formation of the semiconductor structure, and thus ensuring the isolation performance of the partition structure 500.

[0132] For example, during the formation of the semiconductor structure, after the metal gate structure is formed, the metal gate structure in some areas may be removed according to process requirements. By making the material of the isolation structure 500 have high hardness and density, the probability of the isolation structure 500 being damaged during the removal of the metal gate structure can be effectively reduced, thereby improving the integrity of the isolation structure 500.

[0133] Therefore, in this embodiment, the partition structure 500 is made of silicon nitride. In other embodiments, the partition structure may also be made of other nitrogen-containing dielectric materials.

[0134] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, including a substrate and a fin standing on the substrate, a dummy gate structure is formed on the substrate and across the fin, the dummy gate structure covers part of the top and part of the sidewall of the fin; cutting the dummy gate structure to form a partition opening, which divides the dummy gate structure in the extension direction of the dummy gate structure; smoothing the dummy gate structure exposed by the sidewall of the partition opening; the smoothing method comprises: forming a reaction layer in the partition opening, the reaction layer conformally covers the sidewall of the partition opening; after forming the reaction layer, annealing treatment is performed to recombine the reaction layer and the material of the dummy gate structure at the interface between the reaction layer and the dummy gate structure, and the reaction layer is converted into a smoothing layer.

2. The method of forming a semiconductor structure of claim 1, wherein, The material of the reaction layer is the same as that of the dummy gate structure.

3. The method of forming a semiconductor structure of claim 2, wherein, The annealing treatment is performed by using a rapid thermal annealing process.

4. The method of forming a semiconductor structure of claim 2, wherein, The annealing treatment is performed in a nitrogen-containing gas atmosphere.

5. The method of forming a semiconductor structure of claim 2, wherein, After the smoothing layer is formed, the smoothing layer is removed.

6. The method of forming a semiconductor structure of claim 5, wherein, The step of removing the smoothing layer comprises: modifying the smoothing layer to convert it into a sacrificial layer, the etch resistance of the sacrificial layer is less than that of the smoothing layer; the sacrificial layer is removed.

7. The method of forming a semiconductor structure of claim 6, wherein, In the modification step, the smoothing layer is oxidized to convert it into a sacrificial layer.

8. The method of forming a semiconductor structure of claim 1, wherein, After the smoothing of the dummy gate structure exposed by the sidewall of the partition opening, a partition structure is formed in the partition opening.

9. The method of forming a semiconductor structure of claim 1, wherein, The partition opening is formed by using a dry etching process.

10. The method of forming a semiconductor structure of claim 9, wherein, The dry etching process includes an inductively coupled plasma etching process.

11. The method of forming a semiconductor structure of claim 2, wherein, The reaction layer is formed by using a chemical vapor deposition process.

12. The method of forming a semiconductor structure of claim 11, wherein, The process parameters of the chemical vapor deposition process include: a process temperature of 250-450°C and a process time of 8-12 hours.

13. The method of forming a semiconductor structure of claim 3, wherein, The process parameters of the rapid thermal annealing process include: an annealing gas of nitrogen, a gas flow of the annealing gas of 300-500 standard milliliters per minute, a process temperature of 600-800°C, and a process time of 10-30 seconds.

14. The method of forming a semiconductor structure of claim 7, wherein, The process parameters for oxidizing the smoothing layer include: an oxidation gas of oxygen, a process pressure of 5-20 mT, a gas flow of the oxidation gas of 200-500 standard milliliters per minute, a source power of 500-1000 W, and a process time of 15-60 seconds.

15. The method of forming a semiconductor structure of claim 6, wherein, The sacrificial layer is removed by using a wet etching process.

16. The method of forming a semiconductor structure of claim 15, wherein, The etching solution of the wet etching process includes a mixture of diluted hydrofluoric acid solution, sulfuric acid hydrogen peroxide mixed solution, and standard cleaning solution No.

1.

17. The method of forming a semiconductor structure of claim 2, wherein, The thickness of the reaction layer is 10-50 Å.

18. The method of forming a semiconductor structure of claim 1, wherein, The material of the dummy gate structure includes one or both of amorphous silicon and polycrystalline silicon.

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