Semiconductor package and method of manufacture

Abstract

The present disclosure relates to a semiconductor package and method of manufacture. Disclosed are packaged semiconductor devices including a high thermal conductivity molding compound and methods of forming the same. In one embodiment, a semiconductor device includes a first redistribution structure, a first die located over and electrically coupled to the first redistribution structure, a first through via located over and electrically coupled to the first redistribution structure, an insulating layer extending along the first redistribution structure, the first die, and the first through via, and an encapsulant located over the insulating layer, the encapsulant surrounding a portion of the first through via and a portion of the first die, the encapsulant including an electrically conductive filler in a concentration ranging from 70% to about 95% by volume.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor packages and manufacturing methods. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electrical components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density stems from iterative reductions in the minimum feature size, allowing more components to be integrated into a given area. As the demand for miniaturized electronics continues to grow, there is a need for packaging technologies for smaller and more innovative semiconductor dies. One example of such packaging systems is package-on-package (PoP) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. Generally, PoP technology enables the production of semiconductor devices with enhanced functionality and a small footprint on printed circuit boards (PCBs). Summary of the Invention

[0003] A first aspect of this disclosure relates to a semiconductor device comprising: a first redistribution structure; a first die disposed on and electrically coupled to the first redistribution structure; a first through-via disposed on and electrically coupled to the first redistribution structure; an insulating layer extending along the first redistribution structure, the first die, and the first through-via; and a sealant disposed on the insulating layer, the sealant surrounding a portion of the first through-via and a portion of the first die, wherein the sealant comprises a conductive filler in a concentration ranging from 70% to 95% by volume.

[0004] A second aspect of this disclosure relates to a semiconductor device comprising: a first integrated circuit die; a front redistribution structure located on the front side of the first integrated circuit die; a back redistribution structure located on the back side of the first integrated circuit die; a molding compound that seals the first integrated circuit die between the front redistribution structure and the back redistribution structure, the molding compound having a thermal conductivity greater than 40 W / m·K; a through-via extending through the molding compound, wherein the through-via is electrically coupled to the front redistribution structure and the back redistribution structure; and an insulating layer covering the sidewalls of the through-via, wherein the insulating layer separates the through-via from the molding compound.

[0005] A third aspect of this disclosure relates to a method comprising: forming a through-via over a redistribution structure; bonding a semiconductor die to the redistribution structure adjacent to the through-via; depositing an insulating layer over the through-via, the redistribution structure, and the semiconductor die, wherein the insulating layer electrically isolates the through-via, the redistribution structure, and the semiconductor die from each other; preparing a molding compound by mixing an epoxy resin and a conductive filler, wherein the conductive filler comprises 70% to 95% by volume of the molding compound; and depositing the molding compound over the insulating layer, the molding compound being configured to conduct heat from the semiconductor die. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figures 1 to 25 A cross-sectional view is shown during an intermediate step in the process of forming a packaged assembly, according to some embodiments. Detailed Implementation

[0008] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, this document may use spatially relevant terms (e.g., "below," "below," "lower than," "higher than," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0010] Various embodiments provide a packaged semiconductor device with improved heat dissipation and a method of forming the same. The method includes forming an interconnect structure, forming vias over the interconnect structure, and attaching a semiconductor die to the interconnect structure. An insulating layer is formed over the interconnect structure, vias, and semiconductor die, and a molding compound is formed over the insulating layer. The insulating layer may be electrically insulating and may isolate the interconnect structure and the vias of the semiconductor die and any exposed conductive features from each other. This allows the use of conductive materials in the molding compound. The insulating layer may also reduce stress between the molding compound and the underlying structure, which allows the use of materials with higher coefficients of thermal expansion in the molding compound. Greater flexibility in the selection of molding compound materials allows the use of materials with higher thermal conductivity in the molding compound. This, in turn, provides better heat dissipation, improved device quality, improved device performance, and reduced device defects.

[0011] Figure 1 A cross-sectional view of integrated circuit die 50 is shown. Integrated circuit die 50 will be packaged in subsequent processing to form an integrated circuit package. Integrated circuit die 50 may be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, or application-specific integrated circuit (ASIC) chip, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, or a high bandwidth memory (HBM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) chip, etc.), a front-end chip (e.g., an analog front-end (AFE) die), etc., or a combination thereof.

[0012] An integrated circuit die 50 can be formed in a wafer, which may include different device regions that are diced in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 50 can be processed according to applicable manufacturing processes to form an integrated circuit. For example, the integrated circuit die 50 includes a semiconductor substrate 52, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., Figure 1 The surface facing upwards (sometimes called the front), and non-active surfaces (e.g., Figure 1The surface facing down (the middle side), sometimes referred to as the back side.

[0013] Device 54 (represented by a transistor) may be formed on the active surface of semiconductor substrate 52. Device 54 may be an active device (e.g., a transistor or diode), capacitor, resistor, etc. Interlayer dielectric (ILD) 56 is located above the active surface of semiconductor substrate 52. ILD 56 surrounds and may cover device 54. ILD 56 may include one or more dielectric layers formed of materials such as silicon phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped silicon phosphosilicate glass (BPSG), undoped silicon glass (USG), etc.

[0014] Conductive plug 58 extends through ILD 56 to electrically and physically couple device 54. For example, when device 54 is a transistor, conductive plug 58 can couple the gate and source / drain regions of the transistor. Conductive plug 58 can be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or combinations thereof. Interconnect structure 60 is located on ILD 56 and conductive plug 58. Interconnect structure 60 interconnects device 54 to form an integrated circuit. Interconnect structure 60 can be formed by, for example, a metallization pattern in a dielectric layer on ILD 56. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of interconnect structure 60 is electrically coupled to device 54 through conductive plug 58.

[0015] The integrated circuit die 50 also includes pads 62, such as aluminum pads, which are connected to the outside. Pads 62 are located on the active side of the integrated circuit die 50, for example, in and / or on the interconnect structure 60. One or more passivation films 64 are located on the integrated circuit die 50, for example, on portions of the interconnect structure 60 and the pads 62. Openings extend through the passivation films 64 to the pads 62. Die connectors 66, such as conductive pillars (e.g., formed of a metal such as copper), extend through the openings in the passivation films 64 and are physically and electrically coupled to the corresponding pads 62. Die connectors 66 can be formed, for example, by electroplating. Die connectors 66 electrically couple to the corresponding integrated circuit of the integrated circuit die 50.

[0016] Optionally, solder areas (e.g., solder balls or solder bumps) can be provided on pad 62. Solder balls can be used to perform chip probe (CP) testing on the integrated circuit die 50. CP testing can be performed on the integrated circuit die 50 to determine if it is a known good die (KGD). Therefore, only integrated circuit dies 50 that are KGD are subsequently processed and packaged, and dies that fail the CP test are not packaged. After testing, the solder areas can be removed in subsequent processing steps.

[0017] The dielectric layer 68 may or may not be located on the active side of the integrated circuit die 50, for example, on the passivation film 64 and the die connector 66. The dielectric layer 68 laterally seals the die connector 66 and is laterally connected to the integrated circuit die 50. Initially, the die connector 66 may be embedded in the dielectric layer 68 such that the topmost surface of the dielectric layer 68 is higher than the topmost surface of the die connector 66. In some embodiments where the solder region is located on the die connector 66, the solder region may also be embedded in the dielectric layer 68. Alternatively, the solder region may be removed before forming the dielectric layer 68.

[0018] The dielectric layer 68 may be a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.; a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; or a combination thereof. The dielectric layer 68 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, during the formation of the integrated circuit die 50, the die connector 66 is exposed through the dielectric layer 68. In some embodiments, the die connector 66 remains buried and is exposed during subsequent processes for packaging the integrated circuit die 50. Exposing the die connector 66 can remove any solder areas that may be present on the die connector 66.

[0019] In some embodiments, the integrated circuit die 50 is a stacked device comprising a plurality of semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device comprising a plurality of memory dies, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. In such embodiments, the integrated circuit die 50 includes a plurality of semiconductor substrates 52 interconnected by through-substrate vias (TSVs) (also known as through-silicon vias). Each semiconductor substrate 52 may or may not have an interconnect structure 60.

[0020] Figures 2 to 25 A cross-sectional view is shown illustrating the fabrication of an integrated circuit package with improved heat dissipation according to some embodiments. Figure 2 In this embodiment, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer, allowing multiple packages to be formed simultaneously on the carrier substrate 102. In some embodiments, one or more integrated circuit dies 50 may be packaged to form an integrated circuit package in each of a plurality of packaging regions above the wafer. The completed integrated circuit package may also be referred to as an integrated fan-out (InFO) package.

[0021] Release layer 104 may be formed of a polymer-based material, which can be removed together with the carrier substrate 102 from the overlay structure formed in a subsequent step. In some embodiments, release layer 104 is a thermally release material based on epoxy resin that loses its adhesive properties when heated, such as a photothermal conversion (LTHC) release coating. In some embodiments, release layer 104 may be an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV light. Release layer 104 may be dispersed and cured as a liquid, and may be a laminated film or the like laminated onto the carrier substrate 102. The top surface of release layer 104 may be flat and may have a high degree of flatness.

[0022] exist Figure 3 In this process, a front redistribution structure 124 is formed on the release layer 104. The front redistribution structure 124 includes dielectric layers 106, 110, 114, and 118; and metallization patterns 108, 112, 116, and 120 (including conductive pads 120A and 120B). The metallization patterns 108, 112, 116, and 120 may also be referred to as redistribution layers or redistribution lines. Figure 3 The front redistribution structure 124 shown includes four dielectric layers and four metallization patterns. More or fewer dielectric layers and metallization patterns can be formed in the front redistribution structure 124. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

[0023] The front redistribution structure 124 can be formed by depositing a dielectric layer 106 on the release layer 104. In some embodiments, the dielectric layer 106 can be formed of a photosensitive material such as PBO, polyimide, or BCB, which can be patterned using a photolithographic mask. The dielectric layer 106 can be formed by spin coating, lamination, CVD, or a combination thereof.

[0024] Metallization pattern 108 is formed on dielectric layer 106. Metallization pattern 108 can be formed by forming a seed layer (not shown separately) on dielectric layer 106. Seed layer can be a metal layer, which can be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, seed layer comprises a titanium layer and a copper layer above the titanium layer. Seed layer can be deposited by physical vapor deposition (PVD) or the like. Photoresist is formed on seed layer and patterned thereon. Photoresist can be formed by spin coating or the like and can be exposed to be patterned. Pattern of photoresist corresponds to metallization pattern 108. Patterning forms through openings in photoresist to expose seed layer. Conductive material is formed in the openings in photoresist and on the exposed portion of seed layer. Conductive material can be formed by plating (e.g., electroplating or electroless plating). Conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The combination of the portion below seed layer and conductive material forms metallization pattern 108. Remove the portion of the seed layer where no conductive material has formed and the photoresist. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed by an acceptable etching process (e.g., wet etching or dry etching).

[0025] A dielectric layer 110 is deposited on the metallization pattern 108 and the dielectric layer 106. The dielectric layer 110 may be formed of the same or similar materials and methods as the dielectric layer 106. Openings may be patterned through the dielectric layer 110 to expose the underlying metallization pattern 108. The openings may be patterned through the dielectric layer 110 using acceptable processes. In embodiments where the dielectric layer 110 includes a photosensitive material, the dielectric layer 110 may be exposed to a patterned energy source (e.g., a patterned light source) and developed to form openings extending through the dielectric layer 110. In some embodiments, a patterned mask may be formed over the dielectric layer 110, and the dielectric layer 110 may be patterned through the patterned mask using an etching process (e.g., anisotropic etching) to form openings extending through the dielectric layer 110.

[0026] Metallization pattern 112 is formed on dielectric layer 110 and metallization pattern 108. Metallization pattern 112 includes a portion (e.g., a conductor) located on and extending along the top surface of dielectric layer 110 and a portion extending through dielectric layer 110 (e.g., a conductive via). The portion of metallization pattern 112 extending through dielectric layer 110 can be electrically coupled to and physically contact metallization pattern 108. Metallization pattern 112 can be formed from the same or similar materials and in a manner as metallization pattern 108. In some embodiments, metallization pattern 112 has different dimensions than metallization pattern 108. For example, the conductors and / or conductive vias of metallization pattern 112 can be wider or thicker than the conductors of metallization pattern 108. Furthermore, metallization pattern 112 can be formed with a larger spacing than metallization pattern 108.

[0027] A dielectric layer 114 is deposited on the metallization pattern 112 and the dielectric layer 110. The dielectric layer 114 may be patterned to expose the metallization pattern 112. The dielectric layer 114 may be formed of the same or similar material as the dielectric layer 110, and may be formed and patterned in the same or similar manner as the dielectric layer 110.

[0028] Metallization pattern 116 is formed on dielectric layer 114 and metallization pattern 112. Metallization pattern 116 includes a portion (e.g., a conductor) located on and extending along the top surface of dielectric layer 114 and a portion extending through dielectric layer 114 (e.g., a conductive via). The portion of metallization pattern 116 extending through dielectric layer 114 can be electrically coupled to and physically contact metallization pattern 112. Metallization pattern 116 can be formed from the same or similar materials and in a manner as metallization pattern 108. In some embodiments, metallization pattern 116 has different dimensions than metallization patterns 108 and 112. For example, the conductors and / or conductive vias of metallization pattern 116 can be wider or thicker than the conductors and / or conductive vias of metallization patterns 108 and 112. Furthermore, metallization pattern 116 can be formed with a larger spacing than metallization patterns 108 and 112.

[0029] A dielectric layer 118 is deposited on the metallization pattern 116 and the dielectric layer 114. The dielectric layer 118 may be patterned to form openings that expose the metallization pattern 116. The dielectric layer 118 may be formed of the same or similar material as the dielectric layer 110, and may be formed and patterned in the same or similar manner as the dielectric layer 110.

[0030] A metallization pattern 120 is formed in an opening extending through the dielectric layer 118. In some embodiments, the metallization pattern 120 may be formed on both the dielectric layer 118 and the metallization pattern 116. The metallization pattern 120 may be formed from the same or similar materials and in a similar manner to the metallization pattern 108. After the metallization pattern 120 is formed, a planarization process may be performed on the metallization pattern 120 to make the top surface of the metallization pattern 120 flush with the top surface of the dielectric layer 118. The planarization process may be chemical mechanical polishing (CMP) or a grinding process, etc. The metallization pattern 120 may include a conductive pad 120A on which a via (e.g., via 126, hereinafter referred to) may be subsequently formed. Figure 4 (Discussion); and conductive pad 120B, conductive connector (e.g., conductive connector 128, below about) Figure 5 (Discussion) can then be bonded to the conductive pad 120B.

[0031] exist Figure 4 In this embodiment, a via 126 (also referred to as a through-molded interconnect (TMI)) is formed on the conductive pad 120A of the metallization pattern 120. The via 126 may extend away from the topmost dielectric layer (e.g., dielectric layer 118) of the front redistribution structure 124. As an example of forming the via 126, a seed layer (not shown separately) is formed over the front redistribution structure 124 (e.g., over the dielectric layer 118 and the metallization pattern 120). In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In a particular embodiment, the seed layer comprises a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD). In some embodiments, such as where the width of the via 126 is the same as or narrower than the underlying conductive pad 120A, a separate seed layer may be omitted, and the conductive pad 120A may serve as the seed layer.

[0032] A photoresist is formed and patterned on a seed layer (if present) and a front redistribution structure 124. The photoresist can be formed by spin coating or the like and can be exposed to be patterned. The pattern of the photoresist corresponds to vias 126. Patterning is formed through openings in the photoresist to expose the seed layer or conductive pads 120A. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating (e.g., electroplating or electroless plating). The conductive material can include metals such as copper, titanium, tungsten, or aluminum. The portions of the seed layer on which no conductive material is formed and the photoresist are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portions of the seed layer (if present) are removed using an acceptable etching process (e.g., wet etching or dry etching). The remaining portions of the seed layer and the conductive material form vias 126.

[0033] In some embodiments, wire bonding structures may be used instead of vias 126. For example, wire bonding structures (not shown separately) may be formed on each conductive pad 120A. Each wire bonding structure may include a bonding ball formed on the respective conductive pad 120A and a metal wire attached to the respective bonding ball.

[0034] exist Figure 5 In the diagram, two integrated circuit dies 50 are bonded together in the package area shown. Although Figure 5 Two integrated circuit dies 50 are shown bonded in the illustrated package region, but any number of integrated circuit dies 50 can be bonded in each of multiple package regions on the wafer. Figure 5In this configuration, the integrated circuit die 50 is disposed face down, such that the front side of the integrated circuit die 50 faces the conductive pad 120B, and the back side of the integrated circuit die 50 faces away from the conductive pad 120B. The integrated circuit die 50 is bonded to the conductive pad 120B via a conductive connector 128. The conductive connector 128 is formed on the conductive pad 120B. The conductive connector 128 may be a ball grid array (BGA) connector, solder ball, metal pillar, controlled collapse chip connection (C4) bump, microbump, bump formed by electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, etc. The conductive connector 128 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the conductive connector 128 is formed by initially forming a solder layer via vapor deposition, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed, reflow soldering can be performed to shape the material into the desired bump shape. In some embodiments, the conductive connector 128 includes a metal pillar (e.g., a copper pillar) which can be formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillar may be solderless and have vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillar. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof. The metal cap layer can be formed by a plating process.

[0035] exist Figure 6 In this configuration, an underfill 130 is formed between the integrated circuit die 50 and the front redistribution structure 124. The underfill 130 may surround the conductive connector 128. The underfill 130 may be formed by a capillary flow process after attaching the integrated circuit die 50, or by a suitable deposition method before attaching the integrated circuit die 50. In some embodiments, the underfill 130 may be formed of a polymer material, and the underfill 130 may increase the bonding strength between the integrated circuit die 50 and the front redistribution structure 124.

[0036] exist Figure 7In this configuration, an insulating layer 132 is formed over the via 126, the integrated circuit die 50, the underfill 130, and the front redistribution structure 124, and a sealant 134 is formed over the insulating layer 132. The insulating layer 132 may be a conformal layer. In some embodiments, the insulating layer 132 may be deposited by CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), PVD, sputtering, spin coating, thermal spraying, etc. The insulating layer 132 may be formed of an electrically insulating material. In some embodiments, the insulating layer 132 may be formed of a material with high thermal conductivity, for example, a thermal conductivity greater than about 10 W / m·K. In embodiments where the insulating layer 132 is formed of a material with high thermal conductivity, the insulating layer 132 may include aluminum nitride (AlN), boron nitride (BN), beryllium oxide (BeO), diamond, aluminum oxide (Al2O3), magnesium oxide (MgO), combinations thereof, or multiples thereof. In some embodiments, the insulating layer 132 may be formed of a material with low thermal conductivity, such as less than about 10 W / m·K, about 1 W / m·K to about 10 W / m·K, etc. In embodiments where the insulating layer 132 is formed of a material with relatively low thermal conductivity, the insulating layer 132 may include silicon oxide (SiO2), silicon nitride (SiN), etc. X ), silicon oxynitride (SiON) X (e.g., combinations thereof, or multiple layers thereof). In some embodiments, insulating layer 132 may comprise a polymer material. Insulating layer 132 may have a thermal conductivity of about 1 W / m·K to about 100 W / m·K, about 10 7 Ω·cm to about 10 14 Electrical conductivity in Ω·cm, and coefficient of thermal expansion (CTE) from about 0.1 ppm / ℃ to about 10 ppm / ℃.

[0037] A sealant 134 is then formed on the insulating layer 132. The sealant 134 may be a molding compound or epoxy resin, etc. In some embodiments, the sealant 134 may comprise a mixture of epichlorohydrin and any of the following: bisphenol A (BPA), bisphenol A diglycidyl ether (DGEBA), bisphenol F (BPF), phenol, thiol, acid anhydride, amine, fatty alcohol, filler, or combinations thereof. The sealant 134 may be applied by compression molding or transfer molding, etc., and may be formed such that the through-hole 126 and / or the integrated circuit die 50 are embedded or covered. The sealant 134 may be applied in liquid or semi-liquid form and subsequently cured.

[0038] The sealant 134 can be formed of a material with high thermal conductivity, which improves heat dissipation through the sealant 134. For example, in some embodiments, the sealant 134 can be formed of a mixture of epoxy resin and conductive filler, which may include graphite, graphene, carbon nanotubes, conductive particles (e.g., copper (Cu), silicon (Si), silver (Ag), gold (Au), iron (Fe), tungsten (W), combinations thereof, etc.), or combinations thereof. In some embodiments, the graphite filler may include flakes with a size less than 1 μm. The graphene filler may be single-layered or multi-layered and may include flakes with a size less than 10 μm. The carbon nanotube filler may be single-walled or multi-walled and may include sizes less than 50 μm. The conductive filler may have a thermal conductivity from about 10 W / m·K to about 1,000 W / m·K, with about 10 W / m·K being the most common thermal conductivity. -3 Ω·cm to about 10 14 The electrical conductivity is measured in Ω·cm, and the coefficient of thermal expansion (CTE) is measured from about 1 ppm / ℃ to about 10 ppm / ℃. The sealant 134 may include a conductive filler at a concentration of about 5% to about 95% (by volume). In some embodiments, the sealant 134 may include a conductive filler having a concentration range of about 70% to about 95% (by volume), about 5% to about 40% (by volume), or about 30% to about 70% (by volume). Including a conductive filler within the specified concentration range can improve heat dissipation through the sealant 134. In some embodiments, the sealant 134 may also include a non-conductive filler, such as AlN, diamond, BN, BeO, magnesium oxide (MgO), Al2O3, SiO2, silicon (Si), or silicon nitride (SiN). X (or combinations thereof).

[0039] The thermal conductivity of the sealant 134 can be greater than that of the insulating layer 132. In some embodiments, the sealant 134 can have a thermal conductivity greater than about 40 W / m·K, from about 40 W / m·K to about 100 W / m·K, from about 5 W / m·K to about 200 W / m·K, or from about 100 W / m·K to about 200 W / m·K, etc. -3 Ω·cm to about 10 14 Electrical conductivity in Ω·cm, and coefficient of thermal expansion (CTE) from about 0.1 ppm / ℃ to about 20 ppm / ℃.

[0040] Forming an insulating layer 132 over the via 126, the integrated circuit die 50, and the front redistribution structure 124 allows for greater flexibility in the selection of materials for the sealant 134. For example, providing an insulating layer 132 formed of an electrically insulating material prevents short circuits between the via 126, the integrated circuit die 50, and the front redistribution structure 124, even when the sealant 134 is formed of a conductive material. The insulating layer 132 provides a buffer layer between the sealant 134 and each of the via 126, the integrated circuit die 50, and the front redistribution structure 124, which reduces stress. This allows the sealant 134 to be formed of a material with a higher coefficient of thermal expansion. This greater flexibility in selecting materials for the sealant 134 allows for the use of materials with high thermal conductivity, which improves heat dissipation of the integrated circuit die 50. This improves device performance and reduces device defects.

[0041] The insulating layer 132 may have a thickness t1 of about 10 nm to about 100 nm. Forming the insulating layer 132 to a thickness less than the specified range may result in difficulties in its formation and may not adequately provide the advantages of the insulating layer 132 (e.g., providing electrical isolation between the via 126, the integrated circuit die 50, and the front redistribution structure 124, and providing a buffer layer between the sealant 134 and the underlying structure). Furthermore, the insulating layer 132 may be formed of a material with a lower thermal conductivity than the material of the sealant 134. Forming the insulating layer 132 to a thickness greater than the specified range reduces the combined thermal conductivity of the insulating layer 132 and the sealant 134.

[0042] exist Figure 8 In this process, a planarization process is performed on the sealant 134 and the insulating layer 132. For example... Figure 9 As shown, the planarization process can expose via 126. Via 126 passes through insulating layer 132 and sealant 134, and may subsequently be referred to as through via 126. In some embodiments, at least a portion of insulating layer 132 may remain on the back side of integrated circuit die 50. In some embodiments, portions of sealant 134 may also remain on the back side of integrated circuit die 50, or sealant 134 and insulating layer 132 may be planarized to expose the back side of integrated circuit die 50. The planarization process can also remove material from through via 126. After the planarization process, the top surfaces of through via 126, insulating layer 132, and sealant 134 may be flush with each other (e.g., within a range of process variations). In some embodiments, the planarization process may be CMP or polishing processes, etc.

[0043] exist Figure 9In this configuration, a back-side redistribution structure 144 is formed on the sealant 134, the through-hole 126, and the insulating layer 132. The back-side redistribution structure 144 includes a dielectric layer 138 and metallization patterns 136 and 140. The metallization patterns 136 and 140 may also be referred to as redistribution layers or redistribution lines. Figure 9 The back-side redistribution structure 144 shown includes a dielectric layer and two metallization patterns. More or fewer dielectric layers and metallization patterns can be formed in the back-side redistribution structure 144. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

[0044] The back-side redistribution structure 144 can be formed by forming a metallization pattern 136 on the sealant 134, the insulating layer 132, and the through-hole 126. The metallization pattern 136 can be formed from the same or similar materials and in a similar manner to the metallization pattern 108. After the metallization pattern 136 is formed and patterned, the metallization pattern 136 may include portions extending along the top surface of the sealant 134, the top surface of the insulating layer 132, and the top surface of the through-hole 126. The metallization pattern 136 can be electrically coupled to the through-hole 126.

[0045] A dielectric layer 138 is deposited on a metallization pattern 136, a sealant 134, an insulating layer 132, and a through-hole 126. The dielectric layer 138 may be formed of the same or similar materials and in a manner as the dielectric layer 106. Openings may be patterned through the dielectric layer 138 to expose the underlying metallization pattern 136. These openings may be patterned through the dielectric layer 138 using acceptable processes. In embodiments where the dielectric layer 138 includes a photosensitive material, the dielectric layer 138 may be exposed to a patterned energy source (e.g., a patterned light source) and developed to form openings extending through the dielectric layer 138. In some embodiments, a patterned mask may be formed over the dielectric layer 138, and the dielectric layer 138 may be patterned through the patterned mask using an etching process (e.g., anisotropic etching) to form openings extending through the dielectric layer 138.

[0046] Metallization pattern 140 is formed in an opening extending through dielectric layer 138. In some embodiments, metallization pattern 140 may be formed on dielectric layer 138 and metallization pattern 136. Metallization pattern 120 may be formed from the same or similar material and in a similar manner to metallization pattern 108. After metallization pattern 140 is formed, a planarization process may be performed on metallization pattern 140 to make the top surface of metallization pattern 140 flush with the top surface of dielectric layer 138. The planarization process may be CMP or polishing, etc.

[0047] Thus, a first package assembly 100 is formed in the packaged area shown. The first package assembly 100 includes an integrated circuit die 50, a sealant 134, an insulating layer 132, a through-hole 126, a front redistribution structure 124, and a back redistribution structure 144.

[0048] exist Figure 10 In this embodiment, conductive connectors 146 are formed on the metallization pattern 140. Conductive connectors 146 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. Conductive connectors 146 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, conductive connectors 146 are formed by initially forming a solder layer via vapor deposition, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed, reflow soldering can be performed to shape the material into the desired bump shape. In some embodiments, conductive connectors 146 include metal pillars (e.g., copper pillars), which may be formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof. The metal capping layer may be formed by a plating process.

[0049] exist Figure 11In this embodiment, a second packaging assembly 200 is coupled to a conductive connector 146. The second packaging assembly 200 is coupled to a first packaging assembly 100 to form a stack of integrated circuit devices in the illustrated packaging region. The second packaging assembly 200 includes a substrate 202 and one or more stacked dies 210 (e.g., first stacked die 210A and second stacked die 210B) coupled to the substrate 202. Although a set of stacked dies 210 (e.g., first stacked die 210A and second stacked die 210B) is shown, in some embodiments, multiple sets of stacked dies 210 (each set including one or more stacked dies) may be arranged side-by-side and coupled to the surface of the substrate 202. The substrate 202 may be made of a semiconductor material such as silicon, germanium, diamond, etc. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide, gallium phosphide indium, combinations thereof, etc., may be used. The substrate 202 may be a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon-germanium, SOI, silicon-germanium-on-insulator (SGOI), or combinations thereof. In some embodiments, substrate 202 may be based on an insulating core, such as a glass fiber reinforced resin core. The core material may be a glass fiber resin, such as FR4. In some embodiments, the core may include bismaleimide triazine (BT) resin, other printed circuit board (PCB) materials, or thin films. Additive films, such as Ajinomoto additive film (ABF) or other lamination materials, may be used for substrate 202.

[0050] Substrate 202 may include active and passive devices (not shown separately). A variety of devices, such as transistors, capacitors, resistors, combinations thereof, etc., can be used to meet the structural and functional requirements of the design of the second package assembly 200. Any suitable method can be used to form the devices.

[0051] Substrate 202 may also include a metallization layer (not shown separately) and conductive vias 208. The metallization layer may be formed over active and passive devices and is designed to connect various devices to form functional circuitry. The metallization layer may be formed from alternating layers of a dielectric material (e.g., a low-k dielectric material) and a conductive material (e.g., copper) having vias that interconnect the conductive material layers. The metallization layer may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In some embodiments, substrate 202 is substantially devoid of active and passive devices.

[0052] Substrate 202 may include bonding pads 204 on a first side of substrate 202 and bonding pads 206 on a second side of substrate 202 opposite to the first side. Bonding pad 204 may be used for coupling to stacked die 210 and bonding pad 206 may be used for coupling to conductive connector 146. In some embodiments, such as the embodiment shown with bonding pad 206, bonding pads 204 and 206 are formed by forming recesses (not shown separately) in dielectric layers (not shown separately) on the first and second sides of substrate 202. Recesses may be formed to allow bonding pads 204 and 206 to be embedded in the dielectric layer. In other embodiments, such as the embodiment shown with bonding pad 204, the recesses are omitted because bonding pads 204 and 206 may be formed on the dielectric layer. In some embodiments, bonding pads 204 and 206 include thin seed layers (not shown separately) made of copper, titanium, nickel, gold, palladium, or combinations thereof. The conductive material of bonding pads 204 and 206 can be deposited on a thin seed layer. The conductive material can be formed by electrochemical plating, chemical plating, CVD, ALD, PVD, or combinations thereof. In some embodiments, the conductive material of bonding pads 204 and 206 is copper, tungsten, aluminum, silver, gold, or combinations thereof.

[0053] In some embodiments, bonding pads 204 and 206 are UBMs comprising three layers of conductive material, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers (e.g., chromium / chromium-copper alloy / copper / gold, titanium / titanium-tungsten / copper, or copper / nickel / gold) may be used for bonding pads 204 and 206. Any suitable material or material layer that may be used for bonding pads 204 and 206 is fully intended to be included within the scope of the present application. In some embodiments, a conductive via 208 extends through the substrate 202 and couples at least one bonding pad 204 to at least one bonding pad 206.

[0054] In the illustrated embodiment, the stacked die 210 is coupled to the substrate 202 via wire bonding 212, but other connections, such as conductive bumps, may be used. In some embodiments, the stacked die 210 is a stacked memory die. For example, the stacked die 210 may be a memory die, such as a low-power (LP) double data rate (DDR) memory module (e.g., LPDDR1, LPDDR2, LPDDR3, LPDDR4), a DRAM die, a combination thereof, etc.

[0055] The stacked die 210 and lead bonding 212 can be sealed with molding material 214. In some embodiments, compression molding can be used to mold the molding material 214 onto the stacked die 210 and lead bonding 212. In some embodiments, the molding material 214 is a molding compound, polymer, epoxy resin, silica material, etc., or a combination thereof. A curing process can be performed to cure the molding material 214. The curing process can be thermosetting, UV curing, etc., or a combination thereof. In some embodiments, the stacked die 210 and lead bonding 212 are embedded in the molding material 214. After the molding material 214 is cured, a planarization step, such as grinding, is performed to remove excess portions of the molding material 214 and provide a planarized surface for the second packaging assembly 200.

[0056] After the second package assembly 200 is formed, the second package assembly 200 can be bonded to the first package assembly 100 via conductive connectors 146, bonding pads 206, and metallization patterns 140. In some embodiments, the stacked die 210 can be coupled to the integrated circuit die 50 via wire bonding 212, bonding pads 204, conductive vias 208, bonding pads 206, conductive connectors 146, back redistribution structure 144, through-vias 126, and front redistribution structure 124.

[0057] In some embodiments, a solder resist (not shown separately) is formed on a second side of the substrate 202. Conductive connectors 146 may be disposed in openings in the solder resist to electrically and mechanically couple to conductive features in the substrate 202 (e.g., bonding pads 206). The solder resist may be used to protect areas of the substrate 202 from external damage. In some embodiments, the conductive connectors 146 have an epoxy solder resist (not shown separately) formed thereon prior to their reflow soldering, and at least some epoxy portions of the epoxy solder resist are retained after the second package assembly 200 is attached to the first package assembly 100.

[0058] exist Figure 12 In this embodiment, a sealant 148 is formed between the first encapsulation assembly 100 and the second encapsulation assembly 200, and surrounds the conductive connector 146. In some embodiments (not shown separately), the sealant 148 may also be formed around the second encapsulation assembly 200, and the sealant 148 may be formed around the first encapsulation assembly 100. The sealant 148 may be a molding compound, epoxy resin, molding underfill, etc. The sealant 148 may be applied by compression molding or transfer molding, etc. The sealant 148 is also formed in the gap region between the second encapsulation assembly 200 and the underlying first encapsulation assembly 100. The sealant 148 may be applied in liquid or semi-liquid form and subsequently cured.

[0059] exist Figure 13In this process, carrier substrate debonding is performed to separate (or “debond”) carrier substrate 102 from first package assembly 100 (e.g., dielectric layer 106). In some embodiments, debonding includes projecting light (e.g., laser or ultraviolet light) onto release layer 104, such that release layer 104 decomposes under the heat of the light and carrier substrate 102 can be removed. After removing carrier substrate 102 and release layer 104, the main surface of dielectric layer 106 can be exposed.

[0060] After removing the carrier substrate 102 and the release layer 104, a UBM 160 and a conductive connector 162 are formed for external connection to the front redistribution structure 124. The UBM 160 includes a bump portion located on and extending along the main surface of the dielectric layer 106, and a via portion extending through the dielectric layer 106. The via portion of the UBM 160 can be electrically coupled to and physically contact the metallization pattern 108. As a result, the UBM 160 is electrically coupled to the through-via 126 and the integrated circuit die 50 via the front redistribution structure 124. The UBM 160 can be formed from the same or similar materials and in a manner as the metallization pattern 108.

[0061] Conductive connectors 162 are formed on the UBM 160. Conductive connectors 162 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. Conductive connectors 162 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, conductive connectors 162 are formed by initially forming a solder layer via vapor deposition, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is structurally formed, reflow soldering can be performed to shape the material into the desired bump shape. In some embodiments, conductive connectors 162 include metal pillars (e.g., copper pillars), which may be formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof. The metal capping layer may be formed by a plating process.

[0062] Further in Figure 13In this embodiment, a first packaging component 100 is mounted to a substrate 300. The substrate 300 may be made of a semiconductor material such as silicon, germanium, or diamond. In some embodiments, compound materials may also be used, such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide, gallium indium phosphide, or combinations thereof. Furthermore, the substrate 300 may be a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium-on-insulator (SGOI), or combinations thereof. In some embodiments, the substrate 300 may be based on an insulating core, such as a glass fiber reinforced resin core. In some embodiments, the core material may be a glass fiber resin, such as FR4. In some embodiments, the core may include bismaleimide triazine (BT) resin, other printed circuit board (PCB) materials, or other thin films. Additive films such as Ajinomoto additive film (ABF) or other lamination materials may be used for the substrate 300.

[0063] Substrate 300 may include active and passive devices (not shown separately). It may include various devices, such as transistors, capacitors, resistors, combinations thereof, etc. Any suitable method may be used to form the devices. Substrate 300 may also include a metallization layer (not shown separately). The metallization layer may be formed over the active and passive devices and is designed to connect the various devices to form a functional circuit. The metallization layer may be formed from alternating layers of a dielectric material (e.g., a low-k dielectric material) and a conductive material (e.g., copper) with vias having interconnecting conductive material layers. The metallization layer may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In some embodiments, substrate 300 is substantially devoid of active and passive devices.

[0064] The substrate 300 may include bonding pads 302 formed on a first side of the substrate 300 facing the first package assembly 100. In some embodiments, the bonding pads 302 may be formed by forming recesses (not shown separately) in a dielectric layer (not shown separately) on the first side of the substrate 300. Recesses may be formed to allow the bonding pads 302 to be embedded in the dielectric layer. In some embodiments, the recesses are omitted and the bonding pads 302 may be formed on the dielectric layer. In some embodiments, the bonding pads 302 include a thin seed layer (not shown separately) made of copper, titanium, nickel, gold, palladium, or combinations thereof. A conductive material for the bonding pads 302 may be deposited on the thin seed layer. The conductive material may be formed by electrochemical plating, chemical plating, CVD, ALD, PVD, or combinations thereof. In embodiments, the conductive material for the bonding pads 302 includes copper, tungsten, aluminum, silver, gold, or combinations thereof.

[0065] In some embodiments, the bonding pad 302 is a UBM comprising three layers of conductive material, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers, such as chromium / chromium-copper alloy / copper / gold, titanium / titanium-tungsten / copper, or copper / nickel / gold, may be used to form the bonding pad 302. Any suitable material or layer of materials that may be used for the bonding pad 302 is fully intended to be included within the scope of the present application.

[0066] The substrate 300 is electrically coupled and physically attached to the first package assembly 100 via bonding pads 302, conductive connectors 162, and UBM 160. The substrate 300 can be placed on the first package assembly 100 and can be subjected to a reflow soldering process to reflow solder the conductive connectors 162 and bond the bonding pads 302 to the UBM 160 via the conductive connectors 162.

[0067] An underfill 164 can then be formed between the first package assembly 100 and the substrate 300, around the bonding pad 302, UBM 160, and conductive connector 162. The underfill 164 can reduce stress and protect the joint from reflow soldering of the conductive connector 162. The underfill 164 can be formed by a capillary flow process after the first package assembly 100 is attached to the substrate 300, or it can be formed by a suitable deposition method before the first package assembly 100 is attached.

[0068] The insulating layer 132, disposed between the sealant 134 and each of the through-via 126, the integrated circuit die 50, and the metallization pattern 120, allows for a wider variety of materials to be used in the sealant 134. For example, the insulating layer 132 provides electrical isolation, allowing conductive materials to be used in the sealant 134. Furthermore, the insulating layer 132 can provide a physical buffer layer, allowing materials with a high coefficient of thermal expansion to be used in the sealant 134. This allows for the use of materials with high thermal conductivity in the sealant 134, which increases heat dissipation through the sealant 134. This improves device performance and reduces device defects.

[0069] Figure 14 and Figure 15 An embodiment is shown in which the integrated circuit die 50A is directly bonded to the front redistribution structure 124 (without conductive connectors 128 and underfill 130 disposed therebetween). Figure 14 In the middle, the integrated circuit die 50A is bonded to Figure 4The front redistribution structure 124 is shown, and an insulating layer 132 and a sealant 134 are formed on the resulting structure. The integrated circuit die 50A may be the same as or similar to the integrated circuit die 50 discussed above. The integrated circuit die 50A is disposed face down such that the front side of the integrated circuit die 50A faces the conductive pad 120B, while the back side of the integrated circuit die 50A faces away from the conductive pad 120B.

[0070] In some embodiments, the integrated circuit die 50A is bonded to the conductive pad 120B of the metallization pattern 120 using a hybrid bonding configuration. For example, the dielectric layer 68 of the integrated circuit die 50A may be directly bonded to the dielectric layer 118 of the front redistribution structure 124, and the die connector 66 of the integrated circuit die 50A may be directly bonded to the conductive pad 120B. In one embodiment, the bonding between the dielectric layer 68 and the dielectric layer 118 may be an oxide-to-oxide bonding or the like. The hybrid bonding process further bonds the die connector 66 of the integrated circuit die 50A directly to the conductive pad 120B via direct metal-to-metal bonding. Therefore, the electrical connection between the integrated circuit die 50A and the front redistribution structure 124 is provided by the physical connection of the die connector 66 to the conductive pad 120B.

[0071] For example, the hybrid bonding process may begin by applying a surface treatment to the dielectric layer 118 of the front redistribution structure 124 and / or the dielectric layer 68 of the integrated circuit die 50A. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to the dielectric layer 118 and / or the dielectric layer 68 of the integrated circuit die 50A. The hybrid bonding process may then proceed to align the die connector 66 with the conductive pad 120B. Next, the hybrid bonding includes a pre-bonding step during which the die connector 66 is brought into physical contact with the conductive pad 120B. The pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C). The hybrid bonding process proceeds to annealing at a temperature of about 150°C to about 400°C for a duration of about 0.5 hours to about 3 hours. Annealing causes the metal (e.g., copper) of die connector 66 and the metal (e.g., copper) of conductive pad 120B to diffuse into each other, thereby forming a direct metal-to-metal bond. Annealing can also form covalent bonds between dielectric layer 68 and dielectric layer 118. In some embodiments, other bonding parameters and / or methods (e.g., solder bonding) may be used.

[0072] After the integrated circuit die 50A is bonded to the front redistribution structure 124, an insulating layer 132 and a sealant 134 can be formed over the through-via 126, the integrated circuit die 50A, and the front redistribution structure. The insulating layer 132 can be made of materials related to the above-mentioned... Figure 7 The same or similar materials and methods are discussed. Similarly, sealant 134 can be formed using the same or similar methods as described above. Figure 7 The same or similar materials and methods discussed are used to form the product.

[0073] Figure 15 This shows the execution of the above regarding Figures 8 to 13 After the discussion of the process Figure 14 The structure of the integrated circuit die 50A is simplified by directly bonding it to the front redistribution structure 124. This eliminates the steps required to form the underfill 130 and reduces the height of the final structure. Furthermore, the insulating layer 132, disposed between the sealant 134 and each of the through-via 126, the integrated circuit die 50A, and the metallization pattern 120, allows for a wider variety of materials to be used in the sealant 134. For example, the insulating layer 132 provides electrical isolation, allowing conductive materials to be used in the sealant 134. Additionally, the insulating layer 132 can provide a physical buffer layer, allowing materials with a high coefficient of thermal expansion to be used in the sealant 134. This allows for the use of materials with high thermal conductivity in the sealant 134, increasing heat dissipation through the sealant 134. This improves device performance and reduces device defects.

[0074] Figures 16 to 18 An embodiment is shown in which multiple integrated circuit dies 50B and 50C, along with interconnect dies 70, are bonded to a front-side redistribution structure 124. Figure 16 and Figure 17 In the process, integrated circuit dies 50B and 50C, as well as interconnect die 70, are bonded to... Figure 4 The front redistribution structure 124 is shown, and an insulating layer 132 and a sealant 134 are formed on the resulting structure. Integrated circuit dies 50B and 50C may be the same as or similar to the integrated circuit die 50 discussed above. Integrated circuit dies 50B and 50C are disposed face down such that the front side of integrated circuit dies 50B and 50C faces the conductive pad 120B, and the back side of integrated circuit dies 50B and 50C faces away from the conductive pad 120B. Furthermore, integrated circuit die 50B may include a through-substrate via (TSV) 67 (also called a through-silicon via) extending through the semiconductor substrate 52 of integrated circuit die 50B.

[0075] The interconnect die 70 can be a local silicon interconnect (LSI), a large-scale integrated package, an interposer die, etc. The interconnect die 70 includes a substrate 72, in which conductive features are formed. The substrate 72 can be a semiconductor substrate or a dielectric layer, etc. The interconnect die 70 may include a through-substrate via (TSV) 74 (also called a through-silicon via) extending into or through the substrate 72. Figures 16 to 18 In the embodiment shown, the TSV 74 extends through the substrate 72 and is exposed on both the front and back sides of the interconnect die 70.

[0076] Integrated circuit die 50B can be connected via conductive connector 128 and underfill 130, through the connection with the above-mentioned... Figure 5 and Figure 6 The discussion focuses on similar or identical processes used to join the front redistribution structure 124. This is in conjunction with the above discussion regarding... Figure 14 The same or similar hybrid bonding processes discussed can be used to bond interconnect die 70 to integrated circuit die 50B and integrated circuit die 50C to interconnect die 70. Specifically, TSV 74 of interconnect die 70 can be bonded to TSV 67 of integrated circuit die 50B via metal-to-metal bonding; substrate 72 of interconnect die 70 can be bonded to semiconductor substrate 52 of integrated circuit die 50B via oxide-to-oxide bonding; die connector 66 of integrated circuit die 50C can be bonded to TSV 74 of interconnect die 70 via metal-to-metal bonding; and dielectric layer 68 of integrated circuit die 50C can be bonded to substrate 72 of interconnect die 70 via oxide-to-oxide bonding. Figure 16 An embodiment is shown in which each of the integrated circuit dies 50B and 50C and the interconnect die 70 has the same width. Figure 17 An embodiment is shown in which interconnect die 70 may have a width smaller than that of integrated circuit die 50B and integrated circuit die 50C may have a width equal to or smaller than that of interconnect die 70. More generally, the width of each die stacked on the front redistribution structure 124 may be equal to or smaller than the width of the die below it stacked thereon. Although in Figure 16 and Figure 17 Each stack in the diagram shows three dies, but may include any number of interconnect dies 70 and integrated circuit dies 50B and 50C.

[0077] After the integrated circuit dies 50B and 50C and the interconnect die 70 are bonded to the front redistribution structure 124, an insulating layer 132 and a sealant 134 can be formed over the through-via 126, the integrated circuit dies 50B and 50C, the interconnect die 70, and the front redistribution structure 124. The insulating layer 132 can be formed from materials related to the above. Figure 7The same or similar materials and methods are discussed. Similarly, sealant 134 can be formed using the same or similar methods as described above. Figure 7 The same or similar materials and methods are used in the discussion.

[0078] Figure 18 This shows the execution of the above regarding Figures 8 to 13 After the discussion of the process Figure 16 The structure includes an insulating layer 132 disposed between the sealant 134 and each of the through-via 126, integrated circuit dies 50B and 50C, interconnect dies 70, and metallization pattern 120, allowing for a wider variety of materials to be used in the sealant 134. For example, the insulating layer 132 provides electrical isolation, allowing conductive materials to be used in the sealant 134. Furthermore, the insulating layer 132 can provide a physical buffer layer, allowing materials with a high coefficient of thermal expansion to be used in the sealant 134. This allows for the use of materials with high thermal conductivity in the sealant 134, which increases heat dissipation through the sealant 134. This improves device performance and reduces device defects. Additionally, providing a stack of dies surrounded by the sealant 134 improves heat dissipation for all the sealant dies and provides improved functionality to the package structure.

[0079] Figures 19 to 21 An embodiment is shown in which interconnect die 70A is directly bonded to the front redistribution structure 124, and integrated circuit die 50D is directly bonded to interconnect die 70A or directly bonded to interconnect die 70B (interconnect die 70B is directly bonded to interconnect die 70A). Figure 19 In the process, integrated circuit die 50D is bonded to interconnect die 70A, and the stack including integrated circuit die 50D and interconnect die 70A is bonded to... Figure 4 The front redistribution structure 124 is shown. An insulating layer 132 and a sealant 134 are formed on the resulting structure. Figure 20 In the process, integrated circuit die 50D is bonded to interconnect die 70B, interconnect die 70B is bonded to interconnect die 70A, and the stack of integrated circuit die 50D, interconnect die 70B and interconnect die 70A is bonded to... Figure 4 The front redistribution structure 124 is shown. An insulating layer 132 and a sealant 134 are formed on the resulting structure. The integrated circuit die 50D may be the same as or similar to the integrated circuit die 50 discussed above. Integrated circuit dies 50B and 50C are disposed face down such that the front sides of integrated circuit dies 50B and 50C face the conductive pad 120B, and the back sides of integrated circuit dies 50B and 50C face away from the conductive pad 120B. Interconnect dies 70A and 70B may be the same as or similar to the interconnect die 70 discussed above.

[0080] Interconnect die 70A can be connected to the above-mentioned... Figure 14The same or similar hybrid bonding processes are discussed for bonding to the front redistribution structure 124. Specifically, the TSV 74 of interconnect die 70A can be bonded to the conductive pad 120B of the front redistribution structure 124 via metal-to-metal bonding, and the substrate 72 of interconnect die 70A can be bonded to the dielectric layer 118 of the front redistribution structure 124 via oxide-to-oxide bonding. Interconnect die 70B can be bonded to the dielectric layer 118 of the front redistribution structure 124 via the same or similar hybrid bonding processes discussed above. Figure 14 The same or similar hybrid bonding processes are discussed for bonding to interconnect die 70A. Specifically, the TSV 74 of interconnect die 70B can be bonded to the TSV 74 of interconnect die 70A via metal-to-metal bonding, and the substrate 72 of interconnect die 70B can be bonded to the substrate 72 of interconnect die 70A via oxide-to-oxide bonding. Integrated circuit die 50D can be bonded to the substrate 72 of interconnect die 70A via the same or similar hybrid bonding processes discussed above. Figure 14 The same or similar hybrid bonding processes are discussed for bonding to interconnect dies 70A or 70B. Specifically, die connector 66 of integrated circuit die 50D can be bonded to TSV74 of interconnect die 70A or 70B via metal-to-metal bonding, and dielectric layer 68 of integrated circuit die 50D can be bonded to substrate 72 of interconnect die 70A or 70B via oxide-to-oxide bonding.

[0081] Figure 19 An embodiment is shown in which each of the integrated circuit die 50D and the interconnect die 70A has the same width, and each integrated circuit die 50D is bonded to the front redistribution structure 124 via a single interconnect die 70A. Figure 20 An embodiment is shown in which interconnect die 70B can have a width smaller than that of interconnect die 70A and integrated circuit die 50D can have a width equal to or smaller than that of interconnect die 70B. More generally, the width of each die stacked on the front redistribution structure 124 can be equal to or smaller than the width of the die below it stacked thereon. Further in Figure 20 In this configuration, each integrated circuit die 50D is bonded to the front redistribution structure 124 via interconnect dies 70B and 70A. Although in Figure 19 Two dies are shown in each stack and in Figure 20 Each stack in the diagram shows three dies, but may include any number of interconnect dies 70A, interconnect dies 70B, and integrated circuit dies 50D.

[0082] After the integrated circuit die 50D and interconnect dies 70A and 70B are bonded to the front redistribution structure 124, an insulating layer 132 and a sealant 134 can be formed on the through-via 126, the integrated circuit die 50D, the interconnect dies 70A and 70B, and the front redistribution structure 124. The insulating layer 132 can be formed from the above-mentioned... Figure 7 The same or similar materials and methods are discussed. Similarly, sealant 134 can be formed using the same or similar methods as described above. Figure 7 The materials discussed are the same or similar materials and are formed in the same way.

[0083] Figure 21 This shows the execution of the above regarding Figures 8 to 13 After the discussion of the process Figure 19 The structure includes an insulating layer 132 disposed between the sealant 134 and each of the through-via 126, integrated circuit die 50D, interconnect dies 70A and 70B, and metallization pattern 120, allowing for a wider variety of materials to be used in the sealant 134. For example, the insulating layer 132 provides electrical isolation, allowing conductive materials to be used in the sealant 134. Furthermore, the insulating layer 132 can provide a physical buffer layer, allowing materials with a high coefficient of thermal expansion to be used in the sealant 134. This allows for the use of materials with high thermal conductivity in the sealant 134, which increases heat dissipation through the sealant 134. This improves device performance and reduces device defects. Moreover, providing a stack of dies surrounded by the sealant 134 improves heat dissipation for all the sealant dies and provides improved functionality to the package structure.

[0084] Figures 22 to 25 Insulating layer 408 is shown. Figures 23 to 25 (As shown) An embodiment is formed along the sidewall of the through-hole 126, and not on the front redistribution structure 125 or the remainder of the integrated circuit die 50. Figure 22 In the middle, mask layer 402 and photoresist 404 are formed in Figure 3 The mask layer 402 is shown on the front redistribution structure 124. The mask layer 402 may include, for example, silicon nitride or silicon oxynitride. In some embodiments, the mask layer 402 may be a polymer layer. For example, the mask layer 402 can be formed by spin coating, lamination, CVD, ALD, etc. A photoresist 404 is formed on the mask layer 402. The photoresist 404 can be formed by depositing a photosensitive layer on the mask layer 402 using spin coating or the like.

[0085] The photoresist 404 and mask layer 402 can then be patterned. The photoresist 404 can be patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing it to remove exposed or unexposed portions. An opening 406 is formed in the mask layer 402, extending through the photoresist 404. The photoresist 404 can be used as a mask to etch the mask layer 402 using any acceptable etching process (e.g., reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof). The mask layer 402 can be etched using an anisotropic etching process.

[0086] exist Figure 23 In the process, photoresist 404 is removed and an insulating layer 408 is formed along the sidewall of mask layer 402 in opening 406. Photoresist 404 can be removed by an acceptable ashing or stripping process (e.g., using oxygen plasma). Insulating layer 408 can be formed of the same or similar material as insulating layer 132 and deposited in the same or similar manner as insulating layer 132. After depositing insulating layer 408, insulating layer 408 can be etched to expose conductive pads 120A of front redistribution structure 124. Insulating layer 408 can have a thickness t2 ranging from about 10 nm to about 100 nm. Forming insulating layer 408 to a thickness less than the specified range may result in difficulties in forming insulating layer 408 and may not be sufficient to provide the advantages of insulating layer 408 (e.g., providing electrical isolation for subsequently formed vias (e.g., via 126), as discussed below). Figure 24 (Discussion). Furthermore, the insulating layer 408 can be made of a sealant with a lower thermal conductivity than the subsequently formed sealant (e.g., sealant 134, discussed below). Figure 25 The material formation of the material (discussion). Forming the insulating layer 408 to a thickness greater than the specified range reduces the combined thermal conductivity of the insulating layer 408 and the sealant 134.

[0087] exist Figure 24In this configuration, via 126 is formed on conductive pad 120A of the metallization pattern 120 and fills opening 406. Via 126 may extend away from the topmost dielectric layer (e.g., dielectric layer 118) of the front redistribution structure 124 and may extend between portions of insulating layer 408 formed on opposite sidewalls of each opening 406. As an example of forming via 126, a seed layer (not shown separately) is formed in the opening 406 above conductive pad 120A and insulating layer 408 and above mask layer 402. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In a particular embodiment, the seed layer comprises a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using, for example, PVD. In some embodiments, such as those where the width of via 126 is equal to or narrower than the underlying conductive pad 120A, a separate seed layer may be omitted, and conductive pad 120A may serve as the seed layer. A conductive material is then formed on the seed layer and fills the opening 406. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. After the conductive material is formed, a planarization process can be performed on the conductive material and the seed layer. The planarization process can be CMP or polishing, etc. The remaining portion of the seed layer and conductive material forms the via 126. After the planarization process, the top surface of the via 126, the top surface of the insulating layer 408, and the top surface of the mask layer 402 can be flush with each other (e.g., within the range of process variations).

[0088] exist Figure 25 In the middle, remove the mask layer 402 and perform the above-mentioned steps. Figures 5 to 13 The discussed process (the process for forming the insulating layer 132 is omitted). The mask layer 402 can be removed by an etching process, such as isotropic or anisotropic etching. The inclusion of the insulating layer 408 disposed between the sealant 134 and the through-via 126 allows for a wider variety of materials to be used in the sealant 134. For example, the insulating layer 408 provides electrical isolation, allowing conductive materials to be used in the sealant 134. Furthermore, the insulating layer 408 can provide a physical buffer layer, allowing materials with a high coefficient of thermal expansion to be used in the sealant 134. This allows materials with high thermal conductivity to be used in the sealant 134, which increases heat dissipation through the sealant 134. This improves device performance and reduces device defects. Furthermore, forming the insulating layer 408 only along the sidewalls of the through-via 126 improves the deposition accuracy of the insulating layer 408 and reduces the amount of material used for the insulating layer 408. However, forming the insulating layer 408 only along the sidewalls of the through-via 126 may also increase cost compared to the embodiment that forms the insulating layer 132.

[0089] The embodiments can achieve various advantages. For example, forming an insulating layer above the underlying vias, redistribution structures, and integrated circuit dies allows for the use of a wider variety of materials in the sealant formed on top of the insulating layer. The insulating layer can provide electrical insulation and physical buffering between the sealant and the underlying structure, allowing the sealant to be formed from both conductive and materials with higher coefficients of thermal expansion. This allows for the use of materials with higher thermal conductivity in the sealant, which improves heat dissipation through the sealant, enhances device performance, and reduces device defects.

[0090] According to one embodiment, a semiconductor device includes: a first redistribution structure; a first die disposed on and electrically coupled to the first redistribution structure; a first through-via disposed on and electrically coupled to the first redistribution structure; an insulating layer extending along the first redistribution structure, the first die, and the first through-via; and a sealant disposed on the insulating layer, the sealant surrounding a portion of the first through-via and a portion of the first die, the sealant comprising a conductive filler at a concentration ranging from 70% to 95% by volume. In one embodiment, the sealant has a thermal conductivity greater than 40 W / m·K. In one embodiment, the top surface of the sealant is flush with the top surface of the first through-via and the top surface of the insulating layer, and the top surface of the sealant is higher than the top surface of the first die. In one embodiment, the insulating layer extends along the sidewalls of the first through-via, the top surface of the first redistribution structure, and the top surface and sidewalls of the first die. In one embodiment, the first die is bonded to the first redistribution structure by oxide-to-oxide bonding and metal-to-metal bonding. In one embodiment, a first die is bonded to a first redistribution structure via a conductive connector. The semiconductor device also includes a first underfill surrounding the conductive connector, and an insulating layer extends along the sidewalls of the first underfill. In one embodiment, the thickness of the insulating layer ranges from 10 nm to 100 nm, and the thermal conductivity of the sealant ranges from 40 W / m·K to 100 W / m·K.

[0091] According to another embodiment, a semiconductor device includes: a first integrated circuit die; a front redistribution structure located on the front side of the first integrated circuit die; a back redistribution structure located on the back side of the first integrated circuit die; a molding compound that seals the first integrated circuit die between the front redistribution structure and the back redistribution structure, the molding compound having a thermal conductivity greater than 40 W / m·K; a through-via extending through the molding compound and electrically coupled to the front redistribution structure and the back redistribution structure; and an insulating layer covering the sidewalls of the through-via, the insulating layer separating the through-via from the molding compound. In one embodiment, the molding compound includes conductive particles selected from copper (Cu), silicon (Si), silver (Ag), gold (Au), iron (Fe), and tungsten (W), and the molding compound includes conductive particles at a concentration ranging from 70% to 95% by volume. In one embodiment, the thermal conductivity of the molding compound ranges from 40 W / m·K to 100 W / m·K, and the thermal conductivity of the insulating layer is less than the thermal conductivity of the molding compound. In one embodiment, the insulating layer comprises at least one of the following: aluminum nitride (AlN), boron nitride (BN), beryllium oxide (BeO), diamond, or aluminum oxide (Al2O3). In one embodiment, the semiconductor device further comprises an interconnect die bonded to the first integrated circuit die by metal-to-metal bonding and oxide-to-oxide bonding. In one embodiment, the molding compound body contacts the front redistribution structure, the back redistribution structure, and the first integrated circuit die. In one embodiment, the insulating layer covers the top surface of the front redistribution structure and the back surface and sidewalls of the first integrated circuit die, and the insulating layer separates the front redistribution structure and the first integrated circuit die from the molding compound.

[0092] According to another embodiment, a method includes: forming a through-via over a redistribution structure; bonding a semiconductor die to the redistribution structure adjacent to the through-via; depositing an insulating layer over the through-via, the redistribution structure, and the semiconductor die, the insulating layer electrically isolating the through-via, the redistribution structure, and the semiconductor die from each other; and preparing a molding compound by mixing an epoxy resin and a conductive filler, the conductive filler comprising 70% to 95% by volume of the molding compound; and depositing the molding compound over the insulating layer, the molding compound being configured to conduct heat from the semiconductor die. In one embodiment, the insulating layer is deposited using a conformal deposition process. In one embodiment, the method further includes planarizing the molding compound and the insulating layer to expose the through-via. In one embodiment, bonding the semiconductor die to the redistribution structure includes: reflow soldering a conductive connector between the semiconductor die and the redistribution structure; and forming an underfill material around the conductive connector, the insulating layer being deposited on the sidewalls of the underfill material. In one embodiment, bonding the semiconductor die to the redistribution structure includes forming an oxide-to-oxide bond and a metal-to-metal bond between the semiconductor die and the redistribution structure. In one embodiment, bonding a semiconductor die to a redistribution structure includes bonding a die stack to the redistribution structure, the die stack including a semiconductor die and an interconnect die, wherein an insulating layer is also deposited on the interconnect die.

[0093] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0094] Example 1. A semiconductor device, comprising:

[0095] First redistribution structure;

[0096] The first die is located on the first redistribution structure and electrically coupled to the first redistribution structure;

[0097] A first through-hole is located on the first redistribution structure and electrically coupled to the first redistribution structure;

[0098] An insulating layer extends along the first redistribution structure, the first die, and the first through-hole; and

[0099] A sealant is located above the insulating layer, the sealant surrounding a portion of the first through-hole and a portion of the first die, wherein the sealant comprises conductive filler in a concentration ranging from 70% to about 95% by volume.

[0100] Example 2. The semiconductor device according to Example 1, wherein the sealant has a thermal conductivity greater than 40 W / m·K.

[0101] Example 3. The semiconductor device according to Example 1, wherein the top surface of the sealant is flush with the top surface of the first through-hole and the top surface of the insulating layer, and wherein the top surface of the sealant is higher than the top surface of the first die.

[0102] Example 4. The semiconductor device according to Example 1, wherein the insulating layer extends along the sidewall of the first through-hole, the top surface of the first redistribution structure, and the top surface and sidewall of the first die.

[0103] Example 5. The semiconductor device according to Example 1, wherein the first die is bonded to the first redistribution structure by oxide-to-oxide bonding and metal-to-metal bonding.

[0104] Example 6. The semiconductor device according to Example 1, wherein the first die is bonded to the first redistribution structure via a conductive connector, wherein the semiconductor device further includes a first underfill surrounding the conductive connector, and wherein the insulating layer extends along the sidewall of the first underfill.

[0105] Example 7. The semiconductor device according to Example 1, wherein the thickness of the insulating layer ranges from 10 nm to 100 nm, and wherein the thermal conductivity of the sealant ranges from 40 W / m·K to 100 W / m·K.

[0106] Example 8. A semiconductor device comprising:

[0107] First integrated circuit die;

[0108] The front redistribution structure is located on the front side of the first integrated circuit die;

[0109] The back-side redistribution structure is located on the back side of the first integrated circuit die;

[0110] A molding compound that seals the first integrated circuit die between the front redistribution structure and the back redistribution structure, wherein the molding compound has a thermal conductivity greater than 40 W / m·K;

[0111] A through-hole extends through the molding compound, wherein the through-hole is electrically coupled to the front redistribution structure and the back redistribution structure; and

[0112] An insulating layer covers the sidewalls of the through-hole, wherein the insulating layer separates the through-hole from the molding compound.

[0113] Example 9. The semiconductor device according to Example 8, wherein the molding compound comprises conductive particles selected from copper (Cu), silicon (Si), silver (Ag), gold (Au), iron (Fe) and tungsten (W), and wherein the molding compound comprises conductive particles in a concentration ranging from 70% to 95% by volume.

[0114] Example 10. The semiconductor device according to Example 8, wherein the thermal conductivity of the molding compound is in the range of 40 W / m·K to 100 W / m·K, and wherein the thermal conductivity of the insulating layer is less than the thermal conductivity of the molding compound.

[0115] Example 11. The semiconductor device according to Example 8, wherein the insulating layer comprises at least one of the following: aluminum nitride (AlN), boron nitride (BN), beryllium oxide (BeO), diamond, or aluminum oxide (Al2O3).

[0116] Example 12. The semiconductor device according to Example 8 further includes: an interconnect die, the interconnect die being bonded to the first integrated circuit die by metal-to-metal bonding and oxide-to-oxide bonding.

[0117] Example 13. The semiconductor device according to Example 8, wherein the molded compound entity contacts the front redistribution structure, the back redistribution structure and the first integrated circuit die.

[0118] Example 14. The semiconductor device according to Example 8, wherein the insulating layer covers the top surface of the front redistribution structure and the back surface and sidewalls of the first integrated circuit die, and wherein the insulating layer separates the front redistribution structure and the first integrated circuit die from the molding compound.

[0119] Example 15. A method comprising:

[0120] A through-hole is formed on the redistributed structure;

[0121] The semiconductor die is bonded to the redistribution structure adjacent to the through-hole;

[0122] An insulating layer is deposited over the through-via, the redistribution structure, and the semiconductor die, wherein the insulating layer electrically isolates the through-via, the redistribution structure, and the semiconductor die from each other;

[0123] A molding compound is prepared by mixing an epoxy resin and a conductive filler, wherein the conductive filler comprises 70% to 95% by volume of the molding compound; and

[0124] The molding compound is deposited on the insulating layer and is configured to conduct heat from the semiconductor die.

[0125] Example 16. The method according to Example 15, wherein the insulating layer is deposited by a conformal deposition process.

[0126] Example 17. The method according to Example 15 further includes: planarizing the molding compound and the insulating layer to expose the through-hole.

[0127] Example 18. The method according to Example 15, wherein bonding the semiconductor die to the redistribution structure comprises:

[0128] Reflow soldering conductive connectors between the semiconductor die and the redistribution structure; and

[0129] An underfill material is formed around the conductive connector, wherein the insulating layer is deposited on the sidewalls of the underfill material.

[0130] Example 19. The method according to Example 15, wherein bonding the semiconductor die to the redistribution structure includes forming an oxide-to-oxide bond and a metal-to-metal bond between the semiconductor die and the redistribution structure.

[0131] Example 20. The method according to Example 15, wherein bonding the semiconductor die to the redistribution structure includes bonding a die stack to the redistribution structure, the die stack including the semiconductor die and interconnect dies, wherein the insulating layer is further deposited on the interconnect dies.

Claims

1. A semiconductor device, comprising: First redistribution structure; A first die is located on the first redistribution structure and electrically coupled to the first redistribution structure; A first through-hole is located on the first redistribution structure and electrically coupled to the first redistribution structure; An insulating layer extends along the first redistribution structure, the first die, and the first through-hole, wherein the thickness of the insulating layer ranges from 10 nm to 100 nm; and A sealant is located above the insulating layer, the sealant surrounding a portion of the first through-hole and a portion of the first die, wherein the sealant comprises conductive filler in a concentration ranging from 70% to 95% by volume.

2. The semiconductor device according to claim 1, wherein, The sealant has a thermal conductivity greater than 40 W / m•K.

3. The semiconductor device according to claim 1, wherein, The top surface of the sealant is flush with the top surface of the first through-hole and the top surface of the insulating layer, wherein the top surface of the sealant is higher than the top surface of the first die.

4. The semiconductor device according to claim 1, wherein, The insulating layer extends along the sidewall of the first through-hole, the top surface of the first redistribution structure, and the top surface and sidewall of the first die.

5. The semiconductor device according to claim 1, wherein, The first die is bonded to the first redistribution structure by oxide-to-oxide bonding and metal-to-metal bonding.

6. The semiconductor device according to claim 1, wherein, The first die is bonded to the first redistribution structure via a conductive connector, wherein the semiconductor device further includes a first underfill surrounding the conductive connector, and wherein the insulating layer extends along the sidewall of the first underfill.

7. The semiconductor device according to claim 1, wherein, The thermal conductivity of the sealant ranges from 40 W / m•K to 100 W / m•K.

8. A semiconductor device, comprising: First integrated circuit die; The front redistribution structure is located on the front side of the first integrated circuit die; The back-side redistribution structure is located on the back side of the first integrated circuit die; A molding compound that seals the first integrated circuit die between the front redistribution structure and the back redistribution structure, the molding compound having a thermal conductivity greater than 40 W / m•K; A through-hole extends through the molding compound, wherein the through-hole is electrically coupled to the front redistribution structure and the back redistribution structure; and An insulating layer covers the sidewalls of the through-hole, wherein the insulating layer separates the through-hole from the molding compound, and the thickness of the insulating layer ranges from 10 nm to 100 nm.

9. The semiconductor device according to claim 8, wherein, The molding compound comprises conductive particles selected from copper (Cu), silicon (Si), silver (Ag), gold (Au), iron (Fe), and tungsten (W), and wherein the molding compound comprises conductive particles in a concentration ranging from 70% to 95% by volume.

10. The semiconductor device according to claim 8, wherein, The thermal conductivity of the molding compound ranges from 40 W / m•K to 100 W / m•K, and wherein the thermal conductivity of the insulating layer is less than that of the molding compound.

11. The semiconductor device according to claim 8, wherein, The insulating layer includes at least one of the following: aluminum nitride (AlN), boron nitride (BN), beryllium oxide (BeO), diamond, or aluminum oxide (Al2O3).

12. The semiconductor device according to claim 8, further comprising: Interconnect die, which is bonded to the first integrated circuit die by metal-to-metal bonding and oxide-to-oxide bonding.

13. The semiconductor device according to claim 8, wherein, The molded compound entity contacts the front redistribution structure, the back redistribution structure, and the first integrated circuit die.

14. The semiconductor device according to claim 8, wherein, The insulating layer covers the top surface of the front redistribution structure and the back and sidewalls of the first integrated circuit die, and wherein the insulating layer separates the front redistribution structure and the first integrated circuit die from the molding compound.

15. A method comprising: A through-hole is formed on the redistributed structure; The semiconductor die is bonded to the redistribution structure adjacent to the through-hole; An insulating layer is deposited on the through-via, the redistribution structure, and the semiconductor die, wherein the insulating layer electrically isolates the through-via, the redistribution structure, and the semiconductor die from each other, and the thickness of the insulating layer ranges from 10 nm to 100 nm. A molding compound is prepared by mixing an epoxy resin and a conductive filler, wherein the conductive filler comprises 70% to 95% by volume of the molding compound; and The molding compound is deposited on the insulating layer and is configured to conduct heat from the semiconductor die.

16. The method according to claim 15, wherein, The insulating layer is deposited using a conformal deposition process.

17. The method of claim 15, further comprising: The molding compound and the insulating layer are planarized to expose the through-hole.

18. The method according to claim 15, wherein, Bonding the semiconductor die to the redistribution structure includes: Reflow soldering conductive connectors between the semiconductor die and the redistribution structure; and An underfill material is formed around the conductive connector, wherein the insulating layer is deposited on the sidewalls of the underfill material.

19. The method according to claim 15, wherein, Bonding the semiconductor die to the redistribution structure includes forming oxide-to-oxide and metal-to-metal bonds between the semiconductor die and the redistribution structure.

20. The method of claim 15, wherein, Bonding the semiconductor die to the redistribution structure includes bonding a die stack to the redistribution structure, the die stack including the semiconductor die and interconnect dies, wherein the insulating layer is further deposited on the interconnect dies.

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