Memory cell and semiconductor memory device having memory cells

Abstract

A highly integrated memory cell and a semiconductor memory device including the same are provided. According to the present invention, a semiconductor memory device includes a substrate, an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, and including a thin body channel, a bit line extending in a direction perpendicular to the substrate and connected to one side of the active layer, a capacitor connected to the other side of the active layer, and a first word line and a second word line extending in a direction crossing the thin body channel, the thin body channel being interposed between the first word line and the second word line, wherein a thickness of the thin body channel is less than a thickness of the first word line and the second word line.

Description

[0001] Cross-references to related applications This application claims priority to Korean Patent Application No. 10-2021-0014052, filed on February 1, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor memory device, and more particularly, to a memory cell or a semiconductor memory device including the memory cell. Background Technology

[0003] The integration density of two-dimensional semiconductor memory devices is primarily determined by the area occupied by a single memory cell. Therefore, the level of technology for forming microstructures significantly impacts integration density. The integration density of two-dimensional semiconductor memory devices continues to improve. However, this increase is limited because fine patterning requires very expensive tools. Therefore, three-dimensional (3D) semiconductor memory devices with memory cells arranged in a three-dimensional manner are being proposed. Summary of the Invention

[0004] Embodiments of this disclosure provide highly integrated memory cells and semiconductor memory devices including the memory cells.

[0005] According to one embodiment of the present invention, a semiconductor memory device includes: a substrate; an active layer spaced apart from the substrate, extending in a direction parallel to the substrate and including a thin-body channel; a bit line extending in a direction perpendicular to the substrate and connected to one side of the active layer; a capacitor connected to the other side of the active layer; and a first word line and a second word line extending in a direction intersecting the thin-body channel, the thin-body channel being inserted between the first word line and the second word line, wherein the thickness of the thin-body channel is less than (i.e., thinner than) the thickness of the first word line and the second word line.

[0006] According to one embodiment, a semiconductor memory device includes: a substrate and a memory cell array, the memory cell array including memory cells stacked along a direction perpendicular to the substrate, wherein each memory cell includes: a bit line oriented perpendicularly to the substrate; a capacitor laterally spaced from the bit line; an active layer laterally oriented between the bit line and the capacitor; and a word line disposed on top of the active layer and laterally oriented to intersect the active layer, wherein the active layer includes a thin-body channel with a thickness less than the thickness of the word line.

[0007] According to one embodiment, a semiconductor memory device includes a substrate and a three-dimensional memory cell array of memory cells disposed on an upper portion of the substrate. Each memory cell of the three-dimensional memory cell array includes a transistor and a first word line and a second word line. The transistor includes a thin-body channel oriented parallel to the surface of the substrate. The first word line and the second word line are opposite to each other. The thin-body channel is inserted between the first word line and the second word line, and the thickness of the thin-body channel is thinner than the thickness of the first word line and the second word line.

[0008] This disclosure includes a vertically stacked active layer comprising thin-body channels. Therefore, refresh characteristics can be improved by enhancing the floating body effect (FBE). Attached Figure Description

[0009] Figure 1 This is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention.

[0010] Figure 2A It is along Figure 1 A cross-sectional view of a semiconductor memory device taken by line A1-A1'.

[0011] Figure 2B This is an enlarged view of the transistor TR.

[0012] Figure 2C This is a modified example of transistor TR'.

[0013] Figure 3A This is a schematic perspective view of a semiconductor memory device according to an embodiment of the present invention.

[0014] Figure 3B This is a layout diagram of a semiconductor memory device according to an embodiment of the present invention.

[0015] Figure 3C It is along Figure 3B A cross-sectional view of a semiconductor memory device taken by line A11-A11'.

[0016] Figure 4 This is a schematic cross-sectional view of a memory cell array of a semiconductor memory device according to an embodiment of the present invention.

[0017] Figure 5A This is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention.

[0018] Figure 5B It is along Figure 5A A cross-sectional view of a semiconductor memory device taken by line A2-A2'.

[0019] Figure 5C This is a magnified view of a transistor.

[0020] Figure 5D yes Figure 4 A modified example of transistor TR10.

[0021] Figure 6A This is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention.

[0022] Figure 6B It is along Figure 6A A cross-sectional view of a semiconductor memory device taken by line A3-A3'.

[0023] Figure 6C This is a magnified view of a transistor.

[0024] Figure 6D yes Figure 6C A modified example of the transistor TR20.

[0025] Figure 7A This is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention.

[0026] Figure 7B It is along Figure 7A The cross-sectional view taken by line A4-A4'.

[0027] Figure 8A This is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention.

[0028] Figure 8B It is along Figure 8A A cross-sectional view of a semiconductor memory device taken by line A5-A5'.

[0029] Figure 8C This is a magnified view of a transistor.

[0030] Figure 8D This is a modified example of transistor TR40.

[0031] Figure 9 This is a schematic perspective view of a semiconductor memory device according to an embodiment of the present invention.

[0032] Figure 10A This is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention.

[0033] Figure 10B It is along Figure 10A A cross-sectional view of a semiconductor memory device taken by line A6-A6'.

[0034] Figure 10C This is a magnified view of a transistor.

[0035] Figure 11A This is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention.

[0036] Figure 11B It is along Figure 11A A cross-sectional view of a semiconductor memory device taken by line A7-A7'.

[0037] Figure 11C This is a magnified view of a transistor. Detailed Implementation

[0038] The various embodiments described herein will be illustrated with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematic representations of the invention. Therefore, the structure of the drawings can be modified by manufacturing techniques and / or tolerances. Embodiments of the invention are not limited to the specific structures shown in the drawings, but include any variations in structure that can be produced according to manufacturing processes. Furthermore, any regions and region shapes shown in the drawings are schematic diagrams intended to illustrate specific examples of the regional structures of the various elements and are not intended to limit the scope of the invention.

[0039] The embodiments described below can increase memory cell density and reduce parasitic capacitance by vertically stacking memory cells.

[0040] Figure 1 This is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention. Figure 2A It is along Figure 1 A cross-sectional view of a semiconductor memory device taken by line A1-A1'. Figure 2B This is an enlarged view of the transistor TR.

[0041] See Figure 1 , Figure 2A and Figure 2B According to embodiments of the present invention, a unit memory cell MC of a 3D semiconductor memory device may include: a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include: an active layer ACT, a gate dielectric layer GD, and a double word line DWL. The capacitor CAP may include a memory node SN, a dielectric layer DE, and a plate node PN. The bit line BL may have a cylindrical shape extending in a first direction D1. The active layer ACT may have a strip shape extending in a second direction D2 intersecting the first direction D1. The double word line DWL may have a linear shape extending in a third third direction D3 intersecting the first direction D1 and the second direction D2. The plate node PN of the capacitor CAP may be connected to the plate line PL.

[0042] Bit lines BL can be vertically oriented along a first direction. Bit lines BL can be referred to as vertically oriented bit lines or cylindrical bit lines. Bit lines BL can include conductive materials. Bit lines BL can include silicon-based materials, metal-based materials, or combinations thereof. Bit lines BL can include, for example, polysilicon, metals, metal nitrides, metal silicides, or combinations thereof. Vertically stacked memory cells MC can share a single bit line BL. For example, bit lines BL can include polysilicon, titanium nitride (TiN), tungsten, or combinations thereof. For example, bit lines BL can include polysilicon doped with N-type impurities or titanium nitride (TiN). Bit lines BL can include a stack of titanium nitride and tungsten (TiN / W).

[0043] The transistor TR may include an active layer ACT, a gate dielectric layer GD, and a double word line DWL. The DWL may extend in a third direction D3, and the active layer ACT may extend in a second direction D2. The active layer ACT may be arranged laterally from the bit line BL. The double word line DWL may include a first word line WL1 and a second word line WL2. The first word line WL1 and the second word line WL2 may face each other, with the active layer ACT inserted between the first word line WL1 and the second word line WL2. The gate dielectric layer GD may be formed on the upper and lower surfaces of the active layer ACT. The gate dielectric layer GD may include a gate dielectric layer extension GDE that covers a side of the double word line DWL, such as a side adjacent to the second source / drain region DR.

[0044] The active layer ACT can include semiconductor materials or oxide semiconductors. For example, the active layer ACT can include silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO). The active layer ACT can include: a thin-body channel CH, a first source / drain region SR between the thin-body channel CH and the bit line BL, and a second source / drain region DR between the thin-body channel CH and the capacitor.

[0045] Both the first source / drain region SR and the second source / drain region DR can be doped with the same conductive impurities. Both the first source / drain region SR and the second source / drain region DR can be doped with N-type or P-type impurities. Both the first source / drain region SR and the second source / drain region DR can include at least one impurity selected from arsenic (AS), phosphorus (P), boron (B), indium (IN), or combinations thereof. A first side of the first source / drain region SR can be connected to the bit line BL. A second side of the first source / drain region SR can be connected to the thin-body channel CH. A first side of the second source / drain region DR can be connected to the memory node SN. A second side of the second source / drain region DR can be connected to the thin-body channel CH. The second sides of the first source / drain region SR and the second source / drain region DR can partially overlap with one side of the first word line WL1 and one side of the second word line WL2, respectively. The lateral length of the thin-body channel CH along the second direction D2 can be shorter than the lateral length of each of the first source / drain region SR and the second source / drain region DR along the second direction D2. In one embodiment, the lateral length of the thin-body channel CH along the second direction D2 can be longer than the lateral length of each of the first source / drain region SR and the second source / drain region DR along the second direction D2. A bit-line side ohmic contact BOC can be formed between the first source / drain region SR and the bit line BL. The bit-line side ohmic contact BOC can be formed by a reaction between the metal of the bit line BL and the silicon of the first source / drain region SR. The bit-line side ohmic contact BOC may include a metal silicide and can be formed on one edge of the active layer ACT, i.e., on the first side of the first source / drain region SR. A memory node side ohmic contact SOC can be formed between the second source / drain region DR and the memory node SN. The memory node side ohmic contact SOC may include a metal silicide and can be formed on the other edge of the active layer ACT, i.e., on the first side of the second source / drain region DR. The ohmic contact SOC on the storage node side can be formed by the reaction between the metal of the storage node SN and the silicon of the second source / drain region DR.

[0046] The gate dielectric layer (GD) can include: silicon oxide, silicon nitride, metal oxide, metal nitride, metal silicate, high-k materials, ferroelectric materials, antiferroelectric materials, or combinations thereof. Specifically, the gate dielectric layer (GD) can include: silicon oxide (SiO2), silicon nitride (Si3N4), hafnium oxide (IV) (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), aluminum nitride (AlON), hafnium nitride (HfON), hafnium silicate (HfSiO), hafnium silicon nitride (HfSiON), etc.

[0047] Double-word-line (DWL) materials can include metals, metal mixtures, metal alloys, or semiconductor materials. Double-word-line DWL materials can include titanium nitride compounds, tungsten, polycrystalline silicon, or combinations thereof. For example, a double-word-line DWL can include a TiN / W stack, wherein the titanium nitride compound and tungsten are stacked in the stated order. Double-word-line DWL materials can include N-type work function materials or P-type work function materials. N-type work function materials can have a low work function of less than 4.5, while P-type work function materials can have a high work function of more than 4.5.

[0048] The capacitor CAP can be laterally disposed from the transistor TR along the second direction D2. The capacitor CAP can include a storage node SN extending laterally from the active layer ACT along the second direction D2. The capacitor CAP can also include a dielectric layer DE formed on the storage node SN and a plate node PN formed on the dielectric layer DE. The storage node SN, the dielectric layer DE, and the plate node PN can be laterally arranged along the second direction D2. The storage node SN can have a laterally oriented cylindrical shape. The dielectric layer DE can conformally cover the inner and outer walls of the storage node SN. The plate node PN can have a shape extending to the inner and outer walls of the storage node SN formed on the dielectric layer DE. The plate node PN can be connected to a plate line PL. The storage node SN can be electrically connected to the second source / drain region DR and the storage node-side ohmic contact SOC. In one embodiment, the plate node PN together with the plate line PL can have an "E" shape, such as... Figure 2A The cross-sectional view is shown below.

[0049] The storage node SN can have a 3D structure. The 3D structure of the storage node SN can have a lateral 3D structure oriented laterally along the second direction D2. As an example of a 3D structure, the storage node SN can be cylindrical. In one embodiment, the storage node SN can be cylindrical or cylindrical-cylindrical. Cylindrical-cylindrical can refer to a structure combining cylindrical and cylindrical shapes. The uppermost surface of the storage node SN can be at the same level as the top surface of the first word line WL1. The lowermost surface of the storage node SN can be at the same level as the bottom surface of the second word line WL2.

[0050] A plate-type node PN may include internal node N1 and external nodes N2, N3, and N4. Internal node N1 and external nodes N2 through N4 can be interconnected. Internal node N1 may be located inside the housing of the storage node SN. External nodes N2 and N3 may be located outside the housing of the storage node SN, with a dielectric layer DE inserted between external nodes N2 and N3. External node N4 can interconnect internal node N1 with external nodes N2 and N3. External nodes N2 and N3 may be configured to surround the outer wall of the storage node SN. External node N4 can serve as a plate line PL.

[0051] Storage nodes (SN) and plate nodes (PN) can include: metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, storage nodes (SN) and plate nodes (PN) can include: titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, or tungsten nitride / tungsten (WN / W) stacks. Plate nodes (ON) can include combinations of metal-based materials and silicon-based materials. For example, plate nodes (PN) can be titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stacks. In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium (SiGe) can be used as a gap filler material inside the cylinder of the storage node SN, titanium nitride (TiN) can be used as a plate node PN of the capacitor CAP, and tungsten nitride (WN) can be a low-resistance material.

[0052] The dielectric layer DE may comprise silicon oxide, silicon nitride, high-k materials, or combinations thereof. The high-k material may have a higher dielectric constant than silicon oxide. In one embodiment, silicon oxide (SiO2) may have a dielectric constant of approximately 3.9, and the dielectric layer DE may comprise a high-k material having a dielectric constant of 4 or greater. In one embodiment, the high-k material may have a dielectric constant of approximately 20 or greater. High-k materials may include: hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In one embodiment, the dielectric layer DE may be formed from a composite layer comprising two or more layers of the aforementioned high-k materials.

[0053] The dielectric layer DE can be formed from a zirconium (Zr)-based oxide. The dielectric layer DE can have a stacked structure including zirconium oxide (ZrO2). The stacked structure including zirconium oxide (ZrO2) can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can have a structure where alumina (Al2O3) is stacked on top of zirconium oxide (ZrO2). The ZAZ stack can have a structure where zirconium oxide (ZrO2), alumina (Al2O3), and zirconium oxide (ZrO2) are stacked sequentially in the aforementioned order. The ZA and ZAZ stacks can be referred to as zirconium oxide (ZrO2)-based layers. In one embodiment, the dielectric layer DE can be formed from a hafnium (Hf)-based oxide. The dielectric layer DE can have a stacked structure including hafnium oxide (HfO2). Layered structures including hafnium oxide (HfO2) can include HA (HfO2 / Al2O3) stacks or HAH (HfO2 / Al2O3 / HfO2) stacks. HA stacks can have a structure where alumina (Al2O3) is stacked on top of hafnium oxide (HfO2). HAH stacks can have a structure in which hafnium oxide (HfO2), alumina (Al2O3), and hafnium(IV) oxide (HfO2) are stacked sequentially in the aforementioned order. HA and HAH stacks can be referred to as hafnium oxide (HfO2)-based layers. In ZA stacks, ZAZ stacks, HA stacks, and HAH stacks, alumina (Al2O3) can have a higher band gap than zirconium oxide (ZrO2) and hafnium(IV) oxide (HfO2). Alumina (Al₂O₃) can have a lower dielectric constant than zirconium oxide (ZrO₂) and hafnium oxide (HfO₂). Therefore, the dielectric layer DE can include a stack of a high-k material and a high-bandgap material with a larger bandgap than the high-k material. The dielectric layer DE can include silicon oxide (SiO₂) instead of alumina (Al₂O₃) as the high-bandgap material. Because the dielectric layer DE contains a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be thinner than the high-k material. In one embodiment, the dielectric layer DE can include a laminated structure of alternating layers of high-k and high-bandgap materials. For example, the dielectric layer DE can include: ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the laminated structure described above, alumina (Al2O3) can be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0054] In one embodiment, the dielectric layer DE may include a stacked structure, laminated structure, or hybrid structure comprising zirconium oxide, hafnium oxide, and aluminum oxide.

[0055] In one embodiment, an interface control layer for improving leakage current can be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2). The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0056] Capacitors (CAP) can include metal-insulator-metal (MIM) capacitors. Storage nodes (SN) and plate nodes (PN) can include metal-based materials.

[0057] Capacitors (CAPs) can be replaced by other data storage materials. For example, data storage materials can include phase change materials, magnetic tunnel junction materials, or variable resistance materials.

[0058] An oxide-based dielectric layer IL1 can be formed between the bit line BL and the double word line DWL. The oxide-based dielectric layer IL1 may include silicon oxide.

[0059] A nitride-based dielectric layer IL2 and a carbon-containing dielectric layer IL3 can be formed between the dual word line (DWL) and the memory node (SN). The nitride-based dielectric layer IL2 may include a silicon nitride compound. The carbon-containing dielectric layer IL3 may include a silicon carbon nitride compound (SiCN), a silicon carbon oxide (SiCO), or a combination thereof. The nitride-based dielectric layer IL2 can be formed between the first word line (WL1) and the memory node (SN). The carbon-containing dielectric layer IL3 can be formed between the second word line (WL2) and the memory node (SN). The carbon-containing dielectric layer IL3 can have etch selectivity relative to the oxide-based dielectric layer IL1 and the nitride-based dielectric layer IL2. In other words, the carbon-containing dielectric layer IL3 can be used as an etch stop layer.

[0060] See you again Figure 2A and 2B The transistor TR is a unit transistor and therefore can have a double word line (DWL). In the double word line DWL, the first word line WL1 and the second word line WL2 can have the same potential. For example, the first word line WL1 and the second word line WL2 can form a single parallel-driven memory cell MC. Equal word line drive voltages can be applied to the first word line WL1 and the second word line WL2. That is, the unit memory cell MC according to an embodiment of the present invention may include a double word line DWL, with the first word line WL1 and the second word line WL2 adjacent to a single thin-body channel CH.

[0061] In one embodiment, the first word line WL1 and the second word line WL2 may have different potentials. For example, a word line drive voltage may be applied to the first word line WL1, and a reference voltage (e.g., ground voltage) may be applied to the second word line WL2. The second word line WL2 may be referred to as a back word line or a shielded word line. In one embodiment, the reference voltage (e.g., ground voltage) may be applied to the first word line WL1, and the word line drive voltage may be applied to the second word line WL2.

[0062] Each of the first word line WL1 and the second word line WL2 may have a first thickness V1, which is measured in a direction parallel to the first direction D1. The active layer ACT may have a second thickness V2, which is measured in a direction parallel to the first direction D1. The first thickness V1 and the second thickness V2 may refer to vertical thicknesses. The second thickness V2 may be less than the first thickness V1. The thickness of the active layer ACT may be less than the thickness of the first word line WL1 and the second word line WL2. The active layer ACT may be referred to as a thin-body active layer.

[0063] The thin channel CH may have a second thickness V2, which is measured in a direction parallel to the first direction D1. The second thickness V2 of the thin channel CH may be less than the thickness of the first word line WL1 and the second word line WL2. The second thickness V2 of the thin channel CH may be greater than (i.e., thicker than) the thickness of the gate dielectric layer GD. The thin channel CH and the gate dielectric layer GD may have the same thickness.

[0064] The first source / drain region SR may have a third thickness V3, which is measured in a direction parallel to the first direction D1. The second source / drain region DR may have a fourth thickness V4, which is measured in a direction parallel to the first direction D1. The third thickness V3 of the first source / drain region SR, the fourth thickness V4 of the second source / drain region DR, and the second thickness V2 of the thin-body channel CH may be the same. The third thickness V3 of the first source / drain region SR and the fourth thickness V4 of the second source / drain region DR may be less than the first thickness V1 of the first word line WL1 and the second word line WL2.

[0065] The second thickness V2 of the thin channel CH can be equal to or less than 7 nm. The third thickness V3 of the first source / drain region SR and the fourth thickness V4 of the second source / drain region DR can be equal to or less than 7 nm. In one embodiment, the third thickness V3 of the first source / drain region SR and the fourth thickness V4 of the second source / drain region DR can be less than the first thickness V1 of the first word line WL1 and the second word line WL2, but greater than the second thickness V2 of the thin channel CH.

[0066] The upper and lower surfaces of the active layer ACT can be flat surfaces. That is, the upper and lower surfaces of the active layer ACT can be parallel to each other along the second direction D2.

[0067] Figure 2C The diagram shows... Figure 1 Example of a modified transistor.

[0068] See Figure 2C The transistor TR' may include an active layer ACT1 and a double word line DWL1. The double word line DWL1 may include a first word line WL1' and a second word line WL2' facing each other, with the active layer ACT1 inserted between the first word line WL1' and the second word line WL2'. The active layer ACT1 may include: a thin-body channel CH', a first source / drain region SR' on one side of the thin-body channel CH', and a second source / drain region DR' on the other side of the thin-body channel CH'.

[0069] Each of the first word line WL1' and the second word line WL2' of the dual word line DWL1 may include a first curved surface, also referred to as a circular surface RS1, and the active layer ACT1 may include a second curved surface, also referred to as a circular surface RS2. The first circular surface RS1 and the second circular surface RS2 may face each other. A gate dielectric layer may be formed between the dual word line DWL1 and the active layer ACT1.

[0070] Comparing the thicknesses measured in a direction parallel to the first direction D1, the edge thickness V1' of the first word line WL1' and the second word line WL2' can be greater than the center thickness V2' of the thin channel CH'. The average thickness of the thin channel CH' can be less than the average thickness of the first word line WL1' and the second word line WL2'. The average thickness of the thin channel CH' can be equal to or less than 7 nm. The average thickness of the first source / drain region SR' and the average thickness of the second source / drain region DR' can be greater than the average thickness of the thin channel CH', but thinner than the average thickness of the first word line WL1' and the second word line WL2'. Here, the average thickness of the feature can refer to the average value between the thickest and thinnest parts of the feature.

[0071] Figure 3A This is a schematic perspective view of a semiconductor memory device according to an embodiment of the present invention. Figure 3B This is a layout diagram of semiconductor memory devices. Figure 3C It is along Figure 3B The cross-sectional view taken from line A11-A11'.

[0072] See Figures 3A to 3C The semiconductor memory device 100 may include a memory cell array (MCA). Figure 1-2CThe unit memory cells MC can be arranged in a first direction D1 to a third direction D3, and a multi-layer memory cell array MCA can be configured. The memory cell array MCA can include a 3D array of memory cells MC. The 3D memory cell array can include a vertical memory cell array and a horizontal memory cell array. A vertical memory cell array can refer to an array of memory cells MC arranged vertically along the first direction D1. A horizontal memory cell array can refer to an array of memory cells MC arranged laterally along the third direction D3. The vertical memory cell array can be referred to as a column array of memory cells MC, and the horizontal memory cell array can be referred to as a row array of memory cells MC. Bit lines BL can be vertically oriented to connect to the vertical memory cell array, and double word lines DWL can be horizontally oriented to connect to the horizontal memory cell array. Bit lines connected to the vertical memory cell array can be referred to as common bit lines. Adjacent cells of a vertical memory cell array continuously arranged along the third direction can be connected to different common bit lines. Double word lines connected to the horizontal memory cell array can be referred to as common double word lines. Adjacent cells of a vertical memory cell array continuously arranged along the first direction D1 can be connected to different common double word lines.

[0073] The memory cell array MCA may include multiple memory cells MC, and each memory cell MC may include a vertically oriented bit line BL, a horizontally oriented active layer ACT, a double word line DWL, and a horizontally oriented capacitor CAP. Figure 3A The illustration shows an example of a 3D memory cell array consisting of four memory cells (MCs).

[0074] Each bit line BL can contact an adjacent layer of an active layer ACT that is continuously arranged along a first direction D1. Adjacent layers of active layers ACT that are continuously arranged along a third direction D3 can share a double word line DWL. Each capacitor CAP can be connected to each active layer ACT. Capacitors CAP can share a board line PL. Each active layer ACT can be thinner than the first word line WL1 and the second word line WL2 of the double word line DWL.

[0075] In a memory cell array (MCA), two double word lines (DWLs) can be stacked vertically along a first direction D1. Each double word line (DWL) may include a pair of first word lines (WL1) and second word lines (WL2). Between the first word lines (WL1) and the second word lines (WL2), multiple active layers (ACTs) can be arranged laterally along a second direction D3 and spaced apart from each other. Thin-walled channels (CHs) of the active layers (ACTs) can be disposed between the first word lines (WL1) and the second word lines (WL2).

[0076] The double word line (DWL) may include edge portions, each edge portion having a stepped shape. The stepped shape may define a contact portion (CA). Each of the first word line (WL1) and the second word line (WL2) may include an edge portion, i.e., a contact portion (CA). Each contact portion (CA) may have a stepped shape.

[0077] Each contact portion CA can be connected to the first word line pad WLP1 and the second word line pad WLP2. On the upper layer, the contact portion CA of the first word line WL1 and the second word line WL2 can be connected to the first word line pad WLP1. On the lower layer, the contact portion CA of the first word line WL1 and the second word line WL2 can be connected to the second word line pad WLP2. On the upper layer, the first word line WL1 and the second word line WL2 can be interconnected via the first word line pad WLP1. On the lower layer, the first word line WL1 and the second word line WL2 can be interconnected via the second word line pad WLP2.

[0078] The semiconductor memory device 100 may further include a substrate PERI, and the substrate PERI may include peripheral circuitry. Hereinafter, the substrate PERI will be simply referred to as the peripheral circuitry PERI. The bit lines BL of the memory cell array MCA may be vertically oriented to the surface of the peripheral circuitry PERI. The double word lines DWL may be laterally oriented to be parallel to the surface of the peripheral circuitry PERI.

[0079] The peripheral circuitry (PERI) can be located at a lower level than the memory cell array (MCA). This can be referred to as a PERI-on-Cell (COP) structure. The peripheral circuitry may include one or more control circuits to drive the memory cell array (MCA). At least one control circuit of the peripheral circuitry (PERI) may include: an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuitry (PERI) may include: an address decoder circuit, a read circuit, and a write circuit. At least one control circuit of the peripheral circuitry (PERI) may include: a planar channel transistor, a recessed channel transistor, a buried gate transistor, and a fin-channel transistor (FinFET).

[0080] For example, the peripheral circuitry PERI may include sub-word line drivers SWD1 and SWD2 and a sense amplifier SA. The first word line WL1 and the second word line WL2 at the high level can be connected to the sub-word line driver SWD1 via the first word line pad WLP1 and the first metal interconnect MI1. The first word line WL1 and the second word line WL2 at the low level can be connected to the sub-word line driver SWD2 via the second word line pad WLP2 and the second metal interconnect MI2. The bit line BL can be connected to the sense amplifier SA via the third metal interconnect MI3. The third metal interconnect MI3 may include a multi-level metal (MLM) structure containing multiple vias and multiple metal interconnects.

[0081] Figure 4 This is a schematic cross-sectional view of a memory cell array of a semiconductor memory device according to an embodiment of the present invention. Figure 4 The illustration shows a semiconductor memory device 110 with a PERI (POC) structure on a cell basis. Figure 4 , can be omitted Figure 3C A detailed description of the repeating components shown.

[0082] See Figure 4 The semiconductor memory device 110 may include a memory cell array MCA and peripheral circuitry PERI'. The peripheral circuitry PERI' may be located at a higher level than the memory cell array MCA and above the memory cell array MCA. This may be referred to as a PERI on-cell (POC) structure.

[0083] Figure 5A This is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention. Figure 5B It is along Figure 5A A cross-sectional view of a semiconductor memory device taken by line A2-A2'. Figure 5C This is a magnified view of a transistor. Figures 5A to 5C In the middle, it can be omitted. Figures 1 to 4 A detailed description of the repeating components shown.

[0084] See Figures 5A to 5C The unit memory cell MC10 of the 3D semiconductor memory device may include: a bit line BL, a transistor TR10, and a capacitor CAP. The transistor TR10 may include: an active layer ACT10, a gate dielectric layer GD, and a double word line DWL. The capacitor CAP may include a memory node SN, a dielectric layer DE, and a plate node PN. The bit line BL may have a cylindrical shape extending in a first direction D1. The active layer ACT10 may have a strip shape extending in a second direction D2 intersecting the first direction D1. The double word line DWL may have a linear shape extending in a third third direction D3 intersecting both the first direction D1 and the second direction D2. The plate node PN of the capacitor CAP may be connected to a plate line PL. The bit line BL may be oriented perpendicularly to the first direction D1.

[0085] Transistor TR10 may include an active layer ACT10, a gate dielectric layer GD, and a double word line DWL. The double word line DWL may extend in a third direction D3. The active layer ACT10 may extend in a second direction D2. The active layer ACT10 may be arranged laterally from the bit line BL. The double word line DWL may include a first word line WL1 and a second word line WL2. The first word line WL1 and the second word line WL2 may face each other, with the active layer ACT10 inserted between the first word line WL1 and the second word line WL2. The gate dielectric layer GD may be formed on the upper and lower surfaces of the active layer ACT10. The gate dielectric layer GD may include a gate dielectric layer extension GDE that covers the side of the double word line DWL, such as the side of the double word line DWL adjacent to the second source / drain region DR1.

[0086] The active layer ACT10 may include: a thin-body channel CH, a first source / drain region SR between the thin-body channel CH and the bit line BL, and a second source / drain region DR1 between the thin-body channel CH and the capacitor CAP. A first side of the first source / drain region SR may be connected to the bit line BL. A second side of the first source / drain region SR may be connected to the thin-body channel CH. A first side of the second source / drain region DR1 may be connected to the memory node SN. A second side of the second source / drain region DR1 may be connected to the thin-body channel CH. Each second side of the first source / drain region SR and the second source / drain region DR1 may partially overlap with the sides of the first word line WL1 and the second word line WL2. A bit-line side ohmic contact BOC may be formed between the first source / drain region SR and the bit line BL. The bit-line side ohmic contact BOC may be formed by a reaction between the metal of the bit line BL and the silicon of the first source / drain region SR. The bit-line side ohmic contact (BOC) may include a metal silicide and may be formed on the edge of the active layer ACT10, i.e., on the first side of the first source / drain region SR. The memory node side ohmic contact (SOC) may be formed between the second source / drain region DR1 and the memory node SN. The memory node side ohmic contact (SOC) may also include a metal silicide and may be formed on the other edge of the active layer ACT10, i.e., on the first side of the second source / drain region DR1. The memory node side ohmic contact (SOC) may be formed through a reaction between the metal of the memory node SN and the silicon of the second source / drain region DR1.

[0087] See you again Figure 5CThe second source / drain region DR1 may include a first side region DRE1 and a second side region DRE2. The thickness V41 of the first side region DRE1 of the second source / drain region DR1 may be greater than the thickness V4 of the second side region DRE2. The thickness V41 of the first side region DRE1 of the second source / drain region DR1 may be greater than the thickness V2 of the thin-body channel CH. The thickness V3 of the first source / drain region SR may be less than the thickness V41 of the first side region DRE1 of the second source / drain region DR1. The thickness V3 of the first source / drain region SR may be the same as the thickness V2 of the thin-body channel CH and the thickness V4 of the second side region DRE2 of the second source / drain region DR1.

[0088] As described above, the active layer ACT10 can have a partially thin structure including thick and thin portions. The thickness V3 of the first source / drain region SR, the thickness V2 of the thin channel CH, and the thickness V4 of the second side region DRE2 of the second source / drain region DR1 can be less than the thickness of each of the first word line WL1 and the second word line WL2 of the dual word line DWL. The thickness V41 of the first side region DRE1 of the second source / drain region DR1 can be equal to or thinner than the thickness of each of the first word line WL1 and the second word line WL2 of the dual word line DWL.

[0089] like Figure 5A The multiple unit memory cells MC10 shown can be arranged on the first direction D1 to the third direction D3, and can be configured as a multi-layer memory cell array MCA. The memory cell array MCA can include multiple memory cells MC10. Each memory cell MC10 can include: a vertically oriented bit line BL, a laterally oriented active layer ACT10, a double word line DWL, and a laterally oriented capacitor CAP. The memory cell array MCA of memory cells MC10 can be similar to... Figure 3A The memory cell array MCA shown is a semiconductor memory device comprising multiple unit memory cells MC10. It may also include peripheral circuitry PERI, and can be arranged in... Figure 3C In the COP structure shown or Figure 4 In the POC structure shown.

[0090] Figure 5D The diagram shows... Figure 5C A modified example of transistor TR10.

[0091] See Figure 5DThe transistor TR11 may include an active layer ACT11 and a double word line DWL1. The double word line DWL1 may include a first word line WL1' and a second word line WL2' facing each other, with the active layer ACT11 inserted between the first word line WL1' and the second word line WL2'. The active layer ACT11 may include a thin-body channel CH', a first source / drain region SR' on one side of the thin-body channel CH', and a second source / drain region DR1' on the other side of the thin-body channel CH'.

[0092] Each of the first word line WL1' and the second word line WL2' of the dual word line DWL1 may include a first circular surface RS1, and the active layer ACT11 may include a second circular surface RS2. The first circular surface RS1 and the second circular surface RS2 may face each other. A gate dielectric layer may be formed between the dual word line DWL1 and the active layer ACT11. The second circular surface RS2 may be formed on the surface of the second side region DRE2 of the second source / drain region DR1'. The surface of the first side region DRE1 of the second source / drain region DR1' may have a flat shape.

[0093] Comparing the thicknesses measured in a direction parallel to the first direction D1, the edge thickness V1' of the first word line WL1' and the second word line WL2' can be greater than the center thickness V2' of the thin channel CH'. The average thickness of the thin channel CH' can be less than the average thickness of the first word line WL1' and the second word line WL2'. The average thickness of the thin channel CH' can be equal to or less than 7 nm. The average thickness of the first source / drain region SR' and the average thickness of the second source / drain region DR1' can be greater than the average thickness of the thin channel CH', but thinner than the average thickness of the first word line WL1' and the second word line WL2'. Here, the average thickness of the feature can refer to the average value between the thickest and thinnest parts of the feature.

[0094] Figure 6A This is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention. Figure 6B It is a cross-sectional view of a semiconductor memory device taken along line A3-A3'. Figure 6C This is a magnified view of a transistor. See also... Figures 6A to 6C , can be omitted Figures 1 to 5C A detailed description of the repeating components shown.

[0095] refer to Figures 6A to 6CThe unit memory cell MC20 of the 3D semiconductor memory device may include: a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include: an active layer ACT20, a gate dielectric layer GD, and a double word line DWL. The capacitor CAP may include: a memory node SN, a dielectric layer DE, and a plate node PN. The bit line BL may have a cylindrical shape extending in a first direction D1. The active layer ACT20 may have a strip shape extending in a second direction D2 intersecting the first direction D1. The double word line DWL may have a linear shape extending in a third third direction D3 intersecting both the first direction D1 and the second direction D2. The plate node PN of the capacitor CAP may be connected to a plate line PL. The bit line BL may be oriented perpendicularly to the first direction D1.

[0096] The transistor TR may include an active layer ACT20, a gate dielectric layer GD, and a double word line DWL. The double word line DWL may extend in a third direction D3. The active layer ACT20 may extend in a second direction D2. The active layer ACT20 may be arranged laterally from the bit line BL. The double word line DWL may include a first word line WL1 and a second word line WL2. The first word line WL1 and the second word line WL2 may face each other, with the active layer ACT20 inserted between the first word line WL1 and the second word line WL2. The gate dielectric layer GD may be formed on the upper and lower surfaces of the active layer ACT20. The gate dielectric layer GD may include a gate dielectric layer extension GDE that covers both sides of the double word line DWL, for example, the side adjacent to the first source / drain region SR1 and the second source / drain region DR1.

[0097] The active layer ACT20 may include: a thin-body channel CH, a first source / drain region SR1 disposed between the thin-body channel CH and the bit line BL, and a second source / drain region DR1 disposed between the thin-body channel CH and the capacitor CAP. A first side of the first source / drain region SR1 may contact the bit line BL. A second side of the first source / drain region SR1 may contact the thin-body channel CH. A first side of the second source / drain region DR1 may contact the memory node SN. A second side of the second source / drain region DR1 may contact the thin-body channel CH. Each of the second sides of the first source / drain region SR1 and the second source / drain region DR1 may partially overlap with the sides of the first word line WL1 and the second word line WL2. A bit-line side ohmic contact BOC may be formed between the first source / drain region SR1 and the bit line BL. The bit-line side ohmic contact BOC may be formed by a reaction between the metal of the bit line BL and the silicon of the first source / drain region SR1. The bit-line side ohmic contact (BOC) may include a metal silicide and is formed on one edge of the active layer ACT20, namely on the first side of the first source / drain region SR1. The memory node side ohmic contact (SOC) may be formed between the second source / drain region DR1 and the memory node SN. The memory node side ohmic contact (SOC) may also include a metal silicide and is formed on the other edge of the active layer ACT20, namely on the first side of the second source / drain region DR1. The memory node side ohmic contact (SOC) may be formed through a reaction between the metal of the memory node SN and the silicon of the second source / drain region DR1.

[0098] See you again Figure 6C The second source / drain region DR1 may include a first side region DRE1 and a second side region DRE2. The thickness V41 of the first side region DRE1 of the second source / drain region DR1 may be greater than the thickness V4 of the second side region DRE2. The thickness V41 of the first side region DRE1 of the second source / drain region DR1 may be greater than the thickness V2 of the thin-body channel CH.

[0099] The first source / drain region SR1 may include a first side region SRE1 and a second side region SRE2. The thickness V31 of the first side region SRE1 of the first source / drain region SR1 may be greater than the thickness V3 of the second side region SRE2. The thickness V31 of the first side region SRE1 of the first source / drain region SR1 may be greater than the thickness V2 of the thin-body channel CH.

[0100] The thickness V3 of the second side region SRE2 of the first source / drain region SR1 can be less than the thickness V31 of the first side region SRE1 of the first source / drain region SR1. The thickness V3 of the second side region SRE2 of the first source / drain region SR1 can be the same as the thickness V2 of the thin channel CH and the thickness V4 of the second side region DRE2 of the second source / drain region DR1.

[0101] The thickness V31 of the first side region SRE1 of the first source / drain region SR1 and the thickness V41 of the first side region DRE1 of the second source / drain region DR1 can be the same. The thickness V31 of the first side region SRE1 of the first source / drain region SR1 and the thickness V41 of the first side region DRE1 of the second source / drain region DR1 can be greater than the thickness V2 of the thin channel CH.

[0102] As described above, the active layer ACT20 can have a partially thin structure including thick and thin portions. The thickness V3 of the second side region SRE2 of the first source / drain region SR1, the thickness V2 of the thin channel CH, and the thickness V4 of the second side region DRE2 of the second source / drain region DR1 can be less than the thicknesses of the first word line WL1 and the second word line WL2 of the dual word line DWL. The thickness V41 of the first side region DRE1 of the second source / drain region DR1 and the thickness V31 of the first side region SRE1 of the first source / drain region SR1 can be equal to or less than the first word line WL1 and the second word line WL2 of the dual word line DWL.

[0103] Figure 6A The illustrated unit memory cell MC20 can be arranged on a first direction D1 to a third direction D3 and configured with a multi-layer memory cell array MCA. The memory cell array MCA can include multiple memory cells MC20. Each memory cell can include: a vertically oriented bit line BL, a laterally oriented active layer ACT20, a double word line DWL, and a laterally oriented capacitor CAP. The memory cell array MCA of the unit memory cells MC20 can be similar to... Figure 3A The memory cell array MCA shown is a semiconductor memory device that includes a memory cell array MCA comprising unit memory cells MC20. It may also include peripheral circuitry PERI, and may be arranged in... Figure 3C In the COP structure shown or Figure 4 The POC structure shown is illustrated.

[0104] Figure 6D The diagram shows... Figure 6C The modified example of transistor TR20 shown is illustrated.

[0105] See Figure 6D The transistor TR21 may include an active layer ACT21 and a dual word line DWL1. The dual word line DWL1 may include a first word line WL1' and a second word line WL2' facing each other, with the active layer ACT21 inserted between the first word line WL1' and the second word line WL2'. The active layer ACT21 may include: a thin-body channel CH', a first source / drain region SR1' on one side of the thin-body channel CH', and a second source / drain region DR1' on the other side of the thin-body channel CH'.

[0106] Each of the first word line WL1' and the second word line WL2' of the dual word line DWL1 may include a first circular surface RS1. The active layer ACT21 may include a second circular surface RS2. The first circular surface RS1 and the second circular surface RS2 may face each other. A gate dielectric layer may be formed between the dual word line DWL1 and the active layer ACT21. The second circular surface RS2 may be formed on the second side region SRE2 of the first source / drain region SR1' and the second side region DRE2 of the second source / drain region DR1'. The surfaces of the first side region SRE1 of the first source / drain region SR1' and the first side region DRE1 of the second source / drain region DR1' may include a planar shape.

[0107] Comparing the thicknesses measured in a direction parallel to the first direction D1, the edge thickness V1' of the first word line WL1' and the second word line WL2' can be greater than the center thickness V2' of the thin-body channel CH'. The average thickness of the thin-body channel CH' can be less than each of the average thicknesses of the first word line WL1' and the second word line WL2'. The average thickness of the thin-body channel CH' can be equal to or less than 7 nm. The average thickness of the first source / drain region SR1' and the average thickness of the second source / drain region DR1' can each be greater than the average thickness of the thin-body channel CH', but thinner than each of the average thicknesses of the first word line WL1' and the second word line WL2'. Here, the average thickness of the feature can refer to the average value between the thickest and thinnest parts of the feature.

[0108] Figure 7A This is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention. Figure 7B It is along Figure 7A The cross-sectional view taken by line A4-A4'. Figure 7A and Figure 7B The unit memory cell in the memory can be similar to Figures 1 to 2B The unit memory cell shown.

[0109] See Figure 7A and Figure 7BThe unit memory cell MC30 of the 3D semiconductor memory device may include: a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include: an active layer ACT30, a gate dielectric layer GD, and a double word line DWL. The capacitor CAP may include: a memory node SN, a dielectric layer DE, and a plate node PN. The bit line BL may have a cylindrical shape extending in a first direction D1. The active layer ACT30 may have a strip shape extending in a second direction D2 intersecting the first direction D1. The double word line DWL may have a linear shape extending in a third direction D2 intersecting the first direction D2 and the second direction D3. The plate node PN of the capacitor CAP may be connected to a plate line PL. The bit line BL may be oriented perpendicularly to the first direction D1.

[0110] The dual word line (DWL) can extend in the third direction D3, and the active layer ACT30 can extend in the second direction D2. The active layer ACT can be laterally oriented from the bit line BL. The dual word line DWL can include a first word line WL1 and a second word line WL2. The first word line WL1 and the second word line WL2 can face each other, and the active layer ACT30 is inserted between the first word line WL1 and the second word line WL2. A gate dielectric layer GD can be formed on the upper and lower surfaces of the active layer ACT30. The gate dielectric layer GD can include a gate dielectric layer extension GDE that covers the side of the dual word line DWL, such as the side adjacent to the second source / drain region DR.

[0111] The active layer ACT30 may include: a thin-body channel CH, a first source / drain region SR disposed between the thin-body channel CH and the bit line BL, and a second source / drain region DR disposed between the thin-body channel CH and the capacitor CAP. A first side of the first source / drain region SR may contact the bit line BL. A second side of the first source / drain region SR may contact the thin-body channel CH. A first side of the second source / drain region DR may contact the memory node SN. A second side of the second source / drain region DR may contact the thin-body channel CH. Each of the second sides of the first source / drain region SR and the second source / drain region DR may partially overlap with the sides of the first word line WL1 and the second word line WL2. A bit-line side ohmic contact BOC and a bit-line contact node BLC may be formed between the first source / drain region SR and the bit line BL. The bit-line side ohmic contact BOC may be in direct contact with the bit line BL, and the bit-line contact node BLC may be in direct contact with the first source / drain region SR. The memory node-side ohmic contact SOC and memory node contact node SNC can be formed between the second source / drain region DR and the memory node SN. The memory node-side ohmic contact SOC can be in direct contact with the memory node SN, and the memory node contact node SNC can be in direct contact with the second source / drain region DR. Each of the bit line contact node BLC and memory node contact node SNC can include polysilicon.

[0112] Bit-line side ohmic contacts (BOCs) can be formed by the reaction between the metal of the bit line (BL) and the silicon of the bit line contact node (BLC). The bit-line side ohmic contacts (BOCs) may include metal silicides. Storage node side ohmic contacts (SOCs) can be formed by the reaction between the metal of the storage node (SN) and the silicon of the storage node contact node (SNC). The storage node side ohmic contacts (SOCs) may include metal silicides.

[0113] The height of the bit line contact node (BLC) and the height of the memory node contact node (SNC) can each be greater than the thickness V2 of the active layer ACT30. The thickness V2 of the active layer ACT30 can be less than the thickness V1 of each of the first word line WL1 and the second word line WL2 of the dual word line (DWL).

[0114] Figure 7A The memory cell array (MCA) can be arranged on a first direction D1 to a third direction D3, and a multi-layer memory cell array (MCA) can be configured. The memory cell array (MCA) can include multiple unit memory cells (MC30). Each unit memory cell (MC30) can include: a vertically oriented bit line (BL), a laterally oriented active layer (ACT), a double word line (DWL), and a laterally oriented capacitor (CAP). The memory cell array (MCA) of unit memory cells (MC30) can be similar to... Figure 3A The memory cell array MCA shown is a semiconductor memory device that includes a memory cell array MCA comprising unit memory cells MC30. It may also include peripheral circuitry PERI, and may be arranged in... Figure 3C In the COP structure shown or Figure 4 In the POC structure shown.

[0115] In one embodiment, Figure 7A The active layer ACT30 of the unit memory cell MC30 shown can be modified to have the same... Figure 5A The active layer ACT10 shown is Figure 6A The active layer ACT20 shown has the same shape.

[0116] According to Figures 1 to 7B In this embodiment, the thickness of the thin-body channel CH can be less than the thickness of each of the first word line WL1 and the second word line WL2 of the dual word line DWL. The active layers ACT, ACT10, and ACT20, which include a thin-body channel CH that is thinner than the first word line WL1 and the second word line WL2, can be referred to as thin-body. The thin-body channel can be referred to as a thin channel. Due to the thin-body channel CH, the memory cells MC, MC10, MC20, and MC30 stacked along the first direction D1 can have improved integration.

[0117] Figure 8AThis is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention. Figure 8B It is along Figure 8A A cross-sectional view of a semiconductor memory device taken by line A5-A5'. Figure 8C This is a magnified view of a transistor. Figures 8A to 8C In the middle, it can be omitted. Figures 1 to 7B A detailed description of the repeating components shown.

[0118] See Figures 8A to 8C The unit memory cell MC40 of the 3D semiconductor memory device may include: a bit line LBL, a transistor TR40, and a capacitor CAP. The transistor TR40 may include: an active layer ACT40, a gate dielectric layer GD, and a double word line VDWL. The capacitor CAP may include: a memory node SN, a dielectric layer DE, and a plate node PN. The double word line VDWL may extend perpendicularly along a first direction D1. The active layer ACT40 may have a stripe extending along a second direction D2 intersecting the first direction D1. The bit line LBL may have a line shape extending along a third third direction D3 intersecting the first direction D1 and the second direction D2. The plate node PN of the capacitor CAP may be connected to the plate line PL.

[0119] The double word line VDWL can be vertically oriented along the first direction D1, the active layer ACT40 can be laterally oriented along the second direction D2, and the bit line LBL can be laterally oriented along the third direction D3.

[0120] Transistor TR40 may include an active layer ACT40, a gate dielectric layer GD, and a double word line VDWL. The double word line VDWL may extend in a first direction D1, and the active layer ACT40 may extend in a second direction D2. The active layer ACT40 may be arranged laterally from the bit line LBL. The double word line VDWL may include a first word line VWL1 and a second word line VWL2. The first word line VWL1 and the second word line VWL2 may face each other, and the active layer ACT40 is inserted between the first word line VWL1 and the second word line VWL2. The gate dielectric layer GD may be formed on a side surface of the active layer ACT40. Here, the side surface of the active layer 40 where the gate dielectric layer GD can be formed is a side surface parallel to the first direction D1.

[0121] The active layer ACT40 may include: a thin-body channel CH, a first source / drain region SR40 between the thin-body channel CH and the bit line LBL, and a second source / drain region DR40 between the thin-body channel CH and the capacitor CAP. A first side of the first source / drain region SR40 may contact the bit line LBL. A second side of the first source / drain region SR40 may contact the thin-body channel CH. A first side of the second source / drain region DR40 may contact the memory node SN. A second side of the second source / drain region DR40 may contact the thin-body channel CH. Each of the second sides of the first source / drain region SR40 and the second source / drain region DR40 may partially overlap with the sides of the first word line VWL1 and the second word line VWL2. A bit-line side ohmic contact BOC may be formed between the first source / drain region SR40 and the bit line LBL. The bit-line side ohmic contact BOC may be formed by a reaction between the metal of the bit line BL and the silicon of the first source / drain region SR40. The bit-line side ohmic contact (BOC) may include a metal silicide and may be formed on one edge of the active layer ACT40, i.e., on the first side of the first source / drain region SR40. The memory node side ohmic contact (SOC) may be formed between the second source / drain region DR40 and the memory node SN. The memory node side ohmic contact (SOC) may also include a metal silicide and may be formed on the other edge of the active layer ACT40, i.e., on the first side of the second source / drain region DR40. The memory node side ohmic contact (SOC) may be formed through a reaction between the metal of the memory node SN and the silicon of the second source / drain region DR40.

[0122] The lateral thickness LT1 of the thin channel Ch can be less than the lateral thickness LT2 of the first word line VWL1 and the second word line VWL2 of the double word line VDWL. Here, the lateral thicknesses LT1 and LT2 can be parallel to the third direction D3, meaning they can be measured in a direction parallel to the third direction D3.

[0123] See you again Figure 8CThe first source / drain region SR40 may include a first side region SRE41 and a second side region SRE42. The lateral thickness LT3 of the first side region SRE41 of the first source / drain region SR40 may be greater than the lateral thickness LT1 of the second side region SRE42. The second source / drain region DR40 may include a first side region DRE41 and a second side region DRE42. The lateral thickness LT4 of the first side region DRE41 of the second source / drain region DR40 may be greater than the lateral thickness LT1 of the second side region DRE42. The lateral thickness LT3 of the first side region SRE41 of the first source / drain region SR40 may be greater than the lateral thickness LT1 of the thin-body channel CH. The lateral thickness LT4 of the first side region DRE41 of the second source / drain region DR40 may be greater than the lateral thickness LT1 of the thin-body channel CH. The lateral thickness of the second side region SRE42 of the first source / drain region SR40 and the second side region DRE42 of the second source / drain region DR40 can be equal to the lateral thickness LT1 of the thin-body channel CH. The lateral thickness LT1 of the thin-body channel CH can be less than the lateral thickness LT2 of each of the first word line VWL1 and the second word line VWL2 of the dual word line VDWL.

[0124] As described above, the active layer ACT40 can have a partially thin structure comprising a thick portion and a thin portion. The thin portion of the active layer ACT40 can at least include a thin body channel CH. The lateral thickness LT1 of the thin body channel CH can be less than the lateral thickness LT2 of each of the first word line VWL1 and the second word line VWL2 of the dual word lines VDWL.

[0125] Figure 8D The illustration shows a modified example of transistor TR40.

[0126] See Figure 8D The transistor TR41 may include an active layer ACT41 and a double word line VDWL1. The double word line VDWL1 may include a first word line WL1' and a second word line WL2' facing each other, with the active layer ACT41 inserted between them. The active layer ACT41 may include: a thin body channel CH', a first source / drain region SR41' on one side of the thin body channel CH', and a second source / drain region DR41' on the opposite side of the thin body channel CH'.

[0127] Each of the first word line WL1' and the second word line WL2' of the dual word line VDWL1 may include a first circular surface RS1, and the active layer ACT21 may include a second circular surface RS2. The first circular surface RS1 and the second circular surface RS2 may face each other. A gate dielectric layer may be formed between the dual word line VDWL1 and the active layer ACT41. The second circular surface RS2 may be formed on the second side region SRE42 of the first source / drain region SR41' and the second side region DRE42 of the second source / drain region DR41'. The surfaces of the first side region SRE41 of the first source / drain region SR41' and the first side region DRE41 of the second source / drain region DR41' may have a planar shape.

[0128] Comparing the thicknesses parallel to the first direction D1, the edge thickness V1' of the first word line WL1' and the second word line WL2' can be greater than the center thickness V2' of the thin channel CH'. The average thickness of the thin channel CH' can be less than the average thickness of the first word line WL1' and the second word line WL2'. The average thickness of the thin channel CH' can be equal to or less than 7 nm. The average thickness of the first source / drain region SR41' and the average thickness of the second source / drain region DR41' can be greater than the average thickness of the thin channel CH', but thinner than the average thickness of the first word line WL1' and the second word line WL2'. Here, the average thickness of the feature can refer to the average value between the thickest and thinnest parts of the feature.

[0129] Figure 9 This is a schematic perspective view of a semiconductor memory device according to an embodiment of the present invention. See also... Figure 8A and Figure 9 , Figure 8A The unit memory cell MC40 can be arranged on a first direction D1 to a third direction D3, and a multi-layer memory cell array MCA can be configured. The memory cell array MCA can include multiple memory cells MC40. Each of the multiple memory cells MC40 can include: a bit line LBL laterally oriented on the third direction D3, an active layer ACT40 laterally oriented on the second direction D2, a double word line DWL vertically oriented on the first direction D1, and a capacitor CAP laterally oriented on the second direction D2. The memory cell array MCA of the unit memory cells MC40 can be similar to Figure 3A The memory cell array (MCA) includes individual memory cells (MC40). The semiconductor memory device may also include peripheral circuitry (PERI). In one embodiment, the arrangement of the peripheral circuitry (PERI) and the memory cell array (MCA) can be determined according to... Figure 3C The COP structure shown is illustrated in Figure 3C. In another embodiment, the arrangement of the peripheral circuitry PERI and the memory cell array MCA can be determined according to... Figure 4 The POC structure shown.

[0130] Figure 10A This is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention. Figure 10B It is along Figure 10A A cross-sectional view of a semiconductor memory device taken by line A6-A6'. Figure 10C This is a magnified view of a transistor. Figures 10A to 10C , can be omitted Figures 1 to 9 A detailed description of the repeating components shown.

[0131] See Figures 10A to 10C The unit memory cell MC50 of the 3D semiconductor memory device may include: a bit line LBL, a transistor TR50, and a capacitor CAP. The transistor TR50 may include: an active layer ACT50, a gate dielectric layer GD, and a double word line VDWL. The capacitor CAP may include: a memory node SN, a dielectric layer DE, and a plate node PN. The double word line VDWL may extend perpendicularly along a first direction D1. The active layer ACT50 may have a stripe extending along a second direction D2 intersecting the first direction D1. The bit line LBL may have a line shape extending along a third third direction D3 intersecting the first direction D1 and the second direction D2. The plate node PN of the capacitor CAP may be connected to the plate line PL.

[0132] The dual word line VDWL can be vertically oriented along the first direction D1, the active layer ACT50 can be laterally oriented along the second direction D2, and the bit line LBL can be laterally oriented along the third direction D3.

[0133] Transistor TR50 may include an active layer ACT50, a gate dielectric layer GD, and a double word line VDWL. The double word line VDWL may extend in a first direction D1, and the active layer ACT50 may extend in a second direction D2. The active layer ACT50 may be arranged laterally from the bit line LBL. The double word line VDWL may include a first word line VWL1 and a second word line VWL2. The first word line VWL1 and the second word line VWL2 may face each other, and the active layer ACT50 is inserted between the first word line VWL1 and the second word line VWL2. The gate dielectric layer GD may be formed on a side surface of the active layer ACT50. Here, the side surface of the active layer ACT50 where the gate dielectric layer GD is formed may be a side surface parallel to the first direction D1.

[0134] The active layer ACT50 may include: a thin-body channel CH, a first source / drain region SR50 between the thin-body channel CH and the bit line LBL, and a second source / drain region DR50 between the thin-body channel CH and the capacitor CAP. A first side of the first source / drain region SR50 may contact the bit line LBL. A second side of the first source / drain region SR50 may contact the thin-body channel CH. A first side of the second source / drain region DR50 may contact the memory node SN. A second side of the second source / drain region DR50 may contact the thin-body channel CH. Each of the second sides of the first source / drain region SR50 and the second source / drain region DR50 may partially overlap with the sides of the first word line VWL1 and the second word line VWL2. A bit-line side ohmic contact BOC may be formed between the first source / drain region SR50 and the bit line LBL. The bit-line side ohmic contact BOC may be formed by a reaction between the metal of the bit line BL and the silicon of the first source / drain region SR50. The bit-line side ohmic contact (BOC) may include a metal silicide and may be formed on one edge of the active layer ACT50, i.e., on the first side of the first source / drain region SR50. The memory node side ohmic contact (SOC) may be formed between the second source / drain region DR50 and the memory node SN. The memory node side ohmic contact (SOC) may include a metal silicide and may be formed on the other edge of the active layer ACT50, i.e., on the first side of the second source / drain region DR50. The memory node side ohmic contact (SOC) may be formed by a reaction between the metal of the memory node SN and the silicon of the second source / drain region DR50.

[0135] The lateral thickness LT1 of the thin channel CH can be less than the lateral thickness LT2 of the first word line VWL1 and the second word line VWL2 of the double word line VDWL. Here, the lateral thicknesses LT1 and LT2 can be measured in a direction parallel to the third direction D3.

[0136] See you again Figure 10CThe first source / drain region SR50 may be strip-shaped. The lateral thickness LT3 of the first source / drain region SR50 may be equal to the lateral thickness LT1 of the thin-body channel CH. The second source / drain region DR50 may include a first side region DRE51 and a second side region DRE52. The lateral thickness LT4 of the first side region DRE51 of the second source / drain region DR50 may be greater than the lateral thickness LT1 of the second side region DRE52. The lateral thickness LT4 of the first side region DRE51 of the second source / drain region DR50 may be greater than the lateral thickness LT1 of the thin-body channel CH. The lateral thickness LT3 of the first source / drain region SR50 and the lateral thickness LT2 of the second side region DRE52 of the second source / drain region DR50 may be equal to the lateral thickness LT1 of the thin-body channel CH. The lateral thickness LT1 of the thin-body channel CH may be less than the lateral thickness LT2 of the first word line VWL1 and the second word line VWL2 of the dual word line VDWL.

[0137] Figure 11A This is a schematic perspective view of a unit memory cell of a semiconductor memory device according to an embodiment of the present invention. Figure 11B It is along Figure 11B A cross-sectional view of a semiconductor memory device taken by line A7-A7'. Figure 11C This is a magnified view of a transistor. Figures 11A to 11C , can be omitted Figures 1 to 10C A detailed description of the repeating components shown.

[0138] See Figures 11A to 11C The unit memory cell MC60 of the 3D semiconductor memory device may include: a bit line LBL, a transistor TR60, and a capacitor CAP. The transistor TR60 may include: an active layer ACT60, a gate dielectric layer GD, and a double word line VDWL. The capacitor CAP may include: a memory node SN, a dielectric layer DE, and a plate node PN. The double word line VDWL may extend perpendicularly along a first direction D1. The active layer ACT60 may have a stripe extending along a second direction D2 intersecting the first direction D1. The bit line LBL may have a line shape extending along a third third direction D3 intersecting the first direction D1 and the second direction D2. The plate node PN of the capacitor CAP may be connected to the plate line PL.

[0139] The double word line VDWL can be vertically oriented along the first direction D1, the active layer ACT60 can be laterally oriented along the second direction D2, and the bit line LBL can be laterally oriented along the third direction D3.

[0140] Transistor TR60 may include an active layer ACT60, a gate dielectric layer GD, and a double word line VDWL. The double word line VDWL may extend in a first direction D1, and the active layer ACT60 may extend in a second direction D2. The active layer ACT60 may be arranged laterally from the bit line LBL. The double word line VDWL may include a first word line VWL1 and a second word line VWL2. The first word line VWL1 and the second word line VWL2 may face each other, and the active layer ACT60 is inserted between the first word line VWL1 and the second word line VWL2. The gate dielectric layer GD may be formed on a side surface of the active layer ACT60. Here, the side surface of the active layer ACT60 on which the gate dielectric GD may be formed is parallel to the first direction D1.

[0141] The active layer ACT60 may include: a thin-body channel CH, a first source / drain region SR60 between the thin-body channel CH and the bit line LBL, and a second source / drain region DR60 between the thin-body channel CH and the capacitor CAP. A first side of the first source / drain region SR60 may contact the bit line LBL. A second side of the first source / drain region SR60 may contact the thin-body channel CH. A first side of the second source / drain region DR60 may contact the memory node SN. A second side of the second source / drain region DR60 may contact the thin-body channel CH. Each of the second sides of the first source / drain region SR60 and the second source / drain region DR60 may partially overlap with the sides of the first word line VWL1 and the second word line VWL2. A bit-line side ohmic contact BOC may be formed between the first source / drain region SR60 and the bit line LBL. The bit-line side ohmic contact BOC may be formed by a reaction between the metal of the bit line BL and the silicon of the first source / drain region SR60. The bit-line side ohmic contact (BOC) may include a metal silicide and may be formed on the edge of the active layer ACT60, i.e., on the first side of the first source / drain region SR60. The memory node side ohmic contact (SOC) may be formed between the second source / drain region DR60 and the memory node SN. The memory node side ohmic contact (SOC) may also include a metal silicide and may be formed on the other edge of the active layer ACT60, i.e., on the first side of the second source / drain region DR60. The memory node side ohmic contact (SOC) may be formed through a reaction between the metal of the memory node SN and the silicon of the second source / drain region DR60.

[0142] The lateral thickness LT1 of the thin channel CH can be less than the lateral thickness LT2 of the first word line VWL1 and the second word line VWL2 of the double word line VDWL. Here, the lateral thicknesses LT1 and LT2 can be measured in a direction parallel to the third direction D3.

[0143] See you again Figure 11CThe second source / drain region DR60 can be strip-shaped. The lateral thickness LT4 of the second source / drain region DR60 can be equal to the lateral thickness LT1 of the thin-body channel CH. The first source / drain region SR60 can include a first side region SRE61 and a second side region SRE62. The lateral thickness LT3 of the first side region SRE61 of the first source / drain region SR60 can be greater than the lateral thickness LT1 of the second side region SRE62. The lateral thickness LT3 of the first side region SRE61 of the first source / drain region SR60 can be greater than the lateral thickness LT1 of the thin-body channel CH. The lateral thickness LT3 of the first source / drain region SR60 and the lateral thickness LT4 of the second source / drain region DR60 can be equal to the lateral thickness LT1 of the thin-body channel CH. The lateral thickness LT1 of the thin-body channel CH can be less than the lateral thickness LT2 of the first word line VWL1 and the second word line VWL2 of the dual word line VDWL.

[0144] See Figure 5D , Figure 6D and Figure 8D ,according to Figures 10A to 11C The thin channel and double letter lines can have circular surfaces. The circular surfaces of the thin channel and the circular surfaces of the double letter lines can face each other.

[0145] Transistors having thin-channels according to the above embodiments of the present invention can be applied to dual-gate field-effect transistors, fin field-effect transistors (FinFETs), gate-around field-effect transistors, and multi-bridge thin-channel field-effect transistors.

[0146] Although this disclosure has been shown and described with reference to specific embodiments thereof, the invention is not limited thereto. It will be readily understood by those skilled in the art that various changes or modifications can be made thereto without departing from the scope of this disclosure.

Claims

1. A semiconductor memory device, comprising: Substrate; An active layer, spaced apart from the substrate, extending in a direction parallel to the substrate, and including a thin-body channel; Bit lines extend in a direction perpendicular to the substrate and connect to one side of the active layer; A capacitor, which is connected to the other side of the active layer; as well as A first letter and a second letter extend in a direction intersecting the thin-body channel, which is inserted between the first letter and the second letter. Wherein, the thickness of the thin channel is less than the thickness of the first character line and the second character line. The semiconductor memory device further includes: Bit line contact node, which is disposed between one side of the active layer and the bit line; The bit line side ohmic contact is disposed between the bit line contact node and the bit line; A storage contact node is disposed on the other side of the active layer between the capacitor; and An ohmic contact is provided on the storage node side, which is disposed between the storage contact node and the capacitor.

2. The semiconductor memory device according to claim 1, wherein, The active layer further includes a first source / drain region connected to the bit line and a second source / drain region connected to the capacitor, and The first source / drain region and the second source / drain region are located on both sides of the thin-body channel.

3. The semiconductor memory device according to claim 2, in, The thickness of the thin channel is less than the thickness of the first source / drain region and the second source / drain region.

4. The semiconductor memory device according to claim 2, wherein... The thickness of the thin channel is less than the thickness of the first source / drain region, and The thickness of the thin channel is equal to the thickness of the second source / drain region.

5. The semiconductor memory device according to claim 2, wherein... The thickness of the thin channel is less than the thickness of the second source / drain region, and The thickness of the thin channel is equal to the thickness of the first source / drain region.

6. The semiconductor memory device according to claim 1, wherein, The thin-body channel comprises a semiconductor material or an oxide semiconductor material.

7. The semiconductor memory device according to claim 1, wherein, The thin-body channel comprises silicon, germanium, silicon-germanium, or indium gallium zinc oxide.

8. The semiconductor memory device of claim 1, further comprising word line pads, the word line pads interconnecting the first word line and the second word line.

9. The semiconductor memory device according to claim 1, wherein, The edge portions of the first and second letter lines have a stepped shape along a direction perpendicular to the substrate.

10. The semiconductor memory device according to claim 1, wherein, Each of the bit line contact node and the storage contact node comprises polysilicon.

11. The semiconductor memory device according to claim 1, wherein, Each of the bit-line side ohmic contacts and the memory node side ohmic contacts comprises a metal silicide.

12. The semiconductor memory device according to claim 1, wherein, The capacitor includes a cylindrical storage node connected to the other side of the active layer.

13. A semiconductor memory device comprising: Substrate; as well as A memory cell array comprising memory cells stacked along a direction perpendicular to the substrate. Each of the memory units includes: Bit lines, which are oriented perpendicularly to the substrate; A capacitor, which is laterally spaced from the bit line; An active layer, laterally oriented between the bit line and the capacitor; and The character line is disposed on the upper part of the active layer and oriented laterally to intersect the active layer. The active layer includes a thin channel, the thickness of which is less than the thickness of the word line. The memory unit further includes: Bit line contact node, which is disposed between one side of the active layer and the bit line; The bit line side ohmic contact is disposed between the bit line contact node and the bit line; A storage contact node is disposed on the other side of the active layer between the capacitor; and An ohmic contact is provided on the storage node side, which is disposed between the storage contact node and the capacitor.

14. The semiconductor memory device of claim 13, wherein... The character lines include a first character line and a second character line, the first character line and the second character line intersecting with the thin-body channel, the thin-body channel being inserted between the first character line and the second character line, and The thickness of the thin channel is less than the thickness of the first and second letter lines.

15. The semiconductor memory device according to claim 13, wherein, The active layer further includes a first source / drain region connected to the bit line and a second source / drain region connected to the capacitor, and The first source / drain region and the second source / drain region are located on both sides of the thin-body channel.

16. The semiconductor memory device according to claim 15, in, The thickness of the thin channel is less than the thickness of each of the first source / drain region and the second source / drain region.

17. The semiconductor memory device of claim 15, wherein... The thickness of the thin channel is less than the thickness of the first source / drain region, and The thickness of the thin channel is equal to the thickness of the second source / drain region.

18. The semiconductor memory device of claim 15, wherein... The thickness of the thin channel is less than the thickness of the second source / drain region, and The thickness of the thin channel is equal to the thickness of the first source / drain region.

19. The semiconductor memory device according to claim 13, wherein, The thin-body channel comprises a semiconductor material or an oxide semiconductor material.

20. The semiconductor memory device according to claim 13, wherein, The word lines of the memory cell have a stepped shape along a direction perpendicular to the surface of the substrate.

21. The semiconductor memory device according to claim 13, wherein, The memory unit includes a dynamic random access memory unit.

22. The semiconductor memory device according to claim 13, wherein, The substrate includes peripheral circuitry for controlling the memory cell array.

23. The semiconductor memory device according to claim 22, wherein, The peripheral circuitry is positioned at a lower or higher level than the memory cell array.

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