Semiconductor devices

Abstract

A semiconductor device includes a plurality of memory cells. Each memory cell includes a stacked structure, a barrier layer, a floating gate layer, a tunnel dielectric layer and a channel layer. The stacked structure includes at least one control layer, at least one erase layer and at least one dielectric layer. The barrier layer and the control layer are coplanarly arranged, the floating gate layer is contained in the barrier layer and is insulated from the control layer by the barrier layer. The tunnel dielectric layer covers one side of the barrier layer and the floating gate layer. The channel layer is located on one side of the tunnel dielectric layer. The erase layer is used to apply a predetermined voltage when performing data read and write operations so that the series resistance of the channel layer is reduced, so as to facilitate the rapid conduction of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and in particular to a three-dimensional flash memory device. Background Art

[0002] In the current semiconductor industry, three-dimensional (3D) flash memory can store information for a long time without power supply, and has the advantages of high integration, fast storage speed, easy erasing and rewriting. With the development of technology, the size of 3D flash memory is gradually decreasing. The cross-sectional area of ​​the channel layer in the 3D flash memory structure is reduced, and it is not easy to reduce the vertical series resistance by ion implantation and other methods, which reduces the writing speed of 3D flash memory when performing data writing operations. Summary of the invention

[0003] The main object of the present invention is to provide a semiconductor device to solve the problem of reduced reading and writing speed in the prior art.

[0004] A semiconductor device includes a plurality of memory cells; each of the memory cells includes:

[0005] A stacked structure comprising at least one control layer, at least one erase layer, and at least one dielectric layer;

[0006] A barrier layer, disposed coplanarly with the control layer;

[0007] a floating gate layer, arranged coplanar with the control layer and insulated from the control layer by the barrier layer;

[0008] a tunnel dielectric layer covering the barrier layer and one side of the floating gate layer;

[0009] A channel layer, located on one side of the tunnel dielectric layer;

[0010] The erasing layer applies a predetermined voltage when performing data reading and writing operations, so that the series resistance of the channel layer is reduced, so as to facilitate the rapid conduction of the semiconductor device.

[0011] When performing data read and write operations, the semiconductor device applies a predetermined voltage to the erase gate to reduce the series resistance of the channel layer, thereby facilitating rapid conduction of the semiconductor device and improving the read and write speed of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0013] Figure 1 It is a schematic cross-sectional view of the semiconductor device of the present invention along the horizontal direction.

[0014] Figure 2 It is a schematic cross-sectional view of the semiconductor device of the present invention along the vertical direction.

[0015] Main component symbols

[0016] Semiconductor device 1

[0017] Storage unit 10

[0018] Stacked structure ST

[0019] Insulation layer 12

[0020] Dielectric layer 11

[0021] Control layer 13

[0022] Erasing layer 112

[0023] Barrier layer 14

[0024] Floating gate layer 15

[0025] Tunnel dielectric layer 16

[0026] Channel layer 17

[0027] Filling layer 18

[0028] The first thickness layer D1

[0029] The second thickness layer D2

[0030] Write path path-A

[0031] Erase path path-B

[0032] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] The terms "first", "second", and "third" in the specification of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the term "comprising" and any variation thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules that are not listed, or may optionally include other steps or modules that are inherent to these processes, methods, products, or devices.

[0035] Specific implementations of the semiconductor device of the present invention will be described below with reference to the accompanying drawings.

[0036] Please refer to Figure 1 as well as Figure 2 The present invention provides a schematic cross-sectional view of a semiconductor device 1 along a horizontal direction and a schematic cross-sectional view along a vertical direction. The semiconductor device 1 is a stacked structure, which is composed of a plurality of memory cells 10. Figure 1 Only one storage unit 10 is shown in the horizontal direction. Figure 2 The schematic diagram of the cross section along the vertical direction of two adjacent storage units 10 is shown in FIG. 1. In at least one embodiment of the present invention, the semiconductor device 1 may be a three-dimensional flash memory. Each storage unit 10 may perform data writing and data erasing operations.

[0037] Each of the memory cells 10 includes a stacked structure ST, an insulating layer 12 , a floating gate layer 15 , a barrier layer 14 , a tunnel dielectric layer 16 , a channel layer 17 and a filling layer 18 .

[0038] The stacked structure ST includes at least one control layer 13, at least one erase layer 112, and at least one dielectric layer 11. Figure 2As shown in FIG. 1 , the stacked structure ST includes two control layers 13, three erase layers 112 and one dielectric layer 11. The control layer 13 is sandwiched between the adjacent dielectric layers 11 and the blocking layer 14. The erase layer 112 and the control layer 13 are isolated by the dielectric layer 11. The erase layer 112 and the floating gate layer 15 are isolated by the dielectric layer 11 and the blocking layer 14. In at least one embodiment of the present invention, the dielectric layer 11 is made of an insulating material; and the erase layer 112 is made of a low-resistance conductive material, such as a metal, a silicide, etc.

[0039] In at least one embodiment of the present invention, the barrier layer 14, the tunnel dielectric layer 16, the channel layer 17 and the filling layer 18 in the control layer 13 are substantially annular structures (eg Figure 1 The channel layer 17 is disposed on the outer side of the filling layer 18 , and the tunnel dielectric layer 16 is disposed on the outer side of the channel layer 17 .

[0040] The floating gate layer 15 is contained in the barrier layer 14. In the second direction Y, the floating gate layer 15 and the control layer 13 are coplanar. The floating gate layer 15 is a semi-annular structure (eg Figure 1 In the first direction X, the floating gate layer 15 is partially overlapped with the erase layer 112. In at least one embodiment of the present invention, the floating gate layer 15 is made of silicide or other materials with good conductivity. The floating gate layer 15 is used to store data.

[0041] In the second direction Y, the dielectric material between the erase layer 112 and the channel layer 17 has a first thickness layer D1; in the first direction X, the dielectric material between the erase layer 112 and the floating gate layer 15 has a second thickness layer D2; the breakdown voltage of the first thickness layer D1 is greater than the breakdown voltage of the second thickness layer D2 (e.g. Figure 2 shown).

[0042] The insulating layer 12 insulates and isolates the adjacent barrier layer 14 in the second direction Y, and insulates and isolates the tunnel dielectric layer 16 from the tunnel dielectric layer 16 in the adjacent storage unit 10 in the third direction Z (eg, Figure 1 In at least one embodiment of the present invention, the insulating layer 12 is made of silicon oxide material.

[0043] When the storage unit 10 performs a data writing operation, a corresponding voltage is applied to the control layer 13, so that electrons enter the floating gate layer 15 from the channel layer 17 through the tunnel dielectric layer 16 along the writing path path-A, thereby realizing data storage (such as Figure 2At the same time, a predetermined voltage is applied to the erase layer 112, so that the series resistance of the channel layer 17 is reduced, so as to facilitate the rapid conduction of the semiconductor device 1, thereby improving the data reading and writing speed. In at least one embodiment of the present invention, the predetermined voltage ranges from 3 to 8 volts. In other embodiments, the predetermined voltage can also be adjusted according to the performance of the semiconductor device 1, and can be other voltage ranges and values.

[0044] When the memory cell 10 performs a data erasing operation, a forward voltage is applied to the erasing layer 112, the floating gate layer 15 is floated, and a voltage less than the forward voltage is applied to the control layer 13 to prevent a breakdown phenomenon between the erasing layer 112 and the control layer 13. At the same time, a ground voltage or a negative voltage is provided on the channel layer 17, so that electrons flow from the floating gate layer 15 along the erasing path path-B through the dielectric layer 11 and the side wall of the blocking layer 14 located at the overlapping part of the erasing layer 112 and the floating gate layer 15 into the erasing layer 112, rather than through the tunnel dielectric layer 16 (such as Figure 2 In at least one embodiment of the present invention, the forward voltage is 10-15 V. In other embodiments, the forward voltage may also be other values.

[0045] When performing data read and write operations, the semiconductor device 1 applies a predetermined voltage to the erase gate 112 to reduce the series resistance of the channel layer 17, thereby facilitating rapid conduction of the semiconductor device 1 and improving the read and write speed of the semiconductor device 1.

[0046] It should also be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0047] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device comprising a plurality of memory cells; each of the memory cells comprising: A stacked structure comprising at least one control layer, at least one erase layer, and at least one dielectric layer; A barrier layer, disposed coplanarly with the control layer; a floating gate layer, contained in the barrier layer and insulated from the control layer by the barrier layer; a tunnel dielectric layer covering the barrier layer and one side of the floating gate layer; A channel layer, located on one side of the tunnel dielectric layer; The erase layer and the control layer are isolated by the dielectric layer; the erase layer and the floating gate layer are isolated by the dielectric layer; in a second direction perpendicular to the extension direction of the channel layer, the blocking layer, the tunnel dielectric layer and the channel layer are in an annular structure, the tunnel dielectric layer is arranged on the outside of the channel layer, and the stacked structure is arranged on the outside of the tunnel dielectric layer; the control layer, the erase layer and the dielectric layer are stacked along the extension direction of the channel layer; along the extension direction of the channel layer, the floating gate layer and the erase layer are partially overlapped; when performing data read and write operations, a predetermined voltage is applied to the erase layer, so that the series resistance of the channel layer is reduced, so as to facilitate the rapid conduction of the semiconductor device.

2. The semiconductor device according to claim 1, wherein In a direction parallel to the surface of the stacked structure, the dielectric material located between the erase layer and the channel layer has a first thickness layer; in a direction perpendicular to the stacked structure, the dielectric material located between the erase layer and the floating gate layer has a second thickness layer; the breakdown voltage of the first thickness layer is greater than the breakdown voltage of the second thickness layer.

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