Integrated circuit device and electronic system including the same

Abstract

Integrated circuit devices and electronic systems are disclosed. The integrated circuit devices include a base structure; a gate stack on the base structure and including a plurality of gate electrodes spaced apart from one another; a first upper insulating layer on the gate stack; a plurality of channel structures penetrating the gate stack, each of the plurality of channel structures including a respective alignment key protruding from the gate stack; a second upper insulating layer overlapping the respective alignment key of each of the plurality of channel structures; a top support layer on the second upper insulating layer; a bit line on the top support layer; and a plurality of bit line contacts electrically connecting a respective channel structure of the plurality of channel structures to the bit line. Sidewalls of the first upper insulating layer include first step portions.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2021-0014972 filed with the Korean Intellectual Property Office on February 2, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to an integrated circuit device and an electronic system including the integrated circuit device, and more specifically, to an integrated circuit device having a non-volatile vertical memory device and an electronic system including the integrated circuit device. Background Technology

[0004] There is a need for an integrated circuit device capable of storing high-capacity data in electronic systems requiring data storage. To increase the data storage capacity of an integrated circuit device, its integration density can be increased. In particular, the integration density of a memory device is a crucial factor in determining the economic viability of a product. The integration density of a two-dimensional memory device is primarily determined by the area occupied by a single memory cell, and is therefore greatly influenced by the level of fine patterning technology. However, the equipment required to form fine patterns is expensive, and the area of ​​the die is limited; therefore, the integration density of two-dimensional memory devices can only be increased in a limited way. Therefore, there is a need for a vertical memory device with a three-dimensional structure. Summary of the Invention

[0005] The present invention provides an integrated circuit device and an electronic system including the integrated circuit device.

[0006] According to the present invention, an integrated circuit device includes: a substrate structure; a gate stack located on the substrate structure and including a plurality of gate electrodes spaced apart from each other in a first direction perpendicular to the main surface of the substrate structure; a first upper insulating layer located on the gate stack; and a plurality of channel structures penetrating the gate stack and contacting the substrate structure. Each of the plurality of channel structures includes a corresponding alignment key projecting from the gate stack. The integrated circuit device includes a second upper insulating layer located in a key opening of the first upper insulating layer and overlapping with the corresponding alignment key of each of the plurality of channel structures; a top support layer located on the second upper insulating layer; a bit line located on the top support layer; and a plurality of bit line contacts penetrating the second upper insulating layer and the top support layer and electrically connecting the respective channel structures of the plurality of channel structures to the bit line. The sidewall of the first upper insulating layer includes a first stepped portion.

[0007] According to the present invention, an integrated circuit device includes: a substrate structure; a gate stack disposed on the substrate structure and including a plurality of gate electrodes spaced apart from each other in a first direction perpendicular to a main surface of the substrate structure; and a plurality of channel structures penetrating the gate stack and contacting the substrate structure. Each of the plurality of channel structures includes a corresponding alignment key projecting from the gate stack. The integrated circuit device includes a first upper insulating layer disposed on the gate stack, the first upper insulating layer including key openings overlapping the plurality of channel structures in the first direction. The integrated circuit device includes a second upper insulating layer disposed in the key openings of the first upper insulating layer. The second upper insulating layer overlaps with a corresponding alignment key of each of the plurality of channel structures. The second upper insulating layer includes a recessed portion located on its upper side. The integrated circuit device includes an embedded insulating pattern disposed in the recessed portion of the second upper insulating layer, a top support layer disposed on the second upper insulating layer and disposed on the embedded insulating pattern, a bit line disposed on the top support layer, and a plurality of bit line contacts penetrating the second upper insulating layer, the embedded insulating pattern, and the top support layer. A corresponding bit line contact of the plurality of bit line contacts electrically connects a corresponding channel structure of the plurality of channel structures to a bit line.

[0008] According to the present invention, an electronic system includes a main substrate, an integrated circuit device located on the main substrate, and a controller located on the main substrate and electrically connected to the integrated circuit device. The integrated circuit device includes: a substrate structure; a peripheral circuit structure located on the substrate structure; input / output pads electrically connected to the peripheral circuit structure; a gate stack located on the peripheral circuit structure and including a plurality of gate electrodes spaced apart from each other in a first direction perpendicular to the main surface of the substrate structure; a plurality of channel structures extending in the first direction and penetrating the gate stack, each of the plurality of channel structures including a corresponding alignment key projecting from the gate stack; a first upper insulating layer located on the gate stack and including a key opening overlapping the plurality of channel structures in the first direction. The sidewalls of the key opening include a first stepped portion. The integrated circuit device includes a second upper insulating layer located in the key opening of the first upper insulating layer and on the corresponding alignment key of each of the plurality of channel structures; a top support layer located on the second upper insulating layer; a bit line located on the top support layer; and a plurality of bit line contacts penetrating the second upper insulating layer and the top support layer and electrically connecting the respective channel structures of the plurality of channel structures to the bit line. Attached Figure Description

[0009] Embodiments of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram of an integrated circuit device according to an exemplary embodiment of the present invention;

[0011] Figure 2This is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an exemplary embodiment of the present invention;

[0012] Figure 3 This is a plan view of the main components of an integrated circuit device according to an exemplary embodiment of the present invention;

[0013] Figure 4 yes Figure 3 A cross-sectional view of the integrated circuit device along line IV-IV';

[0014] Figure 5 yes Figure 4 A magnified view of the "V" region in the image;

[0015] Figure 6 This is a cross-sectional view of a portion of an integrated circuit device according to an exemplary embodiment of the present invention;

[0016] Figure 7 This is a cross-sectional view of an integrated circuit device according to an exemplary embodiment of the present invention;

[0017] Figures 8A to 8O This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an exemplary embodiment of the present invention;

[0018] Figure 9 This is a diagram of an electronic system including an integrated circuit device, based on an exemplary embodiment of the present invention.

[0019] Figure 10 This is a perspective view of an electronic system including an integrated circuit device, based on an exemplary embodiment of the present invention.

[0020] Figure 11 It is a cross-sectional view of a semiconductor package including an integrated circuit device according to an exemplary embodiment of the present invention; and

[0021] Figure 12 This is a cross-sectional view of a semiconductor package including an integrated circuit device according to an exemplary embodiment of the present invention. Detailed Implementation

[0022] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 This is a block diagram of an integrated circuit device 10 according to an exemplary embodiment of the present invention.

[0024] Reference Figure 1 The integrated circuit device 10 may include a memory cell array 20 and peripheral circuits 30.

[0025] The memory cell array 20 may include multiple memory cell blocks BLK1, BLK2, ..., BLKn. Each of the multiple memory cell blocks BLK1, BLK2, ..., BLKn may include multiple memory cells. The multiple memory cell blocks BLK1, BLK2, ..., BLKn may be connected to the peripheral circuitry 30 via bit line BL, word line WL, serial select line SSL, and ground select line GSL.

[0026] The memory cell array 20 can be connected to the page buffer 34 via bit lines BL and to the row decoder 32 via word lines WL, string select lines SSL, and ground select lines GSL. In the memory cell array 20, multiple memory cells included in multiple memory cell blocks BLK1, BLK2, ..., BLKn can be flash memory cells. The memory cell array 20 can include a three-dimensional memory cell array. The three-dimensional memory cell array can include multiple NAND strings, and each of the multiple NAND strings can include multiple memory cells connected to multiple word lines WL, which are all vertically stacked.

[0027] The peripheral circuitry 30 may include a line decoder 32, a page buffer 34, a data input / output circuitry 36, and control logic 38. Although not shown, the peripheral circuitry 30 may also include various circuits such as voltage generation circuits configured to generate the various voltages required for the operation of the integrated circuit device 10, error correction circuits for correcting data read from the memory cell array 20, and input / output interfaces.

[0028] The peripheral circuit 30 can receive address ADDR, command CMD and control signal CTRL from the outside of the integrated circuit device 10, and send data DATA to or receive data DATA from the outside of the integrated circuit device 10.

[0029] The components of peripheral circuit 30 are described in detail below.

[0030] The row decoder 32 can select at least one of a plurality of memory cell blocks BLK1, BLK2, ..., BLKn in response to an external address ADDR, and select the word line WL, serial select line SSL, and ground select line GSL of the selected memory cell block. The row decoder 32 can transmit voltage to the word line WL of the selected memory cell block to perform memory operations.

[0031] Page buffer 34 can be connected to memory cell array 20 via bit line BL. When the program runs, page buffer 34 can operate as a write driver to apply a voltage to bit line BL according to the data DATA to be stored in memory cell array 20, and when a read operation is performed, page buffer 34 can operate as a sense amplifier to detect the data DATA stored in memory cell array 20. Page buffer 34 can operate according to the control signal PCTL received from control logic 38.

[0032] Data input / output circuit 36 ​​can be connected to page buffer 34 via data line DL. During program execution, data input / output circuit 36 ​​can receive data DATA from memory controller (not shown) and provide program data DATA to page buffer 34 based on the column address C_ADDR received from control logic 38. When performing a read operation, data input / output circuit 36 ​​can provide read data DATA stored in page buffer 34 to memory controller based on the column address C_ADDR received from control logic 38. Data input / output circuit 36 ​​can transmit input addresses or input commands to control logic 38 or row decoder 32.

[0033] Control logic 38 can receive commands CMD and control signals CTRL from the memory controller. Control logic 38 can provide the row address R_ADDR to the row decoder 32 and the column address C_ADDR to the data input / output circuitry 36. In response to the control signal CTRL, control logic 38 can generate various internal control signals used in the integrated circuit device 10. For example, when performing memory operations such as programming or erasing operations, control logic 38 can control the voltage levels applied to the word line WL and bit line BL.

[0034] Figure 2 This is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an exemplary embodiment of the present invention.

[0035] Reference Figure 2 An equivalent circuit diagram of a vertical NAND flash memory device with a vertical channel structure is shown as an example.

[0036] A memory cell array (MCA) may include multiple memory cell strings (MS). An MCA may include multiple bit lines (BL), multiple word lines (WL), at least one string select line (SSL), at least one ground select line (GSL), and a common source line (CSL).

[0037] Multiple memory cell strings (MS) can be formed between multiple bit lines (BL) and a common source line (CSL). Figure 2In this invention, each of the plurality of memory cell strings (MS) includes two string select lines (SSL), but the inventive concept is not limited thereto. For example, each of the plurality of memory cell strings (MS) may include one string select line (SSL).

[0038] Each of the multiple memory cell strings MS may include a string select transistor SST, a ground select transistor GST, and multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn. The drain region of the string select transistor SST may be connected to the bit line BL, and the source region of the string select transistor SST may be connected to the common source line CSL. The common source line CSL may include the region to which the source regions of the multiple ground select transistors GST are commonly connected.

[0039] The serial select transistor SST can be connected to the serial select line SSL, and the ground select transistor GST can be connected to the ground select line GSL. Multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn can be connected to multiple word lines WL respectively.

[0040] Figure 3 This is a plan view of the main components of an integrated circuit device 100 according to an exemplary embodiment of the present invention. Figure 4 yes Figure 3 A cross-sectional view of the integrated circuit device 100 along line IV-IV'. Figure 5 yes Figure 4 An enlarged view of the "V" region in the image.

[0041] Reference Figures 3 to 5 The integrated circuit device 100 may include a cell array structure CS, which includes a memory cell area MCR and a connection area CON.

[0042] The memory cell region (MCR) may include a region having the above reference. Figure 2 The area of ​​the vertical channel structure NAND-type memory cell array MCA is described. The connection area CON may include an area in which pads PAD are formed for electrically connecting the memory cell array MCA formed in the memory cell area MCR and the peripheral circuit area (not shown) to each other.

[0043] The substrate structure 110 may include a semiconductor substrate. The semiconductor substrate may include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI oxide semiconductors. For example, group IV semiconductors may include silicon (Si), germanium (Ge), or silicon-germanium. The semiconductor substrate may provide a wafer in which a bulk wafer or epitaxial layer is formed. In other embodiments, the semiconductor substrate may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. In some example embodiments, the substrate structure 110 may include a vertically stacked lower substrate layer and an upper substrate layer. In this case, the lower substrate layer may include a metallic material such as tungsten (W), and the upper substrate layer may include a semiconductor layer such as silicon.

[0044] On the substrate structure 110, the gate stack GS can extend in a first direction (X direction) and a second direction (Y direction) parallel to the main surface of the substrate structure 110. The gate stack GS may include a plurality of gate electrodes 130 and a plurality of insulating layers 140, and the plurality of gate electrodes 130 and the plurality of insulating layers 140 can be alternately arranged in a third direction (Z direction) perpendicular to the upper surface of the substrate structure 110.

[0045] The gate electrode 130 may include a buried conductive layer 132 and an insulating pad 134 covering the upper, bottom, and side surfaces of the buried conductive layer 132, or the upper, bottom, and side surfaces of the buried conductive layer 132. For example, the buried conductive layer 132 may include a metal such as tungsten, a metal silicide such as tungsten silicide, doped polysilicon, or any combination thereof. In some embodiments, the insulating pad 134 may include a high-k dielectric material such as alumina.

[0046] Multiple gate electrodes 130 can correspond to the above reference. Figure 2 The described memory cell string MS includes a ground select line GSL, a word line WL, and at least one string select line SSL. For example, the bottommost gate electrode 130 can be used as the ground select line GSL, the topmost gate electrode 130 can be used as the string select line SSL, and the remaining gate electrodes 130 can be used as the word line WL. Therefore, the memory cell string MS may include a ground select transistor GST, a string select transistor SST, and memory cell transistors MC1, MC2, ..., MCn-1 and MCn connected in series with each other.

[0047] Multiple word line cutouts 150 for filling the word line cutout opening WLH can be arranged on the substrate structure 110. The multiple word line cutouts 150 can extend in a first direction (X direction). The multiple word line cutouts 150 can extend from the substrate structure 110 in a third direction (Z direction). Gate stacks GS arranged between a pair of word line cutouts 150 can form a block, and the pair of word line cutouts 150 can limit the width of the gate stacks GS in a second direction (Y direction). The word line cutouts 150 can have an insulating structure. The word line cutouts 150 can include silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. For example, the word line cutouts 150 can include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), or any combination thereof.

[0048] Multiple channel structures 160 can extend from the upper surface of the substrate structure 110 along a third direction (Z direction) through the gate electrode 130 in the memory cell region (MCR). The multiple channel structures 160 can be spaced apart from each other in a first direction (X direction) and a second direction (Y direction). The multiple channel structures 160 can be arranged in a zigzag or staggered shape.

[0049] Multiple channel structures 160 may extend in the third direction (Z direction) through a gate stack GS. The multiple channel structures 160 may fill a channel via 160H penetrating the gate stack GS. Each of the multiple channel structures 160 may include a gate insulating layer 162, a channel layer 164, a buried insulating layer 166, and a conductive plug 168. The gate insulating layer 162 and the channel layer 164 may be sequentially disposed on the sidewall of the channel via 160H. For example, the gate insulating layer 162 may be conformally disposed on the side surface of the channel via 160H, and the channel layer 164 may be conformally disposed on the bottom of the sidewall of the channel via 160H. The buried insulating layer 166, filling the remaining space of the channel via 160H, may be disposed on the channel layer 164. In a plan view, the channel layer 164 may surround the buried insulating layer 166. A conductive plug 168, which contacts the channel layer 164 and blocks the entrance (e.g., the uppermost end) of the channel aperture 160H, may be disposed above the channel aperture 160H. In other embodiments, in a plan view, the buried insulating layer 166 may be omitted within the cylindrical interior formed by the gate insulating layer 162, and the channel layer 164 may fill the remaining portion of the channel aperture 160H. In this case, the channel layer 164 may have a columnar shape.

[0050] Multiple channel structures 160 may contact the substrate structure 110. In some embodiments, a channel layer 164 may contact the upper surface of the substrate structure 110 at the bottom of a channel hole 160H. In other embodiments, a contact semiconductor layer (not shown) having a specific height from the substrate structure 110 may be formed on the bottom surface of the channel hole 160H, and the channel layer 164 may be electrically connected to the substrate structure 110 via the contact semiconductor layer. In other embodiments, the bottom surface of the channel layer 164 may be arranged at a horizontal height below the upper surface of the substrate structure 110 in the vertical direction.

[0051] In an example embodiment, each of the plurality of channel structures 160 may include an alignment key 161 protruding from the uppermost insulating layer 140 in the gate stack GS. The alignment key 161 may refer to a portion of each of the channel structures 160 protruding from the uppermost insulating layer 140. The alignment key 161 may include a portion of a conductive plug 168 and a gate insulating layer 162 surrounding that portion of the conductive plug 168 in a plan view. For example, the uppermost insulating layer 140 includes a recessed portion on its upper side, and the plurality of alignment keys 161 of the plurality of channel structures 160 may be located in the recessed portion of the uppermost insulating layer 140. In the manufacturing process of the integrated circuit device 100, the plurality of alignment keys 161 of the plurality of channel structures 160 may be used as alignment structures for photolithography processes. For example, the plurality of alignment keys 161 of the plurality of channel structures 160 may be used as alignment structures for forming a mask pattern for forming word line cut openings (WLH). Relative to the substrate or base structure 110, the bottom surface of the alignment key 161 may be lower than the top surface of the conductive plug 168, but higher than the bottom portion of the conductive plug 168. The bottom surface of the alignment key 161 may be lower than the top surface of the gate insulating layer 162 of the channel structure 160.

[0052] The gate insulating layer 162 may have a structure in which a tunneling dielectric layer, a charge storage layer, and a barrier dielectric layer are sequentially arranged on the outer wall of the channel layer 164. The tunneling dielectric layer may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage layer may include a region in which electrons passing through the tunneling dielectric layer from the channel layer 164 can be stored, and may include silicon nitride, boron nitride, boron silicon nitride, or polycrystalline silicon doped with impurities. The barrier dielectric layer may include silicon oxide, silicon nitride, or a metal oxide having a dielectric constant larger than that of silicon oxide.

[0053] Within a single block, the uppermost gate electrode 130 can be divided into two parts in a plane relative to the string isolation insulating layer (not shown). These two parts can constitute the above reference. Figure 2 The string selection line described is SSL.

[0054] The gate stack GS can extend within the connection region CON and may include pad portions PAD. Within the connection region CON, the further the plurality of gate electrodes are from the upper surface of the substrate structure 110, the less the plurality of gate electrodes 130 extend in the first horizontal direction (X direction) (i.e., into the connection region CON). The pad portion PAD may represent a stepped portion of the gate electrodes 130. A covering insulating layer 120 may be disposed on the pad portion PAD. Contact structures CNT connected to the gate electrodes 130 via the covering insulating layer 120 may be disposed within the connection region CON.

[0055] Contact structures CNTs connected to the pad portion PAD of the gate electrode 130 via the covering insulating layer 120 can be arranged in the connection area CON. The contact structure CNT may have a tapered column shape, the width of which decreases from its upper end to its lower end in the third direction (Z direction).

[0056] Although not shown, multiple dummy channel structures (not shown) extending vertically (Z-direction) from the upper surface of the substrate structure 110 through the gate stack GS can also be formed in the connection region CON. These dummy channel structures can be formed to prevent tilting or bending of the gate stack GS during the manufacturing process of the integrated circuit device 100 and to ensure structural stability. The multiple dummy channel structures can have a structure and shape similar to those of the multiple channel structures 160.

[0057] The first upper insulating layer 170 may be disposed on the gate stack GS and the cover insulating layer 120. For example, the first upper insulating layer 170 may include silicon oxide or silicon oxynitride.

[0058] The first upper insulating layer 170 may include a key opening 172 at a location that vertically overlaps with a region where a plurality of alignment keys 161 are disposed therein, of which a plurality of channel structures 160 are arranged. The key opening 172 may be formed directly on a recessed portion of the uppermost insulating layer 140 of the gate stack GS. The key opening 172 may penetrate the first upper insulating layer 170 in a vertical direction. The key opening 172 may be generally tapered in shape, with its width increasing in the direction away from the substrate structure 110.

[0059] The sidewall 174 defining the key opening 172 of the first upper insulating layer 170 may include an inclined surface. For example, the sidewall 174 defining the key opening 172 of the first upper insulating layer 170 may include an inclined surface that is inclined at an angle relative to a third direction (Z direction) perpendicular to the upper surface of the substrate structure 110.

[0060] The sidewall 174 defining the key opening 172 of the first upper insulating layer 170 may include a step portion 173. In a plan view, the step portion 173 may extend continuously along the circumference of the key opening 172. Because the sidewall 174 of the first upper insulating layer 170 includes the step portion 173, the sidewall 174 of the first upper insulating layer 170 may include at least two segments extending in different directions from each other. For example, when the sidewall 174 of the first upper insulating layer 170 includes two segments connected to each other between the lower and upper ends of the sidewall 174, the angle between the extending directions of the two segments may be in the range of approximately 20° to approximately 90°. In other words, the difference between the angle between one of the two segments of the sidewall 174 of the first upper insulating layer 170 and a reference direction (e.g., a direction parallel to the main surface of the substrate structure 110) and the angle between the other segment of the two segments and the reference direction may be in the range of approximately 20° to approximately 90°.

[0061] In an example embodiment, the sidewall 174 of the first upper insulating layer 170 may include a first segment 174a, a second segment 174b, and a third segment 174c connected between the lower and upper ends of the sidewall 174. In this case, the extension direction of the first segment 174a may be different from the extension direction of the second segment 174b, and the extension direction of the second segment 174b may be different from the extension direction of the third segment 174c. For example, the first tilt angle between the extension direction of the first segment 174a and a first direction (X direction) perpendicular to the main surface of the substrate structure 110 may be greater than the second tilt angle between the extension direction of the second segment 174b and a first direction (X direction) parallel to the main surface of the substrate structure 110, and the second tilt angle of the second segment 174b may be smaller than the third tilt angle between the extension direction of the third segment 174c and a first direction (X direction) parallel to the main surface of the substrate structure 110.

[0062] In the example embodiment, the horizontal distance (X or Y direction) between the lower and upper ends of the sidewall 174 of the first upper insulating layer 170 can be in the range of about 0.1 μm to about 10 μm.

[0063] In an example embodiment, the first upper insulating layer 170 may include a first sub-insulating layer and a second sub-insulating layer sequentially stacked on the gate stack GS. The first sub-insulating layer may include a material different from that of the second sub-insulating layer. For example, the first sub-insulating layer may include silicon nitride, while the second sub-insulating layer may include silicon oxide.

[0064] For example, to form the first upper insulating layer 170, a process of coating an insulating material layer on the gate stack GS and a process of forming a bond opening 172 can be performed sequentially. The process of forming the bond opening 172 may include a first etching process and a second etching process performed sequentially on the insulating material layer. In this case, the width of the mask opening of the mask pattern used in the second etching process may be greater than the width of the opening of the mask pattern used in the first etching process. Therefore, the sidewall 174 of the first upper insulating layer 170 may undergo the first etching process and the second etching process to form a step portion 173.

[0065] A second upper insulating layer 182 may be disposed on the first upper insulating layer 170. The key openings 172 of the first upper insulating layer 170 may be filled with the second upper insulating layer 182. The key openings 172 may at least partially fill the second upper insulating layer 182, such that the second upper insulating layer 182 may cover or overlap the plurality of alignment keys 161 of the plurality of channel structures 160. The second upper insulating layer 182 may comprise silicon oxide or silicon oxynitride.

[0066] The key opening 172 of the first upper insulating layer 170 at least partially fills the second upper insulating layer 182, and a recessed portion 182R may be formed on the upper side of the second upper insulating layer 182. The recessed portion 182R of the second upper insulating layer 182 may be a portion recessed from its peripheral portion. In a plan view, the recessed portion 182R of the second upper insulating layer 182 may have dimensions overlapping with the areas where the plurality of alignment keys 161 of the plurality of channel structures 160 are arranged. In the key opening 172 of the first upper insulating layer 170, the second upper insulating layer 182 is formed along a curve formed by the plurality of alignment keys 161 of the plurality of channel structures 160 protruding from the uppermost insulating layer 140, therefore, the recessed portion 182R of the second upper insulating layer 182 may provide an uneven surface.

[0067] A top support layer TS may be disposed on the second upper insulating layer 182. During the manufacturing process of the integrated circuit device 100, the top support layer TS provides structural stability to the gate stack GS, thereby preventing process failures due to bending or tilting of the gate stack GS. The top support layer TS may comprise silicon oxide or silicon oxynitride.

[0068] Multiple vias (TSHs) may be formed in the top support layer (TS). The multiple vias (TSHs) may vertically overlap with the word line cutouts (WLHs). The multiple vias (TSHs) may at least partially fill the upper embedded layer (184). In some embodiments, the upper embedded layer (184) may comprise the same material as the word line cutout element (150). The upper embedded layer (184) may comprise silicon oxide or silicon oxynitride.

[0069] An embedded insulating pattern 190 may be disposed between a second upper insulating layer 182 and an upper support layer such as a top support layer TS. A recessed portion 182R of the second upper insulating layer 182 may be filled with the embedded insulating pattern 190. The embedded insulating pattern 190 may be located between the second upper insulating layer 182 and the top support layer TS, and may be surrounded by the second upper insulating layer 182 in a plan view. The embedded insulating pattern 190 may overlap with a plurality of alignment keys 161 of the plurality of channel structures 160 in the vertical direction (Z direction). For example, in a plan view, the embedded insulating pattern 190 may have planar regions that overlap with all of the plurality of alignment keys 161 of the plurality of channel structures 160.

[0070] The embedded insulating pattern 190 may include an upper surface 192U, a lower surface 192L, and a side surface 192S. The upper surface 192U of the embedded insulating pattern 190 may contact the lower surface of the top support layer TS, and the lower surface 192L of the embedded insulating pattern 190 may face the plurality of channel structures 160. The side surface 192S of the embedded insulating pattern 190 may extend between the lower surface 192L and the upper surface 192U of the embedded insulating pattern 190. The side surface 192S of the embedded insulating pattern 190 may be surrounded by and in contact with the second upper insulating layer 182.

[0071] The upper surface 192U of the embedded insulating pattern 190 can be flat. In an example embodiment, the embedded insulating pattern 190 and the second upper insulating layer 182 can have flat surfaces through the same planarization process. Through the planarization process, the upper surface 192U of the embedded insulating pattern 190 can be coplanar with the upper surface of the second upper insulating layer 182.

[0072] Furthermore, since the embedded insulating pattern 190 at least partially fills the recessed portion 182R of the second upper insulating layer 182, the lower surface 192L and side surface 192S of the embedded insulating pattern 190 can have shapes corresponding to the shapes of the surfaces provided by the recessed portion 182R of the second upper insulating layer 182.

[0073] The lower surface 192L of the buried insulating pattern 190 may have an uneven shape. As described above, the recessed portion 182R of the second upper insulating layer 182 provides an uneven surface corresponding to the curve formed by the protrusions of the multiple alignment keys 161 of the multiple channel structures 160 from the uppermost insulating layer 140 located in the gate stack GS. Therefore, the lower surface 192L of the buried insulating pattern 190, which is at least partially filled in the recessed portion 182R of the second upper insulating layer 182, may have an uneven shape.

[0074] The side surface 192S of the embedded insulating pattern 190 can extend obliquely from the lower surface 192L of the embedded insulating pattern 190 to the upper surface 192U. The side surface 192S of the embedded insulating pattern 190 can extend obliquely outward from the lower end to the upper end.

[0075] For example, the embedded insulating pattern 190 may include a material different from the material of each of the first upper insulating layer 170 and the second upper insulating layer 182. For example, the embedded insulating pattern 190 may include polysilicon.

[0076] Bit line contacts BLC can contact the conductive plugs 168 of the channel structure 160 via the top support layer TS and the second upper insulating layer 182. Bit lines BL of the bit line contacts BLC can extend along a second direction (Y direction) on the top support layer TS. The bit line contacts BLC can electrically connect the bit lines BL and the channel structure 160 to each other. In an example embodiment, multiple bit line contacts BLC can be connected to multiple channel structures 160 via an embedded insulating pattern 190 sandwiched between the top support layer TS and the second upper insulating layer 182.

[0077] Furthermore, in the connection area CON, multiple conductive lines ML can be arranged on the top support layer TS. The contact structure CNT can penetrate the top support layer TS, the first upper insulating layer 170, the second upper insulating layer 182, and the cover insulating layer 120. The contact structure CNT can electrically connect the conductive lines ML to the gate electrode 130.

[0078] Figure 6 This is a cross-sectional view of a portion of an integrated circuit device 100a according to an exemplary embodiment of the present invention. Figure 6 It shows the corresponding Figure 4 The "V" portion of the area.

[0079] Reference Figure 6 The key opening 172 of the first upper insulating layer 170a is defined (see...) Figure 4 The sidewall 176 of the first upper insulating layer 170a may include a first stepped portion 175a and a second stepped portion 175b located between the lower end and the upper end. The second stepped portion 175b may be disposed between the first stepped portion 175a and the upper end of the sidewall 176 of the first upper insulating layer 170a. Each of the first stepped portion 175a and the second stepped portion 175b may extend continuously along the circumference or edge of the key opening. The first stepped portion 175a of the sidewall 176 of the first upper insulating layer 170a may be defined by two segments extending in different directions, and the second stepped portion 175b of the sidewall 176 of the first upper insulating layer 170a may be defined by two segments extending in different directions.

[0080] For example, the sidewall 176 of the first upper insulating layer 170a may include a first segment 176a, a second segment 176b, a third segment 176c, a fourth segment 176d, and a fifth segment 176e sequentially connected between the lower and upper ends of the sidewall 176. Two adjacent segments of the first to fifth segments 176a to 176e may extend in different directions. For example, the extension direction of the first segment 176a may be different from the extension direction of the second segment 176b, the extension direction of the second segment 176b and the extension direction of the third segment 176c may be different from the extension direction of the third segment 176c and the extension direction of the fourth segment 176d, and the extension direction of the fourth segment 176d and the extension direction of the fifth segment 176e may be different from the extension direction of the fifth segment 176e. For example, the angle between the extension directions of two adjacent segments of the first to fifth segments 176a to 176e may be in the range of approximately 20° to approximately 90°.

[0081] For example, to form the first upper insulating layer 170a, a process of coating an insulating material layer on the gate stack GS and a process of forming bond openings can be performed sequentially. The process of forming bond openings may include a first etching process, a second etching process, and a third etching process performed sequentially on the insulating material layer. In this case, the width of the mask opening of the mask pattern used in the second etching process may be greater than the width of the opening of the mask pattern used in the first etching process, and the width of the mask opening of the mask pattern used in the third etching process may be greater than the width of the opening of the mask pattern used in the second etching process and the first etching process. Therefore, through the first etching process, the second etching process, and the third etching process, the sidewall 176 of the first upper insulating layer 170a can be formed to have a first step portion 175a and a second step portion 175b.

[0082] Figure 7 This is a cross-sectional view illustrating an example embodiment of an integrated circuit device 100b according to a concept of the present invention.

[0083] Figure 7 The integrated circuit device 100b shown may be substantially similar to the reference 100b. Figures 3 to 5 The integrated circuit device 100 is described because it includes a peripheral circuit structure PS. The following will primarily describe... Figure 7 Integrated circuit device 100b in Figures 3 to 5 The differences between the integrated circuit devices 100 in the middle.

[0084] Reference Figure 7The integrated circuit device 100b may include a peripheral circuit structure PS and a cell array structure CS arranged at a horizontal height that is vertically higher than the peripheral circuit structure PS. The cell array structure CS may include a memory cell area MCR and a connection area CON, and the peripheral circuit structure PS may include a peripheral circuit area.

[0085] The integrated circuit device 100b of this embodiment may have a peripheral cell-on-a-cell (COP) structure, wherein the cell array structure CS is arranged on the peripheral circuit structure PS. The substrate structure 110 may be arranged between the peripheral circuit structure PS and the cell array structure CS.

[0086] The peripheral circuit structure PS may include peripheral circuit transistors 60TR and peripheral circuit lines 70 disposed on the semiconductor substrate 101. In the semiconductor substrate 101, an active region AC may be defined by a device spacer 102, and a plurality of peripheral circuit transistors 60TR may be formed in the active region AC. The plurality of peripheral circuit transistors 60TR may include a peripheral circuit gate 60G and source / drain regions 62 disposed on the semiconductor substrate 101 on opposite sides of the peripheral circuit transistors 60TR.

[0087] The peripheral circuit line 70 may include a plurality of peripheral circuit contacts 72 and a plurality of peripheral circuit metal layers 74. The peripheral circuit transistor 60TR and the interlayer insulating layer 80 covering or overlapping the peripheral circuit transistor 60TR may be disposed on the semiconductor substrate 101. The plurality of peripheral circuit metal layers 74 may have a multilayer structure of multiple metal layers disposed at different vertical horizontal heights.

[0088] Figures 8A to 8O This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device 100 according to an exemplary embodiment of the present invention. Referring below... Figures 8A to 8O Description of manufacturing reference Figures 3 to 5 The method of the integrated circuit device 100 described.

[0089] Reference Figure 8A Multiple insulating layers 140 and multiple molding layers 130M may be alternately formed on the main surface of the substrate structure 110 to form a sacrificial gate stack (SGS). In an example embodiment, the multiple insulating layers 140 may include insulating materials such as silicon oxide, silicon oxynitride, etc. The multiple molding layers 130M may include materials different from those of the multiple insulating layers 140, and the multiple molding layers 130M may include silicon nitride, silicon oxynitride, or polycrystalline silicon doped with impurities.

[0090] Reference Figure 8BThe pad portion PAD can be formed by sequentially patterning the sacrificial gate stack SGS in the connection region CON. In an example embodiment, the pad portion PAD may have a stepped shape with an upper surface at different horizontal heights relative to the substrate structure 110.

[0091] Then, a cover insulating layer 120 can be formed to cover or overlap the pad portion PAD. The cover insulating layer 120 may include an insulating material, such as silicon oxide, silicon oxynitride, etc.

[0092] Reference Figure 8C The sacrificial gate stack SGS can be patterned to form a channel via 160H, and a channel structure 160 including a gate insulating layer 162, a channel layer 164, a buried insulating layer 166 and a conductive plug 168 can be formed on the inner wall of the channel via 160H.

[0093] Reference Figure 8D A first upper insulating layer 170 may be formed on the sacrificial gate stack SGS and the cover insulating layer 120. The first upper insulating layer 170 may include silicon oxide or silicon oxynitride.

[0094] Reference Figure 8E A first mask pattern M1 can be formed on the first upper insulating layer 170. The first mask pattern M1 may include a first mask opening M1O. After forming the first mask pattern M1, the first mask pattern M1 can be used as an etching mask to perform an initial etching process. Through the initial etching process, a portion of the first upper insulating layer 170 is removed, thereby forming an upper opening 172a in the first upper insulating layer 170.

[0095] Reference Figure 8E and Figure 8F A trimming process for the first mask pattern M1 can be performed. The trimmed first mask pattern M1' may have a second mask opening M1O'. The width of the second mask opening M1O' may be greater than the width of the first mask opening M1O. Because the width of the second mask opening M1O' is greater than the width of the first mask opening M1O, the upper surface of the first upper insulating layer 170 surrounding the upper opening 172a can be exposed.

[0096] Reference Figure 8GA second etching process is performed using the modified first mask pattern M1' as an etching mask. For example, the second etching process may include a wet etching process. Through the second etching process, a lower opening 172b connected to the upper opening 172a can be formed. The upper opening 172a and the lower opening 172b may be part of the bond opening 172. Through the second etching process, a portion of the first upper insulating layer 170 can be removed, and a portion of the uppermost insulating layer 140 of the sacrificial gate stack SGS can be removed. The second etching process can be performed such that a portion of each of the plurality of channel structures 160 protrudes from the sacrificial gate stack SGS by a specific height.

[0097] For reference Figures 8E to 8G The width of the second mask opening M1O' of the modified first mask pattern M1' used in the second etching process is greater than the width of the first mask opening M1O of the first mask pattern M1 used in the first etching process. Therefore, the sidewall of the first upper insulating layer 170 formed by the first etching process and the second etching process can have a stepped portion.

[0098] Reference Figure 8H ,exist Figure 8G A lower mask layer 211 is formed on the resulting structure. The lower mask layer 211 is a hard mask and may include, for example, an amorphous carbon layer. The lower mask layer 211 may cover or overlap the first upper insulating layer 170 and at least partially fill the bond openings 172 in the first upper insulating layer 170. The bond openings 172 of the first upper insulating layer 170 are at least partially filled by the lower mask layer 211, and a recessed portion 211R may be formed on the upper side of the lower mask layer 211.

[0099] After forming the lower mask layer 211, an upper mask layer 213 is formed on the lower mask layer 211. The upper mask layer 213 may include a photoresist. The lower mask layer 211 and the upper mask layer 213 may be part of the mask layer 210.

[0100] When the upper mask layer 213 is coated along the surface of the lower mask layer 211, there is a concern that coating defects may occur in the upper mask layer 213 as the slope of the sidewalls provided by the recessed portion 211R of the lower mask layer 211 increases. However, in embodiments of the present invention, as shown in reference... Figures 8E to 8G The sidewalls of the first upper insulating layer 170, which defines the bond opening 172 through a two-etch process, can have a gentle slope. For example, compared to the case where an opening exposing multiple channel structures 160 is formed in the first upper insulating layer 170 through a single etching process, the sidewalls of the first upper insulating layer 170 formed through a two-etch process have a gentle slope. The sidewalls of the lower mask layer 211 also have a gentle slope, thereby eliminating coating defects in the upper mask layer 213.

[0101] Reference Figure 8I The mask opening 215 is formed through a patterning process of the mask layer 210. For example, the upper mask layer 213 is patterned to form an upper opening, and the lower opening of the lower mask layer 211 can be formed by using the upper mask layer 213, in which the upper opening is formed, as an etching mask. The upper opening in the upper mask layer 213 and the lower opening in the lower mask layer 211 can constitute the mask opening 215 in the mask layer 210. When the patterning process is performed to form the mask opening 215 in the mask layer 210, the alignment bonds of the plurality of channel structures 160 can be used as alignment structures for the photolithography process.

[0102] After forming the mask opening 215 in the mask layer 210, a portion of the sacrificial gate stack SGS can be removed to form the word line dicing opening WLH. The word line dicing opening WLH can be formed by an etching process that uses the mask layer 210 as an etching mask.

[0103] Reference Figure 8J ,from Figure 8I The mask layer 210 is removed from the product, and then a second upper insulating layer 182 is formed. The second upper insulating layer 182 may be formed on the first upper insulating layer 170 and at least partially fills the key openings 172 of the first upper insulating layer 170. A recessed portion 182R may be formed on the upper part of the second upper insulating layer 182, and the key openings 172 are at least partially filled by the second upper insulating layer 182. In the key openings 172 of the first upper insulating layer 170, the second upper insulating layer 182 is formed along a curve formed by the protrusion of the uppermost insulating layer 140 of the sacrificial gate stack SGS through a plurality of alignment keys of a plurality of channel structures 160, so the recessed portion 182R of the second upper insulating layer 182 can provide an uneven surface. In addition, the second upper insulating layer 182 may cover the inner wall of the word line cut opening WLH. The second upper insulating layer 182 may include silicon oxide or silicon oxynitride.

[0104] After forming the second upper insulating layer 182, a material layer 220 may be formed on the second upper insulating layer 182. A portion of the material layer 220 may be formed within the word line cutout WLH, and may be formed on a portion of the second upper insulating layer 182 covering the inner wall of the word line cutout WLH. The material layer 220 may include an insulating material. For example, the material layer 220 may include polysilicon.

[0105] Reference Figure 8J and Figure 8K , can be Figure 8JThe product undergoes a planarization process. The planarization process may include removing a portion of the material layer 220, thereby partially exposing the second upper insulating layer 182. Through the planarization process, a portion of the material layer 220 may form an embedded insulating pattern 190 in a recessed portion 182R of the second upper insulating layer 182, and other portions of the material layer 220 may form a sacrificial embedded layer 221 in a letter-cut opening WLH. Through the planarization process, the exposed upper surface of the embedded insulating pattern 190, the exposed surface of the second upper insulating layer 182, and the exposed surface of the sacrificial embedded layer 221 may be on the same plane.

[0106] Reference Figure 8L A top support layer TS comprising a plurality of hole TSHs can be formed on the second upper insulating layer 182 and the embedded insulating pattern 190. In a plan view, the plurality of hole TSHs can vertically overlap with the word line cutting openings WLH and can be spaced apart from each other in a first horizontal direction (X direction). In the process of forming the plurality of hole TSHs, the portion of the second upper insulating layer 182 below the plurality of hole TSHs can be removed.

[0107] Reference Figure 8L and Figure 8M The sacrificial buried layer 221 exposed through multiple vias TSH is removed, and a portion of the second upper insulating layer 182 in the word line cut opening WLH is also removed. For example, multiple wet etching processes can be performed to remove the sacrificial buried layer 221 and a portion of the second upper insulating layer 182 within the word line cut opening WLH.

[0108] Reference Figure 8M and Figure 8N Multiple molding layers 130M exposed through the sidewalls of the word line cutting opening WLH can be removed. The removal process for the multiple molding layers 130M can include a wet etching process using a phosphoric acid solution as an etchant. Multiple gate electrodes 130 can be formed by embedding conductive material in the locations where the multiple molding layers 130M are removed.

[0109] Reference Figure 8O The word line cutout 150 can be formed by at least partially filling the word line cutout opening WLH with insulating material, and the upper embedded layer 184 can be formed by at least partially filling the hole TSH with insulating material. In some embodiments, the upper embedded layer 184 and the word line cutout 150 can be formed by the same process, and the upper embedded layer 184 can have the same material as the word line cutout 150.

[0110] Then, a contact structure CNT can be formed that is electrically connected to the pad portion PAD through the top support layer TS, the second upper insulating layer 182, the first upper insulating layer 170, and the cover insulating layer 120. Then, a bit line contact BLC can be formed that is electrically connected to the channel structure 160 through the top support layer TS, the second upper insulating layer 182, and the first upper insulating layer 170.

[0111] Next, please refer to Figure 4 A bit line BL electrically connected to the bit line contact BLC can be formed on the top support layer TS, and a conductive line ML electrically connected to the contact structure CNT can be formed.

[0112] Figure 9 This is a diagram illustrating an electronic system 1000 including an integrated circuit device 1100 according to an exemplary embodiment of the present invention.

[0113] Reference Figure 9 The electronic system 1000 according to the present invention may include an integrated circuit device 1100 and a controller 1200 electrically connected to the integrated circuit device 1100.

[0114] Electronic system 1000 may include a storage device or an electronic device that includes a storage device, such as a storage device, that contains one or more integrated circuit devices 1100. For example, electronic system 1000 may include a solid-state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device that includes at least one integrated circuit device 1100.

[0115] Integrated circuit device 1100 may include a non-volatile vertical memory device. For example, integrated circuit device 1100 may include a device containing the above-referenced memory. Figures 3 to 7 The NAND flash memory device of at least one of the described integrated circuit devices 100, 100a, and 100b. In some embodiments, the first structure 1100F may be arranged adjacent to the second structure 1100S.

[0116] The first structure 1100F can be a peripheral circuit structure, which includes a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S can be a memory cell structure, which includes a bit line BL, a common source line CSL, multiple word lines WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and multiple memory cell strings CSTR between the bit line BL and the common source line CSL.

[0117] In the second structure 1100S, each of the plurality of memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs arranged between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. Various modifications can be made to the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 according to embodiments.

[0118] In some embodiments, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. A first lower gate line LL1 and a second lower gate line LL2 may respectively include the gate electrodes of the lower transistors LT1 and LT2. A word line WL may include the gate electrode of a memory cell transistor MCT, and a first upper gate line UL1 and a second upper gate line UL2 may respectively include the gate electrodes of the upper transistors UT1 and UT2.

[0119] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, multiple word lines WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via multiple first connection lines 1115 extending from the first structure 1100F to the second structure 1100S. Multiple bit lines BL can be electrically connected to the page buffer 1120 via multiple second connection lines 1125 extending from the first structure 1100F to the second structure 1100S.

[0120] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one of the plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130.

[0121] The integrated circuit device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection lines 1135 extending from the first structure 1100F to the second structure 1100S.

[0122] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 may include a plurality of integrated circuit devices 1100, and in this case, the controller 1200 may control the plurality of integrated circuit devices 1100.

[0123] Processor 1210 controls the overall operation of electronic system 1000, including controller 1200. Processor 1210 operates according to firmware and can control NAND controller 1220 to access integrated circuit device 1100. NAND controller 1220 may include NAND interface 1221 for handling communication with integrated circuit device 1100. Control commands for controlling integrated circuit device 1100, data to be recorded on multiple memory cell transistors (MCTs) of integrated circuit device 1100, and data to be read from multiple memory cell transistors (MCTs) of integrated circuit device 1100 can be sent via NAND interface 1221. Host interface 1230 provides communication functionality between electronic system 1000 and external host. When a control command is received from external host via host interface 1230, processor 1210 can control integrated circuit device 1100 in response to the control command.

[0124] Figure 10 This is a perspective view of an electronic system 2000 including an integrated circuit device, according to an exemplary embodiment of the present invention.

[0125] Reference Figure 10 An electronic system 2000 according to some embodiments of the present invention may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and dynamic random access memory (DRAM) 2004.

[0126] The main substrate 2001 may include a connector 2006, which includes a plurality of pins to be connected to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host via one or more interfaces such as USB, PCI-Express, Serial Advanced Technology Attachment (SATA), M-PHY for Universal Flash Memory (UFS), etc. In some embodiments, the electronic system 2000 may be operated by power supplied from the external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 via a plurality of conductive interconnect patterns 2005 formed on the main substrate 2001.

[0127] The controller 2002 can record data on and / or read data from the semiconductor package 2003, and / or increase the operating speed of the electronic system 2000.

[0128] DRAM 2004 may include a buffer memory for mitigating the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may also operate as a high-speed cache memory and provide space for temporary data storage during the control operation of the semiconductor package 2003. When the electronic system 2000 includes DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0129] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a semiconductor package having a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 electrically connecting the plurality of semiconductor chips 2200 and the package substrate 2100 to each other, and a molding layer 2500 covering or overlapping the plurality of semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0130] The package substrate 2100 may include a printed circuit board including a plurality of package-on-pads 2130. Each of the plurality of semiconductor chips 2200 may include an input / output pad 2201. The input / output pad 2201 may correspond to... Figure 9 The input / output pads 1101 are included. Each of the plurality of semiconductor chips 2200 may include a plurality of gate stacks 3210 and a plurality of channel structures 3220. The plurality of semiconductor chips 2200 may include the above-mentioned references. Figures 3 to 7 At least one of the described integrated circuit devices 100, 100a and 100b.

[0131] In some embodiments, the connection structure 2400 may include bonding wiring for electrically connecting input / output pads 2201 and package-on-package pads 2130 to each other. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, a plurality of semiconductor chips 2200 may be electrically connected to each other using a bonding wiring method, and may be electrically connected to a plurality of package-on-package pads 2130 of the package substrate 2100. In some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other using a connection structure including through-silicon vias (TSVs) instead of the connection structure 2400 using a bonding wiring method.

[0132] In some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be included in a package. In some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be mounted on a separate insert substrate other than the main substrate 2001, and the controller 2002 and the plurality of semiconductor chips 2200 may be connected to each other by wires formed on the insert substrate.

[0133] Figure 11 and Figure 12 This is a cross-sectional view of semiconductor packages 3003 and 4003 including integrated circuit devices according to an exemplary embodiment of the present invention.

[0134] Specifically, Figure 11 and Figure 12 It shows along Figure 10 The detailed structure of the cross section taken by line A-A' in the diagram.

[0135] Reference Figure 11 In the semiconductor package 3003, the package substrate 2100 may include a printed circuit board.

[0136] The package substrate 2100 may include a main body portion 2120 and a plurality of package pads 2130 disposed on the upper surface of the main body portion 2120 (see See Figure 10 The package includes a plurality of lower pads 2125 disposed on or exposed through the lower surface of the main body portion 2120, and a plurality of internal lines 2135 within the main body portion 2120 electrically connecting the plurality of package upper pads 2130 and the plurality of lower pads 2125 to each other. The plurality of package upper pads 2130 may be electrically connected to a plurality of connection structures 2400 (see...). Figure 10 Multiple lower pads 2125 can be connected to multiple conductive connection portions 2800. Figure 10 Multiple conductive interconnect patterns 2005 on the main substrate 2001 of the electronic system 2000 shown.

[0137] Each of the plurality of semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region comprising a plurality of peripheral lines 3110. (See reference...) Figure 7 As described, the first structure 3100 may include a peripheral circuit transistor 60TR. Figure 11 In the middle, the first structure 3100 has the same as Figure 7 The peripheral circuit region of the integrated circuit device 100b shown has the same structure, but the technical concept of the present invention is not limited thereto.

[0138] The second structure 3200 may include a common source line 3205, a gate stack 3210 on the common source line 3205, a channel structure 3220 penetrating the gate stack 3210, and a bit line 3240 electrically connected to the channel structure 3220.

[0139] Each of the plurality of semiconductor chips 2200 may include a plurality of peripheral lines 3110 electrically connected to the first structure 3100 and extending into the second structure 3200 vias 3245. The vias 3245 may be disposed outside the gate stack 3210. In other embodiments, the semiconductor package 3003 may also include vias penetrating the gate stack 3210. Each of the plurality of semiconductor chips 2200 may also include input / output pads 2201 electrically connected to the plurality of peripheral lines 3110 of the first structure 3100 (see...). Figure 10 ).

[0140] Reference Figure 12 Semiconductor package 4003 has the same characteristics as the reference. Figure 11 The semiconductor package 3003 described has a similar construction.

[0141] The semiconductor package 4003 may include a plurality of semiconductor chips 2200a. Each of the plurality of semiconductor chips 2200a may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 bonded to the first structure 4100 by means of a wafer bonding method.

[0142] The first structure 4100 may include a peripheral circuit region, which includes peripheral lines 4110 and a plurality of first junction structures 4150. (See reference...) Figure 7 As described, the first structure 4100 may include peripheral circuitry transistor 60TR. Figure 12 In the middle, the first structure 4100 has the same as Figure 7 The peripheral circuit region of the integrated circuit device 100b shown has the same structure, but the technical concept of the present invention is not limited thereto.

[0143] The second structure 4200 may include a common source line 4205, a gate stack 4210 between the common source line 4205 and the first structure 4100, and a channel structure 4220 penetrating the gate stack 4210.

[0144] Furthermore, each of the plurality of semiconductor chips 2200a may include being electrically connected to a plurality of gate electrodes 130 (see [link to semiconductor chip 130]). Figure 4 Multiple second bonding structures 4250. For example, a portion of the multiple second bonding structures 4250 may be configured to be connected to a bit line 4240 electrically connected to the channel structure 4220. Other portions of the multiple second bonding structures 4250 may be configured to be electrically connected to the gate electrode 130 via multiple contact structures CNT.

[0145] The plurality of first bonding structures 4150 of the first structure 4100 and the plurality of second bonding structures 4250 of the second structure 4200 may contact and bond with each other. The portions at which the plurality of first bonding structures 4150 and the plurality of second bonding structures 4250 bond with each other may include metal, such as copper (Cu), but are not limited thereto.

[0146] According to an exemplary embodiment of the invention, a portion of each of the plurality of channel structures 160 can be used as an alignment structure for a photolithography process in the manufacturing process of an integrated circuit device, thereby reducing alignment defects that may occur in the photolithography process.

[0147] Furthermore, according to an exemplary embodiment of the invention, a key opening 172 exposing a portion of each of the plurality of channel structures 160 is formed by sequentially performing a first etching process and a second etching process. Therefore, the sidewalls of the first upper insulating layer 170 defining the key opening 172 can have a gentle slope. Thus, the lower masking layer 211 (see [reference]) fills the key opening 172 of the first upper insulating layer 170. Figure 8H It also has sidewalls with a gentle slope, thereby removing the upper mask layer 213 coated on the lower mask layer 211 (see...). Figure 8H Coating defects in )

[0148] Although the concept of the invention has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: Substrate structure; A gate stack located on the substrate structure, wherein the gate stack includes a plurality of gate electrodes spaced apart from each other in a first direction perpendicular to the main surface of the substrate structure; A first upper insulating layer is located on the gate stack; Multiple channel structures that penetrate the gate stack and contact the substrate structure, wherein each of the multiple channel structures includes a corresponding alignment key protruding from the gate stack; The second upper insulating layer is located in the key opening of the first upper insulating layer and overlaps with the corresponding alignment key of each of the plurality of channel structures; A top support layer, which is located on the second upper insulating layer; Bit lines are located on the top support layer; as well as Multiple bit line contacts penetrate the second upper insulating layer and the top support layer, and electrically connect corresponding channel structures of the multiple channel structures to the bit lines. The sidewall defining the key opening of the first upper insulating layer includes a first stepped portion.

2. The integrated circuit device according to claim 1, wherein, The sidewall of the first upper insulating layer further includes a second step portion located between the first step portion and the upper end of the sidewall of the first upper insulating layer.

3. The integrated circuit device according to claim 1, further comprising: An insulating pattern is embedded, which overlaps in the first direction with the corresponding alignment key of each of the plurality of channel structures. The embedded insulating pattern is located between the second upper insulating layer and the top support layer.

4. The integrated circuit device according to claim 3, wherein, The embedded insulating pattern comprises polycrystalline silicon.

5. The integrated circuit device according to claim 3, wherein, The plurality of bit line contacts penetrate the embedded insulation pattern.

6. The integrated circuit device according to claim 3, wherein, The embedded insulation pattern includes: The upper surface, which contacts the top support layer; The lower surface, which contacts the second upper insulating layer; and The side surface contacts the second upper insulating layer and slopes from the lower surface of the embedded insulating pattern to the upper surface of the embedded insulating pattern.

7. The integrated circuit device according to claim 6, wherein, The upper surface of the embedded insulating pattern includes a flat surface.

8. The integrated circuit device according to claim 6, wherein, The lower surface of the embedded insulating pattern includes an uneven shape.

9. The integrated circuit device according to claim 1, in, The sidewall of the first upper insulating layer includes a first segment, a second segment, and a third segment connected to each other between the lower end and the upper end of the sidewall of the first upper insulating layer. Wherein, the angle formed by the extension direction of the first segment relative to the second direction parallel to the main surface of the substrate structure is greater than the angle formed by the extension direction of the second segment relative to the second direction, and The angle formed by the extension direction of the second segment relative to the second direction is smaller than the angle formed by the extension direction of the third segment relative to the second direction.

10. The integrated circuit device according to claim 1, further comprising: The peripheral circuit structure is located on the side of the substrate structure opposite to the gate stack.

11. An integrated circuit device, comprising: Substrate structure; A gate stack located on the substrate structure, wherein the gate stack includes a plurality of gate electrodes spaced apart from each other in a first direction perpendicular to the main surface of the substrate structure; Multiple channel structures that penetrate the gate stack and contact the substrate structure, wherein each of the multiple channel structures includes a corresponding alignment key protruding from the gate stack; A first upper insulating layer is located on the gate stack, wherein the first upper insulating layer includes a key opening that overlaps with the plurality of channel structures in the first direction; A second upper insulating layer is located in the key opening of the first upper insulating layer, wherein the second upper insulating layer overlaps with the corresponding alignment key of each of the plurality of channel structures, and wherein the second upper insulating layer includes a recessed portion on the upper side of the second upper insulating layer. An insulating pattern is embedded in the recessed portion of the second upper insulating layer; A top support layer is located on the second upper insulating layer, wherein the top support layer is located on the embedded insulating pattern; Bit lines are located on the top support layer; as well as Multiple bit line contacts that penetrate the second upper insulating layer, the embedded insulating pattern, and the top support layer, wherein a corresponding bit line contact of the multiple bit line contacts electrically connects a corresponding channel structure of the multiple channel structures to the bit line.

12. The integrated circuit device according to claim 11, wherein, The sidewall defining the key opening of the first upper insulating layer includes a first stepped portion.

13. The integrated circuit device according to claim 12, wherein, The sidewalls of the first upper insulating layer include: The first section extends at a first angle of inclination; The second segment extends from the first segment at a second inclination angle smaller than the first inclination angle; and The third section extends from the second section at a third inclination angle greater than the second inclination angle.

14. The integrated circuit device according to claim 12, wherein, The sidewall of the first upper insulating layer further includes a second step portion located between the upper end of the sidewall of the first upper insulating layer and the first step portion.

15. The integrated circuit device according to claim 11, in, The second upper insulating layer and the top support layer comprise silicon oxide, and The embedded insulating pattern includes polycrystalline silicon.

16. The integrated circuit device according to claim 15, wherein, The embedded insulation pattern includes: The upper surface contacts the top support layer and is coplanar with the upper surface of the second upper insulating layer; The lower surface, which faces the plurality of channel structures; and The side surface slopes from the lower surface of the embedded insulating pattern to the upper surface of the embedded insulating pattern.

17. The integrated circuit device according to claim 16, in, The upper surface of the embedded insulating pattern includes a flat surface, and The lower surface of the embedded insulating pattern includes an uneven shape.

18. The integrated circuit device according to claim 16, wherein, The side surface of the embedded insulating pattern is in contact with the second upper insulating layer.

19. An electronic system comprising: main substrate; An integrated circuit device located on the main substrate; as well as A controller, located on the main substrate, wherein the controller is electrically connected to the integrated circuit device. The integrated circuit device includes: Substrate structure; The peripheral circuit structure is located on the substrate structure; Input / output pads, which are electrically connected to the peripheral circuit structure; A gate stack located on the peripheral circuit structure, wherein the gate stack includes a plurality of gate electrodes spaced apart from each other in a first direction perpendicular to the main surface of the substrate structure; A plurality of channel structures extending in the first direction and penetrating the gate stack, each of the plurality of channel structures including a corresponding alignment key protruding from the gate stack; A first upper insulating layer is located on the gate stack, wherein the first upper insulating layer includes a key opening that overlaps with the plurality of channel structures in the first direction, wherein the sidewall of the key opening includes a first step portion; A second upper insulating layer is located in the key opening of the first upper insulating layer, wherein the second upper insulating layer is located on the corresponding alignment key of each of the plurality of channel structures; A top support layer, which is located on the second upper insulating layer; Bit lines, which are located on the top support layer; and Multiple bit line contacts penetrate the second upper insulating layer and the top support layer, and electrically connect corresponding channel structures of the multiple channel structures to the bit lines.

20. The electronic system according to claim 19, in, The main substrate also includes conductive interconnect patterns that electrically connect the integrated circuit device and the controller to each other. The integrated circuit device further includes: An embedded insulating pattern is disposed between the second upper insulating layer and the top support layer, wherein the embedded insulating pattern is located in a recessed portion of the second upper insulating layer; and The side surface of the embedded insulating pattern slopes from the top support layer toward the lower surface of the second upper insulating layer.

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