Semiconductor memory device

Abstract

Embodiments provide a semiconductor memory device that is easily highly integrated. The semiconductor memory device of the embodiments includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line connected to the first memory cell, a second word line connected to the second memory cell, a first transistor provided in the first semiconductor substrate and electrically connected to the first word line, and a second transistor provided in the second semiconductor substrate and electrically connected to the second word line.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-15362 (filed on February 2, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known, comprising: a first semiconductor substrate; a second semiconductor substrate; a first memory cell and a second memory cell disposed therebetween; a first word line connected to the first memory cell; a second word line connected to the second memory cell; a first transistor electrically connected to the first word line; and a second transistor electrically connected to the second word line. Summary of the Invention

[0005] The implementation provides a semiconductor memory device that is easily highly integrated.

[0006] A semiconductor memory device according to one embodiment includes: a first semiconductor substrate; a second semiconductor substrate; a first memory cell and a second memory cell disposed between the first semiconductor substrate and the second semiconductor substrate; a first word line connected to the first memory cell; a second word line connected to the second memory cell; a first transistor disposed on the first semiconductor substrate and electrically connected to the first word line; and a second transistor disposed on the second semiconductor substrate and electrically connected to the second word line. Attached Figure Description

[0007] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10 in the first embodiment.

[0008] Figure 2 This is a schematic side view showing an example of the configuration of the memory system 10.

[0009] Figure 3 This is a schematic top view representing this configuration example.

[0010] Figure 4 This is a schematic block diagram representing the structure of a memory die (MD).

[0011] Figure 5 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0012] Figure 6 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0013] Figure 7This is a schematic exploded perspective view showing an example of the configuration of a memory die (MD).

[0014] Figure 8 This is a schematic exploded perspective view showing an example of the configuration of a memory die (MD).

[0015] Figure 9 It is chip C M A schematic cross-sectional view.

[0016] Figure 10 yes Figure 9 A schematic enlarged view of part A shown in the diagram.

[0017] Figure 11 It is chip C M A schematic bottom view.

[0018] Figure 12 yes Figure 11 A schematic enlarged view of part B shown.

[0019] Figure 13 yes Figure 11 A schematic enlarged view of part C.

[0020] Figure 14 yes Figure 13 A schematic enlarged view of part D.

[0021] Figure 15 yes Figure 14 A schematic enlarged view of the portion shown as E.

[0022] Figure 16 It is chip C P A schematic cross-sectional view.

[0023] Figure 17 This is a schematic cross-sectional view showing the structure of a memory die (MD).

[0024] Figure 18 This indicates that chip C M Storage cell array layer L MCA1 L MCA2 A schematic bottom view of the structure.

[0025] Figure 19 This indicates that chip C M transistor layer L TR A schematic bottom view of the structure.

[0026] Figure 20 This indicates that chip C P A schematic top view of the structure.

[0027] Figure 21 It is chip C Mtransistor layer L TR A schematic bottom view.

[0028] Figure 22 This indicates that chip C P A schematic top view consisting of a portion of it.

[0029] Figure 23 This is a schematic cross-sectional view used to illustrate the semiconductor memory device of the second embodiment.

[0030] Figure 24 This is a schematic cross-sectional view used to illustrate the semiconductor memory device of the third embodiment.

[0031] Figure 25 This is a schematic cross-sectional view used to illustrate the semiconductor memory device of the fourth embodiment.

[0032] Figure 26 This is a schematic cross-sectional view used to illustrate other embodiments of a semiconductor memory device.

[0033] Figure 27 This is a schematic cross-sectional view used to illustrate other embodiments of a semiconductor memory device. Detailed Implementation

[0034] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Also, sometimes the same symbols are used to denote common parts in multiple embodiments, and descriptions are omitted.

[0035] Furthermore, when referred to as "semiconductor memory device" in this specification, it can refer to both memory dies and memory systems that include controller dies, such as memory chips, memory cards, and SSDs (Solid State Drives). It can also refer to devices that include a host computer, such as smartphones, tablets, and personal computers.

[0036] Furthermore, in this specification, when it is said that the first component is "electrically connected" to the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an off state, the first transistor is "electrically connected" to the third transistor.

[0037] Additionally, in this specification, when it is said that the first component is "interconnected" to the second and third components, it sometimes means that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0038] Furthermore, in this specification, when it is said that a circuit or the like "conducts" two wirings, for example, it sometimes means that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings, and that the transistor or the like is in a switched-on state.

[0039] In addition, in this specification, the specified direction parallel to the upper surface of the semiconductor substrate is called the X direction, the direction parallel to the upper surface of the semiconductor substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the semiconductor substrate is called the Z direction.

[0040] In addition, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the specified surface is referred to as the third direction. The first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to each other.

[0041] Furthermore, when using terms such as "upper" or "lower" in this specification, for example, the side of the two semiconductor substrates included in the memory die that has bonding pad electrodes may be designated as the upper semiconductor substrate, and the side that does not have bonding pad electrodes may be designated as the lower semiconductor substrate. Moreover, when referring to the configuration included in the memory die, for example, the direction along the Z direction towards the upper semiconductor substrate may be referred to as "upper," and the direction along the Z direction towards the lower semiconductor substrate may be referred to as "lower." Additionally, when a configuration is referred to as a lower surface or lower end, it refers to the surface or end point on the lower semiconductor substrate side of that configuration; when referred to as an upper surface or upper end, it may also refer to the surface or end point on the upper semiconductor substrate side of that configuration. Furthermore, a surface intersecting the X or Y direction may be referred to as a side surface, etc.

[0042] [First Implementation]

[0043] [Memory System 10]

[0044] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10 in the first embodiment.

[0045] The memory system 10 performs reading, writing, erasing and other operations on user data according to signals transmitted from a host 20. The memory system 10 is, for example, a memory chip, a memory card, an SSD, or other systems capable of storing user data. The memory system 10 includes a plurality of memory dies MD and a controller die CD. The memory dies MD store user data. The controller die CD is connected to the plurality of memory dies MD and the host 20. The controller die CD includes, for example, a processor, a RAM (Random Access Memory), and the like. The controller die CD performs processing such as conversion between logical addresses and physical addresses, bit error detection / correction, garbage collection (compression), and wear leveling.

[0046] Figure 2 is a schematic side view showing an example of the configuration of the memory system 10 according to the present embodiment. Figure 3 is a schematic top view showing the configuration example. For convenience of description, in Figure 2 and Figure 3 a part of the configuration is omitted.

[0047] as shown in Figure 2 , the memory system 10 of the present embodiment includes a mounting substrate MSB, a plurality of memory dies MD and a controller die CD. A bonding pad electrode P is provided in an end region in the Y direction on the upper surface of the mounting substrate MSB X . A region other than the end portion in the Y direction on the upper surface of the mounting substrate MSB is bonded to the lower surface of the memory die MD via an adhesive or the like. The plurality of memory dies MD are stacked on the mounting substrate MSB. A bonding pad electrode P is provided in an end region in the Y direction on the upper surface of the memory die MD X . A region other than the end portion in the Y direction on the upper surface of the memory die MD is bonded to the lower surface of another memory die MD or the controller die CD via an adhesive or the like. The controller die CD is stacked on the memory die MD. A bonding pad electrode P is provided in an end region in the Y direction on the upper surface of the controller die CD X .

[0048] as shown in Figure 3 , the mounting substrate MSB, the plurality of memory dies MD and the controller die CD each include a plurality of bonding pad electrodes P arranged along the X direction X the plurality of bonding pad electrodes P provided on the mounting substrate MSB, the plurality of memory dies MD and the controller die CD X are connected to each other via bonding wires B, respectively.

[0049] In addition, Figure 2 and Figure 3 the configuration shown is merely an example, and the specific configuration can be adjusted as appropriate. For example, in Figure 2 and Figure 3 In the example shown, a controller die CD is stacked on multiple memory dies MD. Furthermore, the memory die MDs and controller die CDs are connected via bonding wires B. Additionally, the multiple memory die MDs and controller die CDs are contained within a single package. However, the controller die CD may also be contained in a different package than the memory die MDs.

[0050] [Circuit configuration of a memory die (MD)]

[0051] Figure 4 This is a schematic block diagram showing the configuration of the memory die MD in the first embodiment. Figure 5 and Figure 6 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0052] In addition, Figure 4 The diagram shows multiple control terminals. Sometimes these multiple control terminals are represented as control terminals corresponding to a high-state active signal (positive logic signal). Other times, multiple control terminals are represented as control terminals corresponding to a low-state active signal (negative logic signal). Still other times, multiple control terminals are represented as control terminals corresponding to both a high-state active signal and a low-state active signal. Figure 4 In the diagram, the symbol for the control terminal corresponding to the active low-state signal includes an overline (overscore). In this specification, the symbol for the control terminal corresponding to the active low-state signal includes a forward slash (" / "). Furthermore, Figure 4 The description is for illustrative purposes only, and the specific form can be adjusted accordingly. For example, some or all of the high-state active signals can be set as low-state active signals, or some or all of the low-state active signals can be set as high-state active signals.

[0053] like Figure 4 As shown, the memory die MD includes a memory cell array MCA and peripheral circuitry PC. The PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. Additionally, the PC includes a cache memory CM, an address register ADR, an instruction register CMR, and a status register STR. Furthermore, the PC includes input / output control circuitry (I / O) and logic circuitry CTR.

[0054] [Circuit configuration of a memory cell array (MCA)]

[0055] like Figure 5As shown, the memory cell array (MCA) has multiple memory blocks (BLK). Each memory block (BLK) has multiple string components (SU). Each string component (SU) has multiple memory strings (MS). One end of each memory string (MS) is connected to the peripheral circuitry (PC) via a bit line (BL). The other end of each memory string (MS) is connected to the peripheral circuitry (PC) via a common source line (SL).

[0056] The memory string (MS) includes a drain-side select transistor (STD), multiple memory cells (MCs) (memory transistors), a source-side select transistor (STS), and a source-side select transistor (STSb). The STD, MCs, STS, and STSb are connected in series between the bit line BL and the source line SL. Hereinafter, the STD, STS, and STSb are sometimes simply referred to as the select transistors (STD, STS, STSb).

[0057] The memory cell MC is a field-effect transistor. The memory cell MC has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge accumulation film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge accumulation film. The memory cell MC stores one bit or more bits of data. Furthermore, the gate electrodes of multiple memory cells MC corresponding to a memory string MS are connected to word lines WL. These word lines WL are collectively connected to all memory strings MS in a memory block BLK.

[0058] The select transistors (STD, STS, STSb) are field-effect transistors. Each select transistor (STD, STS, STSb) has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the select transistors (STD, STS, STSb) are connected to select gate lines (SGD, SGS, SGSb), respectively. One drain-side select gate line SGD is commonly connected to all memory strings MS in a string assembly SU. One source-side select gate line SGS is commonly connected to all memory strings MS in a memory block BLK. One source-side select gate line SGSb is commonly connected to all memory strings MS in a memory block BLK.

[0059] [Circuit configuration of voltage generation circuit VG]

[0060] Voltage generation circuit VG ( Figure 4 For example, it includes a buck circuit and a boost circuit. The buck circuit is, for example, a regulator. The boost circuit is, for example, a charge pump circuit. The buck circuit and boost circuit are respectively connected to the power supply line. A power supply voltage V is supplied to the power supply line.CC and grounding voltage V SS The power supply line is connected, for example, to the reference. Figure 2 , Figure 3 The bonding pad electrode P described X The voltage generation circuit VG generates multiple operating voltages and simultaneously outputs them to multiple voltage supply lines. These operating voltages are supplied to the bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS, SGSb) for example, during read, write, and erase operations of the memory cell array MCA. The operating voltages are appropriately adjusted according to control signals from the sequencer SQC.

[0061] [Circuit configuration of the line decoder RD]

[0062] For example, like Figure 6 As shown, the line decoder RD has a block decoder BLKD.

[0063] The block decoder BLKD has multiple block decoding components (blkd). These multiple blkd components correspond to multiple memory blocks (BLK) in the memory cell array (MCA). Each blkd component has multiple transistors (T). BLK Multiple transistors T BLK This is configured to correspond to the multiple word lines (WL) in the memory block BLK. Transistor T BLK For example, a field-effect type NMOS (N-channel Metal-Oxide Semiconductor) transistor. Transistor T BLK The drain electrode of transistor T is connected to word line WL. BLK The source electrode is connected to wiring CG. Wiring CG is connected to multiple block decoding components (blkd) in the block decoder BLKD. For example, wiring CG can also be connected to all block decoding components (blkd) in the block decoder BLKD. Transistor T BLK The gate electrode is connected to the signal supply line BLKSEL. Multiple BLKSEL signal supply lines are provided corresponding to all block decoding components (blkd). Furthermore, the BLKSEL signal supply lines are connected to all transistors T in the block decoding component (blkd). BLK .

[0064] In read and write operations, for example, data stored in the address register ADR ( Figure 4 Address data D ADDThe row address RA contained in the code contains a signal supply line BLKSEL that is set to "H" (High) state, while the other signal supply lines BLKSEL are set to "L" (Low) state. For example, a specified drive voltage with a positive magnitude is supplied to one signal supply line BLKSEL, while ground voltage V is supplied to the other signal supply lines BLKSEL. SS Therefore, all word lines (WL) in the memory block BLK corresponding to the row address RA are connected to all wiring CGs. Additionally, all word lines (WL) in other memory blocks BLK become floating.

[0065] In addition, the line decoder RD has decoding circuitry and switching circuitry not shown.

[0066] Decoding circuitry (not shown) is, for example, based on data from the sequencer SQC (Synchronizer SQC). Figure 4 The control signals sequentially decode the row address RA, selectively setting one of the multiple signal supply lines BLKSEL to the "H" state and setting the remaining signal supply lines BLKSEL to the "L" state. Based on the output signals from the decoding circuit and the sequencer SQC, the switching circuit supplies multiple voltages output from the voltage generation circuit VG to the desired wiring CG.

[0067] [Circuit configuration of the Sensing Amplifier Module (SAM)]

[0068] Sensing Amplifier Module SAM ( Figure 4 For example, it may include multiple sense amplifiers. Each sense amplifier includes a sense transistor, data wiring, latching circuitry, and voltage transfer circuitry. The gate electrode of the sense transistor is connected to the bit line BL. The drain electrode of the sense transistor is connected to the data wiring. The sense transistor is switched on based on the voltage or current of the bit line BL. The data wiring is charged or discharged based on the on / off state of the sense transistor. The latching circuit latches "1" or "0" data based on the voltage of the data wiring. The voltage transfer circuit connects the bit line BL to either of the two voltage supply lines based on the data latched in the latching circuit.

[0069] [Circuit configuration of the cache memory CM]

[0070] Cache memory CM ( Figure 4 It has multiple latching circuits. These multiple latching circuits are connected to the latching circuits within the sense amplifier module (SAM) via a DBUS wiring connection. The data DAT contained in these multiple latching circuits is sequentially transmitted to the sense amplifier module (SAM) or the input / output control circuit (I / O).

[0071] Additionally, a decoding circuit and a switching circuit (not shown) are connected to the high-speed cache memory CM. The decoding circuit will store data in the address register ADR. Figure 4Address data D ADD The column address CA is decoded. The switching circuit, based on the output signal of the decoding circuit, enables the latch circuit corresponding to the column address CA to be connected to the bus DB.

[0072] [Circuit configuration of the sequencer SQC]

[0073] Sequencer SQC ( Figure 4 According to the instruction data D stored in the instruction register CMR CMD The line decoder RD, sense amplifier module SAM, and voltage generation circuit VG output internal control signals. Additionally, the sequencer SQC appropriately updates the state data D representing its own state. ST Output to the status register STR.

[0074] Additionally, the sequencer SQC generates a ready / busy signal and outputs it to the RY / / BY terminal. During the period when the RY / / BY terminal is in the "L" state (busy period), access to the memory die MD is essentially disabled. Conversely, during the period when the RY / / BY terminal is in the "H" state (ready period), access to the memory die MD is permitted. Furthermore, the RY / / BY terminal is, for example, referenced via... Figure 2 , Figure 3 The bonding pad electrode P described X And thus, it was achieved.

[0075] [Circuit configuration of input / output control circuit (I / O)]

[0076] The input / output control circuit (I / O) includes data signal input / output terminals DQ0-DQ7, trigger signal input / output terminals DQS and / DQS, multiple input circuits, multiple output circuits, a shift register, and a buffer circuit. The multiple input circuits, multiple output circuits, shift register, and buffer circuit are respectively connected to the supplied power supply voltage V. CCQ and grounding voltage V SS The terminals.

[0077] Data signal input / output terminals DQ0~DQ7, trigger signal input / output terminals DQS, / DQS, and the supplied power supply voltage V CCQ The terminals, for example, are referenced. Figure 2 , Figure 3 The bonding pad electrode P described XThis is achieved by the following: Data input via data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, address register ADR, or instruction register CMR based on internal control signals from the logic circuit CTR. Conversely, data output via data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit based on internal control signals from the logic circuit CTR.

[0078] [Circuit configuration of the CTR logic circuit]

[0079] The logic circuit CTR receives external control signals from the controller die CD via external control terminals / CEn, CLE, ALE, / WE, RE, and / RE, and outputs internal control signals to the input / output control circuit I / O accordingly. Furthermore, the external control terminals / CEn, CLE, ALE, / WE, RE, and / RE are connected via, for example, through a reference... Figure 2 , Figure 3 The bonding pad electrode P described X And thus, it was achieved.

[0080] [Structure of memory die MD]

[0081] Figure 7 and Figure 8 This is a schematic exploded perspective view showing an example of the configuration of a memory die (MD). Furthermore, in Figure 8 In this text, the transistors and other components in a portion of the upper surface of the semiconductor substrate 150 are omitted. Sometimes, transistors and other components are arranged in complex patterns in this region.

[0082] like Figure 7 As shown, the memory die MD has a chip C M With chip C P In chip C M The upper surface is provided with multiple bonding pad electrodes P X Additionally, such as Figure 8 As shown, chip C M It includes a semiconductor substrate 100, a plurality of transistors Tr disposed on the lower surface of the semiconductor substrate 100, a memory cell array MCA disposed below them, and a chip C. M Multiple first bonding electrodes P on the lower surface I1 Chip C P It includes a semiconductor substrate 150, a plurality of transistors Tr disposed on the upper surface of the semiconductor substrate 150, and a chip C. P Multiple second bonding electrodes P on the upper surface I2 Chip C M The memory cell array MCA and multiple transistors Tr in the memory cell array are connected via multiple first bonding electrodes P.I1 and multiple second bonding electrodes P I2 And electrically connected to chip C P The chip contains multiple transistors Tr. M and chip C P The multiple transistors Tr set in the circuit are respectively used as peripheral circuits PC ( Figure 4 It plays a part of the function.

[0083] The following is about chip C M C P Multiple first bonding electrodes P will be set. I1 or multiple second bonding electrodes P I2 The side facing up is called the front, and the side opposite the front is called the back.

[0084] Chip C M and chip C P With chip C M The front of the chip C P The electrodes are arranged in a front-facing configuration. Multiple first bonding electrodes P I1 Corresponding to multiple second bonding electrodes P I2 And it is set and configured to be able to attach to multiple second electrodes P I2 The bonding position. First bonding electrode P I1 With the second electrode P I2 As used to connect chip C M With chip C P The bonding electrodes, which adhere to and make them electrically conductive, function.

[0085] In addition, Figure 7 In the example, chip C M The corners a1, a2, a3, and a4 are respectively connected to chip C P The corners b1, b2, b3, and b4 correspond.

[0086] [Chip C] M [Structure]

[0087] Figure 9 It is chip C M A schematic cross-sectional view. Figure 10 yes Figure 9 A schematic enlarged view of part A shown in the diagram. Figure 11 It is chip C M A schematic bottom view. Figure 12 yes Figure 11 A schematic enlarged view of part B shown. Figure 13 yes Figure 11 A schematic enlarged view of part C. Figure 14 yes Figure 13 A schematic enlarged view of part D. Figure 15 yes Figure 14 A schematic enlarged view of part E shown. Furthermore, in Figure 12 In the text, a portion of the area (the first wiring area R below) has been omitted. HU1 ).

[0088] For example, like Figure 9 As shown, chip C M A transistor layer L is provided on the lower surface of the semiconductor substrate 100. TR Set in transistor layer L TR The wiring layer D0 below the wiring layer D0, the wiring layer D1 below the wiring layer D0, and the wiring layer D2 below the wiring layer D1. Additionally, chip C... M Equipped with a memory cell array layer L located below the wiring layer D2 MCA1 , set in the storage cell array layer L MCA1 The lower storage cell array layer L MCA2 and set in the storage cell array layer L MCA2 The wiring layer M0 below it. Additionally, as... Figure 8 As shown, chip C M It includes a wiring layer M1 located below wiring layer M0, a wiring layer M2 located below wiring layer M1, and a wiring layer M3 located below wiring layer M2.

[0089] For example, like Figure 11 As shown, a four-cell array region R is provided on the semiconductor substrate 100, arranged along the X and Y directions. MCA Additionally, the storage cell array region R MCA It has two memory hole regions R arranged along the X direction. MH Additionally, in the two memory hole regions R MH Two first wiring regions R are arranged along the X direction between them. HU1 and the second wiring area R located between them. HU2 Additionally, a peripheral region R is formed at the end of the semiconductor substrate 100 in the Y direction. P .

[0090] Furthermore, in the following description, it is referred to as "memory cell array region R". MCA “Memory hole area R” MH "First Wiring Area R" HU1 “Second Wiring Area R” HU2A "or surrounding area R" P "At that time, it not only includes the memory cell array layer L" MCA1 L MCA2 The area also includes chip C MOther layers included (semiconductor substrate 100, transistor layer L) TR and the corresponding areas in the wiring layers D0, D1, D2, M0, M1, M2, and chip C P The corresponding region within the included hierarchy.

[0091] [Structure of semiconductor substrate 100]

[0092] Semiconductor substrate 100 is, for example, a semiconductor substrate containing P-type silicon (Si) with P-type impurities such as boron (B). For example, like... Figure 9 As shown, an active region 100A and an insulating region 100I, such as silicon oxide (SiO2), are disposed on the front side of the semiconductor substrate 100. The active region 100A can be an N-type well region containing N-type impurities such as phosphorus (P), a P-type well region containing P-type impurities such as boron (B), or a semiconductor substrate region without N-type well regions or P-type well regions.

[0093] [Transistor layer L] TR [Structure]

[0094] For example, like Figure 9 As shown, a wiring layer GC is disposed on the lower surface of the semiconductor substrate 100, separated by an insulating layer (not shown). The wiring layer GC includes a plurality of electrodes gc facing the front side of the semiconductor substrate 100. Furthermore, each region of the semiconductor substrate 100 and the plurality of electrodes gc included in the wiring layer GC are respectively connected to a contact CS.

[0095] The active region 100A of the semiconductor substrate 100 functions as a channel region for multiple transistors Tr that constitute the peripheral circuit PC and as an electrode for multiple capacitors Cap.

[0096] The multiple electrodes gc contained in the wiring layer GC function as the gate electrodes of multiple transistors Tr that constitute the peripheral circuit PC, and as the other electrode of multiple capacitors Cap.

[0097] The contact CS extends along the Z direction and is connected at its upper end to the lower surface of the semiconductor substrate 100 or the electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection point between the contact CS and the semiconductor substrate 100. The contact CS may also comprise, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) or a metal film such as tungsten (W).

[0098] [Structure of wiring layers D0, D1, and D2]

[0099] For example, like Figure 9 As shown, the multiple wirings contained in wiring layers D0, D1, and D2 are electrically connected to the memory cell array layer L. MCA The composition of the transistor layer LTR The composition and at least one of the semiconductor substrate 100.

[0100] The wiring layers D0, D1, and D2 each contain multiple wirings d0, d1, and d2. These multiple wirings d0, d1, and d2 may, for example, comprise barrier conductive films such as titanium nitride (TiN) and tantalum nitride (TaN), or laminated films of metals such as tungsten (W), copper (Cu), and aluminum (Al).

[0101] [Storage cell array layer L] MCA1 L MCA2 memory hole area R MH [Structure in]

[0102] For example, like Figure 12 As shown, in the memory cell array layer L MCA1 L MCA2 Multiple storage blocks (BLK) are configured along the Y direction. Figure 12 In the example, it is a storage block BLK A ~Storage Block BLK H ).

[0103] Furthermore, in the following description, sometimes it will be from one side of the Y direction (e.g., Figure 12 (From the negative side of the Y direction) the first, fourth, and nth B (n B (positive integers greater than or equal to 1) and the 4nth B A storage block BLK with +1 is called a storage block BLKa. In Figure 12 In the example, storage block BLK is shown as storage block BLKa. A BLK D BLK E BLK H Additionally, in the following description, sometimes the direction from the Y side (e.g., Figure 12 The numbers starting from the negative side of the Y direction are the 2nd, 3rd, 4th, and nth. B +2 and the 4nth B A storage block BLK with +3 bytes is called a storage block BLKf. Figure 12 In the example, BLKf represents the storage block BLK. B BLK C BLK F BLK G .

[0104] Storage block BLK, for example, like Figure 14 As shown, it comprises multiple string modules SU arranged along the Y direction. An inter-block insulating layer ST, such as silicon oxide (SiO2), is disposed between two adjacent memory blocks BLK in the Y direction. Additionally, for example, like... Figure 15As shown, a silicon dioxide (SiO2) inter-string insulating layer SHE is provided between two adjacent string components SU in the Y direction.

[0105] For example, like Figure 9 As shown, the memory block BLK includes multiple conductive layers 110 arranged along the Z-direction and multiple semiconductor pillars 120 extending along the Z-direction. Additionally, for example, like... Figure 10 As shown, the memory block BLK has multiple gate insulating films 130 respectively disposed between multiple conductive layers 110 and multiple semiconductor pillars 120.

[0106] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction. The conductive layer 110 includes components corresponding to the semiconductor pillar 120. Figure 9 Multiple through-holes are provided. The inner peripheral surfaces of the multiple through-holes respectively separate the gate insulating film 130 and the outer peripheral surfaces of the semiconductor pillar 120. The conductive layer 110 may also include a stacked film of barrier conductive film such as titanium nitride (TiN) and metal film such as tungsten (W). In addition, the conductive layer 110 may also include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged along the Z direction. Figure 10 ).

[0107] Above the conductive layer 110, such as Figure 9 As shown, a conductive layer 111 is provided. The conductive layer 111 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Alternatively, an insulating layer such as silicon oxide (SiO2) may be provided between the conductive layer 111 and the conductive layer 110.

[0108] A conductive layer 112 is disposed above the conductive layer 111. The conductive layer 112 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Alternatively, the conductive layer 112 may contain a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers. Furthermore, an insulating layer such as silicon oxide (SiO2) is disposed between the conductive layer 112 and the conductive layer 111.

[0109] Conductive layer 112 serves as the source line SL ( Figure 5 ) to perform its function. Source line SL, for example, for memory cell array region R. MCA ( Figure 11 All storage blocks (BLKs) contained in the ) have common settings.

[0110] Conductive layer 111 serves as the source-side gate selection line SGSb ( Figure 5 The gate electrodes of the multiple source-side selection transistors (STSb) connected to it function. The conductive layer 111 is electrically independent for each memory block (BLK).

[0111] Additionally, one or more of the uppermost conductive layers 110 among the plurality of conductive layers 110 serve as the source-side selected gate line (SGS). Figure 5 The gate electrodes of the multiple source-side selection transistors (STS) connected to it function. The multiple conductive layers 110 are electrically independent for each memory block (BLK).

[0112] Additionally, the plurality of conductive layers 110 located below the conductive layer 110 serve as word lines WL ( Figure 5 ) and multiple storage units MC connected to it Figure 5 The gate electrode of the memory block BLK functions. The plurality of conductive layers 110 are electrically independent for each memory block BLK.

[0113] Additionally, one or more conductive layers 110 located below the conductive layer 110 serve as drain-side selected gate lines (SGD) and multiple drain-side selected transistors (STD) connected thereto. Figure 5 The gate electrode of the conductive layer 110 functions as a gate electrode. The width of the plurality of conductive layers 110 in the Y direction is smaller than that of the other conductive layers 110. Furthermore, an inter-component insulating layer (SHE) is disposed between two adjacent conductive layers 110 in the Y direction. Figure 15 Multiple conductive layers 110, which function as drain-side selected gate lines (SGD), are electrically independent for each string assembly (SU).

[0114] For example, like Figure 15 As shown, the semiconductor pillars 120 are arranged in a specified pattern along the X and Y directions. The semiconductor pillars 120 serve as a memory string (MS). Figure 5 The semiconductor pillar 120 contains multiple memory cells (MCs) and channel regions of selection transistors (STDs, STSs) that function. The semiconductor pillar 120 is, for example, a semiconductor layer such as polysilicon (Si). The semiconductor pillar 120 has, for example, a generally cylindrical shape, and an insulating layer 125 such as silicon oxide is disposed in the central portion. Figure 10 In addition, the outer peripheral surfaces of the semiconductor pillars 120 are surrounded by conductive layers 110 and face each other.

[0115] like Figure 9 As shown, the semiconductor pillar 120 has a structure disposed in the memory cell array layer L. MCA1 Semiconductor Division 120 U and set in the storage cell array layer L MCA2 Semiconductor Division 120 L .

[0116] Semiconductor Division 120 U With memory cell array layer L MCA1 Multiple conductive layers 110 disposed therein are aligned. In the semiconductor section 120... UThe upper end is provided with an impurity region containing N-type impurities such as phosphorus (P). This impurity region is connected to the conductive layer 112. Figure 9 ).

[0117] Semiconductor Division 120 L With memory cell array layer L MCA2 Multiple conductive layers 110 disposed therein are aligned. In the semiconductor section 120... L The lower end is provided with an impurity region containing N-type impurities such as phosphorus (P). This impurity region is connected to the bit line BL via contact Ch and contact Vy.

[0118] Gate insulating film 130 ( Figure 10 It has a generally cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. For example, like... Figure 10 As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133 deposited between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are, for example, insulating films such as silicon oxide (SiO2). The charge storage film 132 is, for example, a film capable of storing charge such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend along the Z-direction along the outer peripheral surface of the semiconductor pillar 120.

[0119] also, Figure 10 The diagram shows an example where the gate insulating film 130 has a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also have a floating gate, such as polysilicon containing N-type or P-type impurities.

[0120] [Storage cell array layer L] MCA2 First wiring area R HU1 [Structure in]

[0121] like Figure 13 As shown, in the first wiring area R HU1 Each of these is configured with a small area r for a corresponding storage block BLK. CC1 Additionally, in the first wiring area R HU1 The small area r of the contact connection is set up corresponding to the storage block BLKf. C4T .

[0122] In the small area r of the contact point CC1 ,like Figure 14 As shown, the ends of multiple conductive layers 110, which function as drain-side selected gate lines (SGD), are provided in the X direction. Additionally, in the contact connection small region r... CC1The device comprises a plurality of contacts CC arranged in a matrix when viewed from the Z direction. The plurality of contacts CC extend along the Z direction and are connected to the conductive layer 110 at their upper ends. The contacts CC may also comprise, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0123] Among the multiple contacts CC arranged along the X direction, the region R closest to the memory hole is... MH The contact CC is connected to the first conductive layer 110 from the bottom. Additionally, the distance from the memory hole region R... MH The second nearest contact CC is connected to the second conductive layer 110 from the bottom. Similarly, the contact point R is located at the distance from the memory hole region R. MH The a-th (where a is a positive integer greater than or equal to 1) nearest contact CC is connected to the a-th conductive layer 110 from the bottom. A portion of the plurality of contacts CC are connected to the chip C via wiring m0, etc., in wiring layer M0. M Or chip C P The drain electrode of transistor Tr in the image.

[0124] Additionally, among the multiple contacts CC, there is a storage block BLKf ( Figure 13 The corresponding contact CC is connected to the small contact connection area r corresponding to the memory block BLKf. C4T The contact C4 in the chip is electrically connected to the chip C through the contact C4. M The transistor Tr is disposed in the semiconductor substrate 100. Additionally, among the plurality of contacts CC, there is a memory block BLKa ( Figure 13 The corresponding contact CC is connected to the contact connection area r of the adjacent memory block BLKf. C4T The contact C4 in the chip is electrically connected to the chip C through the contact C4. M The transistor Tr is disposed in the semiconductor substrate 100.

[0125] In addition, for example, like Figure 14 As shown, in the first wiring area R HU1 A support structure HR is provided, which is located near the contact CC. The support structure HR extends along the Z direction and is connected to the conductive layer 112 at its upper end. The support structure HR includes, for example, an insulating layer such as silicon oxide (SiO2).

[0126] In the small area r of the contact point C4T It has two insulating layers ST arranged along the Y direction. O The two insulating layers ST O It is positioned between two inter-block insulating layers ST arranged along the Y direction. Additionally, for example, like... Figure 9 As shown, in the two insulating layers STO Multiple insulating layers 110A arranged along the Z direction and multiple contacts C4 extending along the Z direction are disposed between them.

[0127] Insulation layer ST O ( Figure 14 It extends along the X and Z directions and connects to the conductive layer 112 at its upper end. Insulating layer ST O For example, it contains silicon dioxide (SiO2).

[0128] The insulating layer 110A is a generally plate-shaped insulating layer extending along the X direction. The insulating layer 110A may also include an insulating layer such as silicon nitride (Si3N4). An insulating layer such as silicon oxide (SiO2) is disposed between the plurality of insulating layers 110A arranged along the Z direction.

[0129] Multiple contacts C4 are arranged along the X direction. Contacts C4 can also comprise laminated films of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W). For example, like... Figure 9 As shown, the outer peripheral surfaces of contact C4 are surrounded by insulating layer 110A and connected to insulating layer 110A. Furthermore, for example, like... Figure 9 As shown, contact C4 extends along the Z direction and is connected to wiring m0 in wiring layer M0 at the lower end and wiring d2 in wiring layer D2 at the upper end.

[0130] In addition, multiple conductive layers 110, which function as drain-side selected gate lines (SGD), can also be connected to the chip C. P The transistor Tr in the chip C is not the chip C. M The transistor Tr in the middle. In this case, the plurality of conductive layers 110 are connected via the contact CC and the first bonding electrode P. I1 and the second bonding electrode P I2 And electrically connected to chip C P The transistor Tr is disposed in the semiconductor substrate 150. Alternatively, in this case, the first wiring region R may be omitted. HU1 The small area r of the connection point in the middle C4T .

[0131] [Storage cell array layer L] MCA1 L MCA2 Second wiring area R HU2 [Structure in]

[0132] like Figure 12 As shown, in the second wiring area R HU2 One side in the X direction (e.g., Figure 12 The area on the negative side of the X direction has multiple contact points connecting small areas r. CC2 and multiple connection points to small areas r C4TMultiple connections connect a small area r. CC2 Set at the location corresponding to the storage block BLKa. Multiple nodes connect to a small area r. C4T Set at the location corresponding to the storage block BLKf.

[0133] In addition, such as Figure 12 As shown, in the second wiring area R HU2 The other side of the X direction (e.g., Figure 12 The area on the X-direction positive side also has multiple connection points connecting to the small area r. CC2 and multiple connection points to small areas r C4T Multiple connections connect a small area r. CC2 Set at the location corresponding to storage block BLKf. Multiple nodes connect to small regions r. C4T Set at the location corresponding to the storage block BLKa.

[0134] In the small area r of the contact point CC2 Multiple conductive layers 110 are provided as part of the structure, functioning as either word lines (WL) or source-side select gate lines (SGS). Additionally, in the contact connection small region r... CC2 It sets up multiple contacts CC arranged along the X direction. For example, like... Figure 9 As shown, the plurality of contacts CC extend along the Z direction and are connected to the conductive layer 110 at their upper ends. The contacts CC may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0135] Among the multiple contacts CC arranged along the X direction, the region R closest to the memory hole is... MH The contact CC is connected to the first conductive layer 110 counting from the top. Additionally, the distance from the memory hole region R... MH The second nearest contact CC is connected to the second conductive layer 110 from the top. Similarly, the contact point R is located at the distance from the memory hole region R. MH The b-th (b is a positive integer less than 1) nearest contact CC is connected to the b-th conductive layer 110 from the top.

[0136] In addition, for example, like Figure 8 and Figure 12 As shown, a portion of the plurality of contacts CC are connected via wiring m0 extending along the Y direction to the contact connection region r corresponding to the memory block BLK adjacent to the memory block BLK. C4T The contact C4 in the chip is electrically connected to the chip C through the contact C4. M The transistor Tr is disposed in the semiconductor substrate 100. Additionally, a portion of the plurality of contacts CC are respectively connected via the first bonding electrode P. I1 and the second bonding electrode P I2And electrically connected to chip C P The transistor Tr is disposed in the semiconductor substrate 150.

[0137] [Structure of wiring layers M0, M1, M2, and M3]

[0138] like Figure 8 As shown, the wiring layers M0, M1, M2, and M3 contain multiple wirings that are electrically connected to the memory cell array layer L, for example. MCA1 L MCA2 The composition of the transistor layer L TR The composition and chip C in P At least one of the components.

[0139] Wiring layers M0, M1, and M2 each contain multiple wirings m0, m1, and m2. These multiple wirings m0, m1, and m2 may, for example, comprise stacked films of barrier conductive films such as titanium nitride (TiN) and tantalum nitride (TaN), or metal films such as tungsten (W) and copper (Cu). Furthermore, a portion of the multiple wirings m0 serves as a bit line BL (…). Figure 5 ) to perform its function. For example, like Figure 15 As shown, the bit lines BL are arranged along the X direction and extend along the Y direction. Furthermore, each of the multiple bit lines BL is connected to a semiconductor pillar 120 contained in each string assembly SU.

[0140] For example, like Figure 8 As shown, wiring layer M3 includes multiple first bonding electrodes P I1 The plurality of first bonding electrodes P I1 For example, it can also include stacked films containing barrier conductive films such as titanium nitride (TiN) and tantalum nitride (TaN) and metal films such as copper (Cu).

[0141] [Chip C] P [Structure]

[0142] Figure 16 It is chip C P A schematic cross-sectional view. Chip C P For example, a transistor layer L is provided on the upper surface of the semiconductor substrate 150. TR ′、Set in transistor layer L TR The wiring layer M7 above the ′, the wiring layer M6 above the wiring layer M7, the wiring layer M5 above the wiring layer M6, and the wiring layer M4 above the wiring layer M5.

[0143] The semiconductor substrate 150 is, for example, a semiconductor substrate containing P-type silicon (Si) containing P-type impurities such as boron (B). An active region 150A and an insulating region 150I, such as silicon oxide (SiO2), are disposed on the front side of the semiconductor substrate 150. The active region 150A can be an N-type well region containing N-type impurities such as phosphorus (P), a P-type well region containing P-type impurities such as boron (B), or a semiconductor substrate region without N-type and P-type well regions.

[0144] [Transistor layer L] TR [Structure of ′]

[0145] For example, like Figure 16 As shown, a wiring layer GC′ is disposed on the upper surface of the semiconductor substrate 150 through an insulating layer (not shown). The wiring layer GC′ includes a plurality of electrodes gc′ facing the front side of the semiconductor substrate 150. In addition, each region of the semiconductor substrate 150 and the plurality of electrodes gc′ contained in the wiring layer GC′ are respectively connected to a contact CS′.

[0146] The active region 150A of the semiconductor substrate 150 functions as a channel region for multiple transistors Tr that constitute the peripheral circuit PC and as an electrode for multiple capacitors.

[0147] The multiple electrodes gc′ contained in the wiring layer GC′ function as the gate electrodes of multiple transistors Tr that constitute the peripheral circuit PC, and as the other electrode of multiple capacitors.

[0148] The contact CS′ extends along the Z direction and is connected at its lower end to the upper surface of the semiconductor substrate 150 or the electrode gc′. An impurity region containing N-type or P-type impurities is formed at the connection point between the contact CS′ and the semiconductor substrate 150. The contact CS′ may, for example, comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) or a metal film such as tungsten (W).

[0149] [Structure of wiring layers M7, M6, and M5]

[0150] Multiple wirings contained in wiring layers M7, M6, and M5 are electrically connected to transistor layer L. TR The composition of the semiconductor substrate 150 is at least one of the components in the semiconductor substrate 150.

[0151] Wiring layers M7, M6, and M5 each contain multiple wirings m7, m6, and m5. These multiple wirings m7, m6, and m5 may, for example, comprise barrier conductive films such as titanium nitride (TiN) and tantalum nitride (TaN), or laminated films of metals such as tungsten (W), copper (Cu), and aluminum (Al).

[0152] Wiring layer M4 contains multiple second bonding electrodes P I2 The plurality of second bonding electrodes PI2 For example, it can also include stacked films containing barrier conductive films such as titanium nitride (TiN) and tantalum nitride (TaN) and metal films such as copper (Cu).

[0153] [The configuration of the transistors Tr that make up the peripheral circuit PC]

[0154] Next, refer to Figures 17-22 The configuration of each transistor Tr that constitutes the peripheral circuit PC is explained. Figure 17 This is a schematic cross-sectional view showing the structure of a memory die (MD). Figure 18 This indicates that chip C M Storage cell array layer L MCA1 L MCA2 A schematic bottom view of the structure. Figure 19 This indicates that chip C M transistor layer L TR A schematic bottom view of the structure. Figure 20 This indicates that chip C P A schematic top view of the structure. Figure 21 It is chip C M transistor layer L TR A schematic bottom view. Figure 22 This indicates that chip C P A schematic top view consisting of a portion of it. Figure 21 and Figure 22 Indicates when viewed from the Z direction and Figure 12 The components are set at overlapping positions in the composition.

[0155] also, Figure 18 The middle picture shows Figure 11 The memory cell array region R (details omitted) MCA Region R in BLT In region R BLT For example, it is set to use the bit line BL ( Figure 9 ) and chip C P The transistor Tr is connected in the configuration. Additionally, in Figures 17-22 In, with Figure 12 Similarly, the first wiring area R is omitted. HU1 .

[0156] [Chip C] M [Configuration of transistor Tr in the system]

[0157] As mentioned above, in chip C M transistor layer L TR Multiple transistors (Tr) are configured. For example... Figure 18 and Figure 19 As shown, among the plurality of transistors Tr, one is located in the second wiring region R. HU2The transistor Tr is used as a reference. Figure 6 The described block decoder BLKD is a part of (transistor T) BLK ) performs its function. In other areas, for example, capacitors (Cap) can also be installed. Figure 17 ) to replace transistor Tr. For example, like Figure 9 As shown, capacitor Cap can also, like transistor Tr, have an active region 100A, an electrode gc, and a gate insulating film disposed between them. Furthermore, the thickness (thickness in the Z direction) of the electrode gc and the gate insulating film constituting capacitor Cap can be the same as the thickness (thickness in the Z direction) of the electrode gc and the gate insulating film constituting transistor Tr. Additionally, capacitor Cap can be connected to the supplied power supply voltage V. CC Or power supply voltage V CCQ bonding pad electrode P X With the supplied ground voltage V SS bonding pad electrode P X between.

[0158] exist Figure 21 In the example, in the second wiring area R HU2 Corresponding to the multiple memory blocks BLK arranged along the Y direction, multiple transistor columns are arranged along the Y direction. Each transistor column has multiple transistors Tr arranged along the X direction.

[0159] In addition, Figure 21 In the example, in connection with the storage block BLK A The small area r of the contact CC is connected. CC2 (Refer to Figure 12 Multiple transistors (Tr) are positioned at the corresponding location. Additionally, in relation to BLK... B Corresponding to and including the storage block BLK A The small area r of the contact C4 C4T (Refer to Figure 12 Multiple transistors Tr are positioned at the corresponding location. The drain electrodes of these multiple transistors Tr are electrically connected to the memory block BLK via contact C4. A The word line WL, etc. Additionally, the drain electrodes of the plurality of transistors Tr are respectively connected via the second wiring region R. HU2 The contacts C4, wiring m0, m1, m2, and the first bonding electrode P are included. I1 and the second bonding electrode P I2 The electrical connection is used as wiring CG ( Figure 6 Any one of the wirings m7, m6, and m5 that performs the function.

[0160] Similarly, in Figure 21In the example, in the small region r of the node connection containing the node CC connected to any memory block BLK. CC2 Multiple transistors Tr are positioned at the corresponding locations. Additionally, a small connection region r is located in the memory block BLK adjacent to this memory block BLK and containing the contact C4 connected to this memory block BLK. C4T Multiple transistors Tr are positioned at corresponding locations. The drain electrodes of these transistors Tr are electrically connected to word lines WL, etc., in the corresponding memory block BLK via contact C4. Furthermore, the drain electrodes of these transistors Tr are connected via the second wiring region R. HU2 The contacts C4, wiring m0, m1, m2, and the first bonding electrode P are included. I1 and the second bonding electrode P I2 The electrical connection is used as wiring CG ( Figure 6 Any one of the wirings m7, m6, and m5 that performs the function.

[0161] In addition, Figure 21 In the example, it will be related to transistor T BLK The width of the corresponding active region 100A in the X direction is represented as width X. TAM The width in the Y direction is represented as Y. TAM Additionally, in Figure 21 In the example, the distance between two adjacent active regions 100A in the X direction will be represented as distance X. TIM The distance between two adjacent active regions 100A in the Y direction is represented as distance Y. TIM .

[0162] [Chip C] P [Configuration of transistor Tr in the system]

[0163] As mentioned above, in chip C P Multiple transistors Tr are disposed on the front side of the semiconductor substrate 150. For example... Figure 18 and Figure 20 As shown, among the plurality of transistors Tr, one is located in the second wiring region R. HU2 The transistor Tr is used as a reference. Figure 6 The described block decoder BLKD is a part of (transistor T) BLK It functions. Additionally, it is located in the memory hole area R. MH The transistor Tr is used as the sense amplifier module SAM or the high-speed cache memory CM. Figure 4 It plays a part of the function.

[0164] exist Figure 22 In the example, in the second wiring area R HU2Corresponding to the multiple memory blocks BLK arranged along the Y direction, multiple transistor columns are arranged along the Y direction. Each transistor column has multiple transistors Tr arranged along the X direction.

[0165] In addition, Figure 22 In the example, in connection with the storage block BLK A The small area r of the contact CC is connected. CC2 (Refer to Figure 12 Multiple transistors (Tr) are positioned at the corresponding location. Additionally, in relation to BLK... B Corresponding to and including the storage block BLK A The small area r of the contact C4 C4T (Refer to Figure 12 Multiple transistors Tr are disposed at the corresponding positions. These multiple transistors Tr are respectively connected via the first bonding electrode P. I1 and the second bonding electrode P I2 And electrically connected to the storage block BLK A The character line WL, etc.

[0166] Similarly, in Figure 22 In the example, in the small region r of the node connection containing the node CC connected to any memory block BLK. CC2 Multiple transistors Tr are positioned at the corresponding locations. Additionally, a small connection region r is located in the memory block BLK adjacent to this memory block BLK and containing the contact C4 connected to this memory block BLK. C4T Multiple transistors Tr are positioned at corresponding locations. These multiple transistors Tr are respectively connected via the first bonding electrode P. I1 and the second bonding electrode P I2 The word lines WL, etc., are electrically connected to the corresponding memory block BLK.

[0167] In addition, Figure 22 In the example, it will be related to transistor T BLK The width of the corresponding active region 100A in the X direction is represented as width X. TAP The width in the Y direction is represented as Y. TAP Additionally, in Figure 22 In the example, the distance between two adjacent active regions 100A in the X direction will be represented as distance X. TIP The distance between two adjacent active regions 100A in the Y direction is represented as distance Y. TIP .

[0168] exist Figure 21 and Figure 22 In the example, the width X TAP Less than width X TAM Additionally, the distance from XTIP Less than distance X TIM Additionally, the width Y TAP With width Y TAM They are equal. Additionally, the distance from Y... TIP With distance Y TIM Equal. Additionally, for example, a transistor T is disposed on the front side of the semiconductor substrate 100. BLK The width of the entire region in the X direction can also be greater than that of the transistor T set on the front side of the semiconductor substrate 150. BLK The width of the entire region in the X direction is large. In this case, for example, chip C P The included transistor T BLK All are set in the second wiring area R HU2 Within the range, and can also chip C P The included transistor T BLK Set in the second wiring area R HU2 Wiring area R 1 HU1 and memory hole area R MH Part of it.

[0169] [Effects of the first embodiment]

[0170] As described above, the multiple conductive layers 110 are electrically connected to the multiple transistors T. BLK Additionally, transistor T BLK It is provided corresponding to the conductive layer 110. That is, transistor T BLK The number of conductive layers 110 is the same as the number of conductive layers 110. Here, in the case of advancing high integration in the Z direction of the semiconductor memory device, the number of conductive layers 110 stacked along the Z direction increases. In this case, transistor T... BLK The number of conductive layers also increases accordingly with the number of conductive layers 110. Here, if we consider the relationship with transistor T... BLK The wiring layout of the circuit connection, then transistor T BLK The circuit from the second wiring area R HU2 Extending the configuration along the X direction helps reduce the wiring area, and is therefore preferred. However, if transistor T BLK If the circuit area increases in the X direction, it becomes difficult to highly integrate semiconductor memory devices in the X direction, which may hinder high integration.

[0171] Therefore, in this embodiment, chip C is used. P The transistor Tr and the chip C M In the transistor Tr, both are used as transistor T. BLK Based on this configuration, transistor T can be... BLKThe circuitry is preferably partitioned and configured in the Z direction to realize a semiconductor memory device that is easily highly integrated in the X direction.

[0172] Additionally, for reasons related to the manufacturing process, sometimes chip C... M The transistor Tr in the chip operates faster than the chip C. P The transistor Tr in the middle is slow. Here, transistor T... BLK For example, with input / output control circuits (I / O) Figure 4 Compared to transistors like T, the necessity for high-speed operation is lower. Therefore, when used as a transistor T... BLK In the case of using chip C, it is believed that even M The transistor Tr and the chip C P The transistor Tr in the semiconductor memory device has a relatively small impact on the operating speed. Therefore, in this embodiment, the impact on the operating speed can be suppressed, and a high degree of integration of the semiconductor memory device can be achieved.

[0173] Additionally, for reasons related to the manufacturing process, sometimes chip C... M The transistor Tr in the chip has a higher degree of integration than the C chip. P The transistor Tr in the chip is difficult to handle. Therefore, in this embodiment, the chip C is constructed using... M transistor T in BLK The width X in the X direction of the active region 100A TAM ( Figure 21 ) compared to the components of chip C P transistor T in BLK The width X in the X direction of the active region 150A TAP ( Figure 22 Therefore, in this embodiment, yield reduction can be suppressed, and a high degree of integration of semiconductor memory devices can be achieved.

[0174] [Second Implementation]

[0175] Next, refer to Figure 23 The semiconductor memory device of the second embodiment will be described. Figure 23 This is a schematic cross-sectional view used to illustrate the semiconductor memory device of the second embodiment.

[0176] For example, like Figure 17 As shown, the memory die MD of the first embodiment includes a chip C containing a memory cell array MCA. M and bonded to chip C M chip C P In addition, the peripheral circuit PC is mainly composed of chip C. P The memory cell array (MCA) contains transistors Tr, and only a few transistors T are used within the Tr of the memory cell array.BLK A part of it. On the other hand, for example, like Figure 23 As shown, the memory die MD2 in the second embodiment includes a chip C containing a memory cell array MCA. M2 and bonded to chip C M2 chip C P2 .

[0177] Chip C M2 Basically related to chip C M The same configuration applies. However, chip C... M2 A semiconductor substrate 200 is used instead of the semiconductor substrate 100. The semiconductor substrate 200 is constructed in essentially the same way as the semiconductor substrate 100. However, among the plurality of transistors Tr disposed on the front side of the semiconductor substrate 200, memory via regions R are disposed in... MH The transistor Tr is used as the sense amplifier module SAM or the high-speed cache memory CM. Figure 4 It plays a part of the function.

[0178] Chip C P2 Basically related to chip C P The same configuration applies. However, chip C... P2 A semiconductor substrate 250 is used instead of the semiconductor substrate 150. The semiconductor substrate 250 is constructed in essentially the same way as the semiconductor substrate 150. However, in chip C... P2 The second wiring region R on the front side of the semiconductor substrate 250 HU2 The capacitor Cap is located in the area outside of the specified area.

[0179] [Third Implementation]

[0180] Next, refer to Figure 24 The semiconductor memory device of the third embodiment will be described. Figure 24 This is a schematic cross-sectional view used to illustrate the semiconductor memory device of the third embodiment.

[0181] For example, like Figure 17 As shown, the memory die MD of the first embodiment includes a chip C containing a memory cell array MCA. M In the chip C M The transistor Tr is configured. Similarly, for example, like a reference... Figure 23 As described, the memory die MD2 of the second embodiment includes a chip C containing a memory cell array MCA. M2 In the chip C M2 The transistor Tr is configured. On the other hand, for example, like... Figure 24 As shown, the memory die MD3 of the third embodiment includes a chip C containing a memory cell array MCA.M3 Adhesive to chip C M3 Chip C on the front (bottom surface) P2 and bonded to chip C M3 Chip C on the back (top surface) P3 .

[0182] Chip C M3 Basically related to chip C M The same configuration applies. However, chip C... M3 It does not have a semiconductor substrate 100 and a transistor layer L TR Additionally, in chip C... M3 Multiple third bonding electrodes P are provided on the back (upper surface). I3 The plurality of third bonding electrodes P I3 Basically with multiple first-adhesion electrodes P I1 It is constructed in the same way.

[0183] Chip C P3 Basically related to chip C P The same configuration applies. However, in chip C... P3 Multiple fourth bonding electrodes P are provided on the front (lower surface) I4 To replace multiple second bonding electrodes P I2 The plurality of fourth bonding electrodes P I4 Basically with multiple second-bonded electrodes P I2 The same configuration is used. However, multiple fourth bonding electrodes P I4 Connected to multiple third bonding electrodes P I3 Instead of multiple first bonding electrodes P I1 Additionally, although the illustration is omitted, it is present in chip C. P3 The back (top surface) is provided with bonding pad electrodes P X .

[0184] [Fourth Implementation]

[0185] Next, refer to Figure 25 The semiconductor memory device of the fourth embodiment will be described. Figure 25 This is a schematic cross-sectional view used to illustrate the semiconductor memory device of the fourth embodiment.

[0186] For example, like Figure 17 As shown, the memory die MD of the first embodiment includes a chip C M and chip C P Additionally, the chip C M With storage cell array layer L MCA1 L MCA2 and transistor layer L TR Additionally, transistor layer LTR In the Z direction, with the memory cell array layer L MCA1 L MCA2 Separation. On the other hand, for example, like Figure 25 As shown, the memory die MD4 of the fourth embodiment includes a chip C containing a memory cell array MCA. M4 and bonded to chip C M4 chip C P4 .

[0187] Chip C M4 Basically related to chip C M The same configuration applies. However, chip C... M4 A semiconductor substrate 400 is used instead of the semiconductor substrate 100. Additionally, chip C... M4 L lacks transistor layer TR The semiconductor substrate 400 is constructed in essentially the same way as the semiconductor substrate 100. However, a memory cell array region R is disposed on the semiconductor substrate 400. MCA ′ to replace the memory cell array region R MCA Storage cell array region R MCA 'Has memory hole area R MH ′ and memory hole region R MH Two adjacent wiring areas R HU Additionally, in the X direction, relative to the memory cell array region R... MCA The transistor region R is located adjacent to ′. TR .

[0188] Storage cell array layer L MCA1 L MCA2 memory hole area R MH The structure of ′ is basically the same as that of chip C M Storage cell array layer L MCA1 L MCA2 memory hole area R MH The structure is the same. However, in the memory hole region R MH No conductive layer 112 is provided. Additionally, the memory hole region R... MH The upper end of the semiconductor pillar 120 is connected to the semiconductor substrate 400 and is not the conductive layer 112.

[0189] Wiring area R HU Basically related to the first wiring area R HU1 and the second wiring area R HU2 It is constructed in the same way. However, the wiring area R HU No connection point is set in the small area r. C4T .

[0190] In transistor region RTR In this process, multiple transistors Tr are disposed on the front (lower surface) of the semiconductor substrate 400. These multiple transistors Tr constitute part of the block decoder BLKD. The multiple transistors Tr are connected to the memory cell array layer L via contacts CC, etc. MCA1 The composition of.

[0191] Chip C P4 Basically related to chip C P The same configuration applies. However, chip C... P4 A semiconductor substrate 450 is used instead of the semiconductor substrate 150. The semiconductor substrate 450 is constructed in essentially the same way as the semiconductor substrate 150. However, among the multiple transistors Tr disposed on the front side (upper surface) of the semiconductor substrate 450, the wiring region R is disposed... HU ′ and transistor region R TR The transistors Tr form part of the block decoder BLKD. The plurality of transistors Tr are connected via contact CC and the first bonding electrode P. I1 , second bonding electrode P I2 Equal to connected to the storage cell array layer L MCA1 L MCA2 The composition of.

[0192] [Other Implementation Methods]

[0193] The semiconductor memory devices of the first to fourth embodiments have been described above. However, these semiconductor memory devices are merely examples, and the specific configuration, operation, etc., can be adjusted appropriately.

[0194] For example, like Figure 17 , Figure 23 and Figure 24 As shown, in the semiconductor memory devices of the first to third embodiments, in the memory cell array region R MCA Two memory hole regions R are set along the X direction. MH In the two memory hole regions R MH The second wiring area R is set between them. HU2 On the other hand, for example, Figure 26 The example chip C M ′ and chip C P Basically the same as the chip C in the first embodiment M and chip C P The same configuration applies. However, in chip C... M In the memory cell array region R, MCA Two second wiring areas R are set up along the X direction. HU2 In the two second wiring areas R HU2The memory hole area R is set in between. MH Additionally, it is set in chip C. M ′ and chip C P Among the multiple transistors Tr on the front side of ′, the second wiring region R is located. HU2 The transistor Tr functions as part of the block decoder BLKD.

[0195] This configuration can also be applied to the semiconductor memory device of the second or third embodiment.

[0196] In addition, for example, like Figure 24 As shown, in the semiconductor memory device of the third embodiment, chip C M3 It lacks a semiconductor substrate. Furthermore, in chip C... M3 Multiple third bonding electrodes P are provided on the back (upper surface). I3 On the other hand, for example Figure 27 The example chip C M3 It features a semiconductor substrate 500. Additionally, chip C... M3 The array comprises multiple through-electrodes TSVs penetrating a semiconductor substrate 500 and electrodes E disposed at the upper ends of the multiple through-electrodes TSVs. In this configuration, the memory cell array layer L... MCA1 L MCA2 A portion of the conductive layer 110 is connected via contact CC, contact C4, and the third bonding electrode P. I3 Through electrode TSV, electrode E and fourth bonding electrode P I4 And connected to chip C P3 The block decoder BLKD contains transistors Tr.

[0197] Additionally, in the above example, the memory cell array layer L will be set. MCA1 L MCA2 Which of the multiple conductive layers 110 is connected to chip C? M C M2 C M4 C M (Hereinafter referred to as "Chip C") M The transistor Tr (etc.) connects which conductive layer 110 to chip C. P C P2 C P3 C P4 C P (Hereinafter referred to as "Chip C") P The transistor Tr (etc.) can be adjusted appropriately.

[0198] For example, the storage cell array layer L can also be used. MCA1 L MCA2One of the multiple conductive layers 110 is connected to chip C. M The transistor Tr, etc., connects another plurality of conductive layers 110 contained therein to the chip C. P Transistor Tr, etc.

[0199] Additionally, for example, connected to chip C P The number of conductive layers 110 in transistor Tr can also be greater than those connected to chip C. M The transistor Tr has a large number of conductive layers 110. As mentioned above, for reasons related to the manufacturing process, sometimes chip C... M The transistor Tr in the chip has a higher degree of integration than the C chip. P The transistor Tr in the chip is difficult to handle. Therefore, sometimes it is done by connecting it to the chip C. P The number of conductive layers 110 in transistor Tr is greater than the number of layers connected to chip C. M The transistor Tr has a large number of conductive layers 110, which can reduce the circuit area.

[0200] Alternatively, for example, the even-numbered or odd-numbered conductive layer 110 counting from the top can be connected to the chip C. P Transistors Tr, which are either the odd-numbered or even-numbered conductive layers 110 counting from the top, are connected to chip C. M Transistor Tr, etc. Alternatively, for example, it could be from one side in the Y direction (e.g., the negative side of the Y direction, see reference). Figure 12 The conductive layer 110 contained in the even-numbered or odd-numbered memory block BLK is connected to the chip C. P The transistor Tr, which is the odd-numbered or even-numbered memory block BLK counted from one side in the Y direction, has a conductive layer 110 connected to the chip C. M The transistor Tr, etc. Alternatively, for example, a reference could also be used. Figure 12 The conductive layer 110 contained in one of the memory blocks BLKa and BLKf described above is connected to the chip C. P The transistor Tr connects another conductive layer 110 contained in the memory blocks BLKa and BLKf to the chip C. M Transistor Tr, etc.

[0201] [other]

[0202] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as set forth in the claims and their equivalents.

[0203] [Explanation of Symbols]

[0204] MC: Storage Unit

[0205] MCA: Memory Cell Array

[0206] WL: Word Line

[0207] Tr: Transistor

[0208] PC: Peripheral Circuits

[0209] P X Bonding pad electrode

[0210] P I1 First bonding electrode

[0211] P I2 : Second bonding electrode

[0212] 100, 150: Semiconductor substrate

[0213] 110: Conductive layer

[0214] 120: Semiconductor column

[0215] 130: Gate insulating film.

Claims

1. A semiconductor memory device comprising: First semiconductor substrate; Second semiconductor substrate; The first memory cell and the second memory cell are disposed between the first semiconductor substrate and the second semiconductor substrate; The first word line is connected to the first storage unit; The second word line is connected to the second storage unit; The first transistor is disposed on the first semiconductor substrate and electrically connected to the first word line; and The second transistor is disposed on the second semiconductor substrate and electrically connected to the second word line; and The first semiconductor substrate has a first active region that functions as part of the first transistor. The second semiconductor substrate has a second active region that functions as part of the second transistor. When the extension direction of the first character line is set as the first direction... The width of the first active region in the first direction is set as the first width. When the width of the second active region in the first direction is set to the second width, The first width is greater than the second width.

2. The semiconductor memory device according to claim 1, comprising a first chip and a second chip, The first chip has the following features: The first semiconductor substrate; The first storage unit and the second storage unit; The first digit line; The second digit line; The first transistor; and The first bonding electrode is electrically connected to the second word line; The second chip has the following features: The second semiconductor substrate; The second transistor; and The second bonding electrode is electrically connected to the second transistor; and The second chip is attached to the first chip via the first bonding electrode and the second bonding electrode.

3. The semiconductor memory device according to claim 1, wherein... It contains a first chip, a second chip, and a third chip. The first chip has the following features: The first storage unit and the second storage unit; The first digit line; The second digit line; The first bonding electrode is electrically connected to the first word line; and The second bonding electrode is electrically connected to the second word line; The second chip has the following features: The first semiconductor substrate; The first transistor; and The third bonding electrode is electrically connected to the first transistor; The third chip has the following features: The second semiconductor substrate; The second transistor; and The fourth bonding electrode is electrically connected to the second transistor; The second chip is attached to the first chip via the first bonding electrode and the third bonding electrode, and The third chip is attached to the first chip via the second and fourth bonding electrodes.

4. A semiconductor memory device comprising: First semiconductor substrate; Second semiconductor substrate; The first memory cell and the second memory cell are disposed between the first semiconductor substrate and the second semiconductor substrate; The first word line is connected to the first storage unit; The second word line is connected to the second storage unit; The first transistor is disposed on the first semiconductor substrate and electrically connected to the first word line; The second transistor is disposed on the second semiconductor substrate and electrically connected to the second word line; and The first contact extends along a second direction intersecting the front surface of the first semiconductor substrate; and The first character line and the second character line are arranged along the second direction. One end of the first contact in the second direction is closer to the first semiconductor substrate than both the first word line and the second word line. The other end of the first contact in the second direction is closer to the second semiconductor substrate than the first word line and the second word line, and The first word line is electrically connected to the first transistor via the first contact.

Images