An enhanced GaN power device and a method for manufacturing the same

Abstract

The application discloses an enhanced GaN power device and a preparation method thereof, and relates to the field of enhanced GaN preparation. The device comprises, from bottom to top, a substrate, a Buffer layer, an AlGaN layer, a P-GaN layer, an LPCVD-SiN layer and a PECVD-SiN layer. The LPCVD-SiN layer and the PECVD-SiN layer of the device are etched with a gate recess in the gate region of the device. A gate electrode is arranged in the gate recess. The LPCVD-SiN layer, the PECVD-SiN layer, the P-GaN layer and the AlGaN layer of the device are etched with a source recess in the source region of the device. A source electrode is arranged in the source recess. The LPCVD-SiN layer, the PECVD-SiN layer, the P-GaN layer and the AlGaN layer of the device are etched with a drain recess in the drain region of the device. A drain electrode is arranged in the drain recess. The application can realize a preparation method with simple process and low cost.

Description

Technical Field

[0001] This invention relates to the field of enhanced GaN fabrication, and in particular to an enhanced GaN power device and its fabrication method. Background Technology

[0002] In recent years, gallium nitride (GaN), a new wide-bandgap semiconductor material, has experienced rapid development due to its superior properties, including a large bandgap, high breakdown electric field, high electron saturation drift velocity, and strong radiation resistance. Theoretically, the critical breakdown electric field EC and breakdown voltage BV of GaN-based power switching devices of the same size and structure will exceed those of Si by more than 10 times. Particularly noteworthy is AlGaN / GaN, based on GaN material, which possesses a unique heterostructure and a high-performance two-dimensional electron gas 2DEG (area density ~10¹³ / cm², high mobility ~1500cm² / Vs⁻¹). Normally off (enhancement-mode) high electron mobility transistors (HEMTs) based on this structure are particularly suitable for fabricating planar power switching devices, enabling lower on-resistance (Ron) and higher switching speed (ton) (its on-resistance Ron will be more than 100 times lower than that of similar Si devices, and the switching frequency can reach 1MHz, exceeding that of similar Si devices by 1000 times).

[0003] For enhancement-mode GaN HEMT devices, the main current method involves growing a P-type GaN layer on the AlGaN surface. The P-GaN depletes the two-dimensional electron gas beneath the gate, achieving normally-off characteristics. During device fabrication, since the P-GaN depletes the two-dimensional electron gas across the entire device region, our goal is to deplete only the electron gas beneath the gate, leaving other areas untouched. This necessitates area etching of the epitaxially grown P-GaN, preserving only the P-GaN layer in the gate region and removing the rest. This is a major challenge in enhancement-mode device fabrication. Because the underlying AlGaN layer must be preserved and undamaged after P-GaN etching, a high-selectivity, low-damage etching process is required. Such etching is difficult to achieve, and even with expensive etching equipment, obtaining ideal etching results is challenging. Summary of the Invention

[0004] To address the above problems, the purpose of this invention is to provide an enhanced GaN power device and its fabrication method.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] An enhanced GaN power device includes, from bottom to top, a substrate, a buffer layer, an AlGaN layer, a P-GaN layer, an LPCVD-SiN layer, and a PECVD-SiN layer;

[0007] Gate grooves are etched in the LPCVD-SiN layer and PECVD-SiN layer in the gate region of the enhancement-mode GaN power device; a gate electrode is disposed in the gate groove;

[0008] Source trenches are etched in the LPCVD-SiN layer, PECVD-SiN layer, P-GaN layer, and AlGaN layer in the source region of the enhancement-type GaN power device; source electrodes are disposed in the source trenches;

[0009] Drain grooves are etched in the LPCVD-SiN layer, PECVD-SiN layer, P-GaN layer and AlGaN layer in the drain region of the enhancement-type GaN power device; a drain electrode is disposed in the drain groove.

[0010] A method for fabricating an enhanced GaN power device, the method comprising:

[0011] A buffer layer, an AlGaN layer, and a P-GaN layer are epitaxially grown sequentially from bottom to top on a Si substrate.

[0012] A SiN layer is grown on the surface of the P-GaN layer using LPCVD to obtain the LPCVD-SiN layer.

[0013] The LPCVD-SiN layer in the gate region is etched to obtain the P-GaN layer in the gate region;

[0014] A SiN layer is grown on the LPCVD-SiN layer and the gate region P-GaN layer by PECVD to obtain the PECVD-SiN layer.

[0015] ICP etching is performed in the source and drain regions to obtain source and drain trenches.

[0016] An ohmic metal layer is sputtered onto the PECVD-SiN layer, the source trench, and the drain trench;

[0017] The ohmic metal layer on the PECVD-SiN layer is etched to obtain the source electrode and the drain electrode.

[0018] The PECVD-SiN layer in the gate region is etched away to obtain a gate trench.

[0019] Gate metal is deposited in the gate groove to obtain the gate electrode.

[0020] Optionally, the step of performing ICP etching in the source and drain regions to obtain source and drain trenches further includes:

[0021] Ion implantation was performed on the buffer layer, AlGaN layer, and P-GaN layer at the outer edges of the source and drain regions, respectively, to obtain insulating regions.

[0022] Optionally, the thickness of the LPCVD-SiN layer is 1nm-1000nm.

[0023] Optionally, the etching of the LPCVD-SiN layer in the gate region to obtain the P-GaN layer in the gate region specifically includes:

[0024] Using an ICP etching machine, the LPCVD-SiN layer in the gate region is etched to obtain the exposed P-GaN layer;

[0025] The exposed P-GaN layer is subjected to high-temperature annealing to obtain the gate region P-GaN layer.

[0026] Optionally, the high-temperature annealing temperature is greater than 600°C; the gas used for high-temperature annealing is nitrogen or oxygen.

[0027] Optionally, the temperature at which a SiN layer is grown on the surface of the P-GaN layer of the epitaxial wafer using LPCVD is greater than 700°C.

[0028] Optionally, the equipment used for epitaxially growing the buffer layer, AlGaN layer and P-GaN layer sequentially from bottom to top on the Si substrate is an MOCVD equipment.

[0029] Optionally, the step of growing a SiN layer on the surface of the P-GaN layer of the epitaxial wafer using LPCVD to obtain the LPCVD-SiN layer further includes:

[0030] The surface of the P-GaN layer of the epitaxial wafer is cleaned.

[0031] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0032] The enhancement-mode GaN power device provided by the present invention includes: a substrate, a buffer layer, an AlGaN layer, a P-GaN layer, an LPCVD-SiN layer, and a PECVD-SiN layer, arranged sequentially from bottom to top; gate trenches are etched in the LPCVD-SiN layer and the PECVD-SiN layer in the gate region of the enhancement-mode GaN power device; a gate electrode is disposed in the gate trench; source trenches are etched in the LPCVD-SiN layer, the PECVD-SiN layer, the P-GaN layer, and the AlGaN layer in the source region of the enhancement-mode GaN power device; a source electrode is disposed in the source trench; and drain trenches are etched in the LPCVD-SiN layer, the PECVD-SiN layer, the P-GaN layer, and the AlGaN layer in the drain region of the enhancement-mode GaN power device; a drain electrode is disposed in the drain trench. This invention utilizes the passivation effect of P-GaN during the LPCVD SiN thin film growth process. First, the entire P-GaN layer is passivated. Then, the LPCVD SiN is etched away in the gate region, followed by high-temperature annealing to activate the P-GaN beneath the gate. This achieves a system where only the P-GaN beneath the gate depletes the two-dimensional electron gas, resulting in enhancement-mode device functionality. This fabrication method is low-cost and simple. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the enhanced GaN power device structure provided by the present invention;

[0035] Figure 2 A flowchart of the method for fabricating enhanced GaN power devices provided by the present invention;

[0036] Figure 3 This is a schematic diagram of the structure obtained in step S1 of the method for fabricating the enhanced GaN power device provided by the present invention;

[0037] Figure 4 This is a schematic diagram of the structure obtained in step S2 of the method for fabricating the enhanced GaN power device provided by the present invention;

[0038] Figure 5 This is a schematic diagram of the structure obtained in step S3 of the method for fabricating the enhanced GaN power device provided by the present invention;

[0039] Figure 6This is a schematic diagram of the structure obtained in step S4 of the method for fabricating the enhanced GaN power device provided by the present invention;

[0040] Figure 7 A schematic diagram of the structure obtained after ion implantation in the method for fabricating enhanced GaN power devices provided by this invention;

[0041] Figure 8 This is a schematic diagram of the structure obtained in step S5 of the method for fabricating the enhanced GaN power device provided by the present invention;

[0042] Figure 9 This is a schematic diagram of the structure obtained in step S7 of the method for fabricating the enhanced GaN power device provided by the present invention;

[0043] Figure 10 This is a schematic diagram of the structure obtained in step S9 of the method for fabricating the enhanced GaN power device provided by the present invention.

[0044] Symbol explanation:

[0045] Source electrode—1, Gate electrode—2, Drain electrode—3, LPCVD-SiN layer—4, PECVD-SiN layer—5, Insulating region—6, P-GaN layer—7, AlGaN layer—8, Buffer layer—9. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] The purpose of this invention is to provide an enhanced GaN power device and its fabrication method, which can achieve a simple and low-cost fabrication method.

[0048] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] like Figure 1 As shown, the present invention provides an enhanced GaN power device comprising, from bottom to top, a substrate, a buffer layer 9, an AlGaN layer 8, a P-GaN layer 7, an LPCVD-SiN layer 4, and a PECVD-SiN layer 5.

[0050] Gate grooves are etched in the LPCVD-SiN layer 4 and PECVD-SiN layer 5 in the gate region of the enhancement-type GaN power device; a gate electrode 2 is disposed in the gate groove.

[0051] Source grooves are etched in the LPCVD-SiN layer 4, PECVD-SiN layer 5, P-GaN layer 7 and AlGaN layer 8 in the source region of the enhancement-type GaN power device; a source electrode 1 is disposed in the source groove.

[0052] Drain grooves are etched in the LPCVD-SiN layer 4, PECVD-SiN layer 5, P-GaN layer 7 and AlGaN layer 8 in the drain region of the enhancement-type GaN power device; a drain electrode 3 is disposed in the drain groove.

[0053] In addition, the enhancement-mode GaN power device also includes an insulating region 6; the insulating region 6 is disposed on the outer edge of the source electrode 1 and the outer edge of the drain electrode 3, the buffer layer 9, the AlGaN layer 8 and the P-GaN layer 7.

[0054] like Figure 2 As shown, the present invention provides a method for fabricating an enhanced GaN power device, the method comprising:

[0055] Step S1: Using Si as a substrate, a buffer layer, an AlGaN layer, and a P-GaN layer are epitaxially grown sequentially from bottom to top. Specifically, the equipment used for this sequential epitaxial growth of the buffer layer, AlGaN layer, and P-GaN layer on the Si substrate is an MOCVD (Multi-Layer Chemical Vapor Deposition) system. Due to the depletion effect of P-GaN, there is almost no two-dimensional electron gas below the AlGaN at this point. Figure 3 As shown.

[0056] Step S2: A SiN layer is grown on the surface of the P-GaN layer using LPCVD to obtain an LPCVD-SiN layer. Specifically, the thickness of the LPCVD-SiN layer is 1 nm-1000 nm. The temperature for growing a SiN layer on the surface of the epitaxial P-GaN layer using LPCVD is greater than 700℃. Because LPCVD SiN growth is a high-temperature process, typically above 700℃, at this temperature, the Mg dopant in P-GaN combines with H ions to form Mg-H bonds, passivating the P-GaN and turning it into an insulating layer. This prevents the P-GaN from providing holes and thus from depleting the two-dimensional electron gas. The two-dimensional electron gas then reforms. Figure 4 As shown.

[0057] Step S3: Etch the LPCVD-SiN layer in the gate region to obtain the P-GaN layer in the gate region. Specifically, using an ICP etching machine, the LPCVD-SiN in the gate region is etched away, exposing the underlying P-GaN to obtain the P-GaN layer in the gate region, and then high-temperature annealing is performed. Further, annealing at 800℃ with N2 is used. After annealing, the P-GaN under the gate is activated and can provide holes, thus depleting the two-dimensional electron gas below (the two-dimensional electron gas in other regions still exists). Figure 5 As shown.

[0058] Step S4: A SiN layer is grown on the LPCVD-SiN layer and the gate region P-GaN layer using PECVD to obtain the PECVD-SiN layer. Specifically, the PECVD-SiN layer serves as a protective layer for the subsequent ohmic metal etching process. Figure 6 As shown.

[0059] Step S5: Perform ICP etching in the source and drain regions to obtain source and drain trenches. Specifically, both the source and drain trenches are ohmic contact trenches. Figure 8 As shown.

[0060] Step S6: Sputter an ohmic metal layer onto the PECVD-SiN layer, source trench, and drain trench.

[0061] Step S7: Etch the ohmic metal layer on the PECVD-SiN layer to obtain the source and drain electrodes. Specifically, after sputtering the entire ohmic metal layer, ohmic metal etching is performed, retaining only the metal in the source and drain regions to form ohmic contacts. The source and drain ohmic metals can be used as the source and drain electrodes, respectively, or subsequent processes can be added to thicken the metal on top of the source and drain ohmic metals to serve as the source and drain electrodes. Figure 9 As shown.

[0062] Step S8: Etch away the PECVD-SiN layer in the gate region to obtain a gate trench. Specifically, etch away the passivation layer in the gate region.

[0063] S8 specifically includes:

[0064] Using an ICP etching machine, the LPCVD-SiN layer in the gate region is etched to obtain the exposed P-GaN layer.

[0065] The exposed P-GaN layer is subjected to high-temperature annealing to obtain the gate region P-GaN layer. Specifically, the high-temperature annealing temperature is greater than 600°C; the gas used for high-temperature annealing is nitrogen or oxygen.

[0066] Step S9: Deposit gate metal in the gate trench to obtain the gate electrode. For example... Figure 10As shown.

[0067] S2 includes the following:

[0068] The surface of the P-GaN layer of the epitaxial wafer is cleaned.

[0069] In addition, prior to S5, it also included:

[0070] Ion implantation was performed on the buffer layer, AlGaN layer, and P-GaN layer at the outer edges of the source and drain regions, respectively, to obtain insulating regions. Specifically, these insulating regions are used to isolate the active regions. Figure 7 As shown.

[0071] This invention proposes a novel method for fabricating enhancement-mode devices. This method eliminates the need for complex P-GaN etching. Instead, it leverages the passivation effect of P-GaN during LPCVD SiN thin film growth. First, the entire P-GaN layer is passivated. Then, the LPCVD SiN in the gate region is etched away, followed by high-temperature annealing to activate the P-GaN beneath the gate. This achieves enhancement-mode functionality by depleting the two-dimensional electron gas with only the P-GaN beneath the gate. This method is low-cost and simple, providing a new means of realizing enhancement-mode devices.

[0072] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0073] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An enhanced GaN power device, characterized in that, include: From bottom to top, the substrate, buffer layer, AlGaN layer, P-GaN layer, LPCVD-SiN layer and PECVD-SiN layer are arranged sequentially. A SiN layer is grown on the surface of the P-GaN layer using LPCVD to obtain an LPCVD-SiN layer; the temperature at which the SiN layer is grown on the surface of the epitaxial P-GaN layer using LPCVD is greater than 700℃. Using an ICP etching machine, the LPCVD-SiN layer in the gate region is etched to obtain the exposed P-GaN layer; The exposed P-GaN layer is subjected to high-temperature annealing to obtain the gate region P-GaN layer; The high-temperature annealing temperature is greater than 600°C; the gas used for high-temperature annealing is nitrogen or oxygen. Gate grooves are etched in the LPCVD-SiN layer and PECVD-SiN layer in the gate region of the enhancement-mode GaN power device; a gate electrode is disposed in the gate groove; Source trenches are etched in the LPCVD-SiN layer, PECVD-SiN layer, P-GaN layer, and AlGaN layer in the source region of the enhancement-type GaN power device; source electrodes are disposed in the source trenches; Drain grooves are etched in the LPCVD-SiN layer, PECVD-SiN layer, P-GaN layer and AlGaN layer in the drain region of the enhancement-type GaN power device; a drain electrode is disposed in the drain groove.

2. The enhanced GaN power device according to claim 1, characterized in that, The enhanced GaN power device further includes an insulating region; the insulating region is disposed on a buffer layer, an AlGaN layer, and a P-GaN layer at the outer edges of the source electrode and the outer edges of the drain electrode.

3. A method for fabricating an enhanced GaN power device, characterized in that, The method is applied to the enhanced GaN power device according to any one of claims 1-2, and the method includes: A buffer layer, an AlGaN layer, and a P-GaN layer are epitaxially grown sequentially from bottom to top on a Si substrate. A SiN layer is grown on the surface of the P-GaN layer using LPCVD to obtain the LPCVD-SiN layer. The LPCVD-SiN layer in the gate region is etched to obtain the P-GaN layer in the gate region; A SiN layer is grown on the LPCVD-SiN layer and the gate region P-GaN layer by PECVD to obtain the PECVD-SiN layer. ICP etching is performed in the source and drain regions to obtain source and drain trenches. An ohmic metal layer is sputtered onto the PECVD-SiN layer, the source trench, and the drain trench; The ohmic metal layer on the PECVD-SiN layer is etched to obtain the source electrode and the drain electrode. The PECVD-SiN layer in the gate region is etched away to obtain a gate trench. Gate metal is deposited in the gate groove to obtain the gate electrode.

4. The method for fabricating an enhanced GaN power device according to claim 3, characterized in that, The step of performing ICP etching in the source and drain regions to obtain source and drain trenches includes, prior to: Ion implantation was performed on the buffer layer, AlGaN layer, and P-GaN layer at the outer edges of the source and drain regions, respectively, to obtain insulating regions.

5. The method for fabricating an enhanced GaN power device according to claim 3, characterized in that, The thickness of the LPCVD-SiN layer is 1nm-1000nm.

6. The method for fabricating an enhanced GaN power device according to claim 3, characterized in that, The LPCVD-SiN layer in the etched gate region is used to obtain the P-GaN layer in the gate region, specifically including: Using an ICP etching machine, the LPCVD-SiN layer in the gate region is etched to obtain the exposed P-GaN layer; The exposed P-GaN layer is subjected to high-temperature annealing to obtain the gate region P-GaN layer.

7. The method for fabricating an enhanced GaN power device according to claim 6, characterized in that, The high-temperature annealing temperature is greater than 600°C; the gas used for high-temperature annealing is nitrogen or oxygen.

8. The method for fabricating an enhanced GaN power device according to claim 3, characterized in that, The temperature at which a SiN layer is grown on the surface of the P-GaN layer of the epitaxial wafer using LPCVD is greater than 700℃.

9. The method for fabricating an enhanced GaN power device according to claim 3, characterized in that, The equipment used for epitaxially growing the buffer layer, AlGaN layer and P-GaN layer sequentially from bottom to top on the Si substrate is an MOCVD equipment.

10. The method for fabricating an enhanced GaN power device according to claim 3, characterized in that, The process of growing a SiN layer on the surface of an epitaxial P-GaN layer using LPCVD to obtain an LPCVD-SiN layer includes, prior to: The surface of the P-GaN layer of the epitaxial wafer is cleaned.

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