Solar cell and method of manufacturing the same, battery module, and photovoltaic system

Abstract

The application is suitable for the technical field of solar cells, and provides a solar cell sheet, a preparation method, a cell assembly and a photovoltaic system. The solar cell sheet comprises a substrate, a first passivation film layer, a first bonding layer, a first main grid line and a first auxiliary grid line. The substrate comprises a first surface and a second surface opposite to each other, the first passivation film layer is arranged on the first surface in a laminated mode, and the first bonding layer is arranged on a preset region of the first passivation film layer in a laminated mode. The first main grid line is arranged on the first bonding layer and embedded into the first bonding layer. The first auxiliary grid line is electrically connected with the first main grid line and embedded into the substrate through the first passivation film layer to be in electrical contact with the substrate. In this way, the first main grid line is embedded into the first bonding layer to form a relatively close contact, so that the first main grid line has a higher pull-off force, and meanwhile, the first main grid line does not directly contact the substrate or the contact depth is relatively shallow, so that the recombination loss of the first main grid line is relatively small.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to a solar cell wafer, its preparation method, a battery module, and a photovoltaic system. Background Technology

[0002] The existing method for metallizing crystalline silicon solar cells involves printing silver paste after the cell is coated. During the sintering process, the silver paste burns through the silicon nitride film, forming silver-silicon contacts on the underside of the metallized grid lines, creating conductive channels. The sub-grid lines collect the current from the silicon and channel it to the main grid. The main grid current then flows out to the external circuit through solder ribbons attached to the main grid.

[0003] The function of the metallized sub-gate line is to collect current from silicon and channel it to the main gate. As the PN junction diffusion depth becomes shallower, the depth to which the sub-gate metal is embedded in silicon must also become shallower to avoid burning through the PN junction. The main function of the main gate line is to collect the current from the sub-gate line and lead it out to the external circuit via solder ribbon. Therefore, from the perspective of current collection alone, the main gate silver paste does not need to burn through the silicon nitride to reach the silicon interface, in order to ensure minimal recombination losses at the silver-silicon interface.

[0004] However, in related technologies, because the main gate line needs to be soldered with solder strips, good solderability is required. To achieve good solderability, the metal and silicon of the main gate need to have a large contact area, and the silver embedded in the silicon also needs to be sufficiently deep. Thus, a larger silver-silicon contact area and a deeper embedding depth lead to an increase in recombination losses. Summary of the Invention

[0005] This invention provides a solar cell and its preparation method, a battery module, and a photovoltaic system, aiming to solve the technical problem of low efficiency in existing solar cells due to increased convergence loss caused by the large contact area and embedding depth of the metal and silicon in the main grid.

[0006] The present invention is implemented as follows: the solar cell of the present invention includes:

[0007] A substrate, the substrate comprising a first surface and a second surface facing away from each other;

[0008] A first passivation film layer is stacked on the first surface;

[0009] A first bonding layer is stacked on a predetermined area of ​​the first passivation film layer;

[0010] The first main gate line is disposed on and embedded in the first bonding layer; and

[0011] The first sub-gate line is electrically connected to the first main gate line and passes through the first passivation film layer to be embedded in the substrate and in electrical contact with the substrate.

[0012] Furthermore, the first bonding layer includes a silicon oxide layer.

[0013] Furthermore, the thickness of the first bonding layer is 0.3um-5um.

[0014] Furthermore, the width of the first main gate line is less than or equal to the width of the first bonding layer.

[0015] Furthermore, the first main gate line does not pass through the first bonding layer; or

[0016] The first main gate line passes through the first bonding layer and is embedded in the first passivation film layer without passing through the first passivation film layer.

[0017] Furthermore, the solar cell also includes a second passivation film layer, a second bonding layer, a second sub-grid line, and a second main grid line. The second passivation film layer is stacked on the second surface, the second bonding layer is stacked on a predetermined area of ​​the second reflective film layer, the second main grid line is disposed on the second bonding layer and embedded in the second bonding layer, and the first sub-grid line is electrically connected to the second main grid line and passes through the second passivation film layer to be embedded in the substrate and in electrical contact with the substrate.

[0018] Furthermore, the second bonding layer includes a silicon oxide layer.

[0019] Furthermore, the thickness of the second bonding layer is 0.3um-5um.

[0020] The present invention also provides a method for preparing a solar cell, the method comprising:

[0021] A substrate is provided, the substrate including a first surface and a second surface opposite to each other;

[0022] A first passivation film is prepared on the first surface;

[0023] A first bonding layer is prepared on a predetermined region of the first passivation film layer;

[0024] A first main gate line is fabricated on the first bonding layer and embedded within the first bonding layer;

[0025] A first sub-gate line is formed on the first passivation film layer, passing through the first passivation film layer and embedded in the substrate and electrically connected to the substrate. The first sub-gate line is electrically connected to the first main gate line.

[0026] Furthermore, after the step of preparing the first bonding layer on the predetermined region of the first passivation film, the preparation method further includes:

[0027] The substrate having the first passivation film layer and the first bonding layer is dried.

[0028] Furthermore, the drying temperature for drying the substrate is 200-500℃, and the drying time is 5-30 minutes.

[0029] Furthermore, the preparation method further includes:

[0030] A second passivation film is prepared on the second surface;

[0031] A second bonding layer is prepared on a predetermined region of the second passivation film layer;

[0032] A second main gate line is fabricated on the second bonding layer and embedded within the second bonding layer;

[0033] A second sub-gate line is formed on the second passivation film layer, passing through the second passivation film layer and embedded in the substrate and electrically connected to the substrate. The second sub-gate line is electrically connected to the second main gate line.

[0034] Further, the first bonding layer is a silicon oxide layer, and the step of preparing the first bonding layer on a predetermined area of ​​the first passivation film layer includes:

[0035] The first bonding layer is prepared in a predetermined area of ​​the first passivation film using a slurry containing silicon oxide.

[0036] Furthermore, the slurry is prepared by mixing, stirring, and grinding silicon oxide, lead oxide, tellurium oxide, copper oxide, and an organic carrier;

[0037] The fumed silica comprises 5%-85% by weight, the lead oxide comprises 0.2%-10% by weight, the tellurium oxide comprises 0.2%-10% by weight, the copper oxide comprises 0.2%-10% by weight, and the organic carrier comprises 0.2%-10% by weight.

[0038] Furthermore, the organic carrier is prepared by mixing and stirring resin and solvent.

[0039] Furthermore, the organic carrier is mixed with resin and solvent at a stirring temperature of 60℃-90℃ and a stirring time of 10min-300min.

[0040] The present invention also provides a battery assembly comprising a plurality of solar cells as described in any of the preceding claims.

[0041] The present invention also provides a photovoltaic system comprising the above-described battery module.

[0042] The beneficial effects achieved by the present invention are as follows: a first bonding layer is provided on the first passivation film layer, and the first main grid line is disposed on the first bonding layer and embedded in the first bonding layer to form a relatively tight contact, so that a high pull-out force can be formed between the first main grid line, the substrate, and the first passivation film layer, thereby giving the first main grid line good welding performance. At the same time, the first main grid line and the substrate do not directly contact each other or the contact depth is shallow, which can reduce the recombination loss of the first main grid line and improve the efficiency of the solar cell. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the photovoltaic system provided by the present invention;

[0044] Figure 2 This is a schematic diagram of the battery assembly provided by the present invention;

[0045] Figure 3 This is a three-dimensional structural diagram of the solar cell provided by the present invention;

[0046] Figure 4 This is a cross-sectional schematic diagram of the solar cell provided by the present invention;

[0047] Figure 5 This is another cross-sectional schematic diagram of the solar cell provided by the present invention;

[0048] Figure 6 This is another cross-sectional schematic diagram of the solar cell provided by the present invention;

[0049] Figure 7 This is another cross-sectional schematic diagram of the solar cell provided by the present invention;

[0050] Figure 8 This is another cross-sectional schematic diagram of the solar cell provided by the present invention;

[0051] Figure 9 This is another cross-sectional schematic diagram of the solar cell provided by the present invention;

[0052] Figure 10 This is a schematic flowchart of the method for preparing solar cells provided by the present invention;

[0053] Figure 11 This is a schematic diagram of the fabrication process of the solar cell provided by the present invention;

[0054] Figure 12 This is another schematic diagram of the process for preparing solar cells provided by the present invention;

[0055] Figure 13 This is another schematic diagram of the process for preparing a solar cell provided by the present invention;

[0056] Figure 14 This is another schematic diagram of the preparation process of the solar cell provided by the present invention.

[0057] Explanation of key component symbols:

[0058] Photovoltaic system 1000, battery module 200, solar cell 100, substrate 10, first surface 11, second surface 12, first passivation film layer 20, first bonding layer 30, first main grid line 40, first sub-grid line 50, second passivation film layer 60, second bonding layer 70, second main grid line 80, second sub-grid line 90. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the invention, and should not be construed as limiting the invention. Furthermore, it should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0060] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0061] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0062] In related technologies, since the main gate line needs to be soldered with solder strips, it needs to have good solderability. In order to have good solderability, the metal and silicon of the main gate need to have a large contact area, and the silver embedded in the silicon also needs to be deep enough. Thus, a large silver-silicon contact area and embedding depth will lead to an increase in recombination loss.

[0063] In this invention, a first bonding layer 30 is stacked on a predetermined area of ​​the first passivation film layer 20, and a first main gate line 40 is disposed on and embedded in the first bonding layer 30. This allows a high pull-out force to be formed between the first main gate line 40, the substrate 10, and the first passivation film layer 20, thereby giving the first main gate line 40 good welding performance. At the same time, the first main gate line 40 does not directly contact the substrate 10 or the contact depth is shallow, reducing the recombination loss of the first main gate line 40. This solves the technical problem in the prior art where a large number of silver-silicon contact surfaces and embedding depths lead to increased recombination losses.

[0064] Example 1

[0065] Please see Figure 1 and Figure 2 The photovoltaic system 1000 in this embodiment of the invention includes the battery module 200 in this embodiment of the invention, and the battery module 200 in this embodiment of the invention includes a plurality of solar cells 100 in this embodiment of the invention.

[0066] Please see Figure 3 In the embodiment of the present invention, the solar cell 100 includes a substrate 10, a first passivation film layer 20, a first bonding layer 30, a first main grid line 40, and a first sub-grid line 50.

[0067] The substrate 10 includes a first surface 11 and a second surface 12 facing away from each other. A first passivation film layer 20 is stacked on the first surface 11, and a first bonding layer 30 is stacked on a predetermined area of ​​the first passivation film layer 20. A first main gate line 40 is disposed on the first bonding layer 30 and embedded in the first bonding layer 30. A first sub-gate line 50 is electrically connected to the first main gate line 40 and passes through the first passivation film layer 20 and is embedded in the substrate 10, making electrical contact with the substrate 10.

[0068] In the solar cell 100, the battery module 200 and the photovoltaic system 1000 of the present invention, a first passivation film layer 20 is provided on the first surface 11 of the substrate 10 of the solar cell 100, a first bonding layer 30 is stacked on a predetermined area of ​​the first passivation film layer 20, a first main grid line 40 is disposed on the first bonding layer 30 and embedded in the first bonding layer 30, and a first sub-grid line 50 is electrically connected to the first main grid line 40 and passes through the first passivation film layer 20 and is embedded in the substrate 10 and makes electrical contact with the substrate 10. Thus, a first bonding layer 30 is provided on the first passivation film layer 20, and the first main grid line 40 is disposed on the first bonding layer 30 and embedded in the first bonding layer 30 to form a relatively tight contact. This allows a high pull-out force to be formed between the first main grid line 40, the substrate 10, and the first passivation film layer 20, thereby giving the first main grid line 40 good welding performance. At the same time, the first main grid line 40 and the substrate 10 do not directly contact each other or the contact depth is shallow. This can reduce the recombination loss of the first main grid line 40 and improve the efficiency of the solar cell 100.

[0069] Specifically, in the embodiments of the present invention, multiple solar cells 100 in the battery assembly 200 can be connected in series to form a battery string, thereby realizing the series current collection and output. For example, the battery cells can be connected in series by setting solder strips (busbars, interconnecting strips), conductive backplates, etc.

[0070] It is understood that in such embodiments, the battery module 200 may further include a metal frame, a backsheet, photovoltaic glass, and an encapsulating film. The encapsulating film may be filled between the front and back of the solar cell 100, the photovoltaic glass, adjacent cells, etc., and as a filler, it may be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulating film may be an EVA film or a POE film, and the specific choice can be made according to the actual situation, without limitation.

[0071] Photovoltaic glass can be applied to the encapsulating film on the front side of the solar cell 100. The photovoltaic glass can be ultra-clear glass, which has high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%. It can protect the solar cell 100 while minimizing impact on its efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and the solar cell 100 together, providing sealing, insulation, waterproofing, and moisture protection for the solar cell 100.

[0072] The backsheet can be attached to the adhesive film on the back of the solar cell 100. The backsheet provides protection and support for the solar cell 100, and has reliable insulation, water resistance, and aging resistance. Multiple options are available for the backsheet, typically tempered glass, acrylic glass, aluminum alloy TPT composite adhesive film, etc., and the specific choice depends on the specific circumstances and is not limited here. The backsheet, solar cell 100, adhesive film, and photovoltaic glass can be mounted on a metal frame. The metal frame serves as the main external support structure for the entire battery module 200, providing stable support and installation for the battery module 200. For example, the battery module 200 can be installed at the desired location using the metal frame.

[0073] Furthermore, in this embodiment, the photovoltaic system 1000 can be applied in photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants. It can also be applied to equipment or devices that utilize solar energy for power generation, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system 1000 are not limited to these; that is, the photovoltaic system 1000 can be applied in all fields that require solar energy for power generation. Taking a photovoltaic power generation system network as an example, the photovoltaic system 1000 may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple battery modules 200. For example, multiple battery modules 200 can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0074] More specifically, in embodiments of the present invention, the solar cell 100 may be a PERC solar cell (emitter and back passivated solar cell), and the substrate 10 of the solar cell 100 may be a silicon wafer, such as a monocrystalline silicon wafer or a polycrystalline silicon wafer. The substrate 10 may be a P-type silicon wafer or an N-type silicon wafer. The P-type silicon wafer may be obtained by phosphorus diffusion on a P-type substrate to form an N-type diffusion layer, while the N-type silicon wafer may be obtained by boron diffusion on an N-type substrate to form a P-type diffusion layer. That is to say, in the present invention, the substrate 10 includes a substrate layer and a diffusion layer, the two of which have opposite polarities. "Opposite polarities" can be understood as one being P-type and the other being N-type. For example, if the substrate layer is a P-type substrate layer, then the diffusion layer is an N-type diffusion layer.

[0075] Furthermore, in embodiments of the present invention, the first surface 11 and the second surface 12 are respectively the front and back surfaces of the substrate 10. That is, when the first surface 11 is the front surface of the substrate 10, the second surface 12 is the back surface of the substrate 10, and when the first surface 11 is the back surface of the substrate 10, the second surface 12 is the front surface of the substrate 10. Figure 4In the embodiments described, the first surface 11 is taken as the front side of the substrate 10 as an example, that is to say, in Figure 4 In the embodiment shown, the first passivation film layer 20 and the first bonding layer 30 are both disposed on the front side of the substrate 10. The first passivation film layer 20 can be a silicon nitride film layer with a thickness of 50nm-90nm. The first passivation film layer 20 can achieve the passivation function of the front side of the substrate 10, and at the same time, it can reduce the reflection of light to improve the efficiency of the solar cell 100.

[0076] In an embodiment of the present invention, when the first surface 11 is the front side of the substrate 10, the first main grid line 40 and the first sub-grid line 50 form the front electrode of the solar cell 100, and when the first surface 11 is the back side of the substrate 10, the first main grid line 40 and the first sub-grid line 50 form the back electrode of the solar cell 100.

[0077] The number of first main grid lines 40 and first sub-grid lines 50 can be multiple. Multiple first sub-grid lines 50 can be connected to each first main grid line 40. The first sub-grid lines 50 are used to collect the current generated by the solar cell 100. Multiple first sub-grid lines 50 collect the current and channel it into the first main grid line 40. It is understood that multiple first sub-grid lines 50 can be connected to each first main grid line 40, and the corresponding first sub-grid lines 50 can respectively converge the current to their corresponding first main grid line 40. Multiple first main grid lines 40 can be welded together with a conductive busbar (not shown in the figure) to achieve the convergence of current on multiple first main grid lines 40 for current extraction.

[0078] In embodiments of the present invention, the first main gate line 40 can be formed by printing main gate silver paste on the first bonding layer 30 and then sintering, and the first sub-gate line 50 can be formed by printing sub-gate silver paste on the first passivation film layer 20 and then sintering. It is understood that the first main gate line 40 and the second sub-gate line 90 can be formed separately or simultaneously. For example, in some cases, the main gate silver paste can be printed on the first bonding layer 30 first, and then sintered to form the first main gate line 40, and then the sub-gate silver paste can be printed and sintered to form the first sub-gate line 50. In another case, the main gate silver paste and the sub-gate silver paste can be printed simultaneously and then sintered together to form the first main gate line 40 and the first sub-gate line 50. The specific formation method is not limited here.

[0079] Furthermore, it should be noted that in this document, the "preset region of the first passivation film layer 20" refers to the region on the first passivation film layer 20 corresponding to the first main gate line 40. The size of the preset region can be the same as or slightly larger than the size of the first main gate line 40; no specific limitation is imposed here. It is understood that in the embodiments of the present invention, the number of "preset regions" corresponds to the number of first main gate lines 40, and each preset region can correspond to one first main gate line 40. Of course, it is understood that in some embodiments, one preset region can correspond to multiple first main gate lines 40, or some of the first main gate lines 40 can correspond to a preset region and a first bonding layer 30, while some of the first main gate lines 40 do not have a first bonding layer 30 below them but directly pass through the first passivation film layer 20 and are embedded into the substrate 10; specific limitations are imposed here.

[0080] Furthermore, in some embodiments, the first bonding layer 30 may be a silicon oxide layer.

[0081] In this way, the silicon oxide layer can ensure that the first main gate line 40 has high bonding strength while preventing direct contact or shallow contact between the first main gate line 40 and the substrate 10, thereby reducing the recombination loss of the first main gate line 40. At the same time, the good insulation properties of the silicon oxide layer can also prevent leakage.

[0082] Further, please refer to Figure 4 In some embodiments, the end of the first sub-gate line 50 that is electrically connected to the first main gate line 40 is also embedded in the first bonding layer 30.

[0083] In this way, the connection point between the first sub-gate line 50 and the first main gate line 40 is embedded in the first bonding layer 30. The first bonding layer 30 can effectively protect the connection point to prevent the first main gate line 40 and the first sub-gate line 50 from breaking when subjected to external impact.

[0084] Of course, please see Figure 5 In other embodiments, one end of the first sub-gate line 50 connected to the first main gate line 40 may also be attached to the surface of the first bonding layer 30 and electrically connected to the portion of the first main gate line 40 exposed from the first bonding layer 30. That is, the first sub-gate line 50 may be electrically connected to the portion of the first main gate line 40 exposed from the first bonding layer 30 after passing upward around the first bonding layer 30. No specific limitations are imposed here.

[0085] In some embodiments, the thickness of the first bonding layer 30 may be 0.3um-5um.

[0086] In this way, on the one hand, it can ensure that the first main gate line 40 has a good embedding depth, thus giving it good pull-out force. Simultaneously, it can prevent the first bonding layer 30 from being too thin, which would cause the first main gate line 40 to directly burn through and embed into the substrate 10 during sintering, leading to increased composite. Furthermore, it can prevent the first bonding layer 30 from being too thin, resulting in poor uniformity during fabrication, with some areas having insufficient thickness or even lacking the first bonding layer 30 altogether. On the other hand, it can also prevent the first bonding layer 30 from being too thick, which would cause a large path slope when connecting the first sub-gate line 50 to the first main gate line 40, potentially leading to breakage. Figure 4 As shown, when the thickness of the first bonding layer 30 is too thick, the first sub-gate line 50 will need to be bent upwards for too long, which may easily lead to breakage.

[0087] Specifically, in this invention, the thickness of the first bonding layer 30 can be 0.3nm, 0.5nm, 0.7nm, 0.9nm, 1nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, 5nm, or any other value within the range of 0.3nm to 5nm. The specific value can be set according to the actual situation and is not limited here.

[0088] Please see Figure 3 and Figure 4 In some embodiments, the width of the first main gate line 40 may be smaller than the width of the first bonding layer 30.

[0089] Thus, setting the width of the first bonding layer 30 to be greater than the width of the first main gate line 40 ensures that the first main gate line 40 is entirely located on the first bonding layer 30 during printing and sintering. Even if there are certain errors in the preparation process, it can be ensured that the silver paste of the first main gate line 40 will not leak into the area outside the first bonding layer 30, which would cause part of the structure of the first main gate line 40 to directly burn through the contact between the first passivation film layer 20 and the substrate 10, resulting in increased recombination.

[0090] Specifically, the width of the first bonding layer 30 can be set in the range of 10um-50um. The width of the first bonding layer 30 can be determined according to the width of the first main gate line 40. It is only necessary to set the width of the first bonding layer 30 to be slightly larger than the width of the first main gate line 40. The specific width can be determined according to the actual situation and is not limited here.

[0091] Of course, it is understood that in some other embodiments, the width of the first main gate line 40 may also be equal to the width of the first bonding layer 30, and no specific limitation is made here.

[0092] Please see Figure 4 and Figure 5 In some embodiments, the first main gate line 40 does not pass through the first bonding layer 30.

[0093] Thus, the first main grid line 40 is only embedded in the first bonding layer 30 and does not contact the substrate 10 and the first passivation film layer 20. In this way, on the one hand, a high pull-out force can be formed between the first bonding layer 30 and the first main grid line 40 to ensure the welding performance of the first main grid line 40. At the same time, the first main grid line 40 and the substrate 10 will not form a silver-silicon contact, and the charge carriers will not reach the metal interface. The recombination loss of the first main grid line 40 is small, thereby improving the efficiency of the solar cell 100.

[0094] Of course, it is understandable that you would like to refer to [the relevant information]. Figure 6 In some embodiments, the first main gate line 40 may also pass through the first bonding layer 30 and be embedded in the first passivation film layer 20 without passing through the first passivation film layer 20.

[0095] In this way, the first main gate line 40 is simultaneously embedded in the first bonding layer 30 and the first passivation film layer 20, which can make the first main gate line 40 have better pull-out force to ensure the welding performance of the first main gate line 40. In addition, the fact that the first main gate line 40 does not directly contact the substrate 10 can also reduce the recombination loss of the first main gate line 40.

[0096] Furthermore, it is understood that in some embodiments, the first main gate line 40 may also pass through the first bonding layer 30 and the first passivation film layer 20 and be embedded in the substrate 10, and the embedding depth of the first main gate line 40 in the substrate 10 is less than a preset threshold.

[0097] Thus, even if the first main gate line 40 passes through the first bonding layer 30 and the first passivation film layer 20, the embedding depth of the first main gate line 40 in the substrate 10 is less than the preset threshold, and the metal structure area between the two is small, which can reduce the recombination loss of the first main gate line 40 to a certain extent.

[0098] Specifically, in such an embodiment, the "preset threshold" can be understood as the embedding depth of the first main gate line 40 directly embedded into the substrate 10 without setting the first bonding layer 30 on the upper part of the first passivation film layer 20, or a value less than this depth. For example, when the first bonding layer 30 is not set, the embedding depth of the first main gate line 40 into the substrate 10 is 2um, then the preset threshold can also be 2um or other values ​​less than 2um.

[0099] It is understandable that the above three settings can be achieved by adjusting the burn-through capability of the main grid silver paste of the first main grid line 40. For example, the different burn-through capabilities of the main grid silver paste can be adjusted by adjusting the proportion of glass powder in the silver paste and the size of the particles.

[0100] Example 2

[0101] Please see Figure 7 In this embodiment, the solar cell 100 may further include a second passivation film layer 60, a second bonding layer 70, a second sub-grid line 90, and a second main grid line 80. The second passivation film layer 60 is stacked on the second surface 12, the second bonding layer 70 is stacked on a predetermined area of ​​the second reflective film layer, the second main grid line 80 is disposed on the second bonding layer 70 and embedded in the second bonding layer 70, and the second sub-grid line 90 is electrically connected to the second main grid line 80 and passes through the second passivation film layer 60 and is embedded in the substrate 10 and makes electrical contact with the substrate 10.

[0102] Thus, a second bonding layer 70 is provided on the second passivation film layer 60, and the second main grid line 80 is disposed on the second bonding layer 70 and embedded in the second bonding layer 70 to form a relatively tight contact. This allows a high pull-out force to be formed between the second main grid line 80, the substrate 10, and the second passivation film layer 60, thereby giving the second main grid line 80 good welding performance. At the same time, the second main grid line 80 does not directly contact the substrate 10 or the contact depth is shallow. This reduces the recombination loss of the second main grid line 80 and improves the efficiency of the solar cell 100.

[0103] Specifically, taking the first surface 11 as the front side and the second surface 12 as the back side as an example, the first main grid line 40 and the first sub-grid line 50 are the front electrodes of the solar cell 100, the second main grid line 80 and the second sub-grid line 90 are the back electrodes of the solar cell 100, and the second passivation film layer 60 and the second bonding layer 70 are both disposed on the back side of the substrate 10. The second passivation film layer 60 can also be a silicon nitride film layer, and its thickness can also be 50nm-90nm. The second passivation film layer 60 can realize the passivation function of the back side of the substrate 10.

[0104] Similar to the first sub-busbar 50 and the first main busbar 40, in this embodiment, there can also be multiple second main busbars 80 and second sub-busbars 90. Multiple second sub-busbars 90 can be connected to each second main busbar 80. The second sub-busbars 90 are used to collect the current generated by the solar cell 100, and the multiple second sub-busbars 90 collect the current and channel it into the second main busbar 80. Multiple second sub-busbars 90 can be connected to each second main busbar 80, and the corresponding second sub-busbars 90 can respectively converge the current to their respective second main busbars 80. Multiple second main busbars 80 can be welded together with conductive busbars to achieve current convergence and current extraction.

[0105] It is understood that, in the embodiments of the present invention, the first main grid line 40 and the first sub-grid line 50 constitute one of the front electrode and the back electrode of the solar cell 100, and the second main grid line 80 and the second sub-grid line 90 constitute the other of the front electrode and the back electrode of the solar cell 100.

[0106] Furthermore, similar to the first main gate line 40, in embodiments of the present invention, the second main gate line 80 can also be formed by printing main gate silver paste on the second bonding layer 70 and then sintering, and the second sub-gate line 90 can be formed by printing sub-gate silver paste on the second passivation film layer 60 and then sintering. It is understood that the second main gate line 80 and the second sub-gate line 90 can be formed separately or simultaneously. For example, in some cases, main gate silver paste can be printed on the second bonding layer 70 first, then sintered to form the second main gate line 80, and then sub-gate silver paste can be printed and sintered to form the second sub-gate line 90. In another case, the main gate silver paste and sub-gate silver paste can be printed simultaneously and then sintered together to form the second main gate line 80 and the second sub-gate line 90. The specific formation method is not limited here.

[0107] Furthermore, it should be noted that, in this invention, similar to the preset region of the first passivation film layer 30 described above, the "preset region of the second passivation film layer 60" refers to the region on the second passivation film layer 60 corresponding to the second main gate line 80. The size of the preset region can be the same as or slightly larger than the size of the second main gate line 80; no specific limitation is imposed here. It is understood that, in the embodiments of this invention, the number of "preset regions" corresponds to the number of second main gate lines 80, with each preset region corresponding to one second main gate line 80. Of course, it is understood that in some embodiments, one preset region may correspond to multiple second main gate lines 80, or some of the second main gate lines 80 may correspond to a preset region and a second bonding layer 70, while some of the second main gate lines 80 may not have a second bonding layer 70 below them but instead directly pass through the second passivation film layer 60 and be embedded into the substrate 10; specific limitations are imposed here.

[0108] Similarly, in such an embodiment, the second bonding layer 70 may also be a silicon oxide layer.

[0109] In this way, the silicon oxide layer can ensure that the second main gate line 80 has high bonding strength while also preventing direct contact or shallow contact between the second main gate line 80 and the substrate 10, thereby reducing the recombination loss of the second main gate line 80. At the same time, the good insulation properties of the silicon oxide layer can also prevent leakage current.

[0110] Further, please refer to Figure 7 In some embodiments, the end of the second sub-gate line 90 that is electrically connected to the second main gate line 80 is also embedded in the second bonding layer 70.

[0111] In this way, the connection point of the second sub-gate line 90 and the second main gate line 80 is embedded in the second bonding layer 70. The second bonding layer 70 can effectively protect the connection point to prevent the second main gate line 80 and the second sub-gate line 90 from breaking when subjected to external impact.

[0112] Of course, please see Figure 8 In other embodiments, one end of the second sub-gate line 90 connected to the second main gate line 80 may also be attached to the surface of the second bonding layer 70 and electrically connected to the portion of the second main gate line 80 exposed in the second bonding layer 70. That is, the second sub-gate line 90 may be electrically connected to the portion of the second main gate line 80 exposed in the second bonding layer 70 after passing upward around the second bonding layer 70. No specific limitations are imposed here.

[0113] In some embodiments, the thickness of the second bonding layer 70 may be 0.3um-5um.

[0114] In this way, on the one hand, it ensures that the second main gate line 80 has a good embedding depth, thus providing good pull-out force. Simultaneously, it avoids the second bonding layer 70 being too thin, which could cause the second main gate line 80 to directly burn through the second bonding layer 70 and the second passivation film layer 60 during sintering, directly embedding into the substrate 10 and leading to increased composite. Furthermore, it avoids the second bonding layer 70 being too thin, resulting in poor uniformity during fabrication, with some areas having insufficient thickness or even lacking the second bonding layer 70 altogether. On the other hand, it also avoids the second bonding layer 70 being too thick, which could lead to a large path slope when connecting the second sub-gate line 90 to the second main gate line 80, potentially causing breakage. Figure 7 As shown, when the thickness of the second bonding layer 70 is too thick, the second sub-gate line 90 will need to be bent downwards for too long, which may easily lead to breakage.

[0115] Specifically, in this invention, the thickness of the second bonding layer 70 can be 0.3nm, 0.5nm, 0.7nm, 0.9nm, 1nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, 5nm, or any other value within the range of 0.3nm to 5nm. The specific value can be set according to the actual situation and is not limited here.

[0116] Please see Figure 7 and Figure 8 In some embodiments, the width of the second main gate line 80 is smaller than the width of the second bonding layer 70.

[0117] Thus, setting the width of the second bonding layer 70 to be greater than the width of the second main gate line 80 ensures that the second main gate line 80 is entirely located on the second bonding layer 70 during printing and sintering. Even if there are certain errors in the preparation process, it can be ensured that the silver paste of the second main gate line 80 will not leak into the area outside the second bonding layer 70, which would cause part of the structure of the second main gate line 80 to directly burn through the second passivation film layer 60, resulting in excessive contact depth with the substrate 10 and increased recombination.

[0118] Specifically, the width of the second bonding layer 70 can be set in the range of 10um-50um, and the width of the second main gate line 80 can be slightly smaller than the width of the second bonding layer 70. The specific width can be determined according to the actual situation and is not limited here.

[0119] Of course, it is understood that in some other embodiments, the width of the second main gate line 80 may also be equal to the width of the second bonding layer 70, and no specific limitation is made here.

[0120] Please see Figure 7 and Figure 8 In some embodiments, the second main gate line 80 does not pass through the second bonding layer 70.

[0121] Thus, the second main grid line 80 is simply embedded within the second bonding layer 70 and does not contact the substrate 10 and the second passivation film layer 60. In this way, on the one hand, a high pull-out force can be formed between the second bonding layer 70 and the second main grid line 80 to ensure the welding performance of the second main grid line 80. At the same time, the second main grid line 80 and the substrate 10 will not form a silver-silicon contact, and charge carriers will not reach the metal interface. The recombination loss of the second main grid line 80 is small, thereby improving the efficiency of the solar cell 100.

[0122] Of course, it is understandable that you would like to refer to [the relevant information]. Figure 9 In some embodiments, the second main gate line 80 may also pass through the second bonding layer 70 and be embedded in the second passivation film layer 60 without passing through the second passivation film layer 60.

[0123] In this way, the second main gate line 80 is simultaneously embedded in the second bonding layer 70 and the second passivation film layer 60, which can make the second main gate line 80 have better pull-out force to ensure the welding performance of the second main gate line 80. In addition, the fact that the second main gate line 80 does not directly contact the substrate 10 can also reduce the recombination loss of the second main gate line 80.

[0124] Furthermore, it is understood that in some embodiments, the second main gate line 80 may also pass through the second bonding layer 70 and the second passivation film layer 60 and be embedded in the substrate 10, with the embedding depth of the second main gate line 80 in the substrate 10 being less than a preset threshold.

[0125] Thus, even if the second main gate line 80 passes through the second bonding layer 70 and the second passivation film layer 60, the embedding depth of the second main gate line 80 in the substrate 10 is less than the preset threshold. The metal structure area between the two is small, which can reduce the recombination loss of the second main gate line 80 to a certain extent.

[0126] Specifically, in such an embodiment, the "preset threshold" can be understood as the embedding depth of the second main gate line 80 directly embedded into the substrate 10 without setting the second bonding layer 70 on the upper part of the second passivation film layer 60, or a value less than this depth. For example, when the second bonding layer 70 is not set, the embedding depth of the second main gate line 80 embedded into the substrate 10 is 2um, then the preset threshold can also be 2um or other values ​​less than 2um.

[0127] It is understandable that the above three settings can be achieved by adjusting the burn-through capability of the main grid silver paste of the second main grid line 80. For example, the different burn-through capabilities of the main grid silver paste can be adjusted by adjusting the proportion of glass powder in the silver paste.

[0128] In addition, please see Figures 7 to 9 In embodiments of the present invention, the first passivation film layer 20 and the second passivation film layer 60 may be symmetrically arranged about the substrate 10, the first bonding layer 30 and the second bonding layer 70 may also be symmetrically arranged about the substrate 10, the first main gate line 40 and the second main gate line 80 may also be symmetrically arranged about the substrate 10, and the first sub-gate line 50 and the second sub-gate line 90 may also be symmetrically arranged about the substrate 10. Of course, it is understood that in some practical embodiments, the first bonding layer 30 and the second bonding layer 70, the first main gate line 40 and the second main gate line 80, and the first sub-gate line 50 and the second sub-gate line 90 may not be symmetrically arranged about the substrate 10. The specific arrangement can be configured according to actual conditions, as long as the first sub-gate line 50 can collect current to the first main gate line 40, and the second sub-gate line 90 can collect current to the second main gate line 80.

[0129] Example 3

[0130] Please see Figure 10 and Figure 11 This invention also provides a method for preparing a solar cell 100. The solar cell 100 in this invention can be prepared by this method. Figure 10 This is a schematic flowchart illustrating the method for preparing the solar cell 100 according to an embodiment of the present invention. Figure 11 This is a schematic diagram illustrating the manufacturing process of the solar cell 100 according to an embodiment of the present invention. The manufacturing method may include the following steps:

[0131] S10: A substrate 10 is provided, the substrate 10 including a first surface 11 and a second surface 12 facing away from each other;

[0132] S20: A first passivation film layer 20 is prepared on the first surface 11;

[0133] S30: A first bonding layer 30 is prepared on a predetermined area of ​​the first passivation film layer 20;

[0134] S40: A first main gate line 40 is prepared on the first bonding layer 30 and embedded in the first bonding layer 30;

[0135] S50: A first sub-gate line 50 is formed on the first passivation film layer 20, passing through the first passivation film layer 20 and embedded in the substrate 10 and electrically connected to the substrate 10. The first sub-gate line 50 is electrically connected to the first main gate line 40.

[0136] The solar cell 100 manufactured by the method of the present invention has a first passivation film layer 20 on its substrate 10, a first bonding layer 30 is stacked on a predetermined area of ​​the first passivation film layer 20, a first main grid line 40 is disposed on the first bonding layer 30 and embedded in the first bonding layer 30, and a first sub-grid line 50 is electrically connected to the first main grid line 40 and passes through the first passivation film layer 20 and is embedded in the substrate 10 and makes electrical contact with the substrate 10. Thus, a first bonding layer 30 is provided on the first passivation film layer 20, and the first main grid line 40 is disposed on the first bonding layer 30 and embedded in the first bonding layer 30 to form a relatively tight contact. This allows a high pull-out force to be formed between the first main grid line 40, the substrate 10, and the first passivation film layer 20, thereby giving the first main grid line 40 good welding performance. At the same time, the first main grid line 40 and the substrate 10 do not directly contact each other or the contact depth is shallow. This can reduce the recombination loss of the first main grid line 40 and improve the efficiency of the solar cell 100.

[0137] Specifically, as mentioned above, the substrate 10 can be a monocrystalline silicon wafer or a polycrystalline silicon wafer. The specific structures of the first passivation film layer 20, the first bonding layer 30, the first main gate line 40, and the first sub-gate line 50 have been explained and elaborated in detail above, and will not be repeated here to avoid being too lengthy.

[0138] Please see Figure 11 In the preparation method of this embodiment, the first passivation film layer 20 can be coated onto the first surface 11 of the substrate 10 by means of a coating device or by screen printing, and the first bonding layer 30 can be formed by coating a paste onto a predetermined area of ​​the first passivation film or by screen printing. The first main gate line 40 and the second main gate line 80 can be formed by printing silver paste onto the first bonding layer 30 and the first passivation film layer 20 respectively and then sintering.

[0139] It should be noted that, in Figure 10 The illustrated embodiment is merely an example of step S40 being performed before step S50. It is understood that in the embodiments of the present invention, step S50 may be executed first and then step S40 may be executed, or steps S40 and S50 may be executed simultaneously. The order of steps S40 and S50 is not limited here.

[0140] Further, please refer to Figure 12 In some embodiments, after step S30 and before steps S40 and S50, the preparation method may further include the following steps:

[0141] S60: The substrate 10 having the first passivation film layer 20 and the first bonding layer 30 is dried;

[0142] Thus, after the first passivation film layer 20 and the first bonding layer 30 are formed, the first bonding layer 30 and the first passivation film layer 20 can be well bonded by drying, so that the two are in close contact, and the organic matter in the first bonding layer 30 can be effectively removed.

[0143] Specifically, in such an embodiment, the drying temperature for drying the substrate 10 is 200-500°C, and the drying time is 5-30 minutes.

[0144] Therefore, setting the temperature between 200-500℃ ensures a tight bond between the first bonding layer 30 and the first passivation film layer 20, while also ensuring the effective removal of organic matter from the first bonding layer 30. Conversely, it avoids insufficient temperature, which could lead to a weak bond between the two layers and prevent the effective removal of organic matter, and also prevents excessively high drying temperatures that could damage the first passivation film layer 20. Similarly, setting the drying time between 5-30 minutes avoids both insufficient drying time (leading to inadequate drying and a weak bond with the first passivation film layer 20) and excessive drying time (damaging the first passivation film layer 20 and affecting the passivation effect).

[0145] Specifically, if the temperature is less than 200°C, the bonding force between the first bonding layer 30 and the first passivation film layer 20 is small, which will cause the two to fail to bond tightly. If the temperature is greater than 500°C, the first passivation film layer 20 may be damaged, affecting the passivation effect. In this embodiment, setting the temperature between 200-500°C can ensure that the first bonding layer 30 and the first passivation film layer 20 can bond relatively tightly while also preventing the first passivation film layer 20 from being damaged, thus ensuring the passivation effect.

[0146] If the drying time is less than 5 minutes, the drying effect of the first bonding layer 30 may be poor, resulting in insufficient bonding between the first bonding layer 30 and the first passivation film layer 20. If the drying time is greater than 30 minutes, the drying time may be too long, causing the first passivation film layer 20 to be damaged. In this embodiment, setting the drying time to 5-30 minutes can ensure a relatively tight bonding between the first bonding layer 30 and the first passivation film layer 20 while also preventing damage to the first passivation film layer 20 to ensure the passivation effect.

[0147] Further, please refer to Figure 13 In some embodiments, the preparation method may further include the step of:

[0148] S70: A second passivation film 60 is prepared on the second surface 12;

[0149] S80: A second bonding layer 70 is prepared on a predetermined area of ​​the second passivation film layer 60;

[0150] S90: A second main gate line 80 is prepared on the second bonding layer 70 and embedded in the second bonding layer 70;

[0151] S100: A second sub-gate line 90 is formed on the second passivation film layer 60, passing through the second passivation film layer 60 and embedded in the substrate 10 and electrically connected to the substrate 10. The second sub-gate line 90 is electrically connected to the second main gate line 80.

[0152] Thus, a second bonding layer 70 is provided on the second passivation film layer 60, and the second main grid line 80 is disposed on the second bonding layer 70 and embedded in the second bonding layer 70 to form a relatively tight contact. This allows a high pull-out force to be formed between the second main grid line 80, the substrate 10, and the second passivation film layer 60, thereby giving the second main grid line 80 good welding performance. At the same time, the second main grid line 80 does not directly contact the substrate 10 or the contact depth is shallow. This reduces the recombination loss of the second main grid line 80 and improves the efficiency of the solar cell 100.

[0153] Specifically, the specific structures of the second passivation film layer 60, the second bonding layer 70, the second main gate line 80, and the second sub-gate line 90 have been explained and elaborated in detail above, and will not be repeated here to avoid being too lengthy.

[0154] In the preparation method of the present invention, the second passivation film layer 60 can also be covered on the second surface 12 of the substrate 10 by means of a coating device or by screen printing, etc., and the second bonding layer 70 can be formed by coating a paste in a predetermined area of ​​the second passivation film or by screen printing. The second main gate line 80 and the second sub-gate line 90 can be formed by printing silver paste on the first bonding layer 30 and the first passivation film layer 20 respectively and then sintering.

[0155] It should be noted that, in Figure 13 The illustrated embodiment is merely an example of step S90 being executed before step S100. It is understood that in the embodiments of the present invention, step S100 may be executed first and then step S90 may be executed, or steps S90 and S100 may be executed simultaneously. The order of steps S90 and S100 is not limited here.

[0156] Furthermore, in the embodiments of the present invention, the order of steps S20 and S70 is not specifically limited. Figure 13 In the example shown, steps S70-S100 are all performed after step S50. It is understood that in the embodiments of the present invention, step S70 can be performed simultaneously with step S20, or step S70 can be performed first and then step S20. That is to say, the preparation of the first passivation film layer 20 and the second passivation film layer 60 can be performed simultaneously or in steps, preferably simultaneously, but no specific limitation is made here.

[0157] Furthermore, it should be noted that the order of steps S30 and S80 is not limited. They can be performed simultaneously or separately, but it is preferred that they be performed simultaneously. That is, the second bonding layer 70 is prepared at the same time as the first bonding layer 30. Moreover, the present invention does not limit the order of steps S40, S50, S90, and S100. Steps S50 and S90 can be performed first, followed by steps S90 and S100, or steps S40 and S90 can be performed simultaneously first, followed by steps S50 and S100 simultaneously. The specific order can be determined according to the actual situation.

[0158] Please see Figure 14 In a preferred embodiment, steps S20 and S70 can be performed simultaneously, that is, the first passivation film layer 20 and the second passivation film layer 60 can be prepared on the first surface 11 and the second surface 12 of the substrate 10 at the same time. At the same time, steps S30 and S80 can also be performed simultaneously, that is, the first bonding layer 30 and the second bonding layer 70 can be prepared on the first passivation film layer 20 and the second passivation film layer 60 at the same time. It is understood that this document does not limit the preparation order of each film layer, and the specific order can be determined according to the actual situation.

[0159] Furthermore, in some embodiments, the first bonding layer 30 may be a silicon oxide layer, and step S30 may include the following steps:

[0160] A first bonding layer 30 is prepared in a predetermined region of the first passivation film layer 20 using a slurry containing silicon oxide.

[0161] Specifically, the slurry can be prepared by mixing, stirring and grinding silicon oxide, lead oxide, tellurium oxide, copper oxide and organic carrier. The silicon oxide material in the slurry can be nano silicon oxide (vapor phase silicon oxide) with a particle diameter between 50nm and 5000nm. By mixing, stirring and grinding the above materials, a slurry with good coating performance can be prepared. When preparing the first bonding layer 30, it is only necessary to coat the slurry in the preset area of ​​the first passivation film layer 20 or print the slurry by screen printing, and then dry it to obtain the first bonding layer 30.

[0162] Specifically, in such embodiments, the weight percentage of fumed silica can be 5%-85%, lead oxide can be 0.2%-10%, tellurium oxide can be 0.2%-10%, copper oxide can be 0.2%-10%, and the organic carrier can be 0.2%-10%. Thus, by using the above weight percentages for mixing, stirring, and grinding, a slurry with better coating performance can be prepared, thereby achieving the preparation of the first bonding layer 30.

[0163] Furthermore, in some embodiments, the organic carrier is prepared by mixing and stirring a resin and a solvent.

[0164] In this way, the resin and solvent are mixed, and the solvent can dissolve the resin to obtain an organic carrier with good flowability. Thus, it is only necessary to add silicon oxide, lead oxide, tellurium oxide and copper oxide and other components to the organic carrier and mix them to support the slurry for making the first bonding layer 30. The organic carrier can ensure that the slurry has good flowability and coating performance.

[0165] Specifically, in such embodiments, the resin may include at least one of ethyl cellulose, polyamide wax, and polyvinyl butyral, and the solvent may include at least one of ethyl alcohol ester dodecyl, diethylene glycol butyl ether acetate, diethylene glycol monobutyl ether, dioctyl phthalate, dimethyl phthalate, terpineol, and ethyl alcohol ester hexadecyl.

[0166] Preferably, the resin may include at least two of ethyl cellulose, polyamide wax, and polyvinyl butyral, with the weight ratio of the two resins being 5%-30%. The solvent may include at least two of dodecyl alcohol ester, diethylene glycol butyl ether acetate, diethylene glycol monobutyl ether, dioctyl phthalate, dimethyl phthalate, terpineol, and hexadecyl alcohol ester, with the weight ratio of the two solvents also being 5%-30%.

[0167] Furthermore, in this embodiment, the resin and solvent can be mixed and stirred in a reaction apparatus (e.g., a reaction vessel) to form the aforementioned slurry. The stirring temperature can be 60°C-90°C, and the stirring time can be 10 min-300 min. Setting the stirring temperature to 60°C-90°C allows the solvent to rapidly dissolve the resin at this temperature, increasing the dissolution rate, while setting the stirring time to 10 min-300 min ensures the solvent can fully dissolve the resin, avoiding incomplete dissolution.

[0168] In the description of this specification, references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the described embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0169] Furthermore, the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A solar cell, characterized in that, include: A substrate, the substrate comprising a first surface and a second surface facing away from each other; A first passivation film layer is stacked on the first surface; A first bonding layer is stacked on a predetermined area of ​​the first passivation film layer; The first main gate line is disposed on the first bonding layer and embedded in the first bonding layer; and The first sub-gate line is electrically connected to the first main gate line and passes through the first passivation film layer to be embedded in the substrate and electrically contact the substrate; The first bonding layer includes a silicon oxide layer; The first main gate line does not pass through the first bonding layer; or The first main gate line passes through the first bonding layer and is embedded in the first passivation film layer without passing through the first passivation film layer.

2. The solar cell according to claim 1, characterized in that, The thickness of the first bonding layer is 0.3um-5um.

3. The solar cell according to claim 1, characterized in that, The width of the first main gate line is less than or equal to the width of the first bonding layer.

4. The solar cell according to claim 1, characterized in that, The solar cell further includes a second passivation film layer, a second bonding layer, a second sub-grid line, and a second main grid line. The second passivation film layer is stacked on the second surface, the second bonding layer is stacked on a predetermined area of ​​the second passivation film layer, the second main grid line is disposed on the second bonding layer and embedded in the second bonding layer, and the second sub-grid line is electrically connected to the second main grid line and passes through the second passivation film layer and is embedded in the substrate and makes electrical contact with the substrate.

5. The solar cell according to claim 4, characterized in that, The second bonding layer includes a silicon oxide layer.

6. The solar cell according to claim 4, characterized in that, The thickness of the second bonding layer is 0.3um-5um.

7. A method for preparing a solar cell, characterized in that, include: A substrate is provided, the substrate including a first surface and a second surface opposite to each other; A first passivation film is prepared on the first surface; A first bonding layer is prepared on a predetermined region of the first passivation film layer; the first bonding layer includes a silicon oxide layer. A first main gate line is fabricated on the first bonding layer and embedded within the first bonding layer; A first sub-gate line is formed on the first passivation film layer, passing through the first passivation film layer and embedded in the substrate and electrically connected to the substrate. The first sub-gate line is electrically connected to the first main gate line. The first main gate line does not pass through the first bonding layer; or The first main gate line passes through the first bonding layer and is embedded in the first passivation film layer without passing through the first passivation film layer.

8. The method for preparing a solar cell according to claim 7, characterized in that, After the step of preparing the first bonding layer on the predetermined region of the first passivation film, the preparation method further includes: The substrate having the first passivation film layer and the first bonding layer is dried.

9. The method for preparing a solar cell according to claim 8, characterized in that, The drying temperature for the substrate is 200-500℃, and the drying time is 5-30 minutes.

10. The method for preparing a solar cell according to claim 7, characterized in that, The preparation method further includes: A second passivation film is prepared on the second surface; A second bonding layer is prepared on a predetermined region of the second passivation film layer; A second main gate line is fabricated on the second bonding layer and embedded within the second bonding layer; A second sub-gate line is formed on the second passivation film layer, passing through the second passivation film layer and embedded in the substrate and electrically connected to the substrate. The second sub-gate line is electrically connected to the second main gate line.

11. The method for preparing a solar cell according to claim 7, characterized in that, The step of preparing the first bonding layer on a predetermined region of the first passivation film includes: The first bonding layer is prepared in a predetermined area of ​​the first passivation film using a slurry containing silicon oxide.

12. The method for preparing a solar cell according to claim 11, characterized in that, The slurry is prepared by mixing, stirring and grinding silicon oxide, lead oxide, tellurium oxide, copper oxide and an organic carrier; The silicon oxide comprises 5%-85% by weight, the lead oxide comprises 0.2%-10% by weight, the tellurium oxide comprises 0.2%-10% by weight, the copper oxide comprises 0.2%-10% by weight, and the organic carrier comprises 0.2%-10% by weight.

13. The method for preparing a solar cell according to claim 12, characterized in that, The organic carrier is prepared by mixing and stirring resin and solvent.

14. The method for preparing a solar cell according to claim 13, characterized in that, The organic carrier is prepared by mixing resin and solvent at a temperature of 60℃-90℃ and a stirring time of 10min-300min.

15. A battery assembly, characterized in that, It includes the solar cell as described in any one of claims 1-6.

16. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 15.

Images