N-type transistor based on nanomaterials and method of fabrication

Abstract

The present disclosure provides an N-type transistor based on nanomaterials, comprising: a substrate layer; a semiconductor material layer disposed on the substrate layer for forming a semiconductor channel region; a first metal electrode disposed on the semiconductor material layer to form a source electrode; and a second metal electrode disposed on the semiconductor material layer to form a drain electrode; wherein the semiconductor material layer is formed of nanomaterials, the bottom of the metal electrode is in contact with the semiconductor material layer, and a hydrophobic material layer is disposed between the substrate layer and the semiconductor material layer to avoid oxidation of the bottom of the metal electrode. The present disclosure also provides an integrated circuit device and a preparation method of a transistor.

Description

Technical Field

[0001] This disclosure relates to the field of transistor technology, and more particularly to an N-type transistor based on nanomaterials and its fabrication method. Background Technology

[0002] Moore's Law is gradually losing its guiding role in the development of silicon-based integrated circuits, while technological advancements are placing increasingly higher demands on integrated circuits. With current mainstream silicon-based processes facing physical and technological limits, new materials and processes are needed to break through these bottlenecks.

[0003] Carbon nanotubes are one of the most promising materials in the post-Moore era. Currently, high-purity, high-density carbon nanotube arrays can be mass-produced on 4-inch wafers, which is the foundation for realizing carbon-based integrated circuits.

[0004] Considering the requirements for low power consumption and heat dissipation, CMOS cells are the inevitable choice for integrated circuits. Although P-type transistors based on carbon nanotube arrays currently have performance exceeding that of silicon-based transistors, the fabrication of N-type transistors with comparable performance faces challenges.

[0005] One of the mainstream methods for fabricating high-performance N-type transistors is to use low work function metals as source and drain electrodes. This is because the Fermi level of low work function metals is flush with the conduction band of carbon nanotubes, and there is no barrier to electron transport under high contact quality, thus leveraging the high mobility of carbon nanotubes. This method has demonstrated good performance on single carbon nanotubes and disordered carbon nanotube films. However, low work function metals are prone to oxidation in air. External water and oxygen can enter the bottom of the contact metal along the arrayed carbon nanotubes during the fabrication process, causing oxidation. This can lead to devices not conducting or exhibiting poor performance. Therefore, it is necessary to improve the process to solve the oxidation problem, thereby enhancing the performance of N-type transistors based on arrayed carbon nanotubes, and realizing high-performance CMOS devices and circuits. Summary of the Invention

[0006] To address at least one of the aforementioned technical problems, this disclosure provides an N-type transistor based on nanomaterials, comprising: Substrate layer; A semiconductor material layer disposed on the substrate layer for forming a semiconductor channel region; A first metal electrode is disposed on the semiconductor material layer to form a source electrode; A second metal electrode is disposed on the semiconductor material layer to form a drain electrode; The semiconductor material layer is formed of nanomaterials, the bottom of the metal electrode is in contact with the semiconductor material layer, and a hydrophobic material layer is disposed between the substrate layer and the semiconductor material layer to prevent the bottom of the metal electrode from being oxidized.

[0007] According to at least one embodiment of the present disclosure, in a nanomaterial-based N-type transistor, both the first metal electrode and the second metal electrode are formed of a low power function metal or an alloy of low power function metals.

[0008] According to at least one embodiment of the nanomaterial-based N-type transistor of the present disclosure, the low power function metal includes, but is not limited to, one of scandium (Sc), yttrium (Y), aluminum (Al), titanium (Ti), and calcium (Ca).

[0009] According to at least one embodiment of the nanomaterial-based N-type transistor of the present disclosure, the alloy of the low power function metal includes, but is not limited to, an alloy formed from two or more of scandium (Sc), yttrium (Y), aluminum (Al), titanium (Ti), and calcium (Ca).

[0010] According to at least one embodiment of the present disclosure, in an N-type transistor based on nanomaterials, the hydrophobic material layer has a coverage area on the substrate layer that is greater than or equal to the coverage area of ​​the semiconductor material layer.

[0011] According to at least one embodiment of the present disclosure, an N-type transistor based on nanomaterials is provided, wherein a first metal electrode and a second metal electrode are spaced apart on the semiconductor material layer along a first direction, both the first metal electrode and the second metal electrode have an extension dimension in a second direction, and both ends of the metal electrode in the second direction extend to the hydrophobic material layer or terminate on the semiconductor material layer. Among them, the first direction and the second direction are mutually perpendicular.

[0012] According to at least one embodiment of the present disclosure, the nanomaterial-based N-type transistor has a semiconductor material layer formed from an array of carbon nanotubes.

[0013] According to at least one embodiment of the present disclosure, the nanomaterial-based N-type transistor, wherein the arrayed carbon nanotubes are two-dimensional or three-dimensional arrayed carbon nanotubes.

[0014] According to at least one embodiment of the present disclosure, the nanomaterial-based N-type transistor has a semiconductor material layer formed from semiconductor nanowires or a two-dimensional semiconductor plane.

[0015] The nanomaterial-based N-type transistor according to at least one embodiment of the present disclosure further includes: A gate electrode is formed between the first metal electrode and the second metal electrode and is located above the semiconductor channel region of the semiconductor material layer; A gate dielectric layer is formed at least between the gate electrode and the semiconductor material layer, between the gate electrode and the first metal electrode, and between the gate electrode and the second metal electrode.

[0016] According to at least one embodiment of the present disclosure, the material of the gate dielectric layer in the nanomaterial-based N-type transistor includes, but is not limited to, HfO2 or Y2O3.

[0017] According to another aspect of this disclosure, an integrated circuit device is provided, comprising: The N-type transistor is an N-type transistor based on nanomaterials according to any embodiment of the present disclosure.

[0018] According to another aspect of this disclosure, a method for fabricating an N-type transistor is provided, comprising the following steps: The first surface of the substrate layer is treated with a hydrophobic coating; A semiconductor material layer is formed on the first surface that has undergone hydrophobic treatment; Metal materials are deposited in the first and second regions of the semiconductor material layer to form the source electrode and drain electrode, respectively. An insulating material is deposited between the first region and the second region to form a gate dielectric layer; A gate electrode is formed on the gate dielectric layer.

[0019] According to a preparation method of at least one embodiment of the present disclosure, the hydrophobic treatment includes: A hydrophobic material layer is formed on the first surface of the substrate layer.

[0020] According to a preparation method of at least one embodiment of the present disclosure, the semiconductor material layer is formed of nanomaterials.

[0021] According to the preparation method of at least one embodiment of the present disclosure, both the source electrode and the drain electrode are formed of a low power function metal material or an alloy of low power function metals.

[0022] The preparation method according to at least one embodiment of the present disclosure is used to prepare an N-type transistor based on nanomaterials according to any embodiment of the present disclosure. Attached Figure Description

[0023] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0024] Figure 1 This is a schematic diagram of the structure of an N-type transistor based on nanomaterials according to one embodiment of the present disclosure.

[0025] Figures 2 to 8 The fabrication process of an N-type transistor based on nanomaterials according to one embodiment of the present disclosure is shown.

[0026] Figure 9 The image shows a TEM (transmission electron microscopy) characterization of the oxidation at the bottom of the contact metal (metal electrode) of an N-type transistor based on an untreated hydrophobic substrate and an array of carbon nanotubes.

[0027] Figure 10 Figure (a) shows a schematic diagram of a substrate that has not undergone hydrophobic treatment exhibiting hydrophilicity. Figure 10 Figure (b) is a schematic diagram showing the hydrophobicity of the substrate after hydrophobic treatment.

[0028] Figure 11 This is a schematic diagram comparing the on-state current and yield of an N-type transistor based on a hydrophobically treated substrate and an N-type transistor based on an untreated substrate.

[0029] Figure 12 This is a schematic flowchart of a method for fabricating an N-type transistor according to one embodiment of the present disclosure.

[0030] Explanation of reference numerals in the attached figures 100N transistor 101 Substrate 102 Hydrophobic material layer 103 Semiconductor material layer 104 Metal Electrode 105 Gate dielectric layer 106 Gate electrode. Detailed Implementation

[0031] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0032] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0033] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0034] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0035] When a component is referred to as being "on" or "above" another component, "connected to," or "joined to" another component, the component may be directly on, directly connected to, or directly joined to the other component, or there may be intermediate components. However, when a component is referred to as being "directly on" another component, "directly connected to," or "directly joined to" another component, there are no intermediate components. Therefore, the term "connection" can refer to a physical connection, an electrical connection, etc., and may or may not have intermediate components.

[0036] For descriptive purposes, this disclosure may use spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side (e.g., in a “sidewall”)” to describe the relationship between one component and another component as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, a component described as “below” or “under” another component or feature would subsequently be positioned “above” said other component or feature. Thus, the exemplary term “below” can encompass both “above” and “below” orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0038] The following text combines Figures 1 to 12 The present invention provides a detailed description of the nanomaterial-based N-type transistor and its fabrication method.

[0039] Figure 1 This is a schematic diagram of the structure of an N-type transistor based on nanomaterials according to one embodiment of the present disclosure.

[0040] refer to Figure 1 One embodiment of the present disclosure includes an N-type transistor 100 based on nanomaterials, comprising: Substrate 101; A semiconductor material layer 103 is disposed on the substrate layer 101 for forming a semiconductor channel region; A first metal electrode 104 is disposed on a semiconductor material layer 103 to form a source electrode; The second metal electrode 104 is disposed on the semiconductor material layer 103 to form a drain electrode; The semiconductor material layer 103 is formed of nanomaterials, the bottom of the metal electrode 104 is in contact with the semiconductor material layer 103, and a hydrophobic material layer 102 is disposed between the substrate layer 101 and the semiconductor material layer 103 to prevent the bottom of the metal electrode 104 from being oxidized.

[0041] The N-type transistor based on nanomaterials disclosed herein is a novel N-type field-effect transistor.

[0042] The inventors of this disclosure have discovered that N-type transistors using low-power-function metals as contact electrodes suffer from a severe decline in contact quality due to oxidation at the bottom of the metal, especially field-effect transistors using nanomaterials as the N-channel layer.

[0043] The nanomaterial-based N-type transistor disclosed herein prevents external water and oxygen from entering through the semiconductor material layer 103 formed by the nanomaterial and contacting the bottom of the metal electrode 104 during the fabrication of the N-type transistor by hydrophobic treatment of the surface of the substrate layer 101, thereby preventing the bottom of the metal electrode 104 from being oxidized.

[0044] The hydrophobic treatment described above in this disclosure can be achieved by forming a hydrophobic material layer 102 on the surface of the substrate layer 101 of the nanomaterial-based N-type transistor 100.

[0045] The hydrophobic material can be hexamethyldisilazane (HMDS). Those skilled in the art, inspired by the technical solutions disclosed herein, can adjust or reselect the hydrophobic material, all of which fall within the protection scope of this disclosure.

[0046] The N-type transistor 100 based on nanomaterials disclosed herein has a substrate 101 that can be made of materials such as silicon wafer, quartz, sapphire, or diamond. Those skilled in the art can select or adjust the material of the substrate 101, and all such selections fall within the protection scope of this disclosure.

[0047] In some embodiments of this disclosure, the semiconductor material layer 103 of the nanomaterial-based N-type transistor 100 is formed of an array of carbon nanotubes.

[0048] On the substrate 101 after hydrophobic treatment, a semiconductor material layer 103 can be formed by pulling an array of carbon nanotubes in a carbon nanotube solution. Those skilled in the art can also use other processes to form an array of carbon nanotubes on the substrate 101 to form the semiconductor material layer 103 described above.

[0049] The arrayed carbon nanotubes described above in this disclosure are two-dimensional arrayed carbon nanotubes or three-dimensional arrayed carbon nanotubes.

[0050] Those skilled in the art can adjust the specific structure of the arrayed carbon nanotubes, all of which fall within the protection scope of this disclosure.

[0051] In some other embodiments of this disclosure, the semiconductor material layer 103 of the nanomaterial-based N-type transistor 100 is formed of semiconductor nanowires or two-dimensional semiconductor planes.

[0052] For the nanomaterial-based N-type transistor 100 of the above embodiments, preferably, the first metal electrode 104 and the second metal electrode 104 described above are both formed of a low power function metal or an alloy of low power function metals.

[0053] Among them, the low power function metal can be one of scandium (Sc), yttrium (Y), aluminum (Al), titanium (Ti), and calcium (Ca).

[0054] Among them, the alloy of low power function metal can be an alloy of two or more metals selected from scandium (Sc), yttrium (Y), aluminum (Al), titanium (Ti), and calcium (Ca), such as ScAl and YAl.

[0055] Low power function metals are commonly used metal electrode materials in field-effect transistors. Any selection or adjustment of specific low power function metals and their alloys by those skilled in the art, based on the technical solutions disclosed herein, falls within the protection scope of this disclosure.

[0056] Continue to refer to Figure 1 According to the preferred embodiment of the nanomaterial-based N-type transistor 100 of the present disclosure, the hydrophobic material layer 102 described in the present disclosure has a larger coverage area on the substrate layer 101 than the semiconductor material layer 103.

[0057] Figures 2 to 8 The fabrication process of an N-type transistor 100 based on nanomaterials according to one embodiment of the present disclosure is shown (hereinafter, based on... Figures 2 to 8 (A detailed description of the fabrication method of the N-type transistor 100 disclosed herein).

[0058] Depend on Figure 6 As can be seen, the hydrophobic material layer 102 of this disclosure has a larger coverage area on the substrate layer 101 than the semiconductor material layer 103, which enables the hydrophobic material layer 102 of this disclosure to better prevent external water and oxygen from entering through the semiconductor material layer 103 formed by nanomaterials and contacting the bottom of the metal electrode 104.

[0059] In some embodiments of this disclosure, the area of ​​the hydrophobic material layer 102 covering the substrate layer 101 is equal to the area of ​​the semiconductor material layer 103.

[0060] Continue to refer to Figure 6 According to a preferred embodiment of the present disclosure, an N-type transistor 100 based on nanomaterials includes: Substrate 101; A semiconductor material layer 103 is disposed on a substrate layer 101; A first metal electrode 104 is disposed on a semiconductor material layer 103 to form a source electrode; The second metal electrode 104 is disposed on the semiconductor material layer 103 to form a drain electrode; The semiconductor material layer 103 is formed of nanomaterials, the bottom of the metal electrode 104 is in contact with the semiconductor material layer 103, and a hydrophobic material layer 102 is disposed between the substrate layer 101 and the semiconductor material layer 103 to prevent the bottom of the metal electrode 104 from being oxidized.

[0061] The first metal electrode 104 and the second metal electrode 104 are spaced apart on the semiconductor material layer 103 along a first direction. Figure 6 In the X direction), both the first metal electrode 104 and the second metal electrode 104 are in the second direction ( Figure 6 The metal electrode 104 has an extension dimension in the Y direction, and both ends of the metal electrode 104 in the second direction extend to the hydrophobic material layer 102. The first direction and the second direction are perpendicular to each other.

[0062] In some embodiments of this disclosure, the two ends of the metal electrode 104 in the second direction may also terminate on the semiconductor material layer 103.

[0063] refer to Figure 8 The present disclosure of the nanomaterial-based N-type transistor 100 further includes: The gate electrode 106 is formed between the first metal electrode 104 and the second metal electrode 104, and is located above the semiconductor channel region of the semiconductor material layer 103. A gate dielectric layer 105 is formed at least between the gate electrode 106 and the semiconductor material layer 103, between the gate electrode 106 and the first metal electrode 104, and between the gate electrode 106 and the second metal electrode 104.

[0064] In this disclosure, the material of the gate electrode 106 of the nanomaterial-based N-type transistor 100 can be any metal material in the prior art. This disclosure does not impose any special limitation on the material of the gate electrode 106. Those skilled in the art can select or adjust the material of the gate electrode 106 under the guidance of the technical solution of this disclosure, and all such selections or adjustments will fall within the protection scope of this disclosure.

[0065] The material of the gate dielectric layer 105 disclosed herein may be HfO2 or Y2O3, etc. Those skilled in the art may also select other types of insulating materials as the gate dielectric layer of this disclosure. Those skilled in the art may select or adjust the material of the gate dielectric layer 105, all of which fall within the protection scope of this disclosure.

[0066] The N-type transistor 100 based on nanomaterials disclosed herein, due to the first surface of its substrate 101 (i.e. Figure 1 The upper surface of the electrode 104 is hydrophobically treated to prevent oxidation of the bottom of the low-power function metal electrode 104 (or reduce the probability of oxidation of the bottom of the low-power function metal electrode 104), thereby improving the contact quality between the metal electrode and the semiconductor nanomaterial layer of the nanomaterial and enabling high-performance and high-yield N-type transistors and CMOS circuits.

[0067] Figure 9 The images show TEM (transmission electron microscopy) characterization of the oxidation at the bottom of the contact metal (metal electrode) of an N-type transistor based on an untreated hydrophobic substrate and an array of carbon nanotubes. Image (a) is the TEM image, and image (b) is the oxygen distribution map for the corresponding region in image (a). In both images (a) and (b), the area to the left of the white line represents the contact area without carbon nanotubes, while the area to the right of the white line represents the contact area with CNTs. It is clearly visible that the contact metal above the CNTs is oxidized.

[0068] Figure 10 Figure (a) shows a schematic diagram of a substrate that has not undergone hydrophobic treatment exhibiting hydrophilicity. Figure 10 Figure (b) is a schematic diagram showing the hydrophobicity of the substrate after hydrophobic treatment.

[0069] With a hydrophilic substrate, external water and oxygen can easily enter the bottom of the contact metal along the carbon nanotubes, causing the bottom of the contact metal to be oxidized; with a hydrophobic substrate, external water and oxygen cannot enter the bottom of the contact metal, thus avoiding oxidation of the bottom of the contact metal.

[0070] Figure 11This is a schematic diagram comparing the on-state current and yield of an N-type transistor based on a hydrophobically treated substrate and an N-type transistor based on an untreated substrate.

[0071] Depend on Figure 11 It can be seen that the N-type transistor based on the hydrophobic substrate layer disclosed herein has a high on-state current and a high yield.

[0072] This disclosure also provides an integrated circuit device, including: an N-type transistor 100, wherein the N-type transistor 100 is a nanomaterial-based N-type transistor 100 according to any embodiment of this disclosure.

[0073] The integrated circuit device includes a CMOS circuit / device, which includes an N-type transistor 100 based on nanomaterials according to any embodiment of the present disclosure.

[0074] Figure 12 This is a schematic flowchart of a method for fabricating an N-type transistor according to one embodiment of the present disclosure.

[0075] refer to Figure 12 The method for fabricating an N-type transistor in this embodiment, S100, includes the following steps: S102, Perform hydrophobic treatment on the first surface of the substrate layer 101; S104. A semiconductor material layer 103 is formed on the first surface that has undergone hydrophobic treatment; S106. Deposit metal materials in the first and second regions of the semiconductor material layer to form the source electrode and drain electrode, respectively. S108. Deposit insulating material between the first region and the second region to form a gate dielectric layer; S110. A gate electrode is formed on the gate dielectric layer.

[0076] In the preferred embodiment of the N-type transistor fabrication method S100 of this disclosure, the hydrophobic treatment described in this disclosure includes: A hydrophobic material layer 102 is formed on the first surface of the substrate layer 101.

[0077] The following text combines Figures 2 to 8 The fabrication process of an N-type transistor 100 according to one embodiment of the present disclosure will be described in detail.

[0078] refer to Figure 2 First, a substrate layer 101 is prepared. The substrate layer 101 can be made of materials such as silicon wafer, quartz, sapphire, or diamond.

[0079] Figure 2 Figure (a) is a schematic diagram of a longitudinal cross-section. Figure 2Figure (b) is a top view.

[0080] refer to Figure 3 The substrate 101 is subjected to hydrophobic treatment. Preferably, a hydrophobic material layer 102 is formed on the first surface (i.e. the upper surface) of the substrate 101. The hydrophobic material layer 102 may be hexamethyldisilazane (HMDS).

[0081] Figure 3 Figure (a) is a schematic diagram of a longitudinal cross-section. Figure 3 Figure (b) is a top view.

[0082] refer to Figure 4 A semiconductor material layer 103 is formed on the hydrophobic material layer 102. In this embodiment, the semiconductor material layer 103 is an array of carbon nanotubes. The array of carbon nanotubes can be formed on the hydrophobic material layer 102 by deposition or pulling.

[0083] Figure 4 Figure (a) is a schematic diagram of a longitudinal cross-section. Figure 4 Figure (b) is a top view.

[0084] refer to Figure 5 The active region of the arrayed carbon nanotubes is patterned to form a semiconductor channel region. Patterning of the active region of the arrayed carbon nanotubes can be performed using photolithography and etching techniques.

[0085] Figure 5 Figure (a) is a schematic diagram of a longitudinal cross-section. Figure 5 Figure (b) is a top view.

[0086] refer to Figure 6 Low-power-function metals are deposited in the source and drain regions above the semiconductor channel region to form a first metal electrode 104 and a second metal electrode 104, namely the source electrode and the drain electrode.

[0087] Figure 6 Figure (a) is a schematic diagram of a longitudinal cross-section. Figure 6 Figure (b) is a top view.

[0088] refer to Figure 7 A gate dielectric layer 105 is prepared. The gate dielectric layer 105 can be formed by atomic layer deposition or other methods. The material of the gate dielectric layer 105 can be HfO2, Y2O3 or other insulating materials.

[0089] Figure 7 Figure (a) is a schematic diagram of a longitudinal cross-section. Figure 7 Figure (b) is a top view.

[0090] refer to Figure 8A gate electrode 106 is fabricated on the gate dielectric layer 105. The gate electrode 106 can be formed by thin film growth, photolithography and etching methods.

[0091] Figure 8 Figure (a) is a schematic diagram of a longitudinal cross-section. Figure 7 Figure (b) is a top view.

[0092] go through Figures 2 to 8 The preparation process prepared the following: Figure 1 The present disclosure shows an N-type transistor 100 based on nanomaterials.

[0093] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0094] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0095] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. An N-type transistor based on nanomaterials, characterized in that, include: Substrate layer; A semiconductor material layer disposed on the substrate layer for forming a semiconductor channel region; A first metal electrode is disposed on the semiconductor material layer to form a source electrode; as well as A second metal electrode is disposed on the semiconductor material layer to form a drain electrode; Both the first metal electrode and the second metal electrode are formed of a low power function metal or an alloy of low power function metals; The bottom of the metal electrode is in contact with the semiconductor material layer, and a hydrophobic material layer is disposed between the substrate layer and the semiconductor material layer to prevent the bottom of the metal electrode from being oxidized; The hydrophobic material layer has a coverage area on the substrate that is greater than or equal to the coverage area of ​​the semiconductor material layer; The first metal electrode and the second metal electrode are spaced apart on the semiconductor material layer along a first direction. Both the first metal electrode and the second metal electrode have an extension dimension in a second direction. Both ends of the metal electrode in the second direction extend into the hydrophobic material layer. Among them, the first direction and the second direction are mutually perpendicular directions; The semiconductor material layer is formed by an array of carbon nanotubes.

2. The N-type transistor based on nanomaterials according to claim 1, characterized in that, The low power function metal includes one of scandium, yttrium, aluminum, titanium, and calcium.

3. The N-type transistor based on nanomaterials according to claim 1, characterized in that, The alloy of the low power function metal includes alloys formed from two or more of scandium, yttrium, aluminum, titanium, and calcium.

4. The N-type transistor based on nanomaterials according to claim 1, characterized in that, The arrayed carbon nanotubes are either two-dimensional or three-dimensional arrayed carbon nanotubes.

5. The N-type transistor based on nanomaterials according to claim 1, characterized in that, The N-type transistor also includes: A gate electrode, formed between the first metal electrode and the second metal electrode, and located above the semiconductor channel region of the semiconductor material layer; and A gate dielectric layer is formed at least between the gate electrode and the semiconductor material layer, between the gate electrode and the first metal electrode, and between the gate electrode and the second metal electrode.

6. The N-type transistor based on nanomaterials according to claim 5, characterized in that, The material of the gate dielectric layer includes HfO2 or Y2O3.

7. An integrated circuit device, characterized in that, include: The N-type transistor is the nanomaterial-based N-type transistor according to any one of claims 1 to 6.

8. A method for fabricating an N-type transistor according to any one of claims 1 to 6, characterized in that, Includes the following steps: The first surface of the substrate layer is treated with a hydrophobic coating; A semiconductor material layer is formed on the first surface that has undergone hydrophobic treatment; Metal materials are deposited in the first and second regions of the semiconductor material layer to form the source electrode and drain electrode, respectively. An insulating material is deposited between the first region and the second region to form a gate dielectric layer; A gate electrode is formed on the gate dielectric layer; The hydrophobic treatment includes: A hydrophobic material layer is formed on the first surface of the substrate layer; Both the source electrode and the drain electrode are formed of low power function metal materials or alloys of low power function metal materials.

Images