Method, apparatus, and system for replacing values in a device

Abstract

One example apparatus includes a processor (930) and a replacement generator (110) coupled to the processor (930) and configured to detect an access by the processor (930) to a first instruction at a first address in a first memory (130), compare the first address to a set of trigger instruction address records in a second memory (135) in response to the detected access, wherein the set of trigger instruction address records includes a first trigger instruction address record (912) associated with a first replacement address record (914) and a first replacement value record (916), and replace a first value specified by the first replacement address record (912) at a second address in a third memory with a second value specified by the first replacement value record (916) based on the first address corresponding to the first trigger instruction address record (912).

Description

[0001] This description generally relates to electronic devices, and more specifically, to methods, apparatus, and systems for replacing values ​​in devices. Background Technology

[0002] Many devices use bootloader instruction sequences. Bootloader instructions can be used in applications to provide initialization instructions to the device, such as configuration values, instructions for initializing peripheral devices, or instructions for loading additional instructions from another memory. Bootloader instructions can access values ​​stored in memory (e.g., processor registers). For example, a first instruction can store a first value in memory, and a second instruction can store a second value in memory. The bootloader instructions can then access the first value, access the second value, and generate a third value by adding the first and second values. A third instruction can then store the third value in memory and / or provide the third value to peripheral electronic devices. In some applications, bootloader instructions can execute after the device is powered on. Attached Figure Description

[0003] Figure 1 This is a block diagram illustrating the usage environment of an instance replacement generator used to correct values ​​in memory.

[0004] Figure 2 It is an instance instruction data table that represents the instance instruction stored at the instance address in memory.

[0005] Figure 3 It is a flowchart representing machine-readable instructions that can be executed to implement an instance instruction processor.

[0006] Figure 4 This is a block diagram of an instance replacement generator used to correct values ​​in memory.

[0007] Figure 5 This is a diagram illustrating the instance trigger data table, which includes instance trigger instruction address records, instance trigger replacement address records, and instance trigger value records.

[0008] Figure 6 This is a flowchart representing machine-readable instructions that can be executed to implement instances that replace the generator.

[0009] Figure 7 This represents an instance that can be executed to replace the generator. Figure 6 The example part of the code block of machine-readable instructions described in the document.

[0010] Figure 8 It is an instance memory data table representing the instance value stored at the instance address in memory, which will be corrected by the instance replacement generator.

[0011] Figure 9 This is a block diagram illustrating an instance use case that includes an instance replacement generator and instance operations performed to replace values ​​in memory.

[0012] Figure 10 This is a flowchart representing machine-readable instructions that can be executed to implement instances that replace the generator.

[0013] Figure 11 It is an instance memory data table representing the instance value stored at the instance address in memory, which will be corrected by the instance replacement generator.

[0014] Figure 12 It is constructed to execute Figure 3 , 6 A block diagram of an instance processor platform that implements instance replacement generators with instructions of type 10 and / or 10. Detailed Implementation

[0015] The accompanying drawings are not to scale. Generally, the same reference numerals in the drawings and this description refer to the same or similar parts. When identifying multiple elements or components that can be individually mentioned, the descriptors “first,” “second,” “third,” etc., are used herein. Unless otherwise specified or understood based on the context, such descriptors do not impose any priority, physical order, or arrangement meaning or chronological order meaning in the list, but are merely used as labels to individually refer to multiple elements or components to facilitate understanding of the described instance. In some instances, the descriptor “first” may be used to refer to an element in the detailed description, while the same element in the claims may be referred to using different descriptors (e.g., “second” or “third”). In such examples, the use of such descriptors is merely for convenience in referring to multiple elements or components.

[0016] When the device is started or powered on, it may need to apply configuration settings and / or execute instructions to initialize (e.g., configure) device functionality. For example, the device may include an accelerometer for tracking the device's acceleration, and when the accelerometer is powered on, it may need to provide configuration commands (e.g., sensor sensitivity settings) to the accelerometer. The instructions may first store the value of the configuration command in memory (e.g., a processor register), then load the value from memory, and then provide the value to the accelerometer.

[0017] Bootloader instructions may contain machine-readable instructions that execute at device startup. In some applications, bootloader instructions may instruct the device to transmit instructions and / or configuration commands to connected devices via an interconnect bus. For example, the device may send a command to an accelerometer instructing it to enter a low-power mode. In other applications, bootloader instructions may contain machine-readable instructions for initializing machine components, such as the initialization process of an operating system. Bootloader instructions may be stored in non-volatile memory (e.g., read-only memory (ROM)) and the sequence of bootloader instructions stored in ROM cannot be modified.

[0018] The bootloader instructions can access and / or modify configuration values. For example, a command to instruct the accelerometer to enter low-power mode can be stored at an address in memory. The configuration values ​​for the bootloader instructions can be stored in memory separate from the non-volatile memory (e.g., processor registers, random access memory, or hard disk drive) that stores the bootloader instructions. For example, the bootloader instructions can be stored in non-volatile memory, and the bootloader instructions include sending a command to the accelerometer. The value of the command to be sent can be stored in a second memory, which can be volatile memory, and the bootloader instructions can include a first instruction for accessing the command value in the volatile memory and a second instruction for providing the command value to the accelerometer.

[0019] During the device's lifetime, replacing (e.g., correcting) the bootloader process can be beneficial. In some instances, values ​​used during the bootloader process may be replaced (e.g., corrected). For example, if a second accelerometer replaces a first accelerometer, and the second accelerometer requires an initialization command value different from that of the first accelerometer, then a correction can be applied to the bootloader process to enable the functionality of the second accelerometer. Because the bootloader instructions stored in ROM cannot be modified, changes to the bootloader instructions can be costly in terms of hardware revisions. In some cases, the device may lose functionality if correction of the bootloader process is not available. In other cases, hardware revisions may increase overhead to support the device's features.

[0020] However, the instruction processor executing the bootloader procedure may include a replacement generator to replace stored and / or accessed values ​​(e.g., correcting initialization command values) during the bootloader procedure. For example, the bootloader procedure may include a first instruction for accessing an initialization command value from a first address in volatile memory and a second instruction for providing the initialization command value to the device. The first instruction may be located at a second address in non-volatile memory, and the second instruction may be located at a third address in non-volatile memory. The instruction processor may identify the first instruction as the instruction to be executed. Before executing the first instruction, the replacement generator may determine whether to perform a replacement of the value stored in volatile memory. The replacement generator may determine whether to perform the replacement by accessing a trigger instruction address, determining the address where the first instruction is located (e.g., from the program counter), and determining whether the trigger instruction address matches (e.g., equals, points to, corresponds to) the address of the first instruction. To perform the replacement of the initialization command value, the replacement generator may access a trigger replacement address (e.g., a pointer to the location of the initialization command value) and a trigger value (e.g., the replacement initialization command value). The replacement generator can replace the initialization command value with a trigger value (for example, triggering the replacement address to point to the value).

[0021] After the replacement generator replaces the initialization command value with a trigger value, the execution unit contained in the instruction processor can execute a first instruction. Since the initialization command value has been corrected before the execution of the first instruction, the bootloader procedure accesses the updated value of the initialization command value (e.g., the trigger value) and executes further instructions based on the updated value. For example, the execution unit can execute a second instruction to provide the updated initialization command value to a peripheral device.

[0022] As used herein, the phrases “correction / to correct” and “update” (including variations thereof) encompass replacing a value stored at an address with a new value. For example, correction may involve replacing a value (e.g., initialization command value 30) at an address (e.g., address 93 in volatile memory) with a replacement value (e.g., initialization command value 32). In some instances described herein, the trigger replacement address and trigger value used during the correction process are stored in a third memory separate from the second memory storing the value to be corrected. However, any other method for storing the address and value used during the correction process may be used alternatively or separately. For example, the address and value used during the correction process may be stored in the second memory storing the value to be corrected. Furthermore, the instances described herein are not limited to replacing a value stored at an address. For example, additional and / or substitution instructions may be executed during the substitution process used to replace the value.

[0023] In some instances, the bootloader process may include instructions to read values ​​stored in memory via an interconnect bus. Before the instruction processor accesses the values ​​stored in memory, a replacement generator may provide an interrupt request to the instruction processor. In response to receiving the interrupt request, the instruction processor may replace the value to be accessed, and then the instruction processor may access the replaced value in memory. For example, the bootloader process may include instructions for accessing a value (e.g., an initialization command value) stored at an address in memory. To access the value, the instruction processor may provide a transaction to memory, the transaction containing a transaction address pointing to the address of the value. The replacement generator may determine whether to perform a value replacement. The replacement generator may determine whether to perform a replacement by accessing the trigger transaction address, accessing the transaction address, and determining whether the trigger transaction address matches the transaction address. The replacement generator may provide an interrupt request to the instruction processor. The instruction processor accesses the trigger replacement address (e.g., a pointer to the location of the value to be replaced) and the trigger value (e.g., the replacement value). The instruction processor (e.g., an execution unit) provides a transaction on the interconnect bus to update the value pointed to by the trigger replacement address with the trigger value. The instruction processor can then access the updated value by providing a second transaction to memory via the interconnect bus.

[0024] Figure 1 This is a block diagram illustrating an instance usage environment 100 containing an instance replacement generator 110 for correcting values ​​in memory. Figure 1 The environment 100 includes an instance instruction processor 120, an instance non-volatile memory 130, and an instance volatile memory 135. The instruction processor 120 includes a replacement generator 110, an instance program counter 140, and an instance execution unit 150.

[0025] Program counter 140 identifies the instruction to be executed. In the example described herein, program counter 140 identifies the instruction to be executed by incrementing a value (e.g., a counter or pointer) in a register indicating the address where the instruction is located. For example, a first instruction may be located at a first address (e.g., address 4 in non-volatile memory 130), and a second instruction may be located at a second address (e.g., address 5 in non-volatile memory 130). Program counter 140 can identify that the first instruction will be executed. After the first instruction is executed, program counter 140 may increment the value in the register (e.g., the register value increments from 4 to 5), and program counter 140 may indicate that a second instruction will be executed. However, any other methods for determining the next instruction to be executed may be used additionally and / or alternatively.

[0026] For example, the first instruction may be located at a first address (e.g., address 4 in non-volatile memory 130), the second instruction may be located at a second address (e.g., address 5 in non-volatile memory 130), and the third instruction may be located at a third address (e.g., address 10 in non-volatile memory 130). The program counter 140 may identify the first instruction as the instruction to be executed. Before executing the first instruction, the program counter 140 may increment the value of a register (e.g., the register value increments from 4 to 5), and then executing the first instruction may update the value in the register (e.g., in a jump instruction, the register value increments from 5 to 10). The program counter 140 may then indicate that the third instruction is the instruction to be executed, rather than the second instruction.

[0027] For example, Figure 1 The program counter 140 in the illustrated example is implemented by logic circuitry, for example, a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of such a system, such as one or more analog or digital circuits, logic circuits, programmable processors, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable logic devices (FPLDs), digital signal processors (DSPs), graphics processing units (GPUs), etc.

[0028] Replacement generator 110 determines whether a replacement (e.g., correction) should be performed. If replacement generator 110 determines that correction should be performed, then replacement generator 110 performs the replacement (e.g., correction). In some instances, determining whether correction should be performed involves identifying whether a trigger instruction address record corresponds to an instruction address. The trigger instruction address record may contain a trigger instruction address, and replacement generator 110 may determine whether the trigger instruction address matches the address of the instruction to be executed. For example, program counter 140 may identify an instruction to be executed located at an address in non-volatile memory 130. Replacement generator 110 may determine whether the trigger instruction address contained in the trigger instruction address record matches or is equal to the address of the instruction.

[0029] The instruction address is the address where the instruction identified by program counter 140 is stored. Replacement generator 110 determines whether the trigger instruction address associated with the trigger instruction address record corresponds to the instruction address. However, any other methods for determining whether a correction should be performed may be used additionally and / or alternatively. In some instances, replacement generator 110 may determine whether a replacement should be performed by accessing a transaction on the interconnect bus (which contains a transaction address), accessing the trigger transaction address, and determining whether the trigger transaction address matches the transaction address.

[0030] In the examples described herein, when correction is performed, replacement generator 110 accesses the address where the value is located (e.g., the trigger replacement address), accesses the correction value (e.g., the trigger value), and replaces the value with the correction value. In other words, replacement generator 110 replaces the value at the address in memory with the correction value. The value at the first address may be located in a first memory (e.g., volatile memory 135), and the correction value may be located in a second memory different from the first memory (e.g., memory contained in replacement generator 110). Any other methods for performing correction may be used additionally and / or alternatively. For example, replacement generator 110 may provide execution unit 150 with at least one instruction for execution. In another example, replacement generator 110 replaces multiple values ​​stored in volatile memory 135 with multiple correction values. In another example, replacement generator 110 may provide an interrupt request to program counter 140 and / or execution unit 150, and instruction processor 120 may access the trigger replacement address and the trigger value, and then replace the value stored at the trigger replacement address with the trigger value. In some instances, replacement generator 110 may be configured to replace a value stored in volatile memory 135 by issuing an interrupt to a processor configured to store a replacement value at an address specified by the replacement value record. Replacement generator 110 may cause the processor to store the replacement value at the address specified by the replacement value record by issuing an interrupt (e.g., by providing an interrupt request).

[0031] For example, Figure 1 The alternative generator 110 of the illustrated example is implemented by logic circuitry, for example, a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of other circuitry, such as one or more analog or digital circuits, logic circuits, programmable processors, ASICs, PLDs, FPLDs, programmable controllers, GPUs, DSPs, etc.

[0032] Execution unit 150 executes instructions recognized by program counter 140. In the example described herein, execution unit 150 executes at least one instruction recognized by program counter 140. However, execution unit 150 may execute more than one instruction recognized by program counter 140. For example, execution unit 150 may execute a first instruction recognized by program counter 140, and then execution unit 150 may execute a second instruction not recognized by program counter 140.

[0033] For example, Figure 1 The execution unit 150 of the illustrated example is implemented by logic circuitry, such as that of a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of such a system, such as one or more analog or digital circuits, logic circuits, programmable processors, ASICs, PLDs, FPLDs, programmable controllers, GPUs, DSPs, etc.

[0034] Figure 1 The non-volatile memory 130 in the illustrated example is implemented by any memory, storage device, and / or storage disk for storing data, such as eFuse, flash memory, magnetic media, optical media, solid-state memory, hard disk drive, thumb drive, etc. Furthermore, the data stored in the non-volatile memory 130 can be in any data format, such as binary data, comma-separated data, tab-separated data, Structured Query Language (SQL) structures, etc. Although in the illustrated example, the non-volatile memory 130 is described as a single device, the non-volatile memory 130 and / or any other data storage device described herein can be implemented by any number and / or type of memory. Figure 1 In the illustrated example, non-volatile memory 130 stores instructions that will be processed by instruction processor 120. Instructions may be stored in non-volatile memory 130 during device assembly.

[0035] Figure 1 The volatile memory 135 in the illustrated example is implemented by any memory, storage device, and / or storage disk for storing data, such as eFuse, flash memory, magnetic media, optical media, solid-state memory, hard disk drive, thumb drive, etc. Furthermore, the data stored in the volatile memory 135 can be in any data format, such as binary data, comma-separated data, tab-separated data, Structured Query Language (SQL) structures, etc. Although the volatile memory 135 is described as a single device in the illustrated example, the volatile memory 135 described herein can be implemented by any number and / or type of memory. Figure 1 In the illustrated examples, volatile memory 135 stores values ​​that can be replaced by the replacement generator 110 with a correction value. In some examples, volatile memory 135 may store trigger instruction addresses, trigger transaction addresses, trigger replacement addresses, and / or trigger values. In some examples, volatile memory 135 may include RAM, storage devices (such as hard disk drives or solid-state drives), central processing unit caches, one or more processor registers, etc.

[0036] Although Figure 3 , 6 and / or 10 instructions for implementation Figure 1 The instance method of the instruction processor 120, but Figure 3 , 6 And / or one or more elements, processes and / or devices described in 10 may be combined, divided, rearranged, omitted, eliminated and / or implemented in any other way. Furthermore, Figure 1The instance program counter 140, instance execution unit 150, instance replacement generator 110, and more generally instance instruction processor 120 may be implemented in hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Therefore, for example, any of the instance program counter 140, instance execution unit 150, instance replacement generator 110, and more generally instance instruction processor 120 may be implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controllers, graphics processing units (GPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (PLDs), and / or field-programmable logic devices (FPLDs). When reading any of the device or system claims of this patent to cover purely software and / or firmware implementations, at least one of the instance program counter 140, instance execution unit 150, and / or instance replacement generator 110 is hereby expressly defined as comprising a non-transitory computer-readable storage device or storage disk including software and / or firmware, such as a memory, digital versatile optical disc (DVD), optical disc (CD), Blu-ray disc, etc. Further... Figure 1 The instance instruction processor 120 may include, except Figure 3 , 6 and / or one or more elements, processes and / or devices other than those described in 10, or which may replace them. Figure 3 , 6 And / or the elements, processes and apparatus described in 10, and / or may include more than one of any or all of the elements, processes and apparatus described. As used herein, the phrase “in communication” (including variations thereof) covers direct and / or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but additionally includes selective communication at periodic time intervals, predetermined intervals, non-periodic intervals and / or one-off events.

[0037] Figure 2 This is an instance instruction data table 200 representing an instance instruction 210 stored at instance address 215 in memory (e.g., non-volatile memory 130). The instruction data table 200 contains address 215 (e.g., an address to a location in non-volatile memory 130) and instruction 210 (e.g., an instruction stored in non-volatile memory 130). Address 215 indicates the address in memory (e.g., non-volatile memory 130) where instruction 210 is stored.

[0038] In the examples described herein, the instructions are machine-readable instructions (e.g., opcodes, machine code, or operations in a compiled computer program), and execution unit 150 executes instructions 210 to ensure device functionality. For example, an electronic device may execute instructions 210 to access acceleration values ​​from an accelerometer. In another example, an electronic device may execute instructions 210 to provide data requested by another device on an interconnect bus. In some instances, instructions 210 may be compiled from a computer program written in a language such as C, C++, assembly language, Swift, etc. Instructions 210 may be generated (e.g., compiled) and stored in memory (e.g., non-volatile memory 130) prior to device assembly. However, instructions 210 may be stored in any additional and / or alternative memory. Instructions 210 may be generated and / or stored in memory during and / or after device assembly.

[0039] exist Figure 2 The example illustrated shows six instruction lines. Each instruction line represents the instruction to be executed by execution unit 150 and the address where the instruction is located (e.g., in non-volatile memory 130). The first instruction line 216 represents instruction 44 stored at address 0. The second instruction line 218 represents instruction 55 stored at address 1. The third instruction line 220 represents instruction 3 stored at address 2. The fourth instruction line 230 represents instruction 55 stored at address 3. The fifth instruction line 240 represents instruction 80 stored at address 4. The sixth instruction line 250 represents instruction 82 stored at address 5.

[0040] The address contained in each of instruction lines 216, 218, 220, 230, 240, and 250 indicates an address in the memory where the instruction is stored. For example, the first instruction line 216 indicates that instruction 44 is stored at address 0 in non-volatile memory 130. Similarly, the second instruction line indicates that instruction 80 is stored at address 4. In the example described herein, instruction 210 is located in non-volatile memory 130. For example, instruction 44 contained in the first instruction line 216 is stored at address 0, and address 0 is located in non-volatile memory 130. However, instruction 210, which will be processed by instruction processor 120, can be stored in any suitable memory, such as volatile memory 135. Although in Figure 2 In the illustrated example, instruction 210 is represented as a two-bit integer, but instructions may additionally and / or alternatively contain any other form. For example, instructions may contain additional information, such as additional machine-readable instructions, instruction parameters, etc. In another example, an instruction may be represented as two 32-bit integers.

[0041] Although Figure 2The illustrated example shows six instruction lines, but the instruction data table 200 can contain any other number of lines. For example, the non-volatile memory 130 can store ten thousand instructions, and the instruction data table 200 can contain ten thousand lines to represent the instructions. Although in Figure 2 In the example described, address 215 and instruction 210 are represented as two-bit integers, but address 215 and instruction 210 can be formatted in any other way. For example, instruction 210 can be formatted as a 64-bit integer.

[0042] Figure 3 , 6 and / or 10 representatives are shown for implementation Figure 1 The instruction processor 120 includes an example of hardware logic, machine-readable instructions, a hardware-implemented state machine, and / or any combination thereof, as shown in the flowchart. Machine-readable instructions may be one or more executable programs or portions thereof for execution by a computer processor, for example, in conjunction with the following... Figure 12 The processor 1212 shown in the described example processor platform 1200. Programs may be embodied in software stored on non-transitory computer-readable storage media, such as CD-ROM, floppy disk, hard disk, DVD, Blu-ray disc, or memory associated with the processor 1212, but the entire program and / or portions thereof may also be executed by a device other than the processor 1212 and / or embodied in firmware or dedicated hardware. Furthermore, although references... Figure 3 The flowcharts illustrated herein describe the example program, but many other methods of implementing the example instruction processor 120 may be used instead. For example, the execution order of the blocks may be changed, and / or some of the described blocks may be altered, eliminated, or combined. Furthermore or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers, logic circuits, etc.) constructed to perform the corresponding operations without executing software or firmware.

[0043] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, packaged format, etc. The machine-readable instructions described herein can be stored as data (e.g., portions of instructions, code, code representation, etc.) that can be used to create, manufacture, and / or produce machine-executable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices and / or computing devices (e.g., servers). Machine-readable instructions may require one or more of the following to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, redistributed, compiled, etc., to make them directly readable, interpretable, and / or executable by computing devices and / or other machines. For example, machine-readable instructions can be stored in multiple parts, which are individually compressed, encrypted, and stored on separate computing devices, wherein these parts, when decrypted, decompressed, and combined, form a set of executable instructions that implement a program such as the program described herein.

[0044] In another instance, machine-readable instructions may be stored in a computer-readable state, but require the addition of libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., to execute the instructions on a specific computing device or other device. In yet another instance, the machine-readable instructions and / or their corresponding programs may need to be configured (e.g., storing settings, inputting data, recording network addresses, etc.) before they can be fully or partially executed. Therefore, the described machine-readable instructions and / or their corresponding programs encompass such machine-readable instructions and / or programs regardless of their specific format or state when stored or otherwise stored or transmitted.

[0045] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0046] As mentioned above, Figure 3 , 6The instance process of and / or 10 may be implemented using executable instructions (e.g., computer and / or machine-readable instructions) stored on non-transitory computer and / or machine-readable media (e.g., hard disk drives, flash memory, read-only memory, optical discs, digital multifunction disks, caches, random access memory, and / or any other storage device or storage disk), wherein information may be stored for any duration (e.g., long-term, permanent, transient, temporary buffered, and / or cached information). As used herein, the term non-transitory computer-readable media is explicitly defined to include any type of computer-readable storage device and / or storage disk, excluding propagation signals and transmission media.

[0047] "Comprising" and "including" (and all forms and tenses thereof) are open-ended terms. Therefore, whenever a claim uses any form of "comprising" or "including" (e.g., including, comprising, having, etc.) in the preamble or in any kind of claim statement, additional elements, terms, etc., may be present without exceeding the scope of the corresponding claim or statement. As used herein, the phrase "at least" is open-ended when used as a transitional term, for example, in the preamble of a claim, in the same way that the terms "comprising" and "including" are open-ended. For example, when the term "and / or" is used in the form of, for example, A, B, and / or C, it refers to any combination or subset of A, B, and C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, and (7) A, B, and C. As used herein in the context of describing structures, components, projects, objects, and / or things, the phrase "at least one of A and B" means an implementation comprising (1) at least one A, (2) at least one B, and (3) any one of at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, projects, objects, and / or things, the phrase "at least one of A or B" means an implementation comprising (1) at least one A, (2) at least one B, and (3) any one of at least one A and at least one B. As used herein in the context of describing the performance / execution of processes, instructions, actions, activities, and / or steps, the phrase "at least one of A and B" means an implementation comprising (1) at least one A, (2) at least one B, and (3) any one of at least one A and at least one B. Similarly, as used herein in the context of describing the execution of processes, instructions, actions, activities and / or steps, the phrase “at least one of A or B” refers to an implementation that includes (1) at least one A, (2) at least one B, and (3) any one of at least one A and at least one B.

[0048] As used herein, singular references (e.g., "a / an", "first", "second", etc.) do not exclude plurals. The term "a / an" as used herein refers to one or more of the entities. The terms "a / an", "one or more", and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or method actions may be implemented by, for example, a single unit or processor. Moreover, although individual features may be included in different instances or claims, these features may be combined, and inclusion in different instances or claims does not imply that the combination of features is unfeasible and / or advantageous.

[0049] Figure 3 This represents a processor that can execute instance instructions (e.g., Figure 1 The flowchart shows the machine-readable instructions 300 of the instruction processor 120. The program counter 140 identifies the instruction to be executed (box 310). In some instances described herein, the program counter 140 identifies the instruction to be executed by incrementing a counter indicating the address where the instruction is stored in non-volatile memory 130. For example, if an instruction previously identified as to be executed is located at address 0, then the program counter 140 may determine that the instruction to be executed is located at address 1. However, any other methods for determining the instruction to be executed may be used additionally and / or alternatively. For example, if a previous instruction was located at address 5, then the program counter 140 may determine that the instruction to be executed is located at address 3. In some instances, the instruction to be executed may be stored at an address in memory separate from non-volatile memory 130. For example, the instruction may be stored in volatile memory 135. In some instances, the program counter 140 may use an instruction previously identified as to be executed to identify the instruction to be executed. For example, instruction 55 may contain a command to execute an instruction at another location, such as a branch instruction or a jump instruction.

[0050] Replacement generator 110 determines whether a correction should be performed (box 320). If replacement generator 110 determines that a correction should be performed, then replacement generator 110 performs the correction. For example, replacement generator 110 may replace a value stored in volatile memory 135 with a replacement value. In another instance, replacement generator 110 may provide an interrupt request to instruction processor 120. In response to the interrupt request, execution unit 150 may execute at least one instruction to replace the value with the replacement value. In some instances, determining whether a correction should be performed includes identifying whether the trigger instruction address matches an instruction address. The instruction address is the address of the instruction identified by program counter 140. In some instances, determining whether a correction should be performed includes identifying whether the trigger transaction address matches a transaction address contained in a transaction on the interconnect bus. The following is in conjunction with... Figure 5Describe further details regarding the trigger instruction address and the trigger transaction address. Any additional and / or alternative methods for determining whether correction should be performed may be used. For example, replacement generator 110 may determine whether an instruction (e.g., instruction 55) matches a trigger instruction address (e.g., trigger instruction address 55).

[0051] Execution unit 150 executes instructions recognized by program counter 140 (box 350). In the example described herein, execution unit 150 executes individual instructions recognized by program counter 140. However, execution unit 150 may execute more than just instructions recognized by program counter 140. For example, execution unit 150 may execute a first instruction recognized by program counter 140, and then execution unit 150 may execute a second instruction that is not recognized by program counter 140 and is located in non-volatile memory 130.

[0052] In the example described herein, instruction processor 120 first identifies the instruction to be executed, determines whether to perform correction, performs correction, and then executes the identified instruction. However, the instruction processor can identify instructions, determine whether to perform correction, perform correction, and / or execute the identified instruction in any order. For example, instruction processor 120 may first identify the instruction to be executed, execute the identified instruction, determine whether to perform correction, and then perform correction. In other examples, the instruction processor may identify instructions, determine whether to perform correction, perform correction, and / or execute the identified instruction in parallel processes, wherein said processes are performed simultaneously.

[0053] Figure 4 It is an instance replacement generator used to correct values ​​stored in memory (e.g., volatile memory 135). Figure 1 A block diagram of the replacement generator 110. The replacement generator 110 includes an instance trigger controller 410, an instance trigger comparator 430, an instance address accessor 440, an instance value accessor 450, an instance replacement executor 460, and an instance local data storage repository 470.

[0054] Figure 1 The instance replacement generator 110 of and / or 4 is not limited to Figure 1 The instruction processor 120. The replacement generator 110 can be used to replace (e.g., correct) values ​​in components not limited to non-volatile memory 130 and / or volatile memory 135. For example, the replacement generator 110 can correct the operation of non-memory components in environment 100, such as accelerometers, sensors, transducers, or any other suitable devices that can be connected to the instruction processor 120. Furthermore, the replacement generator 110 can instruct the instruction processor 120 to provide alternative instructions that will be recognized by program counter 140 and / or executed by execution unit 150 to perform the correction by providing an interrupt request.

[0055] Trigger controller 410 accesses a trigger instruction address record. In the examples described herein, the trigger instruction address record is associated with an instruction address. For example, an instruction may be stored at an address in non-volatile memory 130, and the associated trigger instruction address record may contain a pointer to the instruction address and / or a trigger instruction address having the same value as the instruction address. In some examples, trigger controller 410 may access a trigger transaction address record. The trigger transaction address record is associated with a transaction provided on the interconnect bus. For example, a transaction may contain a transaction address pointing to a value stored in volatile memory 135, and the associated trigger transaction address record may contain a pointer to the transaction address and / or a trigger transaction address having the same value as the transaction address. For example, Figure 4 The trigger controller 410 in the illustrated example is implemented by logic circuitry, for example, a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of such a system, such as one or more analog or digital circuits, logic circuits, programmable processors, ASICs, PLDs, FPLDs, programmable controllers, GPUs, DSPs, etc.

[0056] Trigger comparator 430 accesses the instruction address identified by program counter 140. Trigger comparator 430 determines whether correction should be performed. In the example described herein, trigger comparator 430 determines whether correction should be performed by comparing the trigger instruction address contained in the trigger instruction address record with the instruction address. The following is in conjunction with... Figure 5 This describes an example implementation of storing trigger instruction address records, trigger replacement address records, and trigger value records. However, other methods for comparing trigger instruction address records with instructions may be used alternatively and / or as well. In some instances, the trigger comparator 430 determines whether a replacement should be performed by comparing the trigger transaction address contained in the trigger transaction address record with the transaction address contained in the transaction. For example, Figure 4 The trigger comparator 430 in the illustrated example is implemented by logic circuitry, for example, a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of other circuitry, such as one or more analog or digital circuits, logic circuits, programmable processors, ASICs, PLDs, FPLDs, programmable controllers, GPUs, DSPs, etc.

[0057] Address accessor 440 accesses the trigger replacement address. If trigger comparator 430 determines that the trigger instruction address corresponds to an instruction address identified by program counter 140, then address accessor 440 accesses the trigger replacement address corresponding to the trigger instruction address record. In the examples described herein, the trigger replacement address corresponds to or points to a value stored in volatile memory 135 to be replaced by replacement generator 110. For example, trigger replacement address 44 may indicate that the value to be replaced is stored at address 44 in volatile memory 135. In some instances, address accessor 440 may access the trigger replacement address corresponding to the trigger transaction address record accessed by trigger controller 410. For example, Figure 4 The address accessor 440 in the illustrated example is implemented by logic circuitry, for example, a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of such a system, such as one or more analog or digital circuits, logic circuits, programmable processors, ASICs, PLDs, FPLDs, programmable controllers, GPUs, DSPs, etc.

[0058] Value accessor 450 accesses the trigger value corresponding to the trigger instruction address record. If trigger comparator 430 determines that the trigger instruction address corresponds to an instruction address identified by program counter 140, then value accessor 450 accesses the trigger replacement address corresponding to the trigger instruction address record. In some instances, value accessor 450 may access the trigger replacement address corresponding to the trigger transaction address record accessed by trigger controller 410. For example, Figure 4 The value accessor 450 of the illustrated example is implemented by logic circuitry, for example, a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of such implementation, such as one or more analog or digital circuits, logic circuits, programmable processors, ASICs, PLDs, FPLDs, programmable controllers, GPUs, DSPs, etc.

[0059] Replacement actuator 460 replaces (e.g., corrects) the value stored at an address in memory. Replacement actuator 460 corrects the value stored (e.g., pointing to) the trigger replacement address with a trigger value. In the example described herein, the trigger replacement address is accessed by address accessor 440, and the trigger value is accessed by value accessor 450. The following is in conjunction with... Figure 8 An instance memory data table describes the values ​​corrected by the replacement executor 460. In some instances, the replacement generator 110 may provide an interrupt request to the instruction processor 120. The instruction processor 120 may access the interrupt request and replace the value stored at the address pointed to by the trigger replacement address with the trigger value. For example, Figure 4The alternative actuator 460 in the illustrated example is implemented by logic circuitry, for example, a hardware processor. However, any other type of circuit system may be used, for example, one or more analog or digital circuits, logic circuits, programmable processors, ASICs, PLDs, FPLDs, programmable controllers, GPUs, DSPs, etc.

[0060] For example, Figure 4 The instance local data repository 470 described herein is implemented using any memory, storage device, and / or storage disk for storing data, such as eFuse, flash memory, magnetic media, optical media, solid-state storage, hard disk drive, thumb drive, etc. Furthermore, the data stored in the instance local data repository 470 can be in any data format, such as binary data, comma-separated data, tab-separated data, Structured Query Language (SQL) structures, etc. Although the instance local data repository 470 is described as a single device in the illustrated example, the instance local data repository 470 and / or any other data storage device described herein can be implemented using any number and / or type of memory. For example, the local data repository 470 can be implemented using one or more eFuses. Figure 4 In the example described, instance local data repository 470 stores trigger instruction address records, trigger transaction address records, trigger replacement address records, and trigger value records. The following section combines... Figure 5 Example diagrams illustrating an implementation of the local data repository 470 are provided. In some instances, trigger instruction address records, trigger transaction address records, trigger replacement address records, and / or trigger value records may be stored in volatile memory 135. In some instances, the local data repository 470 may be contained in and / or implemented by volatile memory 135.

[0061] Figure 5This is a diagram illustrating an instance trigger data table 500 containing an instance trigger instruction address record 502, an instance trigger replacement address record 504, and an instance trigger value record 506. The replacement generator 110 accesses the trigger instruction address record 502, the trigger replacement address record 504, and the trigger value record 506 to determine whether a replacement will be performed, the address of the value to be replaced, and / or the replacement value used to update the value when a replacement is performed. In the examples described herein, the trigger instruction address record 502, the trigger replacement address record 504, and the trigger value record 506 are contained (e.g., stored) in a local data repository 470. However, any of the trigger instruction address record 502, the trigger replacement address record 504, or the trigger value record 506 contained in the local data repository 470 may additionally and / or alternatively be contained in any other data repository or memory. For example, a first trigger replacement address record may be contained in volatile memory 135, and a second trigger replacement address record may be stored in the local data repository 470. In some instances, the trigger data table 500 may contain trigger transaction address records.

[0062] In the example described herein, the trigger data table 500 is stored in the local data repository 470 of the replacement generator 110. However, any other methods for storing and / or accessing the trigger data table 500 may be used additionally and / or alternatively. For example, the trigger data table 500 may be stored in volatile memory 135. In another example, a first portion of the trigger data table 500 may be stored in the local data repository 470, and a second portion of the trigger data table 500 may be stored in volatile memory 135.

[0063] The trigger instruction address record contains trigger instruction addresses. A trigger instruction address may correspond to (e.g., equal to, match, point to) the address of an instruction to be executed by execution unit 150. For example, if instruction 44 is stored at address 0 in non-volatile memory 130, as indicated by the first instruction line 216, then trigger instruction address 0 corresponds to address 0. Similarly, if instruction 3 is stored at address 2 in non-volatile memory 130, as indicated by the third instruction line 220, then trigger instruction address 2 corresponds to address 2. In the example described herein, the trigger instruction address record contains trigger instruction addresses that match the address of the instruction stored in non-volatile memory 130. However, a trigger instruction address may correspond to an instruction stored in any memory (e.g., a register in instruction processor 120, volatile memory 135, etc.).

[0064] In some instances, the trigger instruction address record may be a trigger transaction address record, and the trigger instruction address may be a trigger transaction address. A device (e.g., instruction processor 120) may communicate with other devices (e.g., volatile memory 135) by providing transactions on an interconnect bus. As used herein, the phrase "communication" (including variations thereof) encompasses direct and / or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but additionally includes selective communication at periodic time intervals, predetermined intervals, non-periodic intervals, and / or one-off events.

[0065] A transaction may include a transaction type (e.g., a read command, a write command) and a transaction address (e.g., address 92 in volatile memory 135). For example, instruction processor 120 may provide a transaction to volatile memory 135 on an interconnect bus, the transaction including a transaction type indicating a read command and transaction address 92. Volatile memory 135 may respond to the transaction by providing instruction processor 120 with a value located at address 92. A triggering transaction address may correspond to (e.g., equal to, match, point to) an address contained in the transaction (e.g., a transaction address). For example, if a transaction on the interconnect bus includes a transaction type indicating a read command and transaction address 95, then the triggering transaction address 95 corresponds to address 95. Address 95 may be located in volatile memory 135.

[0066] The trigger replacement address record contains trigger replacement addresses. A trigger replacement address may correspond to (e.g., equal to, match to, point to) the address of the value to be replaced (e.g., corrected). In some instances, a trigger replacement address is a pointer to the value to be replaced and stored in memory. For example, if address 3 is located in volatile memory 135, then trigger replacement address 3 points to address 3. In the instance described herein, the trigger replacement address record contains trigger replacement addresses that match the address of the value stored in volatile memory 135 to be replaced by replacement generator 110. However, a trigger replacement address may correspond to (e.g., point to) a value stored in any memory (e.g., a second volatile memory or a register contained in instruction processor 120).

[0067] The trigger value record contains trigger values. A trigger value is a value used to replace another value stored at the address indicated by the trigger replacement address. For example, if the value 0 is stored in volatile memory 135, then trigger value 22 indicates that replacement generator 110 will replace value 0 with trigger value 22. In another instance, if the value 34 is stored at address 93 in volatile memory 135, then the trigger replacement address record contains the trigger replacement address 93, and the trigger value record associated with the trigger replacement address record contains the trigger value 77, and replacement generator 110 can then replace the value 34 stored at address 93 with trigger value 77. Furthermore, if the trigger instruction address record associated with the trigger replacement address record and the trigger value record contains the trigger instruction address 4, then when the address of the instruction identified by program counter 140 matches the trigger instruction address 4, replacement generator 110 can replace value 34 with trigger value 77. The trigger instruction address record, trigger transaction address record, trigger replacement address record, and / or trigger value record may be associated with each other via identifiers, as described below.

[0068] The illustrated example shows four trigger instruction address records, four trigger replacement address records, and four trigger value records. The first example trigger instruction address record 502A contains the identifier "TrigM0" and the first trigger instruction address 2. The second example trigger instruction address record 502B contains the identifier "TrigM1" and the second trigger instruction address 4. The third example trigger instruction address record 502C contains the identifier "TrigM2" and the third trigger instruction address 10. The fourth example trigger instruction address record 502D contains the identifier "TrigM3" and the fourth trigger instruction address 24.

[0069] The first instance-triggered replacement address record 504A contains the identifier "Addr0" and the first triggered replacement address 91. The second instance-triggered replacement address record 504B contains the identifier "Addr1" and the second triggered replacement address 93. The third instance-triggered replacement address record 504C contains the identifier "Addr2" and the third triggered replacement address 99. The fourth instance-triggered replacement address record 504D contains the identifier "Addr3" and the fourth triggered replacement address 97.

[0070] The first instance trigger value record 506A contains the identifier "Val0" and the first trigger value 22. The second instance trigger value record 506B contains the identifier "Val1" and the second trigger value 77. The third instance trigger value record 506C contains the identifier "Val2" and the third trigger value 11. The fourth instance trigger value record 506D contains the identifier "Val3" and the fourth trigger value 88.

[0071] Although Figure 5The illustrated example shows four trigger instruction address records, four trigger replacement address records, and four trigger value records, but any other number of trigger instruction address records, trigger transaction address records, trigger replacement address records, and / or trigger value records may be used additionally and / or alternatively. For example, the local data repository 470 may store two thousand trigger instruction address records, two thousand trigger replacement address records, and two thousand trigger value records. In another example, the trigger data table 500 may contain three trigger transaction address records.

[0072] exist Figure 5 In the illustrated example, each trigger instruction address record is associated with the trigger replacement address record and the trigger instruction record based on the identifier contained in the trigger instruction address record, the trigger replacement address record, and the trigger instruction record. In the example described herein, the records are associated via the last character of the identifier. For example, the identifier “TrigM0” contained in the first trigger instruction address record 502A, the identifier “Val0” contained in the first trigger replacement address record 504A, and the identifier “Val0” contained in the first trigger value record 506A each have the integer “0” as the last character of the identifier. Therefore, the first trigger instruction address record 502A, the first trigger replacement address record 504A, and the first trigger value record 506A are associated. Therefore, if the replacement generator 110 determines that the first trigger instruction address record 502A corresponds to an instruction recognized by the program counter 140 (e.g., the first trigger instruction address contained in the first trigger instruction address record 502A matches the address of the stored instruction), the replacement generator 110 replaces the value stored at the trigger replacement address with the trigger value. Therefore, the replacement generator 110 can replace the value at the first trigger replacement address 91 (e.g., the value at address 91 in volatile memory 135) with the first trigger value 22.

[0073] exist Figure 5In the illustrated example, the identifier “TrigM1” contained in the second trigger instruction address record 502B, the identifier “Addr1” contained in the second trigger replacement address record 504B, and the identifier “Val1” contained in the second trigger value record 506B each contain the character “1” as the last character of the identifier. Therefore, the second trigger instruction address record 502B, the second trigger replacement address record 504B, and the second trigger value record 506B are associated. Similarly, the third trigger instruction address record 502C, the third trigger replacement address record 504C, and the third trigger value record 506C are associated because each identifier contained in records 502C, 504C, and 506C contains the character “3” as the last character of the identifier. Furthermore, the fourth trigger instruction address record 502D, the fourth trigger replacement address record 504D, and the fourth trigger value record 506D are associated because each identifier contained in records 502D, 504D, and 506D contains the character “4” as the last character of the identifier.

[0074] Although Figure 5 In one example, the trigger instruction address record 502, the trigger replacement address record 504, and the trigger value record 506 are associated using the last character of the identifier contained in records 502, 504, and 506, but any other method for associating the trigger instruction address record, trigger transaction address record, trigger replacement address record, and / or trigger value record may be used alternatively or in combination. For example, each of the first trigger instruction address record 502A, the first trigger replacement address record 504A, and the first trigger value record 506A may contain a shared identifier (e.g., “IDENTIFIER01”) to indicate that records 502A, 504A, and 506A are associated. In another example, the trigger data table 500 may contain data structures, such as trigger records, which may contain the first trigger instruction address record 502A, the first trigger replacement address record 504A, and the first trigger value record 506A. The replacement generator 110 can access the trigger records, and records 502A, 504A, and 506A are associated via inclusion in the trigger records.

[0075] In the illustrated example, each trigger instruction address record is associated with a trigger replacement address record and a trigger value record. For example, a first trigger instruction address record 502A is associated with a first trigger replacement address record 504A and a first trigger value record 506A, and a second trigger instruction address record 502B is associated with a second trigger replacement address record 504B and a second trigger value record 506B. However, any number of triggers can be associated with any number of trigger replacement address records and / or any number of trigger value records. For example, each of the first trigger instruction address record 502A, the first trigger replacement address record 504A, the second trigger replacement address record 504B, and the third trigger replacement address record 504C may contain a shared identifier “TRIGGER20”. Therefore, the first trigger replacement address record 504A, the second trigger replacement address record 504B, and the third trigger replacement address record 504C are associated with the first trigger instruction address record 502A. In another example, a trigger instruction address record may contain a pointer to an associated trigger replacement address record (e.g., its memory address) and a pointer to an associated trigger value record.

[0076] In some instances, the trigger data table 500 may be implemented as one or more eFuses. An eFuse may provide a single bit (e.g., a binary number) of memory. In some instances, an eFuse is a memory bit that can be modified and / or written. In some instances, the replacement generator and / or more generally the instruction processor 120 may access records 502, 504, 506 by accessing one or more eFuses.

[0077] Figure 6 This represents an instance that can be executed to replace the generator (e.g., Figure 1 A flowchart of machine-readable instructions for the replacement generator 110 (and / or 4). In some instances, executable... Figure 6 Machine-readable instructions determine whether to perform correction and / or perform correction to replace the value, for example, by Figure 3 Box 320 represents machine-readable instructions. Figure 7 Further explanation Figure 6 Examples. Figure 7 This represents an instance that can be executed to replace the generator (e.g., Figure 1 and / or 4 replacement generator 110) Figure 6 The example portion of code block 700, which describes machine-readable instructions, is shown herein. In the example described herein, a portion of code block 700 contains eight example code lines 705, 708, 710, 715, 720, 725, 730, and 735. However, a portion of code block 700 may contain any number of code lines. For example, a portion of code block 700 may contain one hundred code lines.

[0078] Trigger controller 410 accesses the trigger instruction address record (box 610, line 705). In the example described herein, trigger controller 410 accesses the first trigger instruction address record 502A. However, any other trigger instruction address record may be accessed additionally and / or alternatively. For example, trigger controller 410 may access the third trigger instruction address record 502C.

[0079] Trigger comparator 430 accesses the instruction address identified by program counter 140 (box 620, line 710). Trigger comparator 430 determines whether a correction should be performed. In the example described herein, trigger comparator 430 determines whether a correction should be performed by comparing the trigger instruction address with the instruction address identified by program counter 140. For example, trigger comparator 430 may compare the first trigger instruction address record 502A with the instruction represented by the third instruction line 220 and determine whether trigger instruction address 2 corresponds to instruction address 2. However, other methods for comparing trigger instruction address records and instructions may be used alternatively or separately. For example, trigger comparator 430 may compare the instruction value (e.g., instruction 44 represented by the first instruction line 216) with the trigger instruction address (e.g., trigger instruction address 4 of the second trigger instruction address record 502B).

[0080] If trigger comparator 430 determines that the trigger instruction address corresponds to an instruction address (e.g., box 630 returns YES, line 715 returns TRUE), then address accessor 440 accesses the trigger replacement address corresponding to the trigger instruction address record (box 640, line 720). The trigger replacement address is contained in a trigger replacement address record, and the trigger replacement address record corresponds to the trigger instruction address record using an identifier contained in the record. For example, if the trigger instruction address record is a first trigger instruction address record 502A, then address accessor 440 accesses the trigger replacement address 91 contained in the first trigger replacement address record 504A. In another instance, if the trigger instruction address record is a second trigger instruction address record 502B, then address accessor 440 accesses the trigger replacement address 93 contained in the second trigger replacement address record 504B.

[0081] Value accessor 450 accesses the trigger value corresponding to the trigger instruction address record (box 650, row 720). The trigger value is contained in a trigger value record, and the trigger value record corresponds to the trigger instruction address record using an identifier contained in the record. For example, if the trigger instruction address record is a first trigger instruction address record 502A, then value accessor 450 accesses the trigger value 22 contained in the first trigger value record 506A. In another instance, if the trigger instruction address record is a second trigger instruction address record 502B, then value accessor 450 accesses the trigger value 77 contained in the second trigger value record 506B.

[0082] Replacement actuator 460 replaces (e.g., corrects) the value stored at an address in memory (box 660, line 720). Replacement actuator 460 replaces the value stored at the trigger replacement address accessed by address accessor 440 with the trigger value accessed by value accessor 450. (See below for more details.) Figure 8 An instance memory data table is described that reflects the value corrected by the replacement executor 460. In the instances described herein, the trigger replacement address is accessed by address accessor 440, and the trigger value is accessed by value accessor 450. In some instances, instruction processor 120 may correct the value stored at the address. In other instances, replacement executor 460 may provide an interrupt request to the memory replacement system (e.g., instruction processor 120 or execution unit 150) to instruct the memory replacement system to perform a replacement. In some instances, subsequent instructions identified by program counter 140 and / or executed by execution unit 150 access the value replaced by replacement executor 460.

[0083] In one example, trigger controller 410 accesses a set of trigger instruction address records 502 (box 610). Trigger comparator 430 accesses the instruction address identified by program counter 140 (box 620). Trigger comparator 430 then compares the instruction address with the set of trigger instruction address records 502 to determine if there is a match between the instruction address and any of the trigger instruction address records 502A, 502B, 502C, and 502D. If trigger comparator 430 determines that any of the trigger instruction addresses corresponds to an instruction address (e.g., box 630 returns a result of YES), then at box 640, control returns to address accessor 440.

[0084] In some instances, the replacement actuator 460 may additionally and / or alternatively correct the operation of components other than the values ​​stored in volatile memory 135 (e.g., peripheral devices, non-memory components, other volatile memories). For example, the replacement actuator 460 may identify one or more instructions to be executed by execution unit 150 or other components to ensure device functionality. In some instances, the replacement actuator 460, or more generally the instruction processor 120, may execute instructions as supplements and / or substitutes for instructions identified by program counter 140. The instruction processor 120 may execute instructions to replace values, such as instructions for providing a transaction indicating a write command to volatile memory 135.

[0085] Trigger controller 410 selects (e.g., accesses) a trigger instruction address record (box 670, line 725, line 730). In the example described herein, trigger controller 410 selects a trigger instruction address record that follows a previously selected trigger. For example, if the selected trigger instruction address record is a first trigger instruction address record 502A, then trigger controller 410 selects a second trigger instruction address record 502B. However, any other method for selecting a trigger instruction address record may be used additionally and / or alternatively. For example, the trigger instruction address record may contain an identifier, such as a pointer to the trigger instruction address record to be selected. After trigger controller 410 has accessed the trigger instruction address record, control returns to trigger comparator 430 (box 620, line 735).

[0086] exist Figure 6 In the illustrated example, replacement generator 110 accesses each of the trigger instruction address records to determine whether correction is needed, until the trigger instruction address record no longer corresponds to an instruction address, or until every trigger instruction address record has been accessed. However, replacement generator 110 may access any number of trigger instruction address records. For example, if the first trigger instruction address record 502A corresponds to the current instruction address, then replacement generator 110 may access only the first trigger instruction address record 502A before control returns to instruction processor 120.

[0087] Returning to box 630 (line 715), if the trigger comparator 430 determines that the trigger instruction address record does not correspond to the instruction address (e.g., box 630 returns NO, line 715 returns FALSE), then the process is complete, and control returns to execution unit 150. In some instances, multiple trigger instruction address records can be compared with the instruction address identified by program counter 140. For example, trigger controller 410 can select a second trigger instruction address record (e.g., second trigger instruction address record 502B) and determine whether the second trigger instruction address record corresponds to the instruction address. If trigger comparator 430 determines that the second trigger instruction address record does not correspond to the instruction address, then trigger controller 410 can then select a third trigger instruction address record (e.g., third trigger instruction address record 502C), and trigger comparator 430 determines whether the third trigger instruction address record corresponds to the instruction address.

[0088] Figure 8 This indicates that the instance replacement generator (e.g., stored at the instance address in memory (e.g., volatile memory 135) will be replaced by the instance generator. Figure 1An instance memory data table 800 corrects the instance values ​​of the replacement generator 110 (and / or 4). The memory data table 800 contains a first instance state 802 at time T1, a second instance state 804 at time T2, and a third instance state 806 at time T3. The memory data table 800 contains instance addresses 810 (e.g., addresses to locations in volatile memory 135) and instance values ​​820 (e.g., values ​​stored in volatile memory 135). Address 810 indicates the address where value 820 is stored in memory (e.g., volatile memory 135).

[0089] exist Figure 8 In the example described, memory data table 800 includes a first memory record 830, a second memory record 840, a third memory record 850, and a fourth memory record 860. Address 810, represented in memory records 830, 840, 850, and 860, indicates the address in memory (e.g., in volatile memory 135) where the value represented in the memory record is stored. In the first state 802, the first memory record 830 contains address 91 and the value 0. Therefore, in the first state 802, the memory (e.g., volatile memory 135, a register) contains the value 0 stored at address 91. Further, in the first state 802, the second memory record 840 contains the value 1 and address 92, the third memory record 850 contains the value 34 and address 93, and the fourth memory record 860 contains the value 88 and address 94. Similarly, in the first state 802, the volatile memory 135 contains the value 1 stored at address 92, the value 34 stored at address 93, and the value 88 stored at address 94.

[0090] In the second state 804, the replacement generator 110 replaces the value 0 contained in the first memory record 830 with the value 22. Figure 8 In the example described, memory data table 800 represents the value stored at an address in volatile memory 135. Therefore, replacement generator 110 replaces the value 0 stored at address 91 (indicated in the first memory record 830) with the value 22 from volatile memory 135. However, memory data table 800 can represent any additional and / or alternative memory, peripheral devices communicating with instruction processor 120, etc. For example, memory data table 800 can represent the value stored at an address in second volatile memory, a register contained in instruction processor 120, etc. In the second state 804, the second memory record 840 with the value 1 remains unchanged, the third memory record 850 with the value 34 remains unchanged, and the fourth memory record 860 with the value 88 remains unchanged relative to the first state 802.

[0091] In the third state 806, the replacement generator 110 replaces the value 34 contained in the third memory record 850 with the value 77. Therefore, the replacement generator 110 replaces the value 34 stored at address 93 (which is contained in the third memory record 850) with the value 77 from the volatile memory 135. Furthermore, in the third state 806, the first memory record 830 with the value 22 remains unchanged, the second memory record 840 with the value 1 remains unchanged, and the fourth memory record 860 with the value 88 remains unchanged relative to the second state 804.

[0092] Although Figure 8 The illustrated example shows four instruction records to instruct volatile memory 135 to store four values, but it can contain any other number of values. For example, volatile memory 135 can store ten thousand values. Therefore, memory data table 800 can contain ten thousand memory records. Although address 810 and value 820 are in Figure 8 The memory data table 800 described herein represents values ​​as two-digit numbers, but address 810 and value 820 may additionally and / or alternatively contain any other form. For example, the value may be represented as a 32-bit integer or a string.

[0093] exist Figure 8 In the example described, the memory data table 800 is displayed in three states: a first state 802 at time T1, a second state 804 at time T2, and a third state 806 at time T3. Although in Figure 8 The illustrated example shows three states, but the memory data table 800 can have any number of states. For example, if no correction is performed on the volatile memory 135, the memory data table 800 may contain only the first state 802. In another example, if many corrections are performed, the memory data table 800 may contain three thousand states.

[0094] This article describes Figure 3And / or an extended example of the process described in section 6 for replacing values ​​stored in volatile memory 135 by combining the instructions represented in instruction data table 200 with states 802, 804, 806 of memory data table 800. Control of the process begins at instruction processor 120, and program counter 140 determines that the next instruction record to be executed is instruction 44 at address 0, as represented by first instruction line 216 (box 310). Control is given to replacement generator 110 (box 320), and trigger controller 410 accesses trigger instruction address record 502A, which contains trigger instruction address 2 (box 610). Trigger comparator 430 accesses instruction address 0 (box 620). Trigger comparator 430 determines that trigger instruction address 2 does not correspond to (e.g., match, point to) instruction address 0, and therefore determines that correction should not be performed (e.g., box 630 returns result NO). No correction is performed. Therefore, no value is updated in volatile memory 135, and memory data table 800 remains in the first state 802. Control returns to instruction processor 120, and execution unit 150 executes the instruction recognized by program counter 140 (box 350).

[0095] Program counter 140 determines that the instruction record to be executed is instruction 55 stored at address 1, represented by second instruction line 218 (box 310). Control is given to replacement generator 110 (box 320), and trigger controller 410 accesses the current trigger instruction address record, first trigger instruction address record 502A containing trigger instruction address 2 (box 610). Trigger comparator 430 accesses instruction address 1 (box 620). Trigger comparator 430 determines that trigger instruction address 2 does not correspond to instruction address 1, and therefore determines that no correction should be performed (e.g., box 630 returns result NO). No correction is performed. Therefore, no value is updated in volatile memory 135, and memory data table 800 remains in first state 802. Control returns to instruction processor 120, and execution unit 150 executes the instruction identified by program counter (box 350).

[0096] Program counter 140 determines that the instruction record to be executed is instruction 55 stored at address 2, represented by third instruction line 220 (box 310). Control is given to replacement generator 110, and trigger controller 410 accesses trigger instruction address record, first trigger instruction address record 502A containing trigger instruction address 2 (box 610). Trigger comparator 430 accesses instruction address 2 (box 620). Trigger comparator 430 determines that trigger instruction address 2 corresponds to instruction address 2, and therefore determines that a correction should be performed (e.g., box 630 returns a result YES). Address accessor 440 accesses the trigger replacement address corresponding to the trigger instruction address record (box 640). The trigger instruction address record is first trigger instruction address record 502A. Therefore, the corresponding trigger replacement address record is first trigger replacement address record 504A containing trigger replacement address 91. Value accessor 450 accesses the trigger value corresponding to the trigger instruction address record (box 650). The trigger instruction address record, 502A, corresponds to the first trigger value record 506A. Therefore, the trigger value corresponding to the trigger instruction address record is trigger value 22 contained in the first trigger value record 506A. The replacement executor 460 corrects the memory value record stored in the volatile memory 135. Because the trigger replacement address is 91, the value at address 91 stored in the volatile memory 135 is corrected using trigger value 22 (box 660). Therefore, the memory data table 800 transitions from the first state 802 to the second state 804.

[0097] Trigger controller 410 selects (e.g., accesses) the trigger instruction address record, the second trigger instruction address record 502B containing trigger instruction address 4 (box 670). Control returns to trigger comparator 430, and the trigger comparator accesses instruction address 2 (box 620). Trigger comparator 430 determines that trigger instruction address 4 does not correspond to instruction address 2, and therefore determines that no correction should be performed (e.g., box 630 returns result NO). No correction is performed. Therefore, no value is updated in volatile memory 135, and memory data table 800 remains in the second state 804. Control returns to instruction processor 120, and execution unit 150 executes the instruction recognized by program counter 140 (box 350).

[0098] Program counter 140 determines that the instruction record to be executed is instruction 55 stored at address 3, represented by fourth instruction line 230 (box 310). Control is given to replacement generator 110 (box 320), and trigger controller 410 accesses trigger instruction address record 502B, which contains trigger instruction address 4 (box 610). Trigger comparator 430 accesses instruction address 3 (box 620). Trigger comparator 430 determines that trigger instruction address 4 does not correspond to instruction address 3, and therefore determines that no correction should be performed (e.g., box 630 returns result NO). No correction is performed. Therefore, no value is updated in volatile memory 135, and memory data table 800 remains in second state 804. Control returns to instruction processor 120, and execution unit 150 executes the instruction identified by program counter 140 (box 350).

[0099] Program counter 140 determines that the instruction to be executed is instruction 80 stored at address 4, represented by fifth instruction line 240 (box 310). Control is given to replacement generator 110, and trigger controller 410 accesses the trigger instruction address record, second trigger instruction address record 502B containing trigger instruction address 4 (box 610). Trigger comparator 430 accesses instruction address 4 (box 620). Trigger comparator 430 determines that trigger instruction address 4 corresponds to instruction address 4, and therefore determines that a correction should be performed (e.g., box 630 returns a result YES). Address accessor 440 accesses the trigger replacement address corresponding to second trigger instruction address record 502B (box 640). The trigger instruction address record is second trigger instruction address record 502B, and the corresponding trigger replacement address record is second trigger replacement address record 504B containing trigger replacement address 93. Value accessor 450 accesses the trigger value contained in second trigger value record 506B corresponding to second trigger instruction address record 502B (box 650). Replacement actuator 460 replaces (e.g., corrects) the value stored in volatile memory 135. Because the trigger replacement address is 93, the value at address 93 stored in volatile memory 135 is corrected with trigger value 77 (box 660). Therefore, memory data table 800 transitions from second state 804 to third state 806.

[0100] Trigger controller 410 selects (e.g., accesses) the trigger instruction address record, the third trigger instruction address record 502C containing trigger instruction address 10 (box 670). Control returns to trigger comparator 430, and the trigger comparator accesses instruction address 4 (box 620). Trigger comparator 430 determines that trigger instruction address 4 does not correspond to instruction address 10, and therefore determines that no correction should be performed (e.g., box 630 returns result NO). No correction is performed. Therefore, no value is replaced in volatile memory 135, and memory data table 800 remains in third state 806. Control returns to instruction processor 120, and execution unit 150 executes the instruction recognized by program counter 140 (box 350).

[0101] Program counter 140 determines that the instruction to be executed is instruction 5 stored at address 82, as indicated by instruction line 250 (box 310). Control is given to replacement generator 110 (box 320), and trigger controller 410 accesses the trigger instruction address record, third trigger instruction address record 502C containing trigger instruction address 10 (box 610). Trigger comparator 430 accesses instruction address 82 (box 620). Trigger comparator 430 determines that trigger instruction address 10 does not correspond to instruction address 5, and therefore determines that no correction should be performed (e.g., box 630 returns result NO). No correction is performed. Therefore, no value is updated in volatile memory 135, and memory data table 800 remains in third state 806. Control returns to instruction processor 120, and execution unit 150 executes the instruction identified by program counter 140 (box 350). In some instances, by Figure 3 The process for modifying the value stored in volatile memory 135 as described in section 6 can be continued using further instructions stored in non-volatile memory 130.

[0102] Figure 9 This indicates that an instance replacement generator is included (e.g., Figure 1 A block diagram of an instance use environment 900 of a replacement generator 110 (and / or 4) and an instance operation performed to replace values ​​in memory (e.g., volatile memory 135). Figure 9 The operating environment 900 includes an instruction processor 120, non-volatile memory 130, volatile memory 135, and instance interconnect bus 905.

[0103] Non-volatile memory 130 includes instance replacement instructions 908 that can be recognized and executed by instruction processor 120 to replace values ​​stored in volatile memory 135. Volatile memory 135 includes instance data structure 910. Instruction processor 120 can replace values ​​stored in volatile memory 135 contained in data structure 910. For example, data structure 910 can be a linked list containing a first value and a second value. During execution of instructions stored in non-volatile memory 130, instruction processor 120 can replace the first value contained in data structure 910 stored in volatile memory 135, and instruction processor 120 can then execute instructions to access the first value and / or the second value from volatile memory 135.

[0104] Volatile memory 135 contains an instance trigger transaction address record 912, an instance trigger replacement address record 914, and an instance trigger value record 916. Trigger transaction address record 912 contains the identifier "TrigMarkerN" and the trigger transaction address 91. Trigger replacement address record 914 contains the identifier "AddrN" and the trigger replacement address 91. Trigger value record 916 contains the identifier "ValN" and the trigger value 22. Each identifier contained in records 912, 914, and 916 contains the last character "N". Therefore, records 912, 914, and 916 are associated with each other. In some instances, any of records 912, 914, and 916 may be stored in a local data repository 470 contained in the replacement generator 110. In some instances, multiple records may be stored in the local data repository 470 and / or volatile memory 135. For example, the local data repository 470 may contain four trigger transaction address records, four trigger replacement address records, and four trigger value records.

[0105] exist Figure 9 In this example, volatile memory 135 includes a trigger transaction address record, a trigger replacement record, and a trigger value record. However, any number of trigger transaction address records, trigger replacement records, and / or trigger value records may be stored in volatile memory 135 and / or local data repository 470. For example, a first trigger transaction address record may be stored in local data repository 470, and a second trigger transaction address record may be stored in volatile memory 135.

[0106] The instruction processor 120 includes a replacement generator 110 and an instance central processing unit (CPU) 930. Figure 9 In the example described herein, CPU 930 includes Figure 1 Instance program counter 140 and Figure 1 The instance execution unit 150. The CPU 930 identifies the instructions to be executed and executes the identified instructions. Figure 9In one example, CPU 930 accesses the trigger replacement address, accesses the trigger value, and replaces the value stored at the address indicated by the trigger replacement address with the trigger value in response to an interrupt request provided by the replacement generator 110. For example, Figure 9 The CPU930 in the illustrated example is implemented by logic circuitry, such as that of a hardware processor. However, any other type of circuit system may be used, for example, such as one or more analog or digital circuits, logic circuits, programmable processors, ASICs, PLDs, FPLDs, programmable controllers, GPUs, DSPs, etc.

[0107] Replacement generator 110, non-volatile memory 130, volatile memory 135, and CPU 930 communicate via interconnect bus 905. For example, CPU 930 accesses data stored in non-volatile memory 130 (e.g., replacement instruction 908) via interconnect bus 905. CPU 930 accesses and updates values ​​stored in volatile memory 135 via interconnect bus 905. Furthermore, CPU 930 and replacement generator 110 communicate via interconnect bus 905. Although in Figure 9 An example may include one interconnect bus, but may additionally and / or alternatively include any number of interconnect buses. For example, CPU 930 may communicate with non-volatile memory 130 via a first interconnect bus, and CPU 930 may communicate with volatile memory 135 via a second interconnect bus. Figure 9 In this example, the components in environment 900 (such as CPU 930 and replacement generator 110) are coupled by interconnect bus 905.

[0108] exist Figure 9In the examples described herein, instruction processor 120, volatile memory 135, and non-volatile memory 130 communicate via interconnect bus 905 using transactions. In the examples described herein, a transaction on the interconnect bus includes at least one transaction type (e.g., a read operation or a write operation) and a transaction address indicating, corresponding to, and / or pointing to a value stored in memory. For example, instruction processor 120 may send a transaction having a transaction type indicating a read command and a transaction address indicating address 2 in volatile memory 135. Volatile memory 135 may respond to a transaction provided by CPU 930 and / or instruction processor 120 with a response indicating that a value of 0 is stored at address 2. Replacement generator 110 (e.g., trigger comparator 430) accesses the transaction provided by instruction processor 120 on interconnect bus 905 to determine whether a replacement should be performed. In some instances, the replacement generator 110 is configured to detect processor (e.g., instruction processor 120, CPU 930, execution unit 150, etc.) access to instructions by spying on requests for the first transaction (e.g., via a transaction request) on a bus that couples the processor to memory (e.g., an interconnect bus 905 that couples CPU 930 to non-volatile memory 130). The trigger comparator 430 determines whether the trigger transaction address contained in the trigger transaction address record corresponds to (e.g., matches, equals) the transaction address contained in the transaction.

[0109] Execution unit 150 executes instructions recognized by program counter 140, and instruction processor 120 provides transactions on interconnect bus 905. A transaction includes a transaction type (e.g., a request to read a value from an address) and a transaction address (e.g., a pointer to the address of the value to be read). Trigger controller 410 accesses trigger transaction address record 912 (operation 950). In the example described herein, the trigger transaction address record matches the transaction address via the trigger transaction address contained in the trigger transaction address record. For example, a transaction on interconnect bus 905 may contain transaction address 91, and the corresponding trigger transaction address record may contain trigger transaction address 91.

[0110] The trigger comparator 430 accesses the transaction address contained in the transaction via the interconnect bus 905 and determines whether a correction should be performed. Figure 9In the illustrated example, trigger comparator 430 determines whether correction should be performed by comparing the trigger transaction address 91 contained in the trigger transaction address record 912 with the transaction address (operation 955). For example, in response to detecting access to the address via a transaction, trigger comparator 430 may compare the trigger transaction address record 912 containing the trigger transaction address 91 with the transaction containing the transaction address 41. Since the trigger transaction address 91 and the transaction address 41 do not match, trigger comparator 430 may determine that correction should not be performed. In another example, trigger comparator 430 may compare or match the trigger transaction address 91 with the transaction containing the transaction address 91, and trigger comparator 430 may therefore determine that correction should be performed. However, any other methods for comparing the trigger transaction address record 912 with the transaction may be used additionally and / or alternatively. For example, trigger comparator 430 may determine whether the transaction type (e.g., a read or write command) contained in the transaction corresponds to or matches the trigger transaction type contained in the trigger transaction address record 912.

[0111] If the trigger comparator 430 determines that the triggering transaction address corresponds to (e.g., matches, equals) the transaction address, then the replacement generator 110 provides an interrupt request to the memory replacement system, such as the CPU 930, instruction processor 120, and / or execution unit 150. Figure 9 In the example described herein, replacement generator 110 provides an interrupt request to CPU 930 (operation 960). Replacement generator 110 may send an interrupt request instruction to processor 120 via interconnect bus 905, such that CPU 930 may replace a value located in volatile memory 135 before executing an instruction recognized by program counter 140.

[0112] exist Figure 9 In the example described herein, non-volatile memory 130 contains a replacement instruction 908 recognized and executed by CPU 930 to replace a value in volatile memory 135 in response to an interrupt request provided by replacement generator 110 (operation 963). In other examples, program counter 140 may transfer transactions on interconnect bus 905 to access a value stored in volatile memory 135, wait for a response from replacement generator 110 (e.g., wait for replacement generator 110 to replace a value), and then access the response on interconnect bus 905 from volatile memory 135 to execute instructions later to process the value.

[0113] Instruction processor 120 (e.g., CPU 930, address accessor 440) accesses the trigger replacement address corresponding to the trigger transaction address record (operation 965). For example, if the trigger transaction address record is trigger transaction address record 912, then the corresponding trigger replacement address record is trigger replacement address record 914, because the identifier contained in each record contains the last character "N". Therefore, address accessor 440 accesses the trigger replacement address 91 contained in trigger replacement address record 914.

[0114] Instruction processor 120 (e.g., CPU 930, value accessor 450) accesses the trigger value corresponding to trigger transaction address record 912 (operation 970). For example, if the trigger transaction address record is trigger transaction address record 912, then the corresponding trigger value record is trigger value record 916, because the identifier contained in each record contains the last character "N". Therefore, value accessor 450 accesses the trigger value 22 contained in trigger value record 916.

[0115] CPU 930 replaces (e.g., corrects) the value stored at an address in memory (operation 975). Both the trigger replacement address record 914 and the trigger value record 916 are accessed by CPU 930. In some instances, the trigger replacement address record 914 is accessed by address accessor 440, and the trigger value record 916 is accessed by value accessor 450. In some instances, instruction processor 120 may correct the value stored at an address in memory. In some instances, replacement executor 460 corrects the value at address 91 in volatile memory 135 pointed to by trigger replacement address record 914 with the trigger value 22 contained in trigger value record 916. (The following is in conjunction with...) Figure 11 An instance memory data table describes the values ​​stored in volatile memory 135 and corrected by instruction processor 120.

[0116] If the replacement generator 110 (e.g., the trigger comparator 430) determines that the triggering transaction address record 912 does not correspond to a transaction address included in a transaction, then the CPU 930 can continue to recognize and execute the instruction via the program counter 140 and the execution unit 150. The CPU 930 can provide additional transactions for the replacement generator 110 to access.

[0117] Figure 10 This represents an instance that can be executed to replace the generator (e.g., Figure 1 , 4 A flowchart of machine-readable instructions for the replacement generator 110 (and / or 9). Trigger controller 410 accesses trigger transaction address record 912. (Box 1010). In Figure 10In the example described herein, a trigger transaction address record is associated with a transaction address by matching the trigger transaction address with the transaction address. For example, trigger transaction address record 912 may contain the trigger transaction address 91 corresponding to the transaction containing transaction address 91 on interconnect bus 905.

[0118] Trigger comparator 430 accesses the transaction address contained in a transaction on interconnect bus 905 and determines whether a correction should be performed (Box 1020). In the example described herein, trigger comparator 430 determines whether a correction should be performed by matching the trigger transaction address contained in the trigger transaction address record with the transaction address. For example, trigger comparator 430 may compare trigger transaction address record 912 containing trigger transaction address 91 with the transaction containing transaction address 91. However, any other methods for comparing trigger transaction address records with transactions may be used additionally and / or alternatively. For example, trigger comparator 430 may determine whether the transaction type (e.g., a read or write command) contained in the transaction matches the trigger transaction type contained in trigger transaction address record 912.

[0119] If the trigger comparator 430 determines that the triggering transaction address corresponds to (e.g., matches, equals) the transaction address (e.g., box 1030 returns a result of YES), then the replacement generator 110 provides an interrupt request to the memory replacement system (e.g., CPU 930) (box 1035). Figure 9 In the example described in 10 and / or 10, the replacement generator 110 executes in parallel with the CPU 930, program counter 140, and execution unit 150. Thus, the replacement generator 110 can provide an interrupt request to the instruction processor 120 via the interconnect bus 905, so that the instruction processor 120 (e.g., CPU 930) corrects the value and then executes instructions to access the corrected value.

[0120] An instruction processor (e.g., CPU 930, address accessor 440) accesses the trigger replacement address corresponding to the trigger transaction address record 912 (box 1040). The trigger replacement address is contained in a trigger replacement address record (e.g., trigger replacement address record 914), and the trigger replacement address corresponds to the trigger transaction address record via an identifier contained in each record (e.g., records 912, 914). For example, if the trigger transaction address record is trigger transaction address record 912, then address accessor 440 accesses the trigger replacement address 91 contained in trigger replacement address record 914.

[0121] An instruction processor (e.g., CPU 930, value accessor 450) accesses the trigger value corresponding to trigger transaction address record 912 (box 1050). The trigger value is contained in a trigger value record (e.g., trigger value record 916), and the trigger replacement address corresponds to trigger transaction address record 912 via an identifier contained in both trigger value record 916 and trigger transaction address record 912. For example, if the trigger transaction address record is trigger transaction address record 912, then value accessor 450 accesses the trigger value 22 contained in trigger value record 916.

[0122] An instruction processor (e.g., CPU 930, replacement executor 460) corrects the value at an address stored in memory (box 1060). CPU 930 and / or replacement executor 460 replace the value stored at the address pointed to by the trigger replacement address with the trigger value contained in trigger value record 916. In some instances, CPU 930 accesses the trigger replacement address contained in trigger replacement address record 914 and the trigger value contained in trigger value record 916. In some instances, the trigger replacement address is accessed by address accessor 440, and the trigger value is accessed by value accessor 450. In some instances, CPU 930 may use the trigger value to correct the value at an address stored in volatile memory 135. For example, replacement executor 460 may provide an interrupt request to a memory replacement system (e.g., instruction processor 120, CPU 930, program counter 140, and / or execution unit 150) to instruct the memory replacement system to perform a replacement. In some instances, instructions identified by program counter 140 and / or executed by execution unit 150 access values ​​replaced by instruction processor 120, replacement executor 460, and / or CPU 930.

[0123] Trigger controller 410 selects (e.g., accesses) the trigger transaction address record (box 1070). In some instances, trigger controller 410 selects the trigger transaction address record based on an identifier contained in a previously selected trigger transaction address record. For example, if a previously selected trigger transaction address record contains the identifier "0", then trigger controller 410 may select the trigger transaction address record containing the identifier "1". However, any other method for selecting the trigger transaction address record may be used additionally and / or alternatively. After trigger controller 410 has selected the trigger transaction address record, control returns to trigger comparator 430 at box 1030.

[0124] Returning to box 1030, if the trigger comparator 430 determines that the trigger transaction address record does not correspond to a transaction address included in a transaction (e.g., box 1030 returns a result of NO), then control returns to CPU 930. In some instances, multiple trigger transaction address records can be compared with a transaction address. For example, the trigger controller 410 can select a second trigger transaction address record and determine whether the second trigger transaction address record corresponds to a transaction address. If the trigger comparator 430 determines that the second trigger transaction address record does not correspond to a transaction address, then the trigger controller 410 can then select a third trigger transaction address record, and the trigger comparator 430 determines whether the third trigger transaction address record corresponds to a transaction address included in a transaction.

[0125] Figure 11 This indicates that the instance replacement generator (e.g., stored at the instance address in memory (e.g., volatile memory 135) will be replaced by the instance generator. Figure 1 , 4 An instance memory data table 1100 corrects the instance values ​​of the replacement generator 110 (and / or 9). The memory data table 1100 contains a first instance state 1102 at time T1 and a second instance state 1104 at time T2. The memory data table 1100 contains an instance address 1110 (e.g., an address to a location in volatile memory 135) and an instance value 1120 (e.g., a value stored in volatile memory 135 at address 1110). Address 1110 indicates the address at which value 1120 is stored in memory (e.g., volatile memory 135).

[0126] exist Figure 11 In the example described herein, memory data table 1100 contains memory row 1130. In the first state 1102, memory row 1130 contains address 91 and value 0. In other words, in the first state 1102, memory (e.g., volatile memory 135) contains the value 0 stored at address 91. In the second state 1104, replacement generator 110 replaces the value 0 at address 91 in volatile memory with value 22, as represented by memory row 1130. Figure 11 In the example described herein, memory data table 1100 represents the value stored at the address in volatile memory 135. Therefore, replacement generator 110 replaces the value 0 stored at address 91 (indicated in memory row 1130) with the value 22 from volatile memory 135. However, memory data table 1100 may represent any additional and / or alternative memory, peripheral devices communicating with instruction processor 120, etc. For example, memory data table 1100 may represent a value stored by another device communicating with instruction processor 120 via interconnect bus 905.

[0127] Although Figure 11 The illustrated example shows a memory row to indicate that a value is stored in volatile memory 135, but it can contain any other number of values. For example, volatile memory 135 can store ten thousand values. Therefore, memory data table 1100 can contain ten thousand memory records. Although address 1110 and value 1120 are in Figure 11 The memory data table 1100 described herein represents values ​​as two-digit numbers, but address 1110 and value 1120 may additionally and / or alternatively contain any other form. For example, value 1120 may be represented as a string or two 64-bit integers.

[0128] exist Figure 11 In the example described, memory data table 1100 is shown as being in a first state 1102 at time T1 and in a second state 1104 at time T2. Although in Figure 11 The illustrated example shows two states, but memory data table 1100 can have any number of states. For example, if no correction is performed on the values ​​stored in volatile memory 135, then memory data table 1100 may contain only the first state 1102. In another example, if many values ​​are corrected in volatile memory 135, then memory data table 1100 may contain three thousand states. In the first state 1102, memory row 1130 in memory data table 1100 at the first state 1102 contains the value 1120 in the initial state.

[0129] This article describes Figure 3 And / or an extended example of the process described in 10 for correcting the value in volatile memory 135 in conjunction with states 1102, 1104 of memory data table 1100. Control of the process begins with CPU 930, and execution unit 150 provides a transaction on interconnect bus 905 to request the value stored in volatile memory 135 (box 350). The transaction contains a transaction type indicating a read command and a transaction address 91. Therefore, execution unit 150 and / or more generally CPU 930 request volatile memory 135 to provide the value stored at address 91 in volatile memory 135. Program counter 140 identifies the instruction to be executed (box 310). The instruction obtains the value at address 91 provided by volatile memory 135 on interconnect bus 905. Therefore, after correcting the value stored at address 91, the instruction can be executed by execution unit 150, and the instruction can access the corrected value.

[0130] Trigger controller 410 accesses trigger transaction address record 912 containing trigger transaction address 91 (box 1010). Trigger comparator 430 accesses a transaction provided by CPU 930, the transaction containing a transaction type indicating a read command and transaction address 91 (box 1020). Trigger comparator 430 determines that trigger transaction address 91 corresponds to (e.g., matches, equals, points to) transaction address 91, and therefore determines that a correction should be performed (e.g., box 1030 returns a result YES).

[0131] Replacement generator 110 provides an interrupt request to instruction processor 120 via interconnect bus 905 (Box 1035). CPU 930 (e.g., execution unit 150) accesses the trigger replacement address 91 contained in the trigger replacement address record 914 corresponding to the trigger transaction address record 912 (Box 1040). As mentioned above, the trigger replacement address record 914 and the trigger value record 916 correspond to the trigger transaction address record 912 via identifiers contained in records 912, 914, and 916. CPU 930 (e.g., execution unit 150) accesses the trigger value 22 contained in the trigger value record 916 corresponding to the trigger transaction address record 912 (Box 1050). CPU 930 replaces the value located at address 91 in volatile memory 135 (e.g., the address pointed to by the trigger transaction address), as shown in memory data table 1100 at second state 1104 (Box 1060).

[0132] Because the trigger replacement address is 91, the value at address 91 in volatile memory 135 is replaced with the trigger value 22. Therefore, the memory data table 1100 representing the values ​​stored in volatile memory 135 transitions from a first state 1102 to a second state 1104. In the second state 1104, the value 1120 contained in memory row 1130 is corrected with the trigger value 22. The trigger comparator 430 selects (e.g., accesses) the trigger transaction address record. (Box 1070). The extended instance terminates. In some instances, by... Figure 10 The process for modifying the value stored in volatile memory 135, as described in section 11, can continue, wherein additional transactions are provided on interconnect bus 905. For example, after performing a correction, execution unit 150 may execute one or more instructions to provide a second transaction on interconnect bus 905 to access the updated value stored at address 91 in volatile memory 135.

[0133] Figure 12 It is constructed to execute Figure 3 , 6 and / or 10 instructions to implement Figure 1 , 4A block diagram of an instance processor platform 1200 for replacement generator 110 of 9. For example, processor platform 1200 may be a server, personal computer, workstation, mobile device (e.g., mobile phone, smartphone, tablet computer (e.g., iPad)). TM Personal digital assistants (PDAs), Internet facilities, game consoles, personal video recorders, set-top boxes, headphones or other wearable devices, or any other type of computing device.

[0134] The processor platform 1200 of the illustrated example includes a processor 1212. The processor 1212 of the illustrated example is hardware. For example, the processor 1212 may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The hardware processor may be a semiconductor-based (e.g., silicon-based) device. In this example, the processor implements a trigger controller 410, a trigger comparator 430, an address accessor 440, a value accessor 450, and a replacement actuator 460.

[0135] The processor 1212 of the illustrated example includes local memory 1213 (e.g., cache). The processor 1212 of the illustrated example communicates via bus 1218 with main memory, which includes volatile memory 1214 and non-volatile memory 1216. The volatile memory 1214 may be synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), etc. Dynamic Random Access Memory The non-volatile memory 1216 may be implemented using flash memory and / or any other desired type of memory device. Access to the main memory 1214, 1216 is controlled by a memory controller.

[0136] The processor platform 1200 of the illustrated example also includes interface circuitry 1220. Interface circuitry 1220 can be implemented using any type of interface standard, such as an Ethernet interface, Universal Serial Bus (USB), etc. Interfaces, Near Field Communication (NFC) interfaces and / or PCI high-speed interfaces.

[0137] In the illustrated example, one or more input devices 1222 are connected to interface circuitry 1220. Input devices 1222 allow users to input data and / or commands into processor 1212. Input devices may be implemented, for example, audio sensors, microphones, cameras (still or video), keyboards, buttons, mice, touchscreens, trackpads, trackballs, and / or voice recognition systems.

[0138] One or more output devices 1224 are also connected to the interface circuit 1220 of the illustrated example. The output devices 1224 may be implemented, for example, via display devices (e.g., light-emitting diodes (LEDs), organic light-emitting diodes (OLEDs), liquid crystal displays (LCDs), cathode ray tube displays (CRTs), in-place switching (IPS) displays, touchscreens, etc.), haptic output devices, printers, and / or speakers. Therefore, the interface circuit 1220 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics driver processor.

[0139] The interface circuit 1220 of the illustrated example also includes communication devices, such as a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, and / or network interface, to facilitate the exchange of data with external machines (e.g., any type of computing device) via network 1226. For example, communication may be via Ethernet connection, Digital Subscriber Line (DSL) connection, telephone line connection, coaxial cable system, satellite system, field wireless system, cellular telephone system, etc.

[0140] The processor platform 1200 of the illustrated example also includes one or more mass storage devices 1228 for storing software and / or data. Examples of such mass storage devices 1228 include floppy disk drives, hard disk drives, optical disk drives, Blu-ray disc drives, redundant array of independent disks (RAID) systems, and digital multifunction disk (DVD) drives.

[0141] Figure 3 , 6 The machine-executable instructions 1232 of 10 may be stored in a mass storage device 1228, a volatile memory 1214, a non-volatile memory 1216 and / or on a removable non-transitory computer-readable storage medium (e.g., a CD or DVD).

[0142] From the foregoing, it will be understood that example methods, apparatus, and articles of manufacture for correcting values ​​in a calibration device have been described. The described methods, apparatus, and articles of manufacture improve the efficiency of using a computing device through a bootloader process of the calibration device without modifying bootloader instructions stored in non-volatile memory. Accordingly, the described methods, apparatus, and articles of manufacture relate to one or more improvements in computer functionality.

[0143] This document describes instance methods, devices, and systems for replacing values ​​in a device. Further instances and combinations thereof include the following:

[0144] Example 1 includes an apparatus comprising a processor and a replacement generator coupled to the processor and configured to: detect the processor's access to a first instruction at a first address in a first memory; in response to the detected access, compare the first address with a set of trigger instruction address records in a second memory, wherein the set of trigger instruction address records includes a first trigger instruction address record associated with a first replacement address record and a first replacement value record; and, based on the first address corresponding to the first trigger instruction address record, replace the first value at a second address in a third memory specified by the first replacement address record with a second value specified by the first replacement value record.

[0145] Example 2 includes the device described in Example 1, wherein the first memory is a read-only memory.

[0146] Example 3 includes the device described in Example 1, wherein the replacement generator is configured to detect the access by snooping on a request for the first instruction on the bus that couples the processor to the first memory.

[0147] Example 4 includes the device described in Example 1, wherein the replacement generator is configured to replace the first value at the second address by issuing an interrupt to the processor, the interrupt being configured to cause the processor to store the second value at the second address.

[0148] Example 5 includes the device described in Example 1, wherein the third memory is a register of the processor.

[0149] Example 6 includes the device described in Example 1, wherein the replacement generator accesses the second value by accessing eFuse.

[0150] Example 7 includes the device described in Example 1, wherein the first address is a transaction address contained in a transaction on the interconnect bus.

[0151] Example 8 includes a system comprising: a program counter for identifying a first instruction to be executed, the first instruction being located at a first address in non-volatile memory; a replacement generator for determining whether a second address corresponds to the first address, the second address corresponding to a trigger instruction address record, accessing a third address corresponding to the trigger instruction address record and a location corresponding to a first value, accessing a second value corresponding to the trigger instruction address record, and replacing the first value at the third address with the second value; and an execution unit for executing the second instruction to access the second value.

[0152] Example 9 includes the system described in Example 8, wherein the location of the first value is in a first memory, and the second value accessed by the replacement generator is located in a second memory different from the first memory.

[0153] Example 10 includes the system described in Example 8, wherein the replacement generator replaces the first value by providing an interrupt request to the execution unit.

[0154] Example 11 includes the system described in Example 8, wherein the replacement generator accesses the second value, including accessing eFuse.

[0155] Example 12 includes the system described in Example 8, wherein the first address is a transaction address contained in a transaction on the interconnect bus.

[0156] Example 13 includes the system described in Example 8, wherein the replacement generator accesses a trigger instruction address record containing the second address.

[0157] Example 14 includes a method comprising: accessing a first address corresponding to a first location in nonvolatile memory; determining whether a second address corresponds to the first address, the second address corresponding to a trigger instruction address record; accessing a third address corresponding to the trigger instruction address record and corresponding to a location of a first value; accessing a second value corresponding to the trigger instruction address record, the second value being different from the first value; and replacing the first value at the third address with the second value, the second value being accessed by an instruction.

[0158] Example 15 includes the method of Example 14, wherein the location of the first value is in a first memory, and the second value is located in a second memory different from the first memory before the replacement.

[0159] Example 16 includes the method of Example 14, wherein replacing the first value includes providing an interrupt request to the memory replacement system.

[0160] Example 17 includes the method described in Example 14, wherein the first address is an instruction address identified by the program counter.

[0161] Example 18 includes the method described in Example 14, wherein the first address is a transaction address contained in a transaction on the interconnect bus.

[0162] Example 19 includes the method described in Example 14, wherein the second address corresponds to the location of the instruction to be executed in the non-volatile memory.

[0163] Example 20 includes the method described in Example 14, which includes accessing a trigger instruction address record containing a second address.

[0164] Although certain example methods, apparatuses, and articles of manufacture have been described herein, the scope of this patent is not limited thereto. Rather, this patent covers all methods, apparatuses, and articles of manufacture that reasonably fall within the scope of the claims of this patent.

[0165] The appended claims are hereby incorporated by reference in this detailed description, wherein each claim exists independently as a separate embodiment of the description.

Claims

1. An electronic device comprising: processor; and Replacement generator, which is coupled to the processor and configured to: Detect the processor's transaction with the first instruction at the first address in the first memory; In response to the detected transaction, the trigger controller accesses a set of trigger instruction address records in the second memory to retrieve the first trigger instruction address record; A trigger comparator determines whether to replace the first value in the third memory by comparing the first address with the trigger instruction address in the first trigger instruction address record. The first trigger instruction address record is associated with the first replacement address record and the first replacement value record. Based on the fact that the first address corresponds to the trigger instruction address, the replacement executor replaces the first value at the second address in the third memory specified by the first replacement address record with the second value specified by the first replacement value record, wherein: The first memory is a read-only memory; The second memory is a local data repository; The third memory is a volatile memory; and The first instruction is a bootloader instruction.

2. The electronic device of claim 1, wherein the replacement generator is configured to detect the transaction by snooping on a request for the first instruction on a bus that couples the processor to the first memory.

3. The electronic device of claim 1, wherein the replacement generator is configured to replace the first value at the second address by issuing an interrupt to the processor, the interrupt being configured to cause the processor to store the second value at the second address.

4. The electronic device of claim 1, wherein the replacement generator accesses the second value by accessing eFuse.

5. The electronic device of claim 1, wherein the first address is a transaction address contained in a transaction on the interconnect bus.

6. An electronic system comprising: A program counter is used to identify bootloader instructions to be executed, which are located at a first address in read-only memory; Replacement generator, which is used for: The trigger controller accesses a set of trigger instruction address records in the local data repository to retrieve the trigger instruction address records; The trigger comparator determines whether to replace the first value in the volatile memory by comparing the first address with the second address in the trigger instruction address record; In response to the second address corresponding to the first address: The address accessor retrieves the third address corresponding to the trigger instruction address record and the position corresponding to the first value; The value accessor retrieves the second value corresponding to the trigger instruction address record; and The replacement actuator replaces the first value at the third address with the second value; and An execution unit, which executes a second instruction to access the second value.

7. The electronic system of claim 6, wherein the location of the first value is in the volatile memory, and the second value accessed by the replacement generator is located in the local data repository.

8. The electronic system of claim 6, wherein the replacement generator replaces the first value by providing an interrupt request to the execution unit.

9. The electronic system of claim 6, wherein the replacement generator accesses the second value, including accessing eFuse.

10. The electronic system of claim 6, wherein the first address is a transaction address contained in a transaction on the interconnect bus.

11. The electronic system of claim 6, wherein the replacement generator accesses the trigger instruction address record containing the second address.

12. A method for operating an electronic device, comprising: The processor accesses the first address of the bootloader instruction corresponding to the first location in the read-only memory; The trigger controller accesses a set of trigger instruction address records in the local data repository to retrieve the trigger instruction address records; The trigger comparator determines whether to replace the first value stored in the volatile memory by comparing the first address with the second address in the trigger instruction address record; The address accessor retrieves the third address corresponding to the trigger instruction address record and the position corresponding to the first value; The value accessor retrieves a second value corresponding to the trigger instruction address record, the second value being different from the first value; and The replacement executor replaces the first value at the third address with the second value, and the second value will be accessed by the instruction.

13. The method of claim 12, wherein the location of the first value is in the volatile memory, and the second value is located in the local data repository prior to the replacement.

14. The method of claim 12, wherein replacing the first value comprises providing an interrupt request to a memory replacement system.

15. The method of claim 12, wherein the first address is an instruction address identified by a program counter.

16. The method of claim 12, wherein the first address is a transaction address contained in a transaction on the interconnect bus.

17. The method of claim 12, wherein the second address corresponds to the location in the read-only memory where the bootloader instructions to be executed are stored.

18. The method of claim 12, further comprising accessing the trigger instruction address record containing the second address.

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