Semiconductor device

Abstract

A heat sink (51), one of the heat dissipation parts configured to sandwich semiconductor elements having main electrodes on both sides and electrically connected to the corresponding main electrodes, forms a solder joint between itself and the emitter electrode. The heat sink (51) has a high-wetting region (151b) on the surface of the emitter electrode side, and a low-wetting region (151a) adjacent to the high-wetting region (151b) in a plan view in the thickness direction, defining the outer periphery of the high-wetting region (151b) and having lower solder wettability compared to the high-wetting region (151b). The high-wetting region (151b) has an overlapping region (151c) and a non-overlapping region (151d) connected to the overlapping region (151c) in a plan view. The overlapping region is the region that overlaps with the forming region of the solder joint of the emitter electrode, and solder is disposed in at least a portion of it. The non-overlapping region (151d) includes at least a receiving region (151e) for receiving remaining solder.

Description

[0001] Cross-referencing of related applications

[0002] This application is based on Japanese Patent Application No. 2019-224847, filed on December 12, 2019, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This invention relates to semiconductor devices. Background Technology

[0004] Patent Document 1 discloses a semiconductor device with a double-sided heat dissipation structure, comprising a semiconductor element having main electrodes on both sides, and a wiring component including a heat dissipation section arranged to sandwich the semiconductor element and a terminal section connected to the heat dissipation section as a conductor section. The contents of prior art documents are incorporated herein by reference as an explanation of technical elements.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2007-103909 Summary of the Invention

[0008] In a structure having a joint formed by distributing bonding material between two conductor portions in the thickness direction of the plate, the bonding material absorbs height deviations caused by dimensional tolerances, assembly tolerances, etc., of the elements constituting the semiconductor device. In the case of a height deviation in the direction where the opposing distance between the two conductor portions narrows, the remaining bonding material overflows from the two opposing regions, thereby absorbing the height deviation. If a groove as described in Patent Document 1 is provided on one side of the conductor portion, the remaining bonding material can be contained. The groove is formed by pressure processing. From the above-mentioned viewpoints or other viewpoints not mentioned, further improvements are required for semiconductor devices.

[0009] One object of the present invention is to provide a semiconductor device capable of accommodating the remaining bonding material in a simple structure.

[0010] The semiconductor device disclosed herein includes: at least one semiconductor element having a main electrode on one side and a back side opposite to the one side in the thickness direction; and a wiring component having a plurality of conductor portions and at least one junction portion formed by distributing a bonding material between two conductor portions in the thickness direction, wherein the plurality of conductor portions include at least one set of heat dissipation portions disposed on one side and the back side in the thickness direction in a manner that clamps the semiconductor element and is electrically connected to the corresponding main electrode, and a plurality of terminal portions connected to the heat dissipation portions.

[0011] In at least one of the joints, a first conductor portion, which is one of the conductor portions, has a high wetting region and a low wetting region on a side opposite to a second conductor portion, which is another conductor portion, and the low wetting region has a lower wettability to the joint material compared to the high wetting region. The low wetting region is disposed adjacent to the high wetting region in a plan view in the plate thickness direction to define the outer periphery of the high wetting region.

[0012] The highly wetted region has overlapping and non-overlapping regions in a plan view. The overlapping region is the region that overlaps with the forming region of the joint of the second conductor portion and has bonding material disposed in at least a portion therein. The non-overlapping region is the region connected to the overlapping region but does not overlap with the forming region of the joint of the second conductor portion. Furthermore, the non-overlapping region includes at least a receiving region that accommodates the remaining bonding material for the joint.

[0013] According to the disclosed semiconductor device, the receiving region, which is a high-wetting region, is connected to the overlapping region, and the remaining bonding material readily wets and diffuses from the overlapping region into the receiving region. The remaining bonding material is restricted from wetting and diffusion by the low-wetting region. Thus, the low-wetting region adjacent to the high-wetting region promotes wetting and diffusion into the receiving region and / or inhibits wetting and diffusion outside the receiving region. Therefore, the remaining bonding material can be received into the receiving region even without a groove. As a result, a semiconductor device capable of receiving the remaining bonding material with a simple structure can be provided.

[0014] The various technical solutions disclosed in this specification employ different technical means to achieve their respective purposes. The reference numerals in parentheses within the claims illustratively indicate the correspondence with portions of the embodiments described later, and are not intended to limit the scope of the technology. The purposes, features, and effects disclosed in this specification will become clearer with reference to the following detailed description and accompanying drawings. Attached Figure Description

[0015] Figure 1 It is a diagram showing the schematic structure of the drive system of a vehicle that uses an electric conversion device.

[0016] Figure 2 This is a plan view showing the semiconductor device of the first embodiment.

[0017] Figure 3 This is a plan view of the semiconductor device as seen from the main terminal side.

[0018] Figure 4 It is along Figure 2 A cross-sectional view along line IV-IV.

[0019] Figure 5 It is along Figure 2 A cross-sectional view of the V-V line.

[0020] Figure 6 It is a plan view that omits the state of the sealed resin body.

[0021] Figure 7 It is Figure 6 A plan view viewed from the X1 direction.

[0022] Figure 8 This is a plan view showing the state where the heat sink on the emitter side is omitted.

[0023] Figure 9 This is a plan view showing the semiconductor module of the first embodiment.

[0024] Figure 10 It is Figure 9 A plan view viewed from the X2 direction.

[0025] Figure 11 This is an equivalent circuit diagram of a semiconductor module that takes into account wiring inductance.

[0026] Figure 12 It is a plan view showing the structure inside the encapsulating resin body in a semiconductor device.

[0027] Figure 13 It is a plan view representing a variation.

[0028] Figure 14 It is a plan view representing a variation.

[0029] Figure 15 It is a plan view representing a variation.

[0030] Figure 16 This is a plan view showing the semiconductor module of the second embodiment.

[0031] Figure 17 It is Figure 16 A plan view taken from the X3 direction.

[0032] Figure 18 It is a model of the upper and lower arms used in the position verification of the load line.

[0033] Figure 19 It is a diagram showing the current flowing through each output terminal when the switching element is driven.

[0034] Figure 20 This is an equivalent circuit diagram of a semiconductor module that takes into account wiring resistance.

[0035] Figure 21 It is a graph showing the relationship between the resistance ratio and the effective current ratio.

[0036] Figure 22 It is a graph showing the relationship between the resistance ratio and the effective current ratio.

[0037] Figure 23 It is a graph showing the relationship between the resistance ratio and the effective current ratio.

[0038] Figure 24 It is a graph showing the relationship between the resistance ratio and the effective current ratio.

[0039] Figure 25 It is a plan view representing a variation.

[0040] Figure 26 This is a floor plan representing another example.

[0041] Figure 27 It is a plan view representing a variation.

[0042] Figure 28 It is a plan view representing a variation.

[0043] Figure 29 It is a plan view representing a variation.

[0044] Figure 30 It is a plan view representing a variation.

[0045] Figure 31 This is a plan view showing the semiconductor device according to the third embodiment.

[0046] Figure 32 This is a schematic diagram illustrating the solder reflow process.

[0047] Figure 33 It is a plan view representing a variation.

[0048] Figure 34 It is a plan view representing a variation.

[0049] Figure 35 This is a diagram illustrating the localized concentration of electric current.

[0050] Figure 36 This is a plan view showing the semiconductor device according to the fourth embodiment.

[0051] Figure 37 It is along Figure 36 A sectional view of the XXXVII-XXXVII line.

[0052] Figure 38 It is a diagram representing the model used in the simulation.

[0053] Figure 39 This is a graph showing the relationship between thickness and the maximum current density at the solder joint.

[0054] Figure 40 It is a plan view representing a variation.

[0055] Figure 41 This is a plan view showing the heat sink on the emitter side of the semiconductor device in the fifth embodiment.

[0056] Figure 42 It is a magnified plan view of the heat sink on the emitter side.

[0057] Figure 43 Is with Figure 42 A cross-sectional view of the semiconductor device corresponding to the XLIII-XLIII line.

[0058] Figure 44 It is Figure 43 The XLIV section view is an enlarged view of the area.

[0059] Figure 45 It is a planar diagram showing the wetting and diffusion of the remaining solder.

[0060] Figure 46 Is with Figure 42 A cross-sectional view of the semiconductor device corresponding to the XLVI-XLVI line.

[0061] Figure 47 Is with Figure 42 A cross-sectional view of the semiconductor device corresponding to lines XLVII-XLVII.

[0062] Figure 48 This is a plan view representing a reference example.

[0063] Figure 49 It is a plan view representing a variation.

[0064] Figure 50 It is a plan view representing a variation.

[0065] Figure 51 It is a plan view representing a variation.

[0066] Figure 52 It is along Figure 51 A cross-sectional view of the LII-LII line.

[0067] Figure 53 It is a plan view representing a variation.

[0068] Figure 54 This is a sectional view representing a modified example.

[0069] Figure 55 It is a plan view representing a variation.

[0070] Figure 56 Is Figure 55 The diagram shown is a variation in which the sealing resin body is omitted.

[0071] Figure 57 It is along Figure 55 The cross-sectional view of line LVII-LVII shown.

[0072] Figure 58 It is a plan view representing a variation.

[0073] Figure 59 From Figure 58 A plan view viewed from the X4 direction.

[0074] Figure 60 It is a magnified plan view of the area around the joint.

[0075] Figure 61 This is a plan view showing the semiconductor device according to the sixth embodiment.

[0076] Figure 62 This is the equivalent circuit diagram of the semiconductor device that constitutes the lower arm.

[0077] Figure 63 This is a plan view showing the heat sink and main terminals on the emitter side of the semiconductor device according to the seventh embodiment.

[0078] Figure 64 This is a plan view showing the heat sink and main terminals on the collector side.

[0079] Figure 65 It is a schematic plan view representing a reference example.

[0080] Figure 66 It is a plan view representing a variation.

[0081] Figure 67 It is a plan view representing a variation.

[0082] Figure 68 This is a sectional view representing a modified example.

[0083] Figure 69 It is a plan view representing a variation.

[0084] Figure 70 It is a plan view representing a variation. Detailed Implementation

[0085] Several embodiments are described with reference to the accompanying drawings.

[0086] (First embodiment)

[0087] The semiconductor device and semiconductor module of this embodiment are applied to a power conversion device. The power conversion device is applied, for example, to the drive system of a vehicle. The power conversion device can be applied to vehicles such as electric vehicles (EVs) or hybrid vehicles (HVs). Hereinafter, an example of its application to a hybrid vehicle will be described.

[0088] <Vehicle drive system>

[0089] First, the general structure of the vehicle's drive system will be explained. For example... Figure 1 As shown, the vehicle's drive system 1 includes a DC power supply 2, an electric generator 3, and a power conversion device 4.

[0090] The DC power supply 2 is a rechargeable secondary battery such as a lithium-ion battery or a nickel-metal hydride battery. The electric generator 3 is a three-phase AC rotating electric motor. The electric generator 3 functions as the vehicle's driving force, i.e., an electric motor. Furthermore, it functions as a generator during regeneration. The vehicle includes an engine (not shown) and the electric generator 3 as driving forces. The power conversion device 4 performs power conversion between the DC power supply 2 and the electric generator 3.

[0091] <Circuit Structure of Power Conversion Device>

[0092] Next, the circuit structure of the power conversion device 4 will be explained. For example... Figure 1 As shown, the power conversion device 4 includes an inverter 5, a control circuit section 6, and a smoothing capacitor Cs. The inverter 5 is a power conversion section. The inverter 5 is a DC-AC conversion section. The power conversion section is configured with upper and lower arms 7.

[0093] The upper and lower arms 7 are circuits that connect the upper arm 7U and the lower arm 7L in series. Each of the upper arm 7U and the lower arm 7L has multiple switching elements equipped with gate electrodes. In each of the upper arm 7U and the lower arm 7L, the multiple switching elements are connected in parallel. In this embodiment, an n-channel IGBT is used as the switching element.

[0094] The upper arm 7U has two switching elements Q1. Each of the two switching elements Q1 is connected to a freewheeling diode D1. The diode D1 is connected in anti-parallel to the corresponding switching element Q1. The two parallel-connected switching elements Q1 are controlled by a gate drive signal that switches between high and low levels at the same timing. The gate electrodes of the two switching elements Q1 are electrically connected, for example, to the same drive circuit (gate driver). The upper arm 7U includes two semiconductor elements 31, which will be described later.

[0095] The lower arm 7L has two switching elements Q2. Each of the two switching elements Q2 is connected to a freewheeling diode D2. The diode D2 is connected in anti-parallel to the corresponding switching element Q2. The two parallel-connected switching elements Q2 are controlled by a gate drive signal that switches between high and low levels at the same timing. The gate electrodes of the two switching elements Q2 are electrically connected, for example, to the same drive circuit. The lower arm 7L includes two semiconductor elements 32, which will be described later.

[0096] The switching elements Q1 and Q2 are not limited to IGBTs. For example, MOSFETs can also be used. Parasitic diodes can also be used as diodes D1 and D2.

[0097] The upper arm 7U and the lower arm 7L are connected in series between power lines 8P and 8N, with the upper arm 7U as the power line 8P side. Power line 8P is the high-potential side power line. Power line 8P is connected to the positive terminal of DC power supply 2. Power line 8P is connected to the positive terminal of smoothing capacitor Cs. Power line 8N is the low-potential side power line. Power line 8N is connected to the negative terminal of DC power supply 2. Power line 8N is connected to the negative terminal of smoothing capacitor Cs. Power line 8N is also referred to as the grounding wire.

[0098] Inverter 5 is connected to DC power supply 2 via smoothing capacitor Cs. Inverter 5 has three sets of upper and lower arms 7 as described above. Inverter 5 has three-phase upper and lower arms 7. In each phase, the collector electrode of switching element Q1 is connected to power line 8P. The emitter electrode of switching element Q2 is connected to power line 8N. The emitter electrode of switching element Q1 and the collector electrode of switching element Q2 are interconnected to form the connection point of the upper and lower arms 7.

[0099] The connection points of the upper and lower arms 7 of phase U are connected to the phase U winding of the stator of the generator 3. The connection points of the upper and lower arms 7 of phase V are connected to the phase V winding of the generator 3. The connection points of the upper and lower arms 7 of phase W are connected to the phase W winding of the generator 3. The connection points of the upper and lower arms 7 of each phase are connected to the windings of the corresponding phase via load lines 9 provided for each phase. Load lines 9 are also called output lines.

[0100] Inverter 5, under the switching control of control circuit section 6, converts DC voltage into three-phase AC voltage and outputs it to generator 3. This drives generator 3 to produce a specified torque. During regenerative braking of the vehicle, generator 3 generates three-phase AC voltage due to the rotational force from the wheels. Inverter 5 can also convert the three-phase AC voltage generated by generator 3 back into DC voltage under the switching control of control circuit section 6 and output it to power line 8P. Thus, inverter 5 performs bidirectional power conversion between DC power supply 2 and generator 3.

[0101] The control circuit unit 6 is configured, for example, with a microcomputer. The control circuit unit 6 generates drive commands to operate the switching elements Q1 and Q2 of the inverter 5 and outputs them to a drive circuit unit (not shown). Specifically, the control circuit unit 6 outputs a PWM signal as a drive command. The drive command, for example, is the output duty cycle. The control circuit unit 6 generates the drive commands based on the torque requirement input from a higher-level ECU (not shown) and signals detected by various sensors.

[0102] Various sensors include current sensors that detect the phase current flowing through the windings of each phase of the generator 3, rotation angle sensors that detect the rotation angle of the rotor of the generator 3, and voltage sensors that detect the voltage across the smoothing capacitor Cs, i.e., the voltage of the power line 8P. The power conversion device 4 has these sensors (not shown).

[0103] The power conversion device 4 includes a drive circuit section (not shown). The drive circuit section generates drive signals based on drive commands from the control circuit section 6 and outputs them to the gate electrodes of the corresponding upper and lower arms 7 switching elements Q1 and Q2. This drives the switching elements Q1 and Q2, i.e., turns them on and off. The drive circuit section is provided, for example, for each arm.

[0104] A smoothing capacitor Cs is connected between power lines 8P and 8N. The smoothing capacitor Cs is located between the DC power supply 2 and the inverter 5, and is connected in parallel with the inverter 5. The smoothing capacitor Cs, for example, smooths the DC voltage supplied from the DC power supply 2 and accumulates the charge of that DC voltage. The voltage across the smoothing capacitor Cs becomes the high DC voltage used to drive the electric generator 3.

[0105] The power conversion device 4 may also include a converter, a filter capacitor, etc., as power conversion sections. The converter is a DC-DC converter that transforms DC voltage into DC voltages of different values. The converter is located between the DC power supply 2 and the smoothing capacitor Cs. For example, the converter boosts the DC voltage supplied from the DC power supply 2. The converter may also have a buck function. For example, the converter is configured with upper and lower arms and a reactor. The upper and lower arms of the converter can be made to have the same structure as the upper and lower arms 7. In the case of only boosting function, the lower arm of the converter can be made to have the same structure as the lower arm 7L of the inverter 5, and the upper arm can be constructed using diodes. The filter capacitor is connected in parallel with the DC power supply 2. For example, the filter capacitor removes power supply noise from the DC power supply 2.

[0106] <Structure of Semiconductor Devices>

[0107] Next, the semiconductor devices constituting the inverter 5 will be described. The upper and lower arms 7 are composed of a semiconductor module 10, which will be described later. The semiconductor module 10 includes... Figures 2-8 The two types (two models) of semiconductor devices 11 and 12 shown are used to construct the upper arm 7U, and the semiconductor device 12 constitutes the lower arm 7L.

[0108] Semiconductor devices 11 and 12 have different specifications. Figures 2-8In this design, the thickness direction of each semiconductor element is defined as the Z-direction, the direction orthogonal to the Z-direction and in which at least two semiconductor elements are arranged is defined as the X-direction, and the direction orthogonal to both the Z and X directions is defined as the Y-direction. Unless otherwise specified, the shape along the XY plane defined by the X and Y directions is defined as a planar shape. Figures 2-8 For convenience, the two semiconductor devices 11 and 12 are arranged horizontally in the diagram. Figures 6 to 8 The sealing resin body is omitted from the illustration. Furthermore, in... Figure 8 The heat sink on the emitter side is omitted from the illustration. Figure 8 The diagram shows the state of the lead frame before unnecessary parts such as the tie bar are removed, for convenience.

[0109] First, the semiconductor device 11 on the upper arm 7U side will be described. For the elements of the semiconductor device 11, the last digit of the reference numerals will be set to "1". For example... Figures 2-8 As shown, the semiconductor device 11 includes a sealing resin body 21, a semiconductor element 31, a heat sink 41, 51, a terminal 61, a main terminal 71, and a signal terminal 81.

[0110] The encapsulating resin body 21 encapsulates the corresponding semiconductor element 31, etc. The encapsulating resin body 21 is, for example, made of an epoxy resin. The encapsulating resin body 21 is formed, for example, by transfer molding. Figures 2-5 As shown, the sealing resin body 21 is approximately rectangular in shape. The planar shape of the sealing resin body 21 is approximately rectangular.

[0111] Semiconductor element 31 has a switching element Q1 and a diode D1 formed on a semiconductor substrate. An RC (Reverse Conducting) IGBT is also formed in semiconductor element 31. Semiconductor element 31 is also called a semiconductor chip. Semiconductor element 31 has a vertical structure with current flowing in the Z direction.

[0112] like Figure 4As shown, in the Z direction, a collector electrode 31c is formed on one side (first main surface) of the semiconductor element 31, and an emitter electrode 31e is formed on the back side (second main surface). The collector electrode 31c also serves as the cathode electrode of the diode D1, and the emitter electrode 31e also serves as the anode electrode of the diode D1. The collector electrode 31c is the electrode on the high potential side (main electrode), and the emitter electrode 31e is the electrode on the low potential side (main electrode). A pad (not shown) is also formed on the emitter electrode forming surface as a signal electrode. The pad is formed in the Y direction at the end opposite to the forming region of the emitter electrode 31e. In this embodiment, the semiconductor element 31 has five pads arranged along the X direction. The pads are arranged sequentially for the cathode potential, anode potential, gate electrode, current sensing, and Kelvin emitter for detecting the potential of the emitter electrode 31e of a temperature sensor (temperature-sensing diode) used to detect the temperature of the semiconductor element 30.

[0113] The semiconductor device 11 has a plurality of semiconductor elements 31. The plurality of semiconductor elements 31 are connected in parallel to form the upper arm 7U. In this embodiment, two semiconductor elements 31 are included. Figure 4 and Figure 8 As shown, the two semiconductor elements 31 have a generally identical structure, that is, they have the same shape and the same size. The planar shape of the semiconductor element 31 is generally rectangular. The two semiconductor elements 31 are configured such that the collector electrode 31c is on the same side in the Z direction. The two semiconductor elements 31 are located at approximately the same height in the Z direction and are arranged in the X direction.

[0114] like Figure 2 and Figure 8 As shown, the two semiconductor elements 31 are arranged linearly symmetrically about an axis AX1 orthogonal to both the X and Z directions. In this embodiment, the planar shape of the encapsulating resin body 21 is approximately rectangular, and the two semiconductor elements 31 are arranged such that the axis AX1 is approximately aligned with the center of the outer shape of the encapsulating resin body 21 in the X direction. The pads in the two semiconductor elements 31 are arranged in the same order.

[0115] Heat sinks 41 and 51 function to dissipate heat from semiconductor element 31 to the outside of semiconductor device 11. Heat sinks 41 and 51 are also referred to as heat dissipation components. Heat sinks 41 and 51 are electrically connected to semiconductor element 31, serving as wiring components. Heat sinks 41 and 51 are also referred to as wiring components. Heat sinks 41 and 51 are formed of metal materials such as copper. Heat sinks 41 and 51 are also referred to as metal components.

[0116] Heat sinks 41 and 51 are arranged to sandwich multiple semiconductor elements 31. In the Z-direction, two semiconductor elements 31 are arranged laterally between heat sinks 41 and 51. The semiconductor elements 31 are included within the heat sinks 41 and 51 in a projected view from the Z-direction. The thickness direction of the heat sinks 41 and 51 is approximately parallel to the Z-direction. Figure 2 , Figure 6 and Figure 8 As shown, in heat sinks 41 and 51, the X direction is the longer direction and the Y direction is the shorter direction.

[0117] Heat sinks 41 and 51 are electrically connected to semiconductor element 31 via solder or other bonding components. For example... Figure 4 As shown, heat sink 41 is connected to collector electrode 31c via solder 91a. Heat sink 51 is connected to emitter electrode 31e via solders 91b and 91c and terminal 61. Terminal 61 is a metal component that electrically connects semiconductor element 31 and heat sink 51. In a projected view from the Z direction, terminal 61 has a shape that is approximately the same as emitter electrode 31e. The planar shape of terminal 61 is approximately rectangular. Heat sink 51 is connected to terminal 61 via solder 91c. The side of terminal 61 opposite to heat sink 51 is connected to emitter electrode 31e via solder 91b.

[0118] like Figure 5 , Figure 6 and Figure 7 As shown, the heat sink 51 has a main body 51a and a connector 51b. A semiconductor element 31 is connected to one side of the main body 51a via a terminal block 61. The connector 51b is connected to the main body 51a. The connector 51b is integrally formed with the main body 51a as a single component. The connector 51b extends from one end of the main body 51a in the Y direction. The thickness of the connector 51b is thinner than that of the main body 51a.

[0119] Most of the heat sinks 41 and 51 are covered by the encapsulating resin body 21. The surfaces of the heat sinks 41 and 51 opposite to the semiconductor element 31 are exposed from the encapsulating resin body 21. In the Z direction, the heat sink 41 is exposed from one side 21a of the encapsulating resin body 21, and the heat sink 51 is exposed from the back side 21b opposite to one side 21a. The exposed surface of the heat sink 41 is approximately coplanar with one side 21a, and the exposed surface of the heat sink 51 is approximately coplanar with the back side 21b.

[0120] The main terminal 71 is an external connection terminal through which the main current flows. The semiconductor device 11 has three or more main terminals 71. The main terminal 71 has a collector terminal C1 and an emitter terminal E1. The collector terminal C1 is connected to the heat sink 41. The collector terminal C1 is electrically connected to the collector electrode 41c via the heat sink 41. The emitter terminal E1 is connected to the heat sink 51. The emitter terminal E1 is electrically connected to the emitter electrode 31e via the heat sink 51 and the terminal 61.

[0121] The semiconductor device 11 has three main terminals 71. For example... Figure 2 , Figure 3 , Figure 6 and Figure 8 As shown, the main terminal 71 has one collector terminal C1 and two emitter terminals E1. Figure 8 As shown, the lead frame 101 includes a heat sink 41, a collector terminal C1 serving as a main terminal 71, an emitter terminal E1, and a signal terminal 81.

[0122] The heat sink 41 is thicker than the other parts of the lead frame 101, namely the main terminals 71 and the signal terminals 81. The main terminals 71 and the signal terminals 81 are connected to the component mounting surfaces of the heat sink 41 substantially coplanar. The ends of the multiple main terminals 71 on the same side are connected to the outer frame 101a. The heat sink 41 is fixed to the outer frame 101a via the collector terminal C1 and the suspension conductor 101b. The signal terminals 81 are fixed to the suspension conductor 101b via the connecting rod 101c. The lead frame 101 has multiple reference holes 101d for positioning.

[0123] The collector terminal C1 is integrally formed with the heat sink 41 as a single component. The collector terminal C1 has a bent portion within the sealing resin body 21, protruding outward from near the center in the Z direction on one side 21c of the sealing resin body 21. The emitter terminals E1 each have a counter portion E1a opposite to the connector portion 51b of the heat sink 51. Figure 5 As shown, the opposing portion E1a is connected to the connector portion 51b via solder 91d. The emitter terminal E1 has a curved portion within the encapsulating resin body 21, protruding outward from near the center in the Z direction on the same side 21c as the collector terminal C1. All the main terminals 71 protrude from the side 21c. In the heat sink 51, an annular groove (not shown) may be formed, for example, to surround the connection portions connected to the solder 91c and 91d respectively. Overflowing solder is collected in the groove. To suppress solder wetting and diffusion, a rough coating or a roughened portion formed by laser irradiation may be provided instead of the groove.

[0124] The protruding portions of the collector terminal C1 and the emitter terminal E1 extend in the Y direction. The collector terminal C1 and the emitter terminal E1 are arranged in the X direction, with their respective plate thickness directions approximately aligned with the Z direction. For example... Figure 3 As shown, in the X direction, a collector terminal C1 is arranged between the emitter terminals E1. The arrangement of the main terminals 71 is symmetrical with respect to the center of the arrangement. The main terminals 71 are arranged in the order of emitter terminal E1, collector terminal C1, and emitter terminal E1.

[0125] like Figure 2 and Figure 8 As shown, the collector terminal C1 and the emitter terminal E1 are arranged linearly symmetrically about axis AX1. The collector terminal C1 is positioned on axis AX1, and the center of the width of the collector terminal C1 is approximately aligned with axis AX1. The two emitter terminals E1 are arranged linearly symmetrically about axis AX1. The following... Figure 8 As shown, there is a case where one of the semiconductor elements 31 is referred to as semiconductor element 31a and the other semiconductor element 31 is referred to as semiconductor element 31b. One of the emitter terminals E1 is configured to be biased toward the semiconductor element 31a side relative to the axis AX1, and the other emitter terminal E1 is configured to be biased toward the semiconductor element 31b side relative to the axis AX1.

[0126] Signal terminal 81 is connected to the pad of the corresponding semiconductor element 31. Signal terminal 81 is connected to the pad via bonding wire 111 inside the encapsulating resin body 21. Signal terminal 81 protrudes outward from the side of the encapsulating resin body 21, specifically from the side 21d opposite to side 21c. Signal terminal 81 protrudes in the opposite direction to the main terminal 71 in the Y direction.

[0127] In the semiconductor device 11 described above, the encapsulating resin body 21 integrally encapsulates a portion of each of the semiconductor element 31, heat sinks 41 and 51, terminal 61, main terminal 71, and signal terminal 81.

[0128] Next, the semiconductor device 12 on the lower arm 7L side will be described. For the elements of the semiconductor device 12, the last digit of the reference numerals will be "2". The semiconductor device 12 includes a sealing resin body 22, a semiconductor element 32, heat sinks 42 and 52, a terminal block 62, a main terminal 72, and a signal terminal 82. Since the semiconductor device 12 has the same constituent elements and a largely similar structure as the semiconductor device 11, the differences will be mainly described.

[0129] The encapsulating resin body 22 encapsulates the semiconductor element 32, etc. For example... Figure 4As shown, in the Z direction, a collector electrode 32c is formed on one side of the semiconductor element 32, and an emitter electrode 32e is formed on the back side. The semiconductor device 12 also has a plurality of semiconductor elements 32. The plurality of semiconductor elements 32 are connected in parallel to form the lower arm 7L. In this embodiment, two semiconductor elements 32 are provided. The two semiconductor elements 32 have the same structure. The two semiconductor elements 32 are located at approximately the same height in the Z direction and are arranged in the X direction.

[0130] like Figure 2 and Figure 8 As shown, the two semiconductor elements 32 are arranged linearly symmetrically about an axis AX2 orthogonal to both the X and Z directions. In this embodiment, the planar shape of the encapsulating resin body 22 is approximately rectangular, and the two semiconductor elements 32 are arranged such that the axis AX2 is approximately aligned with the center of the outer shape of the encapsulating resin body 22 in the X direction.

[0131] Heat sinks 42 and 52 are configured to sandwich multiple semiconductor elements 32. The thickness direction of heat sinks 42 and 52 is approximately parallel to the Z-direction. Figure 2 , Figure 6 and Figure 8 As shown, in heat sinks 42 and 52, the X direction is set as the longer direction, and the Y direction is set as the shorter direction. For example... Figure 4 As shown, heat sink 42 is connected to collector electrode 32c via solder 92a. Heat sink 52 is connected to emitter electrode 32e via solder 92b, 92c and terminal 62.

[0132] The heat sink 52 has a main body portion 52a connected to the semiconductor element 32 via a terminal block 62, and a connector portion 52b connected to the main body portion 52a. The connector portion 52b extends from one end of the main body portion 52a in the Y direction. The thickness of the connector portion 52b is thinner than that of the main body portion 52a. The heat sink 42 is exposed from one side 22a of the encapsulating resin body 22, and the heat sink 52 is exposed from the back side 22b opposite to the one side 22a. The exposed surface of the heat sink 42 is substantially coplanar with the one side 22a, and the exposed surface of the heat sink 52 is substantially coplanar with the back side 22b.

[0133] Semiconductor device 12 has three or more main terminals 72. Each main terminal 72 has a collector terminal C2 and an emitter terminal E2. The collector terminal C2 is electrically connected to the collector electrode 42c via a heat sink 42. The emitter terminal E2 is electrically connected to the emitter electrode 32e via a heat sink 52 and a terminal block 62. Semiconductor device 12 has the same number of main terminals 72 as semiconductor device 11. Each main terminal 72 has two collector terminals C2 and one emitter terminal E2. Figure 8 As shown, the lead frame 102 includes a heat sink 42, a collector terminal C2 serving as a main terminal 72, an emitter terminal E2, and a signal terminal 82. Figure 8 The label 102a is the outer frame, label 102b is the suspension conductor, label 102c is the connecting rod, and label 102d is the reference hole.

[0134] The collector terminal C2 is integrally provided with the heat sink 42 as a component. The collector terminal C2 has a curved portion within the sealing resin body 22, protruding outward from near the center in the Z direction on one side 22c of the sealing resin body 22. The emitter terminal E2 has a counter portion E2a opposite to the connector portion 52b of the heat sink 52. The counter portion E2a is connected to the connector portion 52b via solder 92d. The emitter terminal E2 has a curved portion within the sealing resin body 22, protruding outward from near the center in the Z direction on the same side 22c as the collector terminal C2. In the heat sink 52, an annular groove may be formed, for example, to surround the connection portions connected to the solder 92c and 92d respectively.

[0135] The protruding portions of collector terminal C2 and emitter terminal E2 extend in the Y direction. Collector terminal C2 and emitter terminal E2 are arranged in the X direction, with their respective plate thickness directions approximately aligned with the Z direction. For example... Figure 3 As shown, in the X direction, the emitter terminal E2 is arranged between the collector terminals C2. The arrangement of the main terminals 72 is symmetrical with respect to the center of the arrangement. The main terminals 72 are arranged in the order of collector terminal C2, emitter terminal E2, collector terminal C2. The arrangement order of the main terminals 72 and the main terminals 71 is opposite to that of each other.

[0136] like Figure 2 and Figure 8 As shown, the collector terminal C2 and the emitter terminal E2 are arranged linearly symmetrically about axis AX2. Emitter terminal E2 is positioned on axis AX2, and the center of the width of emitter terminal E2 is approximately aligned with axis AX2. The two collector terminals C2 are arranged linearly symmetrically about axis AX2. The following... Figure 8 As shown, there is a case where one of the semiconductor elements 32 is designated as semiconductor element 32a and the other semiconductor element 32 is designated as semiconductor element 32b. One collector terminal C2 is configured to be biased toward the semiconductor element 32a side relative to the axis AX2, and the other collector terminal C2 is configured to be biased toward the semiconductor element 32b side relative to the axis AX2.

[0137] Signal terminal 82 is connected to the pad of semiconductor element 32 via bonding wire 112 inside the encapsulating resin body 22. Signal terminal 82 protrudes outward from side 22d opposite to side 22c within the encapsulating resin body 22.

[0138] <Methods for Manufacturing Semiconductor Devices>

[0139] Next, the manufacturing methods of semiconductor devices 11 and 12 will be described. Since the manufacturing processes (steps) of semiconductor devices 11 and 12 are the same, semiconductor device 11 will be used as an example for explanation.

[0140] First, prepare the various elements that constitute the semiconductor device 11. Figure 8 The lead frame 101 is shown. In addition, a semiconductor element 31, a terminal block 61, and a heat sink 51 are prepared.

[0141] Next, a semiconductor element 31 is disposed on the mounting surface of the heat sink 41 of the lead frame 101 via solder 91a. The semiconductor element 31 is disposed on the solder 91a with the collector electrode 31c facing the mounting surface. Next, a terminal 61 is disposed on the emitter electrode 31e via solder 91b. Solder 91c is disposed on the surface of the terminal 61 opposite to the semiconductor element 31. The solder 91c is configured in an amount capable of absorbing height deviations in the semiconductor device 11. Solder 91b and 91c can also be provided on the terminal 61 as pre-soldering. Furthermore, solder 91d is disposed on the opposite portion E1a of the emitter terminal E1. The solder 91d is also configured in an amount capable of absorbing height deviations in the semiconductor device 11.

[0142] The first reflow is performed in this stacked state. Here, the collector electrode 31c of the semiconductor element 31 is connected to the heat sink 41 via solder 91a. Furthermore, the emitter electrode 31e of the semiconductor element 31 is connected to the corresponding terminal 61 via solder 91b. That is, a connector integrating the lead frame 101, the semiconductor element 31, and the terminal 61 is obtained. Solders 91c and 91d serve as pre-soldering in the connector for use in subsequent processes.

[0143] Next, the pads of the semiconductor element 31 are electrically connected to the signal terminal 81. In this embodiment, the pads of the semiconductor element 31 are connected to the signal terminal 81 via bonding wire 111.

[0144] Next, the heat sink 41 is positioned on a pedestal (not shown) with the terminal 61 side facing upwards. Then, the heat sink 51 is positioned on the heat sink 41 with the mounting surface on the terminal 61 side facing downwards. A second reflow is performed in this configuration. Through the second reflow, the heat sink 51 and the connector including the lead frame 101 are integrated.

[0145] Next, the sealing resin body 21 is formed. In this embodiment, transfer molding is used. The connector including the lead frame 101 is placed into the mold, and the sealing resin body 21 is formed. In this embodiment, the sealing resin body 21 is formed to completely cover the heat sinks 41 and 51.

[0146] Next, the unnecessary parts of the lead frame 101, such as the outer frame 101a and the connecting rod 101c, are removed. This yields the semiconductor device 11.

[0147] <Overview of Semiconductor Module Structure>

[0148] Next, the general structure of the semiconductor module will be explained. One semiconductor module constitutes the upper and lower arms 7 of one phase. Three semiconductor modules constitute the inverter 5. (As follows...) Figure 9 and Figure 10 As shown, the semiconductor module 10 includes the aforementioned semiconductor devices 11 and 12, connecting component 13, and cooler 14. Figure 9 For convenience, cooler 14 is omitted.

[0149] The cooler 14 is formed using a metallic material with excellent thermal conductivity, such as aluminum. The cooler 14 is generally a flat, tubular shape. To cool the semiconductor devices 11 and 12 that generate heat during operation, the semiconductor devices 11 and 12 and the cooler 14 are alternately stacked. The semiconductor devices 11 and 12 and the cooler 14 are arranged in the Z direction. The semiconductor devices 11 and 12 are each sandwiched between the coolers 14. The semiconductor devices 11 and 12 are cooled from both sides by the coolers 14.

[0150] Cooler 14 is connected to an inlet pipe and an outlet pipe (not shown). If refrigerant is supplied to the inlet pipe by a pump (not shown), the refrigerant flows through the flow path within the stacked coolers 14. This cools the semiconductor devices 11 and 12 with refrigerant. The refrigerant flowing through each cooler 14 is discharged via the outlet pipe.

[0151] In semiconductor device 11, the collector terminal C1 on the high-potential side is electrically connected to the power line 8P. The emitter terminal E1 on the low-potential side is the output terminal. The collector terminal C1 is also called the P terminal or positive terminal, and the output terminal is also called the O terminal. In semiconductor device 12, the collector terminal C2 on the high-potential side is the output terminal. The emitter terminal E2 on the low-potential side is electrically connected to the power line 8N. The collector terminal C2 is also called the O terminal, and the emitter terminal E2 is also called the N terminal or negative terminal.

[0152] like Figure 9 and Figure 10 As shown, a set of semiconductor devices 11 and 12 constituting the upper and lower arms 7 are arranged adjacent to each other across the cooler 14. The semiconductor devices 11 and 12 are configured such that the collector terminal C1 is opposite to the emitter terminal E2, and the emitter terminal E1 is opposite to the collector terminal C2. Opposition means that the plate surfaces face each other in at least a portion of the protrusions extending from the corresponding sealing resin bodies 21 and 22. In this embodiment, the protrusions extending from the corresponding sealing resin bodies 21 and 22 are opposite each other over approximately the entire area.

[0153] Connector 13 is a component that connects semiconductor devices 11 and 12. Connector 13 is wiring that electrically connects the upper arm 7U and the lower arm 7L. Connector 13 electrically connects the emitter terminal E1 and the collector terminal C2, which serve as output terminals. A semiconductor module 10 has two connectors 13 for connecting two sets of output terminals.

[0154] The connecting component 13 is formed, for example, by machining a metal plate. The connecting component 13 is also called a bridging component or a connecting busbar. The connecting component 13 is connected to the emitter terminal E1 and the collector terminal C2, for example, by welding. In this embodiment, the connecting component 13 is approximately U-shaped. The emitter terminal E1 is connected to one end of the connecting component 13, and the collector terminal C2 is connected to the other end. The connecting components 13 are configured such that the corresponding output terminals are opposite each other on the board surface, and are connected in this configuration. Both connecting components 13 have the same construction.

[0155] Figure 11 This is an equivalent circuit diagram considering the wiring inductance (parasitic inductance) of the upper and lower arms 7 of the semiconductor module 10. Figure 11 In the diagram, for switching element Q1, the switching element formed on semiconductor element 31a is denoted as Q1a, and the switching element formed on semiconductor element 31b is denoted as Q1b. Similarly, for switching element Q2, the switching element formed on semiconductor element 32a is denoted as Q2a, and the switching element formed on semiconductor element 32b is denoted as Q2b. Lc11, Lc12, Le11, and Le12 represent the wiring inductance of the parallel circuit of switching element Q1. Lc21, Lc22, Le21, and Le22 ​​represent the wiring inductance of the parallel circuit of switching element Q2.

[0156] As described above, semiconductor devices 11 and 12 each have three or more main terminals 71 and 72. That is, in semiconductor device 11, at least one of the collector terminal C1 and the emitter terminal E1 is multiple. Similarly, in semiconductor device 12, at least one of the collector terminal C2 and the emitter terminal E2 is multiple. Multiple main terminals of the same type are connected in parallel. For example, the emitter terminal E1 is connected in parallel, and the collector terminal C2 is connected in parallel. This reduces the inductance of the main terminals.

[0157] In semiconductor devices 11 and 12, the main terminals 71 and 72 are arranged in reverse order. The number of emitter terminals E1 and collector terminals C2, which serve as output terminals, is the same. Therefore, compared to the case where the upper and lower arms are constructed using semiconductor devices of the same type, the connection structure between the output terminals is simplified, thereby reducing the inductance of the main circuit wiring. The main circuit is the circuit that includes the smoothing capacitor Cs and the upper and lower arms 7.

[0158] The arrangement of collector terminal C1 and emitter terminal E1 is symmetrical with respect to the center of the arrangement. Compared to an asymmetrical structure, this allows wiring inductors Lc11 and Lc12 to be closer to each other, and wiring inductors Le11 and Le12 to be closer to each other. Furthermore, the arrangement of collector terminal C2 and emitter terminal E2 is symmetrical with respect to the center of the arrangement. Compared to an asymmetrical structure, this allows wiring inductors Lc21 and Lc22 to be closer to each other, and wiring inductors Le21 and Le22 ​​to be closer to each other. Thus, in each of the semiconductor devices 11 and 12, the imbalance of current flowing during switching, i.e., the imbalance of AC current, can be suppressed.

[0159] In semiconductor device 11, with the arrangement order symmetrical, the number of collector terminals C1 and emitter terminals E1 that are adjacent to each other in the X direction is increased. The adjacent collector terminals C1 and emitter terminals E1 are side-by-side facing each other. Through the effect of magnetic flux cancellation, inductance can be reduced. Similarly, inductance can also be reduced in semiconductor device 12.

[0160] Multiple semiconductor elements 31 are symmetrically arranged with respect to an axis AX1 orthogonal to the arrangement direction, i.e., the X direction. Furthermore, the collector terminal C1 and the emitter terminal E1 are arranged linearly symmetrically about the axis AX1. Therefore, the current paths from collector terminal C1 to switching element Q1a to emitter terminal E2 and from collector terminal C1 to switching element Q1b to emitter terminal E2 are approximately linearly symmetrical about the axis AX1. That is, the wiring inductances Lc11 and Lc12 are approximately equal. The wiring inductances Le11 and Le12 are also approximately equal. Therefore, in the semiconductor device 11, AC current imbalance can be effectively suppressed.

[0161] Similarly, multiple semiconductor elements 32 are symmetrically arranged with respect to an axis AX2 orthogonal to the arrangement direction, i.e., the X direction. Furthermore, the collector terminal C2 and the emitter terminal E2 are arranged linearly symmetrically about the axis AX2. Thus, the current paths from collector terminal C2 to switching element Q2a to emitter terminal E2 and from collector terminal C2 to switching element Q2b to emitter terminal E2 are approximately linearly symmetrical about the axis AX2. That is, the wiring inductances Lc21 and Lc22 are approximately equal. The wiring inductances Le21 and Le22 ​​are also approximately equal. Therefore, in the semiconductor device 12, AC current imbalance can be effectively suppressed.

[0162] In this embodiment, the centers of the arranged semiconductor elements 31 are completely aligned in the Y direction. Furthermore, the centers of the arranged semiconductor elements 32 are also completely aligned in the Y direction. This allows for more effective suppression of AC current imbalance. However, complete alignment of the centers is not a limitation. A slight offset in the Y direction can also achieve an effect comparable to the above.

[0163] Furthermore, in order to make electrical connections with the smoothing capacitor Cs and the electric generator 3, the main terminals 71 and 72 are connected to busbars, etc. The busbars are, for example, soldered. Therefore, the above-mentioned effect can be achieved if the main terminals 71 and 72 are made linearly symmetrical at least with respect to the portion forming the current path, that is, the portion up to the connection position with the busbar.

[0164] The axis AX1 is approximately aligned with the center of the outer shape of the encapsulating resin body 21 in the X direction. This allows for miniaturization of the semiconductor device 11 while achieving the aforementioned effects. Similarly, the axis AX2 is approximately aligned with the center of the outer shape of the encapsulating resin body 22 in the X direction. This allows for miniaturization of the semiconductor device 12 while achieving the aforementioned effects.

[0165] Semiconductor devices 11 and 12 are connected by multiple connecting components 13. By increasing the connection path between the upper arm 7U and the lower arm 7L, the inductance of the main circuit wiring can be reduced.

[0166] All main terminals 71 protrude from the side 21c of the encapsulating resin body 21 and are arranged along the X direction. All main terminals 72 protrude from the side 22c of the encapsulating resin body 22 and are arranged along the X direction. This simplifies the connection between the upper arm 7U and the lower arm 7L, as well as the connection with the smoothing capacitor Cs, and reduces the inductance of the main circuit wiring.

[0167] The protruding portions of collector terminal C1 and emitter terminal E2 are roughly opposite each other throughout the entire area, and the protruding portions of emitter terminal E1 and collector terminal C2 are roughly opposite each other throughout the entire area. Therefore, the inductance of the main circuit wiring can be effectively reduced.

[0168] Heat sinks 41 and 51 are common to multiple semiconductor elements 31. Therefore, voltage swings between switching elements Q1 can be suppressed. Similarly, heat sinks 42 and 52 are common to semiconductor elements 32, so voltage swings between switching elements Q2 can be suppressed. Furthermore, the number of components can be reduced.

[0169] <Detailed Structure of Semiconductor Modules>

[0170] Next, the structure of the aforementioned semiconductor module will be explained in detail. Figure 12 and Figure 2Correspondingly, the elements within the sealed resin bodies 21 and 22 are represented by dashed lines.

[0171] The semiconductor module 10 is configured as described above, comprising semiconductor devices 11 and 12 having three or more main terminals 71 and 72. To ensure positional accuracy during resin molding, all main terminals 71 and 72 are configured within lead frames 101 and 102. The reversed arrangement of the main terminals 71 and 72 results in differences in the connection structure between the emitter terminals E1 and E2 and the heat sinks 51 and 52 in the semiconductor devices 11 and 12. This may complicate the manufacturing process and reduce productivity.

[0172] Furthermore, if the emitter terminal E1 and the collector terminal C1 are together formed in the lead frame 101, the heat sink 51 side is not clamped through the mold, and only the heat sink 41 (lead frame 101) side is clamped. Since only one component is clamped, the positional accuracy of the sealing resin body 21 during molding is improved. For example, resin leakage can be suppressed. The same applies to the lead frame 102.

[0173] Regarding the aforementioned problems, in the semiconductor module 10 of this embodiment, as follows: Figures 2-5 and Figure 12 As shown, at least the root portions 71r and 72r of the protruding portions of the sealing resin bodies 21 and 22 and the main terminals 71 and 72 have the same structure. The sealing resin bodies 21 and 22 have the same shape and size. The sealing resin bodies 21 and 22 have the same appearance. The root portions 71r and 72r have the same shape and size.

[0174] The root portions 71r and 72r of the collector terminal C1 and the emitter terminal E2 have the same structure. The root portions 71r and 72r of the emitter terminal E1 and the collector terminal C2 also have the same structure. The arrangement (position) of the root portions 71r and 72r relative to the sealing resin bodies 21 and 22 is also the same. This allows the sealing resin bodies 21 and 22 to be formed using the same mold. By standardizing the mold, productivity can be improved. For example, mold changes can be eliminated.

[0175] Furthermore, the root portions 71r and 72r are the portions of the main terminals 71 and 72 that are clamped by the mold during the molding of the encapsulating resin bodies 21 and 22. They are portions located within a specified range (e.g., approximately 1 mm) from the sides 21c and 22c of the encapsulating resin bodies 21 and 22. The term "same configuration" refers, for example, to the positional relationship where the root portions 71r and 72r approximately completely overlap when viewed from a Z-direction projection, in a state where the semiconductor devices 11 and 12 are stacked in a manner that makes the encapsulating resin bodies 21 and 22 consistent.

[0176] Furthermore, a solder joint 121 via solder 91d is formed between heat sink 51 and emitter E1. A solder joint 122 via solder 92d is formed between heat sink 52 and emitter E2. Moreover, with at least one of the encapsulating resin bodies 21, 22 and root portions 71r, 72r as the position reference for the semiconductor devices 11, 12, at least a portion of the solder joints 121, 122 are located at the same position in the Y direction. Figure 12 As shown, solder joints 121 and 122 are respectively provided on an imaginary line L1 parallel to the X direction.

[0177] Therefore, solder bonding can be performed under the same reflow process and conditions. In particular, a second reflow can be performed under the same process and conditions. When reflowing while conveying along the X direction, for example, the positions of the heaters can be made the same. Furthermore, when the heaters are provided directly below the heat sinks 41 and 42, the heat conduction distances from the heaters to the solder joints 121 and 122 can be made approximately equal. Therefore, during reflow, deviations in the melting state of the solder 91d and 92d can be suppressed.

[0178] Thus, the semiconductor module 10 according to this embodiment can improve productivity while having two types (two models) of semiconductor devices 11 and 12. In particular, in this embodiment, the Y-direction centers of the solder joints 121 and 122 are aligned with each other. As a result, productivity can be further improved.

[0179] Furthermore, the other clamping portions of the lead frames 101 and 102 are also constructed in the same way, and their arrangement relative to the sealing resin bodies 21 and 22 is also the same. For example, the root portions 81r and 82r of the protruding parts of the signal terminals 81 and 82 are constructed in the same way, and their arrangement (position) relative to the sealing resin bodies 21 and 22 is also the same. The root portions 101br and 102br of the protruding parts of the suspension conductors 101b and 102b are constructed in the same way, and their arrangement (position) relative to the sealing resin bodies 21 and 22 is also the same.

[0180] In this embodiment, the protruding portions of the main terminals 71 and 72 have the same structure and are arranged identically. Although the potentials (collector / emitter) of the main terminals 71 and 72 of the semiconductor devices 11 and 12 are opposite, their appearances are identical. This further improves productivity. For example, they can be easily manufactured under the same processes and conditions. For example, they can be connected to the smoothing capacitor Cs under the same processes and conditions.

[0181] In this embodiment, such as Figure 12As shown, the solder joint 121 is arranged linearly symmetrically about axis AX1. The semiconductor element 31 and the solder joint 121 are also arranged linearly symmetrically about axis AX1. Furthermore, the solder joint 122 is arranged linearly symmetrically about axis AX2. The semiconductor element 32 and the solder joint 122 are also arranged linearly symmetrically about axis AX2. This achieves balance during reflow (second reflow) in the X direction. This improves productivity. For example, it can suppress the tilting of heat sinks 51 and 52 in the longer X direction. Furthermore, it can suppress AC current imbalance.

[0182] In this embodiment, the positioning reference holes 101d and 102d provided in the lead frames 101 and 102 are also positioned identically to each other, using the sealing resin bodies 21 and 22 as position references. For example, positioning pins (not shown) are aligned with the reference holes 101d and 102d for positioning. Therefore, the positions of corresponding elements in the semiconductor devices 11 and 12 can be aligned with good accuracy.

[0183] In this embodiment, such as Figure 12 As shown, the width W1 of the plurality of main terminals 71 and the width W2 of the plurality of main terminals 72 are equal. In other words, the widths of the lead frames 101 and 102 in the X direction are equal. Therefore, in each process, before positioning (formal positioning) through the reference holes 101d and 102d, temporary positioning can be performed using the outlines of the lead frames 101 and 102. This reduces the time spent on positioning. Width W1 is the length of the arrangement area of ​​the plurality of main terminals 71 in the width direction of the main terminals 71. Width W2 is the length of the arrangement area of ​​the plurality of main terminals 72 in the width direction of the main terminals 72.

[0184] In this embodiment, the heat sinks 41 and 42, which are thick-walled portions in the lead frames 101 and 102, have the same structure. Since the heat sinks 41 and 42 have the same heat capacity, solder bonding can be performed under the same reflow process and conditions when forming the semiconductor devices 11 and 12. For example, the first reflow can be performed under the same process and conditions.

[0185] In this embodiment, examples are shown where the structures of heat sinks 51 and 52 differ, but the embodiment is not limited to this. Other embodiments are also possible. Figure 13 The heat sinks 51 and 52 shown in the modified example have the same structure. Heat sinks 51 and 52 are identical in shape and size. Heat sinks 51 and 52 have the same heat capacity. This allows for stable second reflow. Furthermore, by standardizing heat sinks 51 and 52, the number of parts can be reduced.

[0186] When semiconductor devices 11 and 12 have the same appearance, at least one of them may be provided with a mark to distinguish it from the other. The mark may be located on the protruding front side beyond the portion connecting the busbar, etc. That is, it may be located in a portion that does not affect the current operation of the upper and lower arms 7. Figure 14 In the illustrated variation, a notch 71m is provided as a marker on one of the emitter terminals E1 of the semiconductor device 11. This prevents the accidental connection of identical semiconductor devices to each other. The position of the notch 71m in the main terminal 71 is not limited to the emitter terminal E1. Other notches besides the notch 71m can also be provided at different locations on the semiconductor device 12. For example, a notch can be provided at the protruding tip of the emitter terminal E2.

[0187] Different markings than the notch can also be used. For example, markings formed by printing, laser processing, etc., can also be used. To improve productivity, the notch described above is preferred. The notch can be formed, for example, when forming the lead frames 101, 102 or when removing the connecting rods 101c, 102c, etc. (conductor cutting).

[0188] This illustration shows examples where semiconductor devices 11 and 12 each have three main terminals 71 and 72, but are not limited to this. They can also be configured to have four or more main terminals 71 and 72. Figure 15 In the illustrated variant, semiconductor devices 11 and 12 have seven corresponding main terminals 71 and 72. Semiconductor device 11 has three collector terminals C1 and four emitter terminals E1. The collector terminals C1 and emitter terminals E1 are arranged alternately in the X direction.

[0189] The semiconductor device 12 includes four collector terminals C2 and three emitter terminals E2. The collector terminals C2 and emitter terminals E2 are arranged alternately in the X direction. The arrangement of the main terminals 71 and 72 is symmetrical with respect to the center of the arrangement. The arrangement order is reversed when viewed from the center of the main terminals 71 and 72. There are four solder joints 121 and three solder joints 122. Figure 15 In the middle, heat sinks 51 and 52 are related to Figure 13 Same construction.

[0190] This illustrates an example where semiconductor devices 11 and 12 have two corresponding semiconductor elements 31 and 32, but are not limited to this. They may also have three or more semiconductor elements 31 and 32.

[0191] Examples of semiconductor devices 11 and 12 with terminals 61 and 62 are shown as having a two-sided heat dissipation structure, but they are not limited to this. A structure without terminals 61 and 62 may also be made. An example is shown where heat sinks 41, 42, 51, and 52 are exposed from their respective encapsulating resin bodies 21 and 22, but a structure where they are not exposed from the encapsulating resin bodies 21 and 22 may also be made. Heat sinks 41, 42, 51, and 52 may also be divided into multiple components, for example, depending on the number of semiconductor elements 31 and 32. However, an integrated design can improve productivity. Furthermore, voltage fluctuations can be suppressed in parallel circuits.

[0192] (Second Implementation)

[0193] In this embodiment, the same reference numerals are assigned to parts that are functionally and / or structurally corresponding to or associated with parts in prior embodiments. The corresponding parts and / or associated parts can be described according to the prior embodiments.

[0194] like Figure 16 and Figure 17 As shown, the semiconductor module 10 of this embodiment also includes a load line 9. The load line 9 is formed of a metal material such as copper. The load line 9 is formed in a plate shape, for example. The load line 9 is also called a busbar. In the semiconductor module 10, a connecting member 13a connected to the load line 9 and a connecting member 13b not connected to the load line 9 are provided as connecting members 13.

[0195] The load line 9 can be either integrally provided with the connecting component 13a or connected to the connecting component 13a. The load line 9 is connected to the connecting component 13a at a predetermined position. Figure 16 and Figure 17 For convenience, the cooler 14 is omitted from the illustration.

[0196] By connecting the load line 9 only to the connecting component 13a, the connection structure with the electric generator 3 can be simplified. Furthermore, the connection between the collector terminal C1 and the emitter terminal E2 and the smoothing capacitor Cs can also be simplified.

[0197] The basic structure of semiconductor devices 11 and 12 is the same as in the prior embodiment. Semiconductor device 11 has one collector terminal C1 and two emitter terminals E1. Semiconductor device 12 has two collector terminals C2 and one emitter terminal E2. The emitter terminals E1 and E2 of semiconductor devices 11 and 12 are soldered to the corresponding heat sinks 51 and 52.

[0198] Hereinafter, one of the emitter terminals E1 will sometimes be referred to as emitter terminal E11 and the other as emitter terminal E12. One of the collector terminals C2 will sometimes be referred to as collector terminal C21 and the other as collector terminal C22. In the X direction, emitter terminal E11 is disposed on the semiconductor element 31a side, and emitter terminal E12 is disposed on the semiconductor element 31b side. Collector terminal C21 is disposed on the semiconductor element 32a side, and collector terminal C22 is disposed on the semiconductor element 32b side.

[0199] The connection position of load line 9 will be explained below.

[0200] Figure 18 The circuit model of the upper and lower arms 7 of the wiring resistor was designed to verify the connection position of the load line 9. Figure 18 The load shown corresponds to the stator winding of the electric generator 3. The load is an inductive load (L load). Hereinafter, the collector terminal C1, which is the P terminal, will sometimes be simply referred to as P, the emitter terminal E2, which is the N terminal, will sometimes be simply referred to as N, and the load line 9, which is the output line, will sometimes be simply referred to as O.

[0201] like Figure 18 As shown, the upper and lower arms 7 have a first path F1 and a second path F2 as paths connecting the upper arm 7U and the lower arm 7L. Hereinafter, they are sometimes simply referred to as paths F1 and F2. The first path F1 has a connecting component 13a, a transmitter terminal E11, and a collector terminal C21. The connecting component 13a is soldered to the transmitter terminal E11 and the collector terminal C21, which serve as output terminals. In the first path F1, the main resistive components include the resistance R1 of the soldered portion between the transmitter terminal E11 and the connecting component 13a, the wiring resistance of the connecting component 13a itself (i.e., resistances R2 and R3), and the resistance R4 of the soldered portion between the collector terminal C21 and the connecting component 13a.

[0202] The second path F2 has a connecting component 13b, a transmitter terminal E12, and a collector terminal C22. The connecting component 13b is soldered to the transmitter terminal E12 and the collector terminal C22, which serve as output terminals. In the second path F2, the main resistive components include the resistance R5 of the solder joint between the transmitter terminal E12 and the connecting component 13b, the wiring resistance of the connecting component 13b itself (resistances R6 and R7), and the resistance R8 of the solder joint between the collector terminal C22 and the connecting component 13b. Figure 18 In the model shown, it is assumed that the load line 9 is connected to the vicinity of the upper arm 7U. In the first path F1, there are resistors R2 and R3 from the connection position of the load line 9 to the lower arm 7L side.

[0203] As described above, in a structure where load line 9 and connecting component 13 are connected, there are two main paths for DC current. DC current refers to the current flowing in a steady state when the switching element is turned on, not during switching. Figure 18 The solid arrows CP1 and CP2 represent the main current paths when the switching elements Q1 (Q1a, Q1b) on the upper arm 7U side are driven. The dashed arrows CP3 and CP4 represent the main current paths when the switching elements Q2 (Q2a, Q2b) on the lower arm 7L side are driven.

[0204] The current path CP1 is collector terminal C1(P) → heat sink 41 → switching elements Q1a, Q1b → heat sink 51 → emitter terminal E11 → connection component 13a → load line 9(O). The current path CP2 is collector terminal C1(P) → heat sink 41 → switching elements Q1a, Q1b → heat sink 51 → emitter terminal E12 → connection component 13b → collector terminal C22 → heat sink 42 → collector terminal C21 → connection component 13a → load line 9(O). Thus, the resistance components of the main circuit wiring are different in current paths CP1 and CP2, which may lead to DC current imbalance.

[0205] Similarly, current path CP3 is load line 9(O) → connection component 13a → collector terminal C21 → heat sink 42 → switching elements Q2a, Q2b → heat sink 52 → emitter terminal E2(N). Current path CP4 is load line 9(O) → connection component 13a → emitter terminal E11 → heat sink 51 → emitter terminal E12 → connection component 13b → collector terminal C22 → heat sink 42 → switching elements Q2a, Q2b → heat sink 52 → emitter terminal E2(N). Thus, the resistance components of the main circuit wiring are different in current paths CP3 and CP4, which may lead to DC current imbalance.

[0206] Figure 19 Indicates in Figure 18 The model shown presents the simulation results of the current flowing through the output terminal when motor lock occurs. Figure 19 (a) represents the current flowing through each output terminal when the upper arm 7U side is driven. Figure 19 (b) represents the current flowing through each output terminal when the lower arm 7L side is driven. Figure 19 In the diagram, the current flowing through the emitter terminal E11 is represented by a solid line, the current flowing through the collector terminal C21 is represented by a dashed line, and the current flowing through the emitter terminal E12 and the collector terminal C22 is represented by a single-dot dashed line.

[0207] In the simulation, the load current is assumed to be 1000 A, and the duty cycle of the output waveform of the upper and lower arms 7 is assumed to be 55%. Furthermore, the values ​​of resistors R1 to R8 are assumed to be equal to r. Relative to the overall resistance of paths F1 and F2 (8r), the resistance of current path CP1 is r, the resistance of current path CP2 is 7r, the resistance of current path CP3 is 3r, and the resistance of current path CP4 is 5r.

[0208] Therefore, current path CP1 flows more easily than current path CP2. When switching element Q1 is driven, the emitter terminal E11 carries a larger current than the emitter terminal E12. Furthermore, current path CP3 flows more easily than current path CP4. When switching element Q2 is driven, the collector terminal C21 carries a larger current than the collector terminal C22. Thus, the current is concentrated at the output terminals constituting path F1, specifically at the emitter terminal E11 and the collector terminal C21.

[0209] When the switching element Q1 is driven, current flows from the upper and lower arms 7 to the load. For example... Figure 19 As shown in (a), during the ON period of the PWM cycle, current flows from the collector terminal C1 (P) to the load line 9 (O) via the switching element Q1. A current of 1000 × 7 / 8 = 875 [A] flows through the emitter terminal E11. During the OFF period, current flows from the emitter terminal E2 (N) to the load line 9 (O) via the diode D2. At this time, a current of 1000 × 3 / 8 = 375 [A] flows through the emitter terminal E11. The current flowing through the emitter terminal E11 is a rectangular wave of 875 [A] (55% duty cycle) and 375 [A] (45% duty cycle). Based on the RMS value, a current of 696 [A] flows through the emitter terminal E11.

[0210] When the switching element Q2 is driven, current flows from the load to the upper and lower arms 7. During the on-time of the PWM cycle, current flows from the load line 9 (O) through the switching element Q2 to the emitter terminal E2 (N). In the collector terminal C21, as... Figure 19 As shown in (b), a current of 1000 × 5 / 8 = 625 [A] flows. During the disconnection period, current flows from the load line 9 (O) through diode D1 to the collector terminal C1 (P). At this time, a current of 1000 × 1 / 8 = 125 [A] flows in the collector terminal C21. The current flowing in the collector terminal C21 is a rectangular wave of 625 [A] (duty cycle 45%) and 125 [A] (duty cycle 55%). Based on the RMS value, a current of 429 [A] flows in the collector terminal C21.

[0211] Thus, in Figure 18In the model shown, the DC current balance of the upper arm 7U is worse than that of the lower arm 7L. Consequently, a larger current flows through the emitter terminal E11, particularly in the collector terminal C21, where the current is concentrated due to the DC current imbalance. This results in a greater voltage pressure on the emitter terminal E11.

[0212] The semiconductor module 10 of this embodiment, like the previous embodiment, has solder joints 121 and 122 as the junctions between heat sinks 51 and 52 and main terminals 71 and 72. Solder joint 121 is formed between heat sink 51 and each of the emitter terminals E11 and E12. Solder joint 122 is formed between heat sink 52 and emitter terminal E2. In the current-concentrated emitter terminal E11 and collector terminal C21, solder joint 121 is formed on emitter terminal E11, but not on collector terminal C21. Collector terminal C21 is continuously disposed as a component with heat sink 42. For example, the larger the flowing current, the higher the electromigration effect. Emitter terminal E11 has lower tolerance to voltage stress compared to collector terminal C21.

[0213] Therefore, in this embodiment, a reference position is set in path F1 so that the wiring resistance from the connection position of load line 9 (hereinafter referred to as the reference position) through the emitter terminal E11 to the heat sink 51 is greater than the wiring resistance from the reference position through the collector terminal C21 to the heat sink 42. Figure 16 and Figure 17 As shown, in the semiconductor module 10 of this embodiment, the load line 9 is connected to the soldered portion of the collector terminal C21 in the generally U-shaped connecting member 13a. The reference position is also called the output branch point.

[0214] Figure 20 yes Figure 16 and Figure 17 The equivalent circuit diagram of the semiconductor module 10 is shown. In the connecting component 13a, the reference position BP for connecting the load line 9 is located near the lower arm 7L. Figure 20 For convenience, the wiring resistance between the reference position BP and the resistor R4 of the welded part of the collector terminal C21 is set to zero, and the reference position BP is set between the wiring resistors R2, R3 and resistor R4 of the connecting part 13a.

[0215] In path F1, the resistance value (first resistance value) of the wiring section from the reference position BP through the emitter terminal E11 and solder joint 121 to the heat sink 51 is the sum of resistors R1, R2, and R3. The resistance value (second resistance value) of the wiring section from the reference position BP through the collector terminal C21 to the heat sink 42 is the value of resistor R4. For example, if the values ​​of each resistor R1 to R8 are r, the first resistance value is 3r, and the second resistance value is r.

[0216] In this way, in the semiconductor device 11 on the emitter terminal E11 side, which has a lower tolerance to voltage pressure, the imbalance of DC current between emitter terminals E11 and E12 can be suppressed. The degree of DC current imbalance between emitter terminals E11 and E12 can be reduced. Therefore, current concentration towards the solder joint 121 formed on the emitter terminal E11 can be suppressed. By suppressing the DC current imbalance, the current flowing to the solder joint 121 can be reduced. Therefore, reliability can be improved in the semiconductor module 10 which has two types of semiconductor devices 11 and 12.

[0217] With the configuration of load line 9 described above, the imbalance of DC current on the collector terminal C2 side increases, and the current flowing through collector terminal C21 increases. However, collector terminal C21 has higher tolerance to voltage stress compared to emitter terminal E11. Therefore, the overall reliability of semiconductor module 10 can be improved.

[0218] Furthermore, this example illustrates that the emitter terminal E11 has a lower withstand capability against applied voltage than the collector terminal C21 due to the presence or absence of solder joints, but it is not limited to this. For example, the collector terminal C21 may be soldered to the heat sink 42, such that the area of ​​the solder joint portion of the collector terminal C21 is larger than the area of ​​the solder joint portion 121 of the emitter terminal E11. The withstand capability against applied voltage is determined by the presence or absence of solder joints, the area of ​​the solder joint portion, etc.

[0219] Alternatively, the structure can be made opposite to this embodiment, where the collector terminal C21 on the lower arm 7L side has lower tolerance to voltage stress compared to the emitter terminal E11 on the upper arm 7U side. In this case, the load line 9 can be provided in path F1 such that the wiring resistance from the reference position BP to the heat sink 42 is greater than the wiring resistance from the reference position BP to the heat sink 51. For example, the reference position BP can be located near the upper arm 7U in the connecting member 13a.

[0220] In this embodiment, the connecting parts 13a and 13b have the same structure. Therefore, it is easy to adjust the DC current imbalance based on the reference position BP of the load line 9. By using connecting parts 13a and 13b with the same structure and performing welding in the same manner, the overall resistance value of path F1 and the overall resistance value of path F2 can be made approximately equal.

[0221] When the resistance values ​​of paths F1 and F2 are equal, it is clear that the resistance ratio x at the intersection of the current flowing through the emitter terminal E11 and the current flowing through the collector terminal C21 is approximately the same as the duty cycle of the output waveform set when the motor is locked. Figure 21 This indicates the relationship between the resistance ratio x and the effective current of the emitter terminal E11 and collector terminal C21 in various duty cycles set when the motor is locked. Hereinafter, the resistance ratio at the crossover point will be represented as x0 for distinction.

[0222] The resistance ratio x is the ratio of the first resistance value to the total resistance value of path F1. Figure 20 In this context, if the total value of resistors R1 to R4 is set to 1, then the total value of resistors R1, R2, and R3 is x, and resistor R4 is (1 - x). The duty cycle for motor locking is typically set to around 50% (e.g., within the range of 40% to 60%). Regarding the duty cycle... Figure 21 (a) is 50%. Figure 21 (b) is 55%. Figure 21 (c) is 60%. The above simulation results are in Figure 21 (b) shows the results when the resistance ratio x is 0.25. When the resistance ratio x = 0.25, the ratio of the effective current of the emitter terminal E11 to the collector terminal C21 is 0.62:0.38.

[0223] like Figure 21 As shown, regardless of the duty cycle, the resistance ratio x0 at the crossover point is consistent with the duty cycle Rd. Figure 21 In (a), the resistance ratio x0 is 0.5. Figure 21 In (b), the resistance ratio x0 is 0.55. Figure 21 In (c), the resistance ratio x0 is 0.6.

[0224] Therefore, if the duty ratio set when the motor is locked is Rd, when the tolerance of the emitter terminal E11 to the energization pressure is lower, the resistance ratio x, i.e., the reference position BP, can be set to satisfy x ≧ Rd. By satisfying this relationship, the effective value current of the emitter terminal E11 can be made to be below the effective value current of the collector terminal C21. Thereby, the reliability of the semiconductor module 10 can be improved. If x > Rd is satisfied, the effective value current of the emitter terminal E11 can be made to be less than the effective value current of the collector terminal C21. Thereby, the reliability of the semiconductor module 10 can be further improved.

[0225] When the tolerance of the collector terminal C21 to the energization pressure is lower, the resistance ratio x, i.e., the reference position BP, can be set to satisfy x ≦ Rd. By satisfying this relationship, the effective value current of the collector terminal C21 can be made to be below the effective value current of the emitter terminal E11. Thereby, the reliability of the semiconductor module 10 can be improved. If x < Rd is satisfied, the effective value current of the collector terminal C21 can be made to be less than the effective value current of the emitter terminal E11. Thereby, the reliability of the semiconductor module 10 can be further improved.

[0226] An example where the connecting members 13a and 13b have the same structure is shown, but it is not limited thereto. An example where the resistance values of the paths F1 and F2 are substantially equal is shown, but it is not limited thereto. It can also be applied to a structure where the connecting members 13a and 13b have different structures. It can also be applied to a structure where the resistance values of the paths F1 and F2 are different. For example, at least one of the width, thickness, and length can be made different in at least a part of the connecting members 13a and 13b. For example, the resistance values of the paths F1 and F2 can be made different by using connecting members 13a and 13b having the same structure and making the welding resistances (resistances R1, R4, R5, R8) different. The connection of the connecting members 13a and 13b to the output terminals is not limited to welding. Fixing means other than welding can also be used, such as fixing by a joining member, fastening, etc.

[0227] For example, in Figure 22 shows the relationship between the ratio of the effective value current and the resistance ratio x when the values of the resistances R1 to R4 on the path F1 side in Figure 20 are respectively set to r and the values of the resistances R5 to R8 on the path F2 side are respectively set to 2r. If the ratio of the overall resistance value of the path F2 to the overall resistance value of the path F1 is k, then k = 2. Regarding the duty ratio, Figure 22 of (a) is 50%, Figure 22 of (b) is 55%, Figure 22 of (c) is 60%.

[0228] As Figure 22As shown in (a), with a duty cycle of 50%, the resistance ratio x0 at the crossover point is consistent with the duty cycle Rd. Figure 22 (b) and Figure 22 As shown in (c), a deviation occurs between the resistance ratio x0 and the duty cycle Rd when the duty cycle is 55% and 60%. The resistance ratio x0 becomes a larger value than the duty cycle Rd. When the duty cycle is 55%, the resistance ratio x0 is 0.6. When the duty cycle is 60%, the resistance ratio x0 is 0.7.

[0229] When the resistance values ​​of paths F1 and F2 are inconsistent, the resistance ratio x0 at the intersection is determined by the following equation 1.

[0230] (Equation 1) x0 = {(Rd - 0.5) × k + 0.5}

[0231] Therefore, when the emitter E11 has a lower tolerance to voltage stress, the resistance ratio x, i.e. the reference position BP, can be set to satisfy the following equation 2.

[0232] (Equation 2)x≧{(Rd-0.5)×k+0.5}

[0233] By satisfying this relationship, the effective value current of the emitter terminal E11 can be made to be less than the effective value current of the collector terminal C21. If Equation 3 below is satisfied, the effective value current of the emitter terminal E11 can be made less than the effective value current of the collector terminal C21.

[0234] (Equation 3) x > {(Rd-0.5)×k+0.5}

[0235] When the collector terminal C21 has a lower tolerance to the applied voltage, the resistance ratio x, i.e. the reference position BP, can be set to satisfy the following equation 4.

[0236] (Equation 4)x≦{(Rd-0.5)×k+0.5}

[0237] By satisfying this relationship, the effective current of collector terminal C21 can be made to be less than the effective current of emitter terminal E11. If Equation 5 below is satisfied, the effective current of collector terminal C21 can be made less than the effective current of emitter terminal E11.

[0238] (Equation 5)x < {(Rd-0.5)×k+0.5}

[0239] The relationships in equations 1 through 5 above also hold true when k = 2. For example, in Figure 23 The value in the text represents the case where k = 1.5. Regarding the duty cycle, Figure 23 No (a) Yes, 50%. Figure 23 (b) is 55%. Figure 23 (c) is 60%. With a duty cycle of 50%, the resistance ratio x0 at the crossover point is consistent with the duty cycle Rd. With a duty cycle of 55%, the resistance ratio x0 is 0.575. With a duty cycle of 60%, the resistance ratio x0 is 0.65. Regardless of the duty cycle, the resistance ratio x0 at the crossover point is consistent with the value calculated using Equation 1 above.

[0240] exist Figure 24 The value in the middle represents the case where k = 0.5. Regarding the duty cycle, Figure 24 (a) is 50%. Figure 24 (b) is 55%. Figure 24 (c) is 60%. With a duty cycle of 50%, the resistance ratio x0 at the crossover point is consistent with the duty cycle Rd. With a duty cycle of 55%, the resistance ratio x0 is 0.525. With a duty cycle of 60%, the resistance ratio x0 is 0.55. Regardless of the duty cycle, the resistance ratio x0 at the crossover point is consistent with the value calculated using Equation 1 above. Furthermore, the relationships in Equations 1 to 5 above also hold, for example, when k = 1.

[0241] The location of load line 9 is not limited to the example above. For example, if the emitter terminal E11 has low tolerance to voltage stress, it can also be positioned as follows: Figure 25 As shown in the modified example, the connecting member 13a is further extended than the connection portion to the collector terminal C21, and the load line 9 is connected to this extended portion. Alternatively, as... Figure 26 As shown in the modified example, in the roughly U-shaped connecting member 13a, the load line 9 is connected to the connecting portion that connects to the connecting portion of the emitter terminal E11 and the collector terminal C21. In this case, it is sufficient to set a difference in welding resistance and / or to make the width of the connecting portion of the connecting member 13a different. Alternatively, as shown... Figure 27 As shown in the modified example, the connecting member 13a is reversed in the Y direction.

[0242] This illustrates an example where the number of connections between the emitter terminal E11 and the collector terminal C21 and the connecting component 13a is the same in path F1, but it is not limited to this. The wiring resistance at the reference position BP can also be adjusted by varying the number of connections between the emitter terminal E11 and the collector terminal C21. For example, in... Figure 28 In the modified example shown, on the back surface in the thickness direction, the connecting member 13a is connected to the collector terminal C21. The connecting members 13a and 13b have different structures. The collector terminal C21 has two connecting portions, and the emitter terminal E11 has one connecting portion. Because of the two connecting portions, the connecting area of ​​the collector terminal C21 is larger. Therefore, the value of resistor R4 is smaller than the value of resistor R1.

[0243] It can also be like Figure 29 As shown in the modified example, connecting parts 13a and 13b are electrically connected by a thin wire 15, such as a wire. The resistance of the thin wire 15 is sufficiently large compared to the resistance of other elements constituting the current paths CP1, CP2, CP3, and CP4. The thin wire 15 does not significantly affect the balance of the DC current.

[0244] This illustrates an example of stacking semiconductor devices 11 and 12 in the Z direction, but is not limited to this. For example, it is also possible to... Figure 30 The variant shown is connected in a planar configuration. Figure 30 The label B1 indicates the busbar on the positive side, and the label B2 indicates the busbar on the negative side. The collector terminal C1 is connected to the positive terminal of the smoothing capacitor Cs via busbar B1. The emitter terminal E2 is connected to the negative terminal of the smoothing capacitor Cs via busbar B2. Figure 30 In the illustration, some elements of semiconductor devices 11 and 12, such as the encapsulated resin bodies 21 and 22, are omitted.

[0245] The structure of semiconductor devices 11 and 12 is not limited to a two-sided heat dissipation structure. A single-sided heat dissipation structure can also be used. Furthermore, the switching elements are not limited to a vertical structure, but can also be used for a horizontal structure (e.g., LDMOS). In the case of a single-sided heat dissipation structure, for example, a connection structure in a planar configuration can be used.

[0246] This illustrates an example of semiconductor devices 11 and 12 having multiple semiconductor elements 31 and 32, but is not limited to this. In a structure having only one semiconductor element 31 and 32, if there are multiple paths, such as two paths F1 and F2, an imbalance of DC current may occur. Therefore, a structure in which semiconductor devices 11 and 12 have only one semiconductor element 31 and 32 can also be applied.

[0247] This illustrates an example where semiconductor devices 11 and 12 are equipped with encapsulating resin bodies 21 and 22, but are not limited to this. Structures without encapsulating resin bodies 21 and 22 may also be constructed.

[0248] (Third Implementation)

[0249] In this embodiment, the same reference numerals are assigned to parts that are functionally and / or structurally corresponding to or associated with parts in prior embodiments. For details regarding the corresponding parts and / or associated parts, please refer to the description of the prior embodiments.

[0250] Figure 31 Semiconductor devices 11 and 12 are shown in this embodiment. Figure 31For ease of illustration, the two semiconductor devices 11 and 12 are arranged horizontally. Figure 31 In, with Figure 12 Similarly, the elements within the sealed resin bodies 21 and 22 are indicated by dashed lines.

[0251] The basic structure of semiconductor devices 11 and 12 is the same as in the prior embodiment. Semiconductor devices 11 and 12 have a two-sided heat dissipation structure. In a plan view viewed from the Z direction, the areas of heat sinks 51 and 52 are smaller than the areas of their corresponding heat sinks 41 and 42. Two semiconductor elements 31 are arranged along the longer direction of heat sink 51 (main body 51a). Similarly, two semiconductor elements 32 are arranged along the longer direction of heat sink 52 (main body 52a).

[0252] Semiconductor device 11 has a solder joint 121. The solder joint 121 is formed between each emitter terminal E1 and the heat sink 51. Semiconductor device 12 has a solder joint 122. The solder joint 122 is formed between emitter terminal E2 and the heat sink 52.

[0253] Semiconductor devices 11 and 12 also include solder joints 131 and 132. Solder joint 131 is formed between each terminal 61 and the heat sink 51. Solder joint 132 is formed between each terminal 62 and the heat sink 52. Figure 31 In order to distinguish them from others, the solder joints 121, 122, 131, and 132 are shaded.

[0254] When the areas of heat sinks 51 and 52 are smaller than the areas of heat sinks 41 and 42, the solder joints on the heat sink 51 and 52 sides are formed by a second reflow as described above. For example, in the case of forming the semiconductor device 12, as... Figure 32 As shown, the connector including the heat sink 42 is positioned on the pedestal 200 with solder 92c and 92d facing upwards. Next, the heat sink 52 is positioned. A second reflow is performed in this configuration. At this time, the position of the heat sink 42 is determined by the component's own weight, the fixture, etc., with the pedestal 200 as the Z-direction position reference.

[0255] Regarding heat sink 52, although it is positioned on base 200 using fixture 201, it is free in the Z direction during solder melting. Depending on the relationship between the center of gravity Cg2 of heat sink 52 and the surface tension of the solder connected to heat sink 52, tilting of heat sink 52 is possible. For example, the possibility that solders 92c and 92d do not solidify at the same time can also be considered. The volume change of the solder from liquid to solid phase may affect tilting. The same applies to semiconductor device 11 (heat sink 51). Figure 32In this diagram, focusing on heat sinks 42 and 52 and solders 92c and 92d, other elements are shown together with heat sink 42 for convenience.

[0256] In the semiconductor device 11 of this embodiment, the main solder joints of the heat sink 51 are arranged linearly symmetrically about an axis AX11 passing through the center of gravity Cg1 of the heat sink 51. The axis AX11 is orthogonal to the longer direction of the heat sink 51, i.e., the X direction, and the Z direction, which is the thickness direction of the semiconductor element 31. Similarly, in the semiconductor device 12, the main solder joints are arranged linearly symmetrically about an axis AX12 passing through the center of gravity Cg2 of the heat sink 52. The axis AX12 is orthogonal to the longer direction of the heat sink 52, i.e., the X direction, and the Z direction, which is the thickness direction of the semiconductor element 32.

[0257] With this configuration, in the longer direction of heat sinks 51 and 52, at approximately the same distance relative to the centers of gravity Cg1 and Cg2, approximately the same surface tension is applied. Thus, on one side and the other side in the longer direction, as... Figure 32 As shown, the torque is roughly balanced. Therefore, when the large heat sinks 41 and 42 are positioned in the Z direction and the solder joints of the heat sinks 51 and 52 are formed in this state, it is possible to suppress the relative tilting of the heat sinks 41 and 42 and the heat sinks 51 and 52.

[0258] In particular, it can suppress tilting in the longer direction. Even with the same tilt, the displacement in the longer direction is greater than that in the shorter direction. According to this embodiment, the amount of displacement can be suppressed. By suppressing the tilt, for example, heat dissipation can be ensured. In the parallel-connected semiconductor elements 31 and 32, deviations in wiring inductance can be suppressed.

[0259] In this embodiment, as solder joints formed on the heat sink 51, the semiconductor device 11 has a solder joint 131 that electrically connects the heat sink 51 to the semiconductor element 31 and a solder joint 121 that electrically connects the heat sink 51 to the emitter terminal E1. The solder joint 131 is formed containing solder 91c, and the solder joint 121 is formed containing solder 91d. The semiconductor device 11 has two solder joints 131 and two solder joints 121.

[0260] The two solder joints 131 are arranged linearly symmetrically about axis AX11. This achieves a balance of surface tension of solder 91c along the longer direction of heat sink 51. The two solder joints 121 are also arranged linearly symmetrically about axis AX11. This achieves a balance of surface tension of solder 91d along the longer direction of heat sink 51. This helps to suppress tilting in the longer direction within heat sink 51.

[0261] Similarly, as solder joints formed on the heat sink 52, the semiconductor device 12 has a solder joint 132 that electrically connects the heat sink 52 to the semiconductor element 32 and a solder joint 122 that electrically connects the heat sink 52 to the emitter terminal E2. The solder joint 132 is formed containing solder 92c, and the solder joint 122 is formed containing solder 92d. The semiconductor device 12 has two solder joints 132 and one solder joint 122.

[0262] The two solder joints 132 are arranged linearly symmetrically about axis AX12. This allows for a balance of surface tension in the solder 92c along the longer direction of the heat sink 52. The solder joints 122 are also arranged linearly symmetrically about axis AX12. This allows for a balance of surface tension in the solder 92d along the longer direction of the heat sink 52. This helps to suppress tilting in the longer direction within the heat sink 52.

[0263] In this embodiment, at least two upper solder joints are provided in descending order of their connection area with the heat sink 51, overlapping the shaft AX21 in the shorter direction of the heat sink 51. The shaft AX21 is orthogonal to the shorter directions of the heat sink 51, namely the Y and Z directions, and passes through the center of gravity Cg1. Since surface tension acts closer to the shaft AX21, the torque that causes tilting in the shorter direction can be reduced. Thus, tilting in the shorter direction within the heat sink 51 can be suppressed. In this embodiment, all solder joints 131 are provided on the shaft AX21.

[0264] Similarly, at least two upper solder joints are provided in descending order of their connection area with the heat sink 52, overlapping the shaft AX22 in the shorter direction of the heat sink 52. The shaft AX22 is orthogonal to the shorter directions of the heat sink 52, namely the Y and Z directions, and passes through the center of gravity Cg2. Since surface tension acts closer to the shaft AX22, the torque that causes tilting in the shorter direction can be reduced. Thus, tilting in the shorter direction within the heat sink 52 can be suppressed. In this embodiment, all solder joints 132 are provided on the shaft AX22.

[0265] In this embodiment, the solder joints 121 and 122 are positioned separately from the axes AX21 and AX22 in the shorter direction, thus avoiding overlap with the axes AX21 and AX22. This simplifies the connection structure between the heat sinks 51 and 52 and the semiconductor elements 31 and 32, as well as the emitter terminals E1 and E2. In particular, in the semiconductor device 11, since the two solder joints 121 are arranged on the same side relative to the axis AX21, the structure can be simplified.

[0266] In this embodiment, as well as Figure 31As shown, all the main terminals 71 protrude from the side 21c of the sealing resin body 21. Furthermore, in a plan view viewed from the Z direction, the center 131c of the solder joint 131 is located further from the solder joint 121 than the axis AX21 in the shorter direction. This allows the surface tension of the solder 91c to act on the offsetting side, which counteracts the torque caused by the surface tension of the solder 91d. Therefore, the tilting of the heat sink 51 in the shorter direction can be effectively suppressed. The center 131c is approximately aligned with the center of the emitter electrode 31e.

[0267] Similarly, all the main terminals 72 protrude from the side 22c of the sealing resin body 22. Furthermore, in a plan view viewed from the Z direction, the center 132c of the solder joint 132 is located further from the solder joint 122 than the axis AX22 in the shorter direction. This allows the surface tension of the solder 92c to act on the offsetting side, which counteracts the torque caused by the surface tension of the solder 92d. Therefore, the tilting of the heat sink 52 in the shorter direction can be effectively suppressed. The center 132c is approximately aligned with the center of the emitter electrode 32e.

[0268] In this embodiment, heat sinks 41, 42, 51, and 52 correspond to heat dissipation components. Heat sinks 41 and 42 correspond to the first component, and heat sinks 51 and 52 correspond to the second component. Solder joints 121, 122, 131, and 132 correspond to multiple solder joints. Solder joints 131 and 132 correspond to the first joint, and solder joints 121 and 122 correspond to the second joint. Shafts AX11 and AX12 correspond to shafts, specifically the first shaft. Shafts AX21 and AX22 correspond to the second shaft.

[0269] Examples of heat sinks 41, 42, 51, and 52 are shown as heat dissipation components, but the examples are not limited to these. For example, at least one of heat sinks 41, 42, and 51, 52 can also be a DBC (Direct Bonded Copper) substrate.

[0270] The number and arrangement of semiconductor elements 31 in semiconductor device 11 are not limited to the examples described above. The number and arrangement of semiconductor elements 32 in semiconductor device 12 are not limited to the examples described above. It is also possible to have three or more semiconductor elements 31 and 32. By having four semiconductor elements 31, in... Figure 33 In the modified example shown, the semiconductor device 11 has four solder joints 131.

[0271] A structure can be constructed in which a portion of multiple semiconductor elements 31, 32 are arranged in the X direction, and the remaining semiconductor elements 31, 32 are offset in the Y direction relative to the arranged semiconductor elements 31, 32. In this case, it is sufficient that the multiple solder joints 131, 132 are symmetrically arranged with respect to the axes AX11, AX12. Figure 34 In the illustrated variation, the semiconductor device 11 has three solder joints 131. Two solder joints 131 are arranged in the X direction with line symmetry relative to axis AX11. The remaining solder joints 131 are offset in the Y direction relative to the other two and are arranged with line symmetry relative to axis AX11. Figure 33 , Figure 34 For convenience, signal terminal 81 and suspension conductor 101b have been omitted. Figure 33 , Figure 34 The text indicates that it refers to semiconductor device 11, but it can also be applied to semiconductor device 12.

[0272] This illustrates an example where semiconductor devices 11 and 12 are equipped with encapsulating resin bodies 21 and 22, but are not limited to this. Structures without encapsulating resin bodies 21 and 22 are also possible.

[0273] (Fourth implementation)

[0274] In this embodiment, the same reference numerals are assigned to parts that are functionally and / or structurally corresponding to or associated with parts in prior embodiments. For details regarding the corresponding parts and / or associated parts, please refer to the description of the prior embodiments.

[0275] The semiconductor device 11 shown in the prior embodiment has a solder joint 121 between a heat sink 51 and a main terminal 71. The semiconductor device 12 has a solder joint 122 between a heat sink 52 and a main terminal 72. Figure 35 The image schematically illustrates the periphery of the solder joint 122 of the semiconductor device 12 as an example. Figure 35 The flow of current is represented by a solid arrow.

[0276] like Figure 35 As shown, solder 92d exists between the connector portion 52b of the heat sink 52 and the opposing portion E2a of the emitter electrode E2, forming a solder joint 122. If the opposing portion E2a is less able to carry current than the connector portion 52b, then in the solder joint 122, the movement that needs to flow further away in the connector portion 52b, which has a lower resistance, is enhanced. As a result, in the solder 92d, the current density on the inner side is greater than that on the front side of the flow direction. Thus, in the solder 92d, the current tends to concentrate locally.

[0277] Both the heat sink 52 and the emitter electrode E2 are formed using metallic materials such as copper. The heat sink 52 and the emitter electrode E2 have at least the same main metal composition. For example, if the opposing portion E2a is thinner than the connector portion 52b, it is more difficult for current to flow through the opposing portion E2a, so the current flow that needs to reach a farther distance in the connector portion 52b is enhanced in the solder joint 122.

[0278] The connector portion 52b and the opposing portion E2a are opposite each other. Solder 92d is located between the connector portion 52b and the opposing portion E2a. In a projection view viewed from the opposing direction, if the terminal mounting surface (opposing surface) of the connector portion 52b is larger than that of the opposing portion E2a, the flow that needs to travel further away in the connector portion 52b in the solder joint 122 is enhanced. The same problem also occurs in the semiconductor device 11. If the current is locally concentrated in the solder 91d and 92d, there is a concern about, for example, electromigration.

[0279] Next, based on Figure 36 and Figure 37 The semiconductor devices 11 and 12 of this embodiment will be described. Figure 36 For convenience, the sealing resin bodies 21 and 22 have been omitted. Figure 37 It is along Figure 36 A sectional view of line XXXVII-XXXVII. In Figure 37 The diagram also includes sealing resin bodies 21 and 22. Figure 37 Corresponding to the prior implementation Figure 5 .

[0280] The heat sink 51 of the semiconductor device 11 has a main body 51a and a connector 51b. Two emitter terminals E1 each have an opposing portion E1a and an extended portion E1b. The opposing portions E1a are arranged on the connector 51b with their surfaces facing each other. The opposing portions E1a are connected to the connector 51b via solder 91d. The extended portion E1b is connected to the opposing portion E1a. The extended portion E1b extends in the Y direction away from the connector 51b. Figure 37 As shown, if the thickness of the joint portion 51b is ta1 and the thickness of the opposing portion E1a is tb1, then at least in the solder joint portion 121, the thickness tb1 is set to be greater than or equal to the thickness ta1 (tb1 ≧ ta1).

[0281] In this embodiment, the thickness of the connector portion 51b is approximately uniform throughout the entire region. Furthermore, the thickness of the opposing portion E1a is also approximately uniform throughout the entire region. Moreover, the thickness tb1 of the opposing portion E1a is greater than the thickness ta1 of the connector portion 51b (tb1>ta1). The arrangement surface of the transmitting end piece E1 in the connector portion 51b is larger than that of the opposing portion E1a. The connector portion 51b has two protrusions 51c corresponding to the two opposing portions E1a. The protrusions 51c protrude in the Y direction away from the main body portion 51a.

[0282] At both ends of the connector portion 51b in the X direction, there are placement areas 51d for opposing portions E1a. In the connector portion 51b, the area opposite to the collector terminal C1 is a non-placement area 51e where opposing portions E1a are not placed. In the X direction, placement area 51d, non-placement area 51e, and placement area 51d are sequentially provided. The width Wa1 of the placement area 51d is the same as the width of the protrusion 51c. The width Wa1 is the length in the X direction.

[0283] Width Wa1 is the length of a direction orthogonal to the thickness direction of the connector portion 51b and the main current flow direction in the connector portion 51b. Width Wa1 is also the length of a direction orthogonal to the thickness direction and the extension direction in which the connector portion 51b extends from the main body portion 51a. A portion of the arrangement area 51d in the Y direction, specifically the portion away from the main body portion 51a, becomes the protrusion 51c. The arrangement areas 51d are generally rectangular in plan view. In the XY plane, solder 91d is connected to the central portion of the arrangement area 51d, while solder 91d is not connected to the surrounding portion surrounding the central portion.

[0284] A portion of the opposing portion E1a is connected to solder 91d. In the opposing portion E1a, the joining portion is located at one end along the longer direction of the emitting electrode E1. The width Wb1 of the opposing portion E1a is narrower than the width Wa1 of the configuration area 51d of the connector portion 51b. That is, the width Wa1 is wider than the width Wb1 (Wa1>Wb1). The width Wb1 is the length in the X direction including the joining portion. The width Wb1 is the length in a direction orthogonal to the plate thickness direction and the longer direction of the emitting electrode E1.

[0285] The heat sink 52 of the semiconductor device 12 has a main body 52a and a connector 52b. Each emitter electrode E2 has an opposing portion E2a and an extended portion E2b. The opposing portions E2a are arranged on the connector 52b with their surfaces facing each other. The opposing portions E2a are connected to the connector 52b via solder 92d. The extended portion E2b is connected to the opposing portion E2a. The extended portion E2b extends in the Y direction away from the connector 52b. Figure 37As shown, if the thickness of the joint portion 52b is ta2 and the thickness of the opposing portion E2a is tb2, then at least in the solder joint portion 122, the thickness tb2 is set to be greater than or equal to the thickness ta2 (tb2 ≧ ta2).

[0286] In this embodiment, the thickness of the connector portion 52b is approximately uniform throughout the entire region. Furthermore, the thickness of the opposing portion E2a is also approximately uniform throughout the entire region. Moreover, the thickness tb2 of the opposing portion E2a is greater than the thickness ta2 of the connector portion 52b (tb2>ta2). The arrangement surface of the transmitting end piece E2 in the connector portion 52b is larger than that of the opposing portion E2a. The connector portion 52b has a protrusion 52c corresponding to the opposing portion E2a. The protrusion 52c protrudes in the Y direction away from the main body portion 52a.

[0287] At the center of the connector portion 52b in the X direction, there is a configuration area 52d for the opposing portion E2a. In the connector portion 52b, the area opposite to the collector terminal C2 is a non-configuration area 52e where the opposing portion E2a is not configured. In the X direction, the non-configuration area 52e, configuration area 52d, and non-configuration area 52e are sequentially arranged. The width Wa2 of the configuration area 52d is the same as the width of the protrusion 52c. The width Wa2 is the length in the X direction.

[0288] Width Wa2 is the length of a direction orthogonal to the thickness direction of the connector portion 52b and the main current flow direction in the connector portion 52b. Width Wa2 is also the length of a direction orthogonal to the thickness direction and the extension direction in which the connector portion 52b extends relative to the main body portion 52a. A portion of the configuration area 52d in the Y direction, specifically the portion away from the main body portion 52a, becomes the protrusion 52c. The configuration area 52d is approximately rectangular in plan view. In the XY plane, solder 92d is connected to the central portion of the configuration area 52d, while solder 92d is not connected to the surrounding portion surrounding the central portion.

[0289] A portion of the opposing portion E2a is connected to solder 92d. In the opposing portion E2a, the joining portion is located at one end along the longer direction of the emitting electrode E2. The width Wb2 of the opposing portion E2a is narrower than the width Wa2 of the configuration area 52d of the connector portion 52b. That is, the width Wa2 is wider than the width Wb2 (Wa2 > Wb2). The width Wb2 is the length in the X direction including the joining portion. The width Wb2 is the length in a direction orthogonal to the plate thickness direction and the longer direction of the emitting electrode E2.

[0290] According to the semiconductor devices 11 and 12 of this embodiment, as described above, the thickness tb1 of the counter portion E1a is greater than or equal to the thickness ta1 of the connector portion 51b. Compared to a structure where the counter portion E1a is thinner than the connector portion 51b, current flows more easily through the counter portion E1a, thus suppressing local current concentration in the solder 91d. Therefore, the reliability of the semiconductor device 11 can be improved. Similarly, the thickness tb2 of the counter portion E2a is greater than or equal to the thickness ta2 of the connector portion 52b. Therefore, the reliability of the semiconductor device 12 can be improved.

[0291] In this embodiment, the surface area of ​​the emitter terminal E1 in the connector portion 51b is larger than that of the opposing portion E1a. The width Wa1 of the configuration region 51d is wider than the width Wb1 of the opposing portion E1a. Although the structure is such that current tends to concentrate locally in the solder 91d, the reliability of the semiconductor device 11 can be improved by satisfying the relationship tb1 ≥ ta1 described above. Similarly, the surface area of ​​the emitter terminal E2 in the connector portion 52b is larger than that of the opposing portion E2a. The width Wa2 of the configuration region 52d is wider than the width Wb2 of the opposing portion E2a. Although the structure is such that current tends to concentrate locally in the solder 92d, the reliability of the semiconductor device 12 can be improved by satisfying the relationship tb2 ≥ ta2 described above.

[0292] In this embodiment, semiconductor devices 11 and 12 include a plurality of corresponding semiconductor elements 31 and 32. The plurality of semiconductor elements 31 are connected to the same main body 51a via solders 91b and 91c. Although the structure is such that current tends to concentrate locally in solder 91d, the reliability of semiconductor device 11 can be improved by satisfying the aforementioned relationship tb1 ≥ ta1. The plurality of semiconductor elements 32 are connected to the same main body 52a via solders 92b and 92c. Although the structure is such that current tends to concentrate locally in solder 92d, the reliability of semiconductor device 12 can be improved by satisfying the aforementioned relationship tb2 ≥ ta2.

[0293] In semiconductor device 12, the number of emitter terminals E2 is less than the number of semiconductor elements 32. The number of emitter terminals E2 is less than the number of collector terminals C2. Semiconductor device 12 has two semiconductor elements 32 and one emitter terminal E2. Thus, although the current is easily concentrated locally at the emitter terminal E2, i.e., the solder 92d of the solder joint 122, the reliability of semiconductor device 11 can be improved by satisfying the above-mentioned relationship tb1≧ta1.

[0294] like Figure 37As shown, in this embodiment, in the semiconductor device 11, the thickness of the opposing portion E1a of the emitter terminal E1 is thicker than the thickness of the collector terminal C1. In the semiconductor device 12, the thickness of the opposing portion E2a of the emitter terminal E2 is thicker than the thickness of the collector terminal C2. Thus, in the main terminals 71 and 72, at least the opposing portions E1a and E2a of the emitter terminals E1 and E2 are made thicker than other portions. Therefore, it is possible to suppress local current concentration without changing the connection conditions between the collector terminals C1 and C2 and the bus bar or the like.

[0295] Next, a more preferable relationship of the thicknesses ta1, ta2, tb1, and tb2 will be described. Figure 38 Represents the model used in the simulation. Figure 39 Represents the simulation results. The periphery of the solder joint portion 122 of the semiconductor device 12 is simplified and set as a model. In Figure 38 , the main flow of the current is indicated by a solid arrow. In Figure 38 (a), the main flow direction of the current flowing through the joint portion 52b and the main flow direction of the current flowing through the emitter terminal E2 are the same. That is, the angle θ formed by the current is 0°. In Figure 38 (b), θ is 90°, and in Figure 38 (c), θ is 180°. In Figure 38 (a) to Figure 38 (c), the width of the solder joint portion 122 is substantially the same as the width Wb2 of the emitter terminal E2.

[0296] In the simulation, the width Wa2 is set to 13 mm, and the width Wb2 is set to 10 mm. In addition, the thickness ta2 of the joint portion 52b is set to 0.5 mm. And the thickness tb2 of the emitter terminal E2 is varied variously, and the maximum value of the current density of the solder joint portion 122 is obtained. Figure 39 (a) represents the result of θ = 0°, Figure 39 (b) represents the result of θ = 90°, Figure 39 (c) represents the result of θ = 180°.

[0297] As Figure 39 (a) shows, in the case of θ = 0°, when tb2 < ta2, the maximum value of the current density shows the maximum value. When tb2 ≥ ta2, compared with tb2 < ta2, the maximum value of the current density shows a smaller value. In addition, when the thickness tb2 is near ta2 × (Wa2 / Wb2), the maximum value of the current density shows the minimum value (the lowest point).

[0298] If the thickness equal to the thickness ta2 is set as tb2s, and the thickness of the lowest point is set as tb2m, the difference Δ between tb2s and tb2m is represented by the following equation 6.

[0299] (Equation 6) Δ = tb2m - tb2s = ta2 × {(Wa2 / Wb2) - 1}

[0300] Within a range that is twice Δ with the lowest point as the vertex, the thickness tb2 is thicker than the thickness ta2. This range is represented by the following Equation 7.

[0301] (Equation 7) ta2 < tb2 ≤ ta2 × {(2 × Wa2 - Wb2) / Wb2}

[0302] By satisfying the relationship of Equation 7, the maximum value of the current density can be made smaller. That is, it is possible to effectively suppress the local concentration of current in the solder joint 122. An example where θ = 0° is shown in the model, but it is not limited to the case where the main flow direction of the current is completely the same. As long as it is within the range of 0° ≤ θ < 45°, that is, as long as the current component in the same direction is relatively large, the effect can be achieved.

[0303] In the case of θ = 90°, although not shown in the figure, when tb2 < ta2, the maximum value of the current density shows the maximum value. As shown in Figure 39 (b) of, in the range of tb2 ≥ ta2, the thicker the thickness tb2, the smaller the maximum value of the current density. In the case of θ = 180°, although not shown in the figure, when tb2 < ta2, the maximum value of the current density shows the maximum value. As shown in Figure 39 (c) of, in the range of tb2 ≥ ta2, the thicker the thickness tb2, the smaller the maximum value of the current density.

[0304] Thus, when 45° ≤ θ ≤ 180°, in the range of tb2 ≥ ta2, the thicker the thickness tb2, the smaller the maximum value of the current density. In particular, if tb2 > ta2 is satisfied, it is possible to effectively suppress the local concentration of current. In addition, the same effect also applies to the semiconductor device 11.

[0305] In the semiconductor devices 11 and 12, the thickness of the opposing portions E1a and E2a of the emission terminals E1 and E2 can also be made substantially equal to the thickness of the extended portions E1b and E2b. The emission terminals E1 and E2 can also be made to have a structure with a uniform thickness throughout the entire length.

[0306] For example, it can also be as shown in Figure 40As shown in the modified example, the thickness of the opposing portion E1a is made thicker than the thickness of the extended portion E1b. The thickness of the extended portion E1b is made thinner than the thickness ta1 of the connector portion 51b. In the transmitter terminal E1, the opposing portion E1a is thicker, and the extended portion E1b is thinner. Therefore, with respect to the transmitter terminal E1, local current concentration can be suppressed without changing the connection conditions with the busbar, etc. Furthermore, compared to a structure with the same thickness throughout its entire length, cost can be reduced. The same applies to the transmitter terminal E2.

[0307] The semiconductor devices 11 and 12 in this embodiment only need to include at least a semiconductor element, a metal part having a main body and a connector electrically connected to the semiconductor element, and a terminal that is soldered to the connector.

[0308] This illustrates an example where semiconductor devices 11 and 12 have two corresponding semiconductor elements 31 and 32, but are not limited to this. They may also have only one semiconductor element 31 and 32, or they may have three or more semiconductor elements 31 and 32. For example, they may also have... Figure 33 As shown, it is structured to have four semiconductor elements 31 electrically connected to the same heat sinks 41 and 51.

[0309] The arrangement of the multiple semiconductor elements 31 and 32 is not limited to the examples described above. It is not limited to a structure in which all semiconductor elements 31 and 32 are arranged in the X direction. It can also be applied to a structure in which a portion of semiconductor element 31 is offset in the Y direction relative to other semiconductor elements 31. It can also be applied to a structure in which a portion of semiconductor element 32 is offset in the Y direction relative to other semiconductor elements 32. For example, it can also be made into... Figure 34 The structure shown.

[0310] This illustrates an example where semiconductor devices 11 and 12 are equipped with encapsulating resin bodies 21 and 22, but are not limited to this. Structures without encapsulating resin bodies 21 and 22 may also be constructed.

[0311] The structure of semiconductor devices 11 and 12 is not limited to a two-sided heat dissipation structure. A single-sided heat dissipation structure can also be used. Furthermore, the switching elements are not limited to a vertical structure; a horizontal structure (such as LDMOS) can also be used.

[0312] (Fifth Embodiment)

[0313] In this embodiment, the same reference numerals are assigned to parts that are functionally and / or structurally corresponding to or associated with parts in prior embodiments. For details regarding the corresponding parts and / or associated parts, please refer to the description of the prior embodiments.

[0314] In the prior embodiment, an example was shown where a groove for receiving residual solder was provided in the heat sink in such a way that it surrounded the joint between the heat sink and the main terminal. Other receiving structures may also be used instead of a groove.

[0315] The basic structure of the semiconductor devices 11 and 12 in this embodiment is the same as that described in the previous embodiments. The semiconductor devices 11 and 12 include wiring components. The wiring components are electrically connected to the semiconductor elements 31 and 32, providing wiring functionality. The wiring components have multiple conductor portions and a junction formed between two conductor portions. Each conductor portion includes at least one set of heat sinks arranged to sandwich the semiconductor elements 31 and 32, and multiple terminal portions connected to the heat sinks. Heat sinks 41, 42, 51, and 52 correspond to heat sinks, and main terminals 71 and 72 correspond to terminal portions. Furthermore, solder joints 121 and 122 correspond to junctions, and solder 91d and 92d correspond to bonding materials. Heat sinks 41, 42, 51, and 52 and main terminals 71 and 72 correspond to wiring components.

[0316] <Containment structure for residual solder>

[0317] based on Figures 41-43 The structure for containing the remaining solder is described. Figure 41 The heat sinks 51 and 52 on the emitter side of the semiconductor devices 11 and 12 in this embodiment are indicated. Figure 42 This is a magnified image of the heat sink 51. Figure 43 Is with Figure 42 A cross-sectional view of the semiconductor device 11 corresponding to the XLIII-XLIII line. Figure 43 For convenience, the sealing resin body 21 has been omitted. In this embodiment, the heat sinks 51 and 52 on the emitter side are provided with a structure for receiving residual solder. The heat sinks 51 and 52 correspond to the first conductor section, and the emitter terminals E1 and E2 correspond to the second conductor section.

[0318] The heat sink 51 has a low-wetting region 151a and a high-wetting region 151b on the side opposite to the emitter electrode E1, i.e., the mounting surface. Figure 41 , 42 In the plan view, the low-wetting region is shaded for clarity. The low-wetting region 151a is a region with lower solder wettability compared to the high-wetting region 151b. The low-wetting region 151a is adjacent to the high-wetting region 151b, and this adjacency defines at least a portion of the outer periphery of the high-wetting region 151b. The low-wetting region 151a is the portion where solder is difficult to wet and spread during bonding, while the high-wetting region 151b is the portion where solder is easy to wet and spread.

[0319] The high-wetting region 151b, in a plan view along the thickness direction (Z direction) of the semiconductor element 31, has an overlapping region 151c that overlaps with the junction formation region of the emitter electrode E1, and a non-overlapping region 151d that is connected to the overlapping region 151c but does not overlap with the junction formation region of the emitter electrode E1. The junction formation region of the emitter electrode E1 is the opposing portion E1a. Solder 91d (not shown) is at least located between the opposing portion E1a and the opposing region of the overlapping region 151c, and the junction 131 is mainly formed in the overlapping region 151c.

[0320] A highly wetted region 151b, including an overlapping region 151c and a non-overlapping region 151d, is formed at the joint portion 51b of the heat sink 51. The overlapping region 151c and the non-overlapping region 151d are surrounded by a low-wetting region 151a. The heat sink 52 forms joint portions 121 between itself and the two emission terminals E1. The heat sink 52 has two overlapping regions 151c. The overlapping regions 151c are generally rectangular in shape with the X direction as the longer direction in a plan view. The two overlapping regions 151c are arranged in the X direction.

[0321] The non-overlapping region 151d includes at least a receiving region 151e. The receiving region 151e is connected to the overlapping region 151c and is a highly wetted region 151b for receiving the remaining solder 91d at the joint 121. In this embodiment, the receiving region 151e is connected to both overlapping regions 151c. In the arrangement direction of the two overlapping regions 151c, one end of the receiving region 151e is connected to one of the overlapping regions 151c, and the other end of the receiving region 151e is connected to the other overlapping region 151c. Thus, a receiving region 151e is configured as a region common to both overlapping regions 151c.

[0322] The non-overlapping region 151d also includes a fillet forming region 151f. The fillet forming region 151f is also a highly wetting region 151b connected to the overlapping region 151c. The fillet forming region 151f is configured to form a fillet capable of producing solder 91d, and is narrower than the receiving region 151e. The fillet forming region 151f corresponds to a narrow-width region.

[0323] The receiving region 151e is connected to one side of the overlapping region 151c, and the weld forming region 151f is connected to the remaining three sides of the overlapping region 151c. In each of the overlapping regions 151c, the two sides in the Y direction and the outer side in the X direction are connected to the weld forming region 151f, and the inner side in the X direction is connected to the receiving region 151e. The inner side in the X direction is the opposite side of the two overlapping regions 151c, and the outer side is the non-opposing side. Thus, the non-overlapping region 151d surrounds the overlapping region 151c. The low-wetting region 151a is adjacent to the non-overlapping region 151d around its entire circumference, defining the outer periphery of the non-overlapping region 151d. The portion of the low-wetting region 151a at the receiving region 151e that forms the outer periphery of the high-wetting region 151b is adjacent over the entire region. The high-wetting region 151b, including the two overlapping regions 151c and the receiving region 151e, is arranged as a straight line along the X direction.

[0324] The width of the non-overlapping region 151d is its length relative to the direction in which the overlapping region 151c is connected, i.e., the arrangement direction in which the overlapping region 151c is arranged. The width of the receiving region 151e is its length in the X direction. In the weld formation region 151f, for example, the width of the portion arranged in the X direction relative to the overlapping region 151f is its length in the X direction. The weld formation region 151f has a width sufficient to form a weld. The receiving region 151e has a width sufficiently wide compared to the width of the weld formation region 151f. The receiving region 151e has a width sufficient to receive the remaining amount of solder 91d when the opposition interval between the overlapping region 151c and the opposing portion E1a is at its narrowest, so as to absorb the height deviation of the semiconductor device 11. The receiving region 151e has a width sufficient to receive the remaining amount of the two overlapping regions 151c relative to the joint 121.

[0325] The heat sink 51 differs from the aforementioned high wetting region 151b in that it has a high wetting region 151g. The high wetting region 151b has an overlapping region 151h, which overlaps with the terminal 61 in a plan view, and a non-overlapping region 151i, which is connected to the overlapping region 151h but does not overlap with the terminal 61. The heat sink 51 and each of the two terminals 61 (semiconductor elements 31) has two corresponding high wetting regions 151g. The non-overlapping region 151i, like the non-overlapping region 151d, includes a receiving region 151j and a solder forming region 151k.

[0326] The receiving area 151j is connected to the overlapping area 151h, and receives solder 91c overflowing from the area opposite to the terminal 61 in the overlapping area 151h. The receiving area 151j is connected to one side of the overlapping area 151h, which has a generally rectangular planar shape, and the weld forming area 151k is connected to the other three sides of the overlapping area 151h. In each of the overlapping areas 151h, the two sides in the X direction and one side in the Y direction are connected to the weld forming area 151k, and the remaining side in the Y direction is connected to the receiving area 151j.

[0327] Thus, the non-overlapping region 151i surrounds the overlapping region 151h. The low-wetting region 151a is adjacent to the non-overlapping region 151i on its entire circumference, defining the outer perimeter of the non-overlapping region 151i. The portion of the low-wetting region 151a at the receiving region 151j that forms the outer perimeter of the high-wetting region 151b is adjacent to the portion of the receiving region 151j on its entire circumference. The two high-wetting regions 151g are respectively generally rectangular in planar shape.

[0328] The weld formation region 151k is a region narrower than the receiving region 151j. The weld formation region 151k has a width sufficient to form a weld. The receiving region 151j has a width sufficiently wide compared to the width of the weld formation region 151k. The receiving region 151j has a width sufficient to receive the remaining amount of solder 91c when the opposing spacing between the overlapping region 151h and the terminal 61 is at its narrowest, in order to absorb the height deviation of the semiconductor device 11.

[0329] The low-wetting region 151a is provided on the mounting surface of the heat sink 51, covering the entire surface except for the high-wetting region 151b and the two high-wetting regions 151g. Since the heat sink 52 has the same structure as the heat sink 51, detailed description is omitted. The heat sink 52 also has a low-wetting region 152a and high-wetting regions 152b and 152g. The low-wetting region 152a covers the entire surface except for the high-wetting regions 152b and 152g. The high-wetting region 152b includes an overlapping region 152c and a non-overlapping region 152d. The high-wetting region 152g includes an overlapping region 152h and a non-overlapping region 152i. The non-overlapping regions 152d and 152i include receiving regions 152e and 152j (not shown) and weld formation regions 152f and 152k. Heat sink 52 has the same shape as heat sink 51 (a common part), and the layout of the low wetting regions 151a and 152a is also the same. Unlike heat sink 51, heat sink 52 has only one overlapping region 152c that overlaps with the opposing portion E2a of the emitter end E2. The overlapping region 152c is located near the center of the high wetting region 152b extending along the X direction.

[0330] <Low-wetting area>

[0331] based on Figure 44The low-wetting area is described. Figure 44 It is Figure 43 The region is magnified by XLIV. Figure 44 For simplicity, solder 91d is omitted in the illustration. The following explanation uses heat sink 51 as an example.

[0332] The heat sink 51 has a base material 160 comprising metal and a metal film 161 and an uneven oxide film 162 disposed on the surface of the base material 160. The base material 160 forms the main part of the heat sink 51. The base material 160 is formed of a Cu-based material. The metal film 161 is formed of a material with higher wettability to solder compared to the base material 160. The metal film 161 is formed over the entire area of ​​the mounting surface of the heat sink 51. The uneven oxide film 162 is formed locally on the mounting surface.

[0333] The uneven oxide film 162 is locally formed on the metal film 161 by irradiating it with a laser. The metal film 161 is provided on the entire area of ​​the surface of the base material 160, for example, except for the exposed surface. The metal film 161 has a base film mainly composed of Ni (nickel) and an upper film mainly composed of Au (gold). In this embodiment, an electroless Ni plating containing P (phosphorus) is used as the base film. The portion of the upper film (Au) exposed in the metal film 161 that comes into contact with the solder diffuses into the solder during reflow. The portion of the upper film (Au) in the metal film 161 that forms the uneven oxide film 162 is removed by laser irradiation during the formation of the uneven oxide film 162. The uneven oxide film 162 is a film of oxide mainly composed of Ni. For example, in the composition constituting the uneven oxide film 162, 80% is Ni₂O₃, 10% is NiO, and 10% is Ni.

[0334] An uneven oxide film 162 is formed in the low wetting region 151a on the mounting surface of the heat sink 51. The uneven oxide film 162 is not formed in the high wetting regions 151b and 151g. The uneven oxide film 162 provides the low wetting region 151a. The metal film 161 exposed from the uneven oxide film 162 provides the high wetting regions 151b and 151g.

[0335] Figure 44The reference numeral 161a shown is a recess formed on the surface of the metal film 161. The recess 161a is formed by irradiation with a pulsed laser. Each pulse forms one recess 161a. Through laser irradiation, the surface portion of the metal film 161 melts, vaporizes, and evaporates to form an uneven oxide film 162. The uneven oxide film 162 is an oxide film derived from the metal film 161. The uneven oxide film 162 is a film of oxide of the main component metal (Ni) of the metal film 161. The uneven oxide film 162 is formed by mimicking the unevenness of the surface of the metal film 161 having recesses 161a. On the surface of the uneven oxide film 162, unevenness is formed at a spacing finer than the width of the recesses 161a. That is, very fine unevenness (roughness) is formed.

[0336] The uneven oxide film 162 can be formed, for example, by the following manufacturing method. First, an electroless Ni plating layer containing phosphorus (P) is applied to a base material 160, followed by an Au plating layer to obtain a metal film 161. After the metal film 161 is formed, a pulsed laser is irradiated onto the mounting surface to melt and evaporate the surface of the metal film 161.

[0337] Adjust the pulsed laser pulses to achieve an energy density ratio of 0 J / cm². 2 Large and 100J / cm 2 The pulse width must be less than 1 μs. To meet this requirement, YAG lasers, YVO4 lasers, fiber lasers, etc., can be used. For example, in the case of a YAG laser, the energy density is 1 J / cm². 2 That's all. In the case of no electrolytic Ni plating, for example at 5 J / cm... 2 Metal film 161 can also be processed under the condition of left and right.

[0338] At this time, by moving the laser source and the heat sink 51 relative to each other, the laser is sequentially irradiated at multiple locations. The surface of the metal film 161 is melted and vaporized by the laser irradiation, forming recesses 161a on the surface of the metal film 161. The average thickness of the laser-irradiated portion of the metal film 161 is thinner than the average thickness of the portion not irradiated by the laser. Furthermore, the multiple recesses 161a formed corresponding to the laser spot are connected, for example, forming a scale-like structure.

[0339] Next, the molten metal film 161 is partially solidified. Specifically, the molten and vaporized metal film 161 is vapor-deposited onto the portion irradiated by the laser and its surrounding portion. In this way, by vapor-depositing the molten and vaporized metal film 161, an uneven oxide film 162 is formed on the surface of the metal film 161. As a result, a heat sink 51 can be prepared having a low wetting region 151a based on the uneven oxide film 162 and high wetting regions 151b and 151g based on the metal film 161 exposed from the uneven oxide film 162.

[0340] Heat sink 52 also has the same structure as heat sink 51. By using the same manufacturing method as heat sink 51, heat sink 52 can be prepared having a low wetting region 152a based on the uneven oxide film 162 and a high wetting region 152b, 152g based on the metal film 161 exposed from the uneven oxide film 162.

[0341] <Summary of Implementation Method 5>

[0342] As described in the previous embodiment, the semiconductor devices 11 and 12, with their dual-sided heat dissipation structure, are sandwiched between two sides in the Z direction by a cooler. Therefore, high surface parallelism and high dimensional accuracy between surfaces are required in the Z direction. Consequently, the solder 91d and 92d are configured in an amount capable of absorbing height deviations in the semiconductor devices 11 and 12. That is, a larger amount of solder 91d and 92d is configured. Furthermore, by applying a load in the Z direction during the second reflow, the height of the semiconductor devices 11 and 12 is made to a predetermined height. The solder 91d and 92d absorb height deviations caused by dimensional tolerances and assembly tolerances of the elements constituting the semiconductor devices 11 and 12.

[0343] For example, if the entire amount of solder 91d is required to make the height of the semiconductor device 11 reach a specified height, the entire amount of solder 91d remains in the opposing region between the opposing portion E1a and the overlapping region 151c due to capillary action, surface tension, etc. In order to reach the specified height, if there is excess solder 91d, by applying an external force exceeding the force that maintains the opposing regions due to capillary action, surface tension, etc., a portion of the solder 91d overflows from the opposing region.

[0344] In this embodiment, the receiving region 151e, which is the high wetting region 151b, is connected to the overlapping region 151c. Therefore, the remaining solder 91d is as follows: Figure 45 As indicated by the hollow arrow, it can easily infiltrate and diffuse from the overlapping region 151c to the containment region 151e. Figure 45 The hollow arrow in the diagram indicates the flow direction (overflow direction) of the remaining solder. Furthermore, the wetting diffusion of the remaining solder 91d is restricted by the low wetting region 151a. The low wetting region 151a, adjacent to the high wetting region 151b, promotes wetting diffusion into the receiving region 151e and / or inhibits wetting diffusion outside the receiving region 151e. Thus, even without a groove, such as... Figure 46 As shown, the remaining solder 91d can also be contained in the containment area 151e. Figure 46 Is with Figure 42 A cross-sectional view of the semiconductor device 11 corresponding to the XLVI-XLVI lines. Figure 46The text indicates the state of solder 91d overflowing. Similarly, even without a groove, the remaining solder 92d can be contained in the containing area 152e.

[0345] As a result, semiconductor devices 11 and 12 can be provided that can accommodate the remaining solder 91d and 92d in a simple structure. Since pressure processing to form the groove is no longer required, manufacturing costs can be reduced.

[0346] Figure 47 Is with Figure 42 A cross-sectional view of semiconductor device 11 corresponding to lines XLVII-XLVII. Figure 47 For convenience, the sealing resin body 21 has been omitted. Figure 47 The example shown is the present example (an example of this embodiment) and the reference example. Since the heat sink 51 and the collector terminal C1 have different potentials, a predetermined insulation distance DI needs to be ensured between them within the encapsulating resin body 21. If the bent portion of the collector terminal C1 is moved away from the heat sink 51 in the Y direction, the insulation distance DI can be ensured, but on the other hand, the volume of the encapsulating resin body 21, and consequently the volume of the semiconductor device 11, becomes larger. Therefore, it is preferable to configure the distance between the bent portion of the collector terminal C1 and the end of the heat sink 51 (connector portion 51b) as the insulation distance DI.

[0347] If such a configuration is adopted, in this example, the gap from the end of the heat sink 51 to the overlapping region 151c is CL1. In the case of the reference example, since there is a groove 151r for containing remaining solder, the gap to the overlapping region 151cr is CL2. The gap CL2 is longer than the gap CL1. The gap CL1 is, for example, about half the length of the gap CL2. Thus, according to this embodiment, the size of the semiconductor device 11 can be miniaturized in the extension direction of the emitter electrode E1 while ensuring the insulation distance DI. In addition, the semiconductor device 12 (heat sink 52) also has the same structure as the semiconductor device 11 (heat sink 51). In the reference example, elements that are the same as or related to the elements of this embodiment (this example) are indicated by adding 'r' to the end of the reference numerals of this embodiment. The same applies in the following reference examples.

[0348] In this embodiment, in the heat sink 51, the receiving region 151e is only connected to a portion of the overlapping region 151c. Furthermore, the low-wetting regions 151a are adjacent to the outer periphery of the high-wetting regions 151b on both sides in the Y direction, which is orthogonal to the arrangement direction (X direction) of the overlapping region 151c and the receiving region 151e, sandwiching the overlapping region 151c and the receiving region 151e. The low-wetting regions 151a on both sides function as guides for the flow of remaining solder 91d. Guided by the low-wetting regions 151a, the remaining solder 91d easily wets and diffuses from the overlapping region 151c into the receiving region 151e. Furthermore, the low-wetting regions 151a on both sides easily retain the remaining solder 91d within the receiving region 151e. The same applies to the heat sink 52.

[0349] In this embodiment, regarding heat sink 51, the low wetting region 151a in the housing region 151e is adjacent to the portion forming the periphery of the high wetting region 151b over the entire region. This suppresses the wetting and diffusion of solder 91d outside the housing region 151e. That is, the remaining solder 91d can be more reliably retained within the housing region 151e. The same applies to heat sink 52.

[0350] In this embodiment, regarding the heat sink 51, the outer peripheries of the low wetting region 151a and the high wetting region 151b are adjacent throughout the region. Thus, the remaining solder 91d reliably wets and diffuses into the receiving region 151e and is retained within the receiving region 151e.

[0351] Figure 48 The example shown is for reference only. In this example, grooves 151r and 152r are provided at the joint portions 51br and 52br of heat sinks 51r and 52r to collect excess solder. Heat sink 51r has grooves 151r near both ends of the joint portion 51br in the X direction. Heat sink 52r has a groove 152r near the center of the joint portion 52br in the X direction. Therefore, heat sinks 51r and 52r cannot be common.

[0352] In contrast, in this embodiment, heat sinks 51 and 52 are made into the same shape, and the wetting patterns of the low wetting regions 151a and 152a and the high wetting regions 151b and 152b are also the same. That is, the irradiation pattern of the laser forming the uneven oxide film 162 is also the same. Figure 45 As shown, in semiconductor device 11, in the high wetting region 151b, the areas near both ends form overlapping regions 151c, and the area between the two overlapping regions 151c forms a receiving region 151e. In semiconductor device 12, in the high wetting region 152b, the area near the center forms overlapping region 152c, and the areas on both sides form receiving regions 152e. By making heat sinks 51 and 52 common components, manufacturing costs can be reduced.

[0353] In this embodiment, a rough oxide film 162 is formed by locally irradiating the metal film 161, which has high solder wettability, with laser light, thus creating low-wetting regions 151a and 152a. The oxide film (rough oxide film 162) has lower solder wettability compared to the metal film 161. Furthermore, because it has fine irregularities on its surface, the contact area with the solder is smaller, and a portion of the solder becomes spherical due to surface tension. That is, the contact angle becomes larger. Therefore, the solder wettability is low. Thus, the rough oxide film 162 is preferred for the low-wetting regions 151a and 152a. Since a laser is used, the patterning of the low-wetting regions 151a and 152a and the high-wetting regions 151b and 152b is easy.

[0354] Furthermore, very fine irregularities are formed on the surface of the uneven oxide film 162, causing the sealing resin bodies 21 and 22 to wrap around each other and create an anchoring effect. In addition, the contact area with the sealing resin bodies 21 and 22 is increased. As a result, the adhesion between the heat sinks 51 and 52, where the uneven oxide film 162 is provided, and the sealing resin bodies 21 and 22 becomes higher.

[0355] Furthermore, in heat sinks 51 and 52, grooves for accommodating remaining solder 91c and 92c can be provided in the portions forming solder joints 131 and 132. If the semiconductor elements 31 and 32 are arranged identically in semiconductor devices 11 and 12, the shape and arrangement of the grooves can be identical. In this embodiment, the same remaining solder accommodating structure as that used in solder joints 121 and 122 is applied to the portions forming solder joints 131 and 132. Therefore, even without providing grooves, the remaining solder 91c and 92c can be accommodated in accommodating areas 151j and 152j. In heat sinks 51 and 52, the pressure processing for forming grooves can be completely eliminated.

[0356] <Variation Example>

[0357] The non-overlapping region 151d must at least include the containment region 151e. For example... Figure 49 As shown, in heat sink 51, a structure can also be made that excludes weld formation region 151f from the non-overlapping region 151d. The high-wetting region 151b only has the overlapping region 151c and the receiving region 151e. Such a structure can achieve the same effect as the embodiment described above. Furthermore, the high-wetting region 151g on the terminal 61 side also forms a structure that excludes weld formation region 151k. The same applies to heat sink 52.

[0358] The low-wetting region 151a and at least a portion thereof need to be adjacent to the high-wetting region 151b. For example... Figure 50As shown, the low-wetting region 151a can also be provided only on both sides of the Y direction, which is orthogonal to the arrangement direction (X direction) of the overlapping region 151c and the receiving region 151e. The low-wetting region 151a extends across the overlapping region 151c and the receiving region 151e on both sides of the Y direction, sandwiching the overlapping region 151c and the receiving region 151e. Figure 50 In, with Figure 49 Similarly, the low-wetting region 151a is continuously adjacent to the overlapping region 151c and the containing region 151e. The same applies to the heat sink 52.

[0359] This illustrates an example where multiple overlapping regions 151c make the containment region 151e common, but it is not limited to this. For example... Figure 51 and Figure 52 As shown, the containment area 151e can also be divided into two overlapping areas 151c. The low wetting area 151a divides the high wetting area 151b into two. Figure 52 Is with Figure 51 A cross-sectional view of the semiconductor device 11 corresponding to the LII-LII line, and Figure 46 Similarly, the state of solder overflow 91d is shown. According to this modified example, the patterns of the low-wetting region and the high-wetting region are different in the heat sinks 51 and 52. However, in aspects other than the common pattern, it can achieve the same effect as the above structure. In the case of the uneven oxide film 162, the laser irradiation pattern can be switched, so heat sinks 51 and 52 of the same shape can be used.

[0360] The containment region 151e may be connected to at least a portion of the overlapping region 151c. This illustrates an example where the containment region 151e is connected to only one of the four sides of the overlapping region 151c, but it is not limited to this. Alternatively, as shown... Figure 53 As shown, the receiving region 151e is configured to connect to two sides of the overlapping region 151c, which has a planar shape that is approximately rectangular. This allows the remaining solder 91d to be dispersed inwards in the X direction and to one side in the Y direction. This increases the volume of the remaining solder 91d. Alternatively, the receiving region 151e can be connected to three sides of the overlapping region 151c. Furthermore, the receiving region 151e can be connected to all four sides of the overlapping region 151c. For example, the receiving region 151e can be configured as a ring to surround the overlapping region 151c. In this case, the receiving region 151e forms the entire periphery of the high-wetting region 151b. It is also possible to separate the receiving regions 151e, which are connected to different sides relative to the common overlapping region 151c, from each other. The same applies to the heat sink 52.

[0361] like Figure 54As shown, a rough oxide film 162 can also be provided on the side of the opposite portion E1a of the emitter electrode E1. The rough oxide film 162 forms a low-wetting region. This suppresses the wetting and diffusion of solder 91d to the side of the emitter electrode E1. Furthermore, a high-wetting region 151b can be defined by the low-wetting region 151a provided on the mounting surface and side of the heat sink 51. By providing a low-wetting region 151a on the side, the mounting surface can be correspondingly enlarged to flexibly utilize the high-wetting region 151b. This also allows for miniaturization of the heat sink 51. Figure 54 The example shown illustrates an instance where an uneven oxide film 162 is provided on the side of the emitter E1 and the side of the heat sink 51, respectively, but it is also possible to provide only one side. The same applies to the heat sink 52.

[0362] The number of semiconductor elements sandwiched by a set of heat sinks is not particularly limited. For example, the above-described structure for containing remaining solder can also be applied to a structure in which only one semiconductor element 31 is disposed between heat sinks 41 and 51, and only one semiconductor element 32 is disposed between heat sinks 42 and 52. It can also be applied to a structure in which three or more semiconductor elements 31 and 32 are disposed.

[0363] The aforementioned structure for containing residual solder is not limited to the semiconductor device 11 constituting the upper arm 7U or the semiconductor device 12 constituting the lower arm 7L. That is, it is not limited to applications involving semiconductor devices constituting one arm. For example, as... Figure 55 , Figure 56 and Figure 57 As shown, it can also be applied to a semiconductor device 10A having semiconductor elements 31, 32 constituting the upper and lower arms 7. One semiconductor device 10A constitutes one phase's upper and lower arms 7. Figure 56 In, relative to Figure 55 The semiconductor device 10A shown omits the encapsulating resin body 20. Figure 57 It is along Figure 55 A cross-sectional view of line LVII-LVII.

[0364] Semiconductor device 10A includes a semiconductor element 31 on the upper arm 7U side and a semiconductor element 32 on the lower arm 7L side. A heat sink 41 is soldered to the collector electrode 31c of semiconductor element 31. A heat sink 51 is soldered to the emitter electrode 31e of semiconductor element 31 via a terminal 61. Similarly, a heat sink 42 is soldered to the collector electrode 32c of semiconductor element 32. A heat sink 52 is soldered to the emitter electrode 32e of semiconductor element 32 via a terminal 62. Heat sink 42 has a body portion connected to semiconductor element 32 and a connector portion 42e connected to the body portion. Heat sink 51 has a body portion connected to semiconductor element 31 and a connector portion 51f connected to the body portion. The connector portions 42e and 51f are arranged opposite each other in the Z direction and connected via solder 93. Heat sink 52 has a connector portion 52b.

[0365] The encapsulating resin body 20 has a surface 20a and a back surface 20b opposite to the surface 20a in the Z direction. The heat dissipation surfaces of heat sinks 41 and 42, opposite to the mounting surfaces, are exposed from the encapsulating resin body 20 in a state substantially coplanar with the surface 20a. The heat dissipation surfaces of heat sinks 51 and 52, opposite to the mounting surfaces, are exposed from the encapsulating resin body 20 in a state substantially coplanar with the back surface 20b. In the semiconductor device 10A, the main terminal 70 has a collector terminal C1, an emitter terminal E2, and an output terminal OP1. The collector terminal C1 is connected to the heat sink 41, and the output terminal OP1 is connected to the heat sink 42. The emitter terminal E2 is solder-bonded to the connector portion 52b of the heat sink 52.

[0366] Furthermore, in the heat sinks 51 and 52 on the emitter side, low-wetting regions 151a and 152a are partially provided on the mounting surface. The low-wetting region 151a is also provided in the connector portion 51f. The connector portion 51f has a low-wetting region 151a and a high-wetting region 151b on its mounting surface side. The high-wetting region 151b has an overlap region 151c that overlaps with the connector portion 42e, and a receiving region 151e. The low-wetting region 151a surrounds the high-wetting region 151b, defining the outer periphery of the high-wetting region 151b. At the solder joint of the connector portions 42e and 51f, in order to absorb height deviation, the remaining solder 93 overflowing from the opposing regions of the connector portions 42e and 51f wets and diffuses from the overlap region 151c into the receiving region 151e. The remaining solder 93 is then retained in the receiving region 151e. In this structure, connectors 42e and 51f are terminal portions located within the semiconductor device 10A. This allows for the application of the junction between terminal portions that electrically connect the upper arm 7U and the lower arm 7L.

[0367] Although not illustrated, the aforementioned residual solder containment structure can also be applied to the solder joint between the firing tip E2 and the heat sink 52 (joint portion 52b). Figures 55-57 The diagram illustrates an example where heat sinks 42 and 51 are provided with connectors 42e and 51f respectively, and the connectors 42e and 51f are soldered together, but this is not a limitation. The above-described structure for containing excess solder can also be applied to a structure where only one of the heat sinks 42 and 51 is provided with a connector (terminal). A structure in which multiple semiconductor elements 31 are arranged in parallel between heat sinks 41 and 51 can also be constructed. The above-described structure for containing excess solder can also be applied to the solder joints of heat sinks 51 and 52 with terminals 61 and 62. The same applies to semiconductor elements 32.

[0368] Examples of heat sinks 41, 42, 51, and 52 are shown as wiring components electrically connected to semiconductor elements 31 and 32, but they are not limited to this. Wiring substrates with conductors made of materials such as Cu disposed on insulators such as ceramics may also be used. Figure 58 and Figure 59 The semiconductor device 10A shown includes wiring substrates 40 and 50 arranged to sandwich semiconductor elements 31 and 32. DBC (Direct Bonded Copper) substrates are used as wiring substrates 40 and 50. Wiring substrates 40 and 50 have insulators 40a and 50a and conductors 40b and 50b. Conductors 40b and 50b are disposed at least on the surface (mounting surface) on the side of semiconductor elements 31 and 32 in the Z direction, in other words, in the thickness direction of the insulator. Here, they are also disposed on the back side of the mounting surface. Figure 59 It is Figure 58 The plan view viewed from the X4 direction magnifies the area around the solder joint between the main terminal and the wiring board.

[0369] Wiring substrate 40 has a plurality of electrically separated conductors 40b on its mounting surface. One conductor 40b is connected to the collector electrode 31c of semiconductor element 31, and the other conductor 40b is connected to the collector electrode 32c of semiconductor element 32. Similarly, wiring substrate 50 also has a plurality of electrically separated conductors 50b on its mounting surface. One conductor 50b is electrically connected to the emitter electrode 31e of semiconductor element 31, and the other conductor 50b is electrically connected to the emitter electrode 32e of semiconductor element 32.

[0370] A solder joint 123 is formed between the collector terminal C1 and the conductor 40b connected to the semiconductor element 31. A solder joint 124 is formed between the output terminal OP1 and the conductor 40b connected to the semiconductor element 32. A solder joint 122 is formed between the emitter terminal E2 and the conductor 50b connected to the semiconductor element 32. A solder joint 125 is formed between the conductor 50b connected to the semiconductor element 31 and the conductor 40b connected to the semiconductor element 32. Thus, the semiconductor device 10A has four solder joints 122 to 125 as joints formed between two conductors.

[0371] Figure 60 This is a plan view showing the periphery of the solder joint 124. The conductor 40b of the wiring substrate 40 has a low-wetting region 142a and a high-wetting region 142b on its mounting surface. The low-wetting region 142a corresponds to the previously shown low-wetting regions 151a and 152a, and the high-wetting region 142b corresponds to the high-wetting regions 151b and 152b. The high-wetting region 142b has an overlapping region 142c that overlaps with the joint forming area of ​​the output terminal OP1, and a non-overlapping region 142d connected to the overlapping region 142c. The non-overlapping region 142d includes only a receiving region 142e. The receiving region 142e is connected only to one side of the overlapping region 142c, which has a generally rectangular planar shape. The low-wetting region 142a surrounds the overlapping region 142c and the receiving region 142e, and is adjacent to the outer periphery of the high-wetting region 142b throughout the region. In the solder joint 124, the remaining solder wets and diffuses from the overlapping region 142c to the receiving region 142e and is retained in the receiving region 142e.

[0372] This example illustrates the application of the aforementioned residual solder containment structure in solder joint 124, but it can also be applied to other solder joints 122, 123, and 125. The aforementioned residual solder containment structure can be applied to all four solder joints 122-125, or it can be applied to at least one. In a semiconductor device constituting an arm (e.g., semiconductor devices 11, 12), wiring substrates 40 and 50 such as DBC substrates can also be used. Furthermore, in the previous embodiment, wiring substrates 40 and 50 such as DBC substrates can be used instead of heat sinks 41, 42, 51, and 52. As a wiring component, a combination of a heat sink and a wiring substrate can also be used.

[0373] This example illustrates how a portion of the mounting surface is designated as low-wetting regions 142a, 151a, and 152a by forming an uneven oxide film 162 through laser irradiation, but it is not limited to this. For instance, thermal oxidation can be performed while the high-wetting regions 142b, 151b, and 152b are masked, thus forming an oxide film in the low-wetting regions 142a, 151a, and 152a. The portions with oxide films exhibit decreased wettability to the bonding material (solder) compared to the portions without oxide films.

[0374] Alternatively, by patterning polyamide resin or epoxy resin, the areas with resin film can be designated as low-wetting regions 142a, 151a, and 152a, and the areas without film can be designated as high-wetting regions 142b, 151b, and 152b. Furthermore, by forming a resin film on the surface of the metal component, the adhesion to the sealing resin bodies 20, 21, and 22 can be improved through a primer effect. Alternatively, inorganic materials with low solder wettability (materials that repel solder) can be used instead of resin materials. The areas with a rough coating can also be designated as low-wetting regions 142a, 151a, and 152a, and the areas without a coating as high-wetting regions 142b, 151b, and 152b.

[0375] The above describes an example of selectively treating the low-wetting regions 142a, 151a, and 152a to form a film with low wettability. However, the high-wetting regions 142b, 151b, and 152b can also be selectively treated. It is also possible to form a structure in which a film (e.g., a coating) with high wettability to the bonding material is formed in the high-wetting regions 142b, 151b, and 152b of the mounting surface, while no film with high wettability is formed in the low-wetting regions 142a, 151a, and 152a.

[0376] The bonding material is not limited to solder. Sintered bonding materials such as Ag or Cu, and conductive adhesives such as Ag paste can also be used.

[0377] (Sixth Embodiment)

[0378] In this embodiment, the same reference numerals are assigned to parts that are functionally and / or structurally corresponding to or associated with parts in prior embodiments. For details regarding the corresponding parts and / or associated parts, please refer to the description of the prior embodiments.

[0379] In the prior embodiment, an example was shown where the pads were arranged in the same order among multiple semiconductor elements connected in parallel. A different arrangement order may also be used.

[0380] Figure 61 The semiconductor device 11 in this embodiment is indicated. Figure 61Corresponding to Figure 12 The basic structure of the semiconductor device 11 is the same as that described in the prior embodiment. The semiconductor device 11 includes two semiconductor elements 31 (31a, 31b) arranged in the X direction. Each semiconductor element 31 has five pads 31p on the formation surface of its emitter electrode 31e (not shown). The five pads 31p are arranged along the X direction. Each of the semiconductor elements 31 has a cathode pad P1 for the cathode potential of a temperature-sensing diode, an anode pad P2 for the anode potential of the same temperature-sensing diode, a gate pad P3 for the gate electrode, a current-sensing pad P4 for current sensing, and a Kelvin emitter pad P5 for detecting the potential of the emitter electrode 31e.

[0381] When viewed from the X5 direction, the pads 31p of the semiconductor element 31a, which forms the switching element Q1a, are arranged in sequence as follows: cathode pad P1, anode pad P2, gate pad P3, current sensing pad P4, and Kelvin emitter pad P5. Similarly, when viewed from the X5 direction, the pads 31p of the semiconductor element 31b, which forms the switching element Q1b, are arranged in sequence as follows: Kelvin emitter pad P5, current sensing pad P4, gate pad P3, anode pad P2, and cathode pad P1.

[0382] <Summary of Implementation Method 6>

[0383] Figure 61 The dashed arrows indicate the path of the current (main current) flowing through the main terminal 71. The main current path is formed via semiconductor element 31 between the collector terminal C1 and the emitter terminal E1. The solid arrows indicate the path of the current (signal current) flowing through the signal terminal 81. The signal current path is formed via semiconductor element 31 between the signal terminal 81 connected to the gate pad P3 and the signal terminal 81 connected to the Kelvin emitter pad P5. The circuits flowing with the main current and the circuits flowing with the signal current are magnetically coupled.

[0384] In this embodiment, similar to the previous embodiment, the two semiconductor elements 31a and 31b are arranged symmetrically with respect to axis AX1. Furthermore, the collector terminal C1 and the emitter terminal E1 are arranged linearly symmetrically with respect to axis AX1. Thus, the paths of the main current on the semiconductor element 31a side and the main current on the semiconductor element 31b side are approximately linearly symmetrical with respect to axis AX1.

[0385] In addition, the arrangement of the pads 31p of the two semiconductor elements 31 is symmetrical with respect to the axis AX1. The signal terminals 81 are also symmetrical with respect to the axis AX1. Therefore, the signal current paths on the semiconductor element 31a side and the semiconductor element 31b side are approximately linearly symmetrical about the axis AX1. Consequently, the magnetic coupling is also approximately linearly symmetrical on the semiconductor element 31a and semiconductor element 31b sides. However, when the arrangement of the pads 31p is the same in both semiconductor elements 31a and 31b, the magnetic coupling is asymmetrical.

[0386] In this embodiment, since the symmetry of the magnetic coupling of the signal current circuit, i.e. the symmetry of mutual inductance, is also taken into account, the imbalance of AC current can be suppressed more effectively.

[0387] (Seventh Embodiment)

[0388] In this embodiment, the same reference numerals are assigned to parts that are functionally and / or structurally corresponding to or associated with parts in prior embodiments. For details regarding the corresponding parts and / or associated parts, please refer to the description of the prior embodiments.

[0389] In this embodiment, the wiring component is characterized by the shape of a heat sink configured to sandwich a semiconductor element. The shape of the heat sink is carefully designed to improve the wiring inductance on the emitter side.

[0390] <The effect of wiring inductance on the emitter side>

[0391] The wiring inductance on the emitter side serves to mitigate the imbalance of AC current in the parallel circuit. Figure 62 This is an equivalent circuit diagram of the semiconductor device 12 constituting the lower arm 7L. Like the previous embodiment, the semiconductor device 12 includes two semiconductor elements 32 (32a, 32b). A wiring inductance Le21 exists between semiconductor element 32a and the emitter terminal E2, and a wiring inductance Le22 ​​exists between semiconductor element 32b and the emitter terminal E2. Therefore, during switching, i.e., when AC current flows, the emitter potential changes (rises).

[0392] Here, let the switching speed of switching element Q2a be dI1 / dt, and the switching speed of switching element Q2b be dI2 / dt. The change in emitter potential ΔVe during switching is equal to the product of the switching speed and the wiring inductance. The change ΔVe1 on the semiconductor element 32a side is ΔVe1 = Le21 × (dI1 / dt). The change ΔVe2 on the semiconductor element 32b side is ΔVe2 = Le22 ​​× (dI2 / dt).

[0393] For example, consider the case where the wiring inductances Le21 and Le22 ​​are equal. The deviation in switching speeds dI1 / dt and dI2 / dt creates a difference in the variation ΔVe. If the values ​​of wiring inductances Le21 and Le22 ​​are large, the difference in variation ΔVe becomes larger, affecting the gate voltage Vge. For example, when dI1 / dt > dI2 / dt, the variation ΔVe1 becomes larger relative to the variation ΔVe2, and the gate voltage Vge1 becomes lower than the gate voltage Vge2. Thus, the gate voltage Vge shifts towards the side that suppresses the AC current imbalance (bias). Therefore, the AC current imbalance can be suppressed.

[0394] When the values ​​of wiring inductances Le21 and Le22 ​​are small, the value of the variation ΔVe becomes smaller. Therefore, even if deviations occur in the switching speeds dI1 / dt and dI2 / dt, the difference between the variations ΔVe1 and ΔVe2 is also small. Consequently, the effect of the wiring inductance in suppressing imbalance is weakened. In other words, if the values ​​of wiring inductances Le21 and Le22 ​​are small, AC current imbalance is more likely to occur due to deviations in the switching speeds dI1 / dt and dI2 / dt, i.e., poor component characteristics.

[0395] <Shape of the heat sink>

[0396] Figure 63 Regarding the semiconductor device 12 of this embodiment, the heat sink 52 on the emitter side and the emitter terminal E2 are shown. Figure 64 This shows the heat sink 42 and collector terminal C2 on the collector side. The structure of collector terminal C2 and emitter terminal E2 is the same as the structure described in the prior embodiment (for example, see...). Figure 12 The configurations of the two semiconductor elements 32 are also the same. The basic structures of the heat sinks 42 and 52 are also the same.

[0397] like Figure 63 As shown, the heat sink 52 of this embodiment has a slit 52s. The slit 52s extends through the heat sink 52 in the Z direction and divides the main body 52a into two islands 52i. One island 52i is a mounting area for the semiconductor element 32a. The other island 52i is a mounting area for the semiconductor element 32b. The main body 52a has a generally rectangular planar shape, having a first long side connected to the emitter electrode E2 and a second long side located on the opposite side of the first long side. The slit 52s opens on the second long side of the main body 52a and extends toward the first long side in the Y direction.

[0398] The slit 52s spans the opposing regions 32t of the two semiconductor elements 32 in the Y direction. That is, the slit 52s extends in the Y direction to a position closer to the emitter E2 (opposing portion E2a) than the semiconductor elements 32. The slit 52s is located approximately at the center of the main body portion 52a (heat sink 52) in the X direction. The two islands 52i are arranged linearly symmetrically about the axis AX2. The slit 52s is sometimes referred to as a notch or separation region.

[0399] like Figure 64 As shown, the heat sink 42 of this embodiment has a slit 42s. The slit 42s extends through the heat sink 42 in the Z direction and divides it into two islands 42i. One island 42i is a mounting area for the semiconductor element 32a. The other island 42i is a mounting area for the semiconductor element 32b. The heat sink 42 has a generally rectangular planar shape, having a first long side connected to the collector terminal C2 and a second long side located on the opposite side of the first long side. The slit 42s opens on the first long side and extends toward the second long side in the Y direction. The slit 42s opens on the opposite side of the opening end of the slit 52s.

[0400] The slit 42s spans the opposing regions 32t of the two semiconductor elements 32 in the Y direction. That is, the slit 42s extends in the Y direction to a position closer to the second long side of the semiconductor element 32. The slit 42s is located approximately at the center of the heat sink 42 in the X direction. The two islands 42i are arranged linearly symmetrically about the axis AX2. The slit 42s is sometimes referred to as a notch or separation region.

[0401] <Summary of Implementation Method 7>

[0402] Figure 63 The dashed lines represent current paths. The current paths on the semiconductor element 32a side and the semiconductor element 32b side merge at the front end of the extension of the slit 52s due to the presence of the slit 52s. Thus, the heat sink 52, having the slit 52s, allows for a longer distance (wiring length) from the semiconductor elements 32a and 32b to the merging point of the two current paths compared to a structure without the slit 52s. In other words, the merging point is farther than in a structure without the slit 52s. This allows for an increase in the values ​​of the wiring inductances Le21 and Le22. Consequently, it helps to suppress AC current imbalances caused by poor component characteristics.

[0403] In this embodiment, the slit 52s spans the opposing region 32t of the semiconductor element 32. Therefore, no confluence portion is formed within the opposing region 32t. This allows for a longer wiring length up to the confluence portion. Consequently, the values ​​of the wiring inductances Le21 and Le22 ​​can be further increased, thereby improving the aforementioned current imbalance suppression effect.

[0404] In this embodiment, the heat sink 52, including the slit 52s, is linearly symmetrical with respect to axis AX2. Therefore, when the slit 52s is provided, the current path on the semiconductor element 32a side and the current path on the semiconductor element 32b side are linearly symmetrical. Consequently, the wiring inductance Le21 and wiring inductance Le22 ​​are approximately equal. This helps to suppress AC current imbalance.

[0405] In this embodiment, the heat sink 52 is divided into two islands 52i by the slit 52s. Multiple islands 52i are formed within a metal plate or conductor. This simplifies the structure.

[0406] Figure 65 The reference example does not have slits 42s and 52s. Solid arrows indicate the current path between collector terminal C2r and semiconductor element 32r. Dashed arrows indicate the current path between emitter terminal E2r and semiconductor element 32r. The current flowing between collector terminal C21r and semiconductor element 32br and the current flowing between semiconductor element 32br and emitter terminal E2r have opposing components. Similarly, the current flowing between collector terminal C22r and semiconductor element 32ar and the current flowing between semiconductor element 32ar and emitter terminal E2r have opposing components.

[0407] Thus, the current flowing between the collector terminal C2r and the semiconductor element 32r, which are located far apart in the X direction, and the current flowing between the semiconductor element 32r and the emitter terminal E2r have mutually opposite components. As a result, the wiring inductance is reduced through magnetic flux cancellation.

[0408] In this embodiment, by providing a slit 52s in the heat sink 52, the current path between the semiconductor element 32 and the emitter terminal E2 becomes... Figure 65 The current paths shown are different. Therefore, the reverse components in the current flowing between semiconductor element 32 and collector terminal C2 and between semiconductor element 32 and emitter terminal E2 can be reduced. Consequently, magnetic flux cancellation can be reduced. In other words, mutual inductance acts on the positive side. As a result, the values ​​of wiring inductances Le21 and Le22 ​​can be increased, thereby suppressing the AC current imbalance caused by poor component characteristics.

[0409] In this embodiment, the heat sink 42 has a slit 42s. Therefore, a slit 42s is formed between the collector terminal C2 and the semiconductor element 32. Figure 64 The current paths are indicated by solid arrows. A current path bypassing the slit 42s is formed between the collector terminal C22 and the semiconductor element 32a. Similarly, a current path bypassing the slit 42s is formed between the collector terminal C21 and the semiconductor element 32b.

[0410] Therefore, compared to a structure without slit 42s, the reverse components in the current flowing between semiconductor element 32 and collector terminal C2, and between semiconductor element 32 and emitter terminal E2, can be reduced. This allows for an increase in the values ​​of wiring inductances Le21 and Le22, thereby suppressing AC current imbalances caused by poor component characteristics.

[0411] In this embodiment, the slit 42s spans the opposing region 32t of the semiconductor element 32. Therefore, the current path formed between the collector terminal C22 and the semiconductor element 32a is approximately J-shaped. Similarly, the current path formed between the collector terminal C21 and the semiconductor element 32b is also approximately J-shaped. This further reduces the reverse current component. Consequently, the values ​​of the wiring inductances Le21 and Le22 ​​can be further increased, thereby improving the aforementioned current imbalance suppression effect.

[0412] In this embodiment, the heat sink 42, including the slit 42s, is linearly symmetrical with respect to axis AX2. Therefore, when the slit 42s is provided, the current path on the semiconductor element 32a side and the current path on the semiconductor element 32b side are linearly symmetrical. Consequently, the wiring inductance Lc21 and wiring inductance Lc22 are approximately equal. This helps to suppress AC current imbalance.

[0413] In this embodiment, the heat sink 42 is divided into two islands 42i by the slit 42s. Multiple islands 42i are formed within a metal plate or conductor. This simplifies the structure.

[0414] <Variation Example>

[0415] This illustrates an example where slits 42s and 52s are respectively provided in heat sinks 42 and 52, but it is not limited to this. It is also possible to create a structure where only slits 42s are provided in heat sink 42, and no slits 52s are provided in heat sink 52. Alternatively, it is possible to create a structure where only slits 52s are provided in heat sink 52, and no slits 42s are provided in heat sink 42.

[0416] Examples of slits 42s and 52s being provided in semiconductor device 12 are shown, but the invention is not limited to this. In semiconductor device 11, the current path without slits is different from... Figure 65 The reference example shown is the same. Therefore, in the semiconductor device 11, a slit may also be provided at least on one of the heat sinks 41 and 51. Through the above-described effect of extending the confluence portion further and / or reducing the effect of magnetic flux cancellation, the values ​​of wiring inductances Le11 and Le12 can be increased. As a result, the imbalance of AC current caused by poor component characteristics can be suppressed.

[0417] For example, in Figure 12In the semiconductor device 11 with the shown structure, a slit may also be provided in the heat sink 41. This slit opens on the long side opposite to the side connected to the collector terminal C1. This reduces magnetic flux cancellation, thereby increasing the values ​​of the wiring inductances Le11 and Le12. In the semiconductor device 11, a slit may also be provided in the heat sink 51. This slit opens on the long side connected to the two emitter terminals E1.

[0418] This illustrates an example of dividing the heat sinks 42 and 52 into multiple islands 42i and 52i by setting slits 42s and 52s, but it is not limited to this. For example, it could also be done as follows: Figure 66 The structure can be configured as shown, with two heat sinks 52. That is, the heat sink 52 can be completely divided into two regions. This achieves the same effect as the structure with slits 52s.

[0419] like Figure 66 As shown, each heat sink 52 has an island 52i. A predetermined gap is provided between the two heat sinks 52 in the X direction. The two heat sinks 52 are electrically connected via a connecting member. Figure 66 In the example shown, the emitter electrode E2 also serves as a connecting component. The opposing portion E2a of the emitter electrode E2 spans the two heat sinks 52. This reduces the number of parts.

[0420] like Figure 67 As shown, it can also be configured with two heat sinks 42. That is, the heat sink 42 can be completely divided into two regions. This achieves the same effect as the structure with slits 42s. Each heat sink 42 has an island 42i. A predetermined gap is provided between the two heat sinks 42 in the X direction. The two heat sinks 42 are electrically connected via a connecting member 43. The connecting member 43 spans the two heat sinks 42.

[0421] Alternatively, a different connecting component than the emitter E2 can be used to electrically connect the two heat sinks 52 (island 52i) and connect this connecting component to the emitter E2. In the semiconductor device 11, a split structure for the heat sinks 41 and 51 can also be used.

[0422] In this embodiment, wiring substrates such as DBC substrates 40 and 50 may be used instead of heat sinks 41, 42, 51, and 52. Figure 68 , Figure 69 and Figure 70 This is one example. Figure 68 Is with Figure 69 and Figure 70 A cross-sectional view of the semiconductor device corresponding to the LXVIII-LXVIII line. Figure 68 For convenience, the sealing resin body 22 and the signal terminal 82 have been omitted. Figure 69 This indicates the wiring substrate 40 on the collector side and the collector terminal C2. Figure 70 This indicates the wiring substrate 50 on the emitter side and the emitter terminal E2.

[0423] Figure 68 The semiconductor device 12 shown is similar to prior embodiments (e.g., see reference 12). Figure 59 Similarly, wiring components include wiring substrates 40 and 50 arranged to sandwich two semiconductor elements 32 (32a, 32b). Wiring substrates 40 and 50 are DBC substrates. Wiring substrates 40 and 50 have insulators 40a and 50a and conductors 40b and 50b. Conductors 40b and 50b are disposed at least on the mounting surface in the Z direction. Here, they are also disposed on the back side of the mounting surface.

[0424] In the wiring substrate 40, the conductor 40b on the mounting surface side has two islands 40i and a slit 40s. The conductor 40b with islands 40i and slits 40s corresponds to the heat sink 42. Island 40i corresponds to island 42i, and slit 40s corresponds to slit 42s. Slit 40s passes through the conductor 40b, dividing the conductor 40b into islands 40i, which serve as mounting areas for semiconductor element 32a, and islands 40i, which serve as mounting areas for semiconductor element 32b. One island 40i is connected to the collector terminal C21, and the other island 40i is connected to the collector terminal C22.

[0425] Conductor 40b is, for example, generally rectangular in shape. Slit 40s opens on the long side connected to collector terminal C2 and extends in the Y direction. Slit 40s spans the opposing regions of semiconductor elements 32a and 32b. Semiconductor element 32, conductor 40b including slit 40s, and collector terminal C2 have the same symmetry as in the embodiment described above.

[0426] In the wiring substrate 50, the conductor 50b on the mounting surface side has two islands 50i and a slit 50s. The conductor 50b with islands 50i and slits 50s corresponds to the heat sink 52. Island 50i corresponds to island 52i, and slit 50s corresponds to slit 52s. Slit 50s passes through the conductor 50b, dividing the conductor 50b into islands 50i that serve as mounting regions for semiconductor element 32a and islands 50i that serve as mounting regions for semiconductor element 32b. The emitter terminal E2 is connected to the portion in the conductor 50b that connects the two islands 50i.

[0427] Conductor 50b is, for example, generally rectangular in shape. Slit 50s opens on the long side opposite to the side connected to emitter E2 and extends in the Y direction. Slit 50s spans the opposing regions of semiconductor elements 32a and 32b. Semiconductor element 32, conductor 50b containing slit 50s, and emitter E2 have the same symmetry as in the embodiment described above.

[0428] In this way, the semiconductor device 12 using wiring substrates 40 and 50 can achieve the same effect as the semiconductor device 12 using heat sinks 42 and 52. Furthermore, as a wiring component, the heat sink can be combined with the wiring substrate. For example, it can be configured with a structure having heat sink 42 and wiring substrate 50 (DBC substrate), or a structure having wiring substrate 40 and heat sink 52. This can also be applied to the semiconductor device 11.

[0429] (Other implementation methods)

[0430] The disclosure in this specification and accompanying drawings is not limited to the illustrated embodiments. The disclosure includes the illustrated embodiments and modifications based on them that can be made by those skilled in the art. For example, the disclosure is not limited to the combination of parts and / or elements shown in the embodiments. The disclosure can be implemented in a wide variety of combinations. The disclosure may have additional parts that can be added to the embodiments. The disclosure includes forms in which parts and / or elements of the embodiments are omitted. The disclosure includes substitutions or combinations of parts and / or elements between one embodiment and other embodiments. The scope of the disclosure is not limited to the description of the embodiments. It should be understood that the various technical scopes of the disclosure are indicated by the description in the claims, and also include all modifications within the meaning and scope equivalent to the claims.

[0431] The disclosures in the specification and drawings are not limited to the claims. The disclosures in the specification and drawings include the technical ideas described in the claims, but also encompass a wider variety of technical ideas than those described in the claims. Therefore, it is possible to extract a diverse range of technical ideas from the disclosures in the specification and drawings without being bound by the claims.

Claims

1. A semiconductor device, characterized in that, have: At least one semiconductor element has a main electrode on one side and on a back side opposite to the aforementioned side in the thickness direction; and The wiring component has a plurality of conductor portions and at least one joint portion formed by distributing a bonding material between two conductor portions in the thickness direction of the plate. The plurality of conductor portions include at least one set of heat dissipation portions disposed in the thickness direction of the plate on one side and the back side respectively in a manner that clamps the semiconductor element and electrically connected to the corresponding main electrode, and a plurality of terminal portions connected to the heat dissipation portions. In at least one of the aforementioned joint portions, a first conductor portion, which is one of the aforementioned conductor portions, has a high wetting region and a low wetting region on a side opposite to a second conductor portion, which is another of the aforementioned conductor portions, and the low wetting region has low wettability to the aforementioned joint material compared to the high wetting region. The low wetting region is provided adjacent to the high wetting region in a plan view viewed from the plate thickness direction to define the outer periphery of the high wetting region. The aforementioned high-wetting region has overlapping and non-overlapping regions in the aforementioned plan view. The overlapping region is the region that overlaps with the region forming the joint of the aforementioned second conductor portion and is provided with the aforementioned bonding material in at least a portion of it. The non-overlapping region is the region that is coplanarly connected to the overlapping region and does not overlap with the region forming the joint of the aforementioned second conductor portion. The aforementioned non-overlapping area includes at least a receiving area that is coplanarly connected to the aforementioned overlapping area and that will contain the remaining joint material at the aforementioned joint.

2. The semiconductor device as claimed in claim 1, characterized in that, The aforementioned receiving area is connected only to a portion of the outer periphery of the aforementioned overlapping area in the aforementioned plan view; The aforementioned low-wetting region is adjacent to the outer periphery of the aforementioned high-wetting region on both sides of the aforementioned direction orthogonal to the arrangement direction of the aforementioned overlapping region and the aforementioned receiving region and the aforementioned plate thickness direction.

3. The semiconductor device as claimed in claim 1, characterized in that, The aforementioned low-wetting region is adjacent to the portion of the outer periphery that forms the aforementioned high-wetting region within the aforementioned containment region throughout the region.

4. The semiconductor device as claimed in claim 1, characterized in that, The aforementioned low-wetting region encloses the aforementioned overlapping and non-overlapping regions that are interconnected, and is adjacent to the periphery of the aforementioned high-wetting region throughout the region.

5. The semiconductor device as claimed in claim 1, characterized in that, The first conductor portion described above has two overlapping regions as the high wetting region, and a receiving region provided between the overlapping regions and connected to the overlapping regions respectively in the arrangement direction of the two overlapping regions.

6. The semiconductor device as claimed in claim 1, characterized in that, The first conductor portion described above has two of the aforementioned receiving regions as the aforementioned high wetting region, and an overlapping region provided between the aforementioned receiving regions and connected to the aforementioned receiving regions in the arrangement direction of the two aforementioned receiving regions.

7. The semiconductor device as claimed in claim 1, characterized in that, In the first conductor portion, a film with low wettability to the bonding material is formed only in the low wettability region of the high wettability region and the low wettability region.

8. The semiconductor device as claimed in claim 7, characterized in that, The first conductor portion described above has a base material, a metal film formed on the surface of the base material, and an uneven oxide film, wherein the uneven oxide film is an oxide of a metal that is the same as the main component of the metal film and the surface is continuous to form an uneven surface; The aforementioned uneven oxide film is formed only in the aforementioned low-wetting areas as a film with low wettability to the aforementioned bonding material.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The non-overlapping areas mentioned above include only the aforementioned containment areas.

10. The semiconductor device according to any one of claims 1 to 8, characterized in that, The aforementioned non-overlapping region includes the aforementioned receiving region and the narrow-width region, which is connected to the aforementioned overlapping region at a different location from the aforementioned receiving region, and whose length in the arrangement direction of the aforementioned overlapping region is shorter than that of the aforementioned receiving region.

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