Display device

Abstract

A display device is provided. The display device according to an embodiment includes a substrate; and a plurality of unit pixels disposed on the substrate, wherein each of the plurality of unit pixels includes a first electrode; a second electrode spaced apart from the first electrode and surrounding a periphery of the first electrode; light emitting elements disposed between the first electrode and the second electrode and each including a first end and a second end; a third electrode superposed with the first electrode and the first end of the light emitting elements and contacting the first electrode and the first end of the light emitting elements; and a fourth electrode superposed with the second electrode and the second end of the light emitting elements and contacting the second electrode and the second end of the light emitting elements, wherein the light emitting elements are disposed radially around the first electrode.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to a display device. Background Technology

[0002] Recently, interest in information display has been growing. Therefore, research and development of display devices have been ongoing. Summary of the Invention

[0003] Technical issues

[0004] When the light-emitting element is set to be biased in a specific direction, the light emitted from the light-emitting element will be concentrated in that specific direction, and the light output distribution of the display device will be uneven.

[0005] The purpose of this disclosure is to provide a display device having a uniform light output distribution.

[0006] Another object of this disclosure is to provide a display device in which the area where the light-emitting element is disposed can be increased.

[0007] The purpose of this disclosure is not limited to the foregoing, and other unmentioned purposes will be clearly understood by those skilled in the art from the appended claims.

[0008] Technical solution

[0009] To achieve the above objectives, a display device according to embodiments of the present disclosure may include: a substrate; and a plurality of unit pixels disposed on the substrate. Each of the plurality of unit pixels may include: a first electrode; a second electrode spaced apart from the first electrode and surrounding the periphery of the first electrode; a light-emitting element disposed between the first electrode and the second electrode, and each including a first end and a second end; a third electrode superimposed on the first electrode and the first end of the light-emitting element, and contacting the first electrode and the first end of the light-emitting element; and a fourth electrode superimposed on the second electrode and the second end of the light-emitting element, and contacting the second electrode and the second end of the light-emitting element. The light-emitting elements may be radially disposed around the first electrode.

[0010] The first electrode may include: a first center electrode, which is formed in a circular shape in a plan view; a first peripheral electrode, which surrounds at least a portion of the first center electrode; and a first connecting electrode, which connects the first center electrode and the first peripheral electrode to each other.

[0011] The second electrode may include: a second central electrode surrounding at least a portion of the first central electrode; a second peripheral electrode surrounding at least a portion of the second central electrode; and a second connecting electrode connecting the second central electrode and the second peripheral electrode to each other.

[0012] The second central electrode can be formed as an annular shape with an opening on at least one side in a plan view.

[0013] In the plan view, the first peripheral electrode may surround at least a portion of the second central electrode and be formed as an annular shape with an opening on at least one side.

[0014] The second peripheral electrode can be disposed outside the first peripheral electrode.

[0015] The light-emitting element can be disposed in at least one of the regions between the first central electrode and the second central electrode, between the second central electrode and the first peripheral electrode, and between the first peripheral electrode and the second peripheral electrode.

[0016] The display device may further include an insulating layer disposed on the first electrode and the second electrode. The insulating layer may include a first opening formed to expose at least a portion of the first electrode; and a second opening formed to expose at least a portion of the second electrode. A third electrode may contact the first electrode through the first opening. A fourth electrode may contact the second electrode through the second opening.

[0017] The display device may further include a fixing layer disposed on the insulating layer and the light-emitting elements. The fixing layer may contact at least a portion of the outer peripheral surface of each of the light-emitting elements and allows exposure of the first end and the second end.

[0018] The fixing layer may include organic materials, and at least a portion of the fixing layer may be disposed between the light-emitting element and the insulating layer.

[0019] The fixing layer may include inorganic materials, and voids may be formed at least partially between the light-emitting element and the insulating layer.

[0020] Each of the plurality of unit pixels may further include: a first dike disposed between the substrate and the first electrode; and a second dike disposed between the substrate and the second electrode. A light-emitting element may be disposed between the first dike and the second dike.

[0021] The display device may further include: a partition wall surrounding at least some of the plurality of unit pixels and disposed on an insulating layer. At least a portion of the second partition wall may be superimposed on the partition wall.

[0022] The fourth electrode may be spaced apart from the third electrode and is configured to surround the periphery of the third electrode.

[0023] The display device may further include an insulating pattern disposed between the third electrode and the fourth electrode. The insulating pattern may be disposed on one of the third electrode and the fourth electrode. The remaining one of the third electrode and the fourth electrode may be disposed on the insulating pattern.

[0024] The display device may further include: a driving transistor disposed between a substrate and a plurality of unit pixels, and electrically connected to a light-emitting element. The driving transistor may include: a semiconductor pattern disposed on the substrate; a gate electrode disposed on the semiconductor pattern; and a first transistor electrode and a second transistor electrode disposed on the gate electrode. The semiconductor pattern may include: a first region contacting the first transistor electrode; a second region spaced apart from the first region and contacting the second transistor electrode; and a channel region disposed between the first region and the second region. The first transistor electrode may be electrically connected to a first bridge wire disposed on a layer different from the first transistor electrode. The first bridge wire may be electrically connected to one of the first electrode and the second electrode.

[0025] The first bridge connection can contact the first electrode through a contact hole that overlaps with the first electrode.

[0026] The first transistor electrode can be electrically connected to a second bridge wire disposed on the same layer as the first transistor electrode. The second bridge wire can be electrically connected to the first electrode. The first bridge wire can be electrically connected to the second electrode.

[0027] To achieve the above objectives, a display device according to embodiments of the present disclosure may include: a substrate; and a plurality of unit pixels disposed on the substrate. Each of the plurality of unit pixels may include: a first electrode having a spiral shape wound in a clockwise or counterclockwise direction away from a center point in a planar view; a second electrode having a spiral shape wound in the same direction as the first electrode away from a center point in a planar view, and spaced apart from the first electrode; and a light-emitting element disposed between the first electrode and the second electrode.

[0028] Multiple unit pixels may include a first unit pixel and a second unit pixel adjacent to the first unit pixel. The first electrode and the second electrode of the first unit pixel are wound in different directions than the first electrode and the second electrode of the second unit pixel.

[0029] The light-emitting elements can be arranged radially around the center point.

[0030] Each light-emitting element may include a first end and a second end. Each of the plurality of unit pixels may include: a third electrode, which is superimposed on the first end and the first electrode of the light-emitting element and contacts the first electrode and the first end of the light-emitting element; and a fourth electrode, which is superimposed on the second end and the second electrode of the light-emitting element and contacts the second electrode and the second end of the light-emitting element, and is spaced apart from the third electrode.

[0031] In the planar diagram, both the third and fourth electrodes can have a spiral shape that winds in the same direction as the first and second electrodes while moving away from the center point.

[0032] Each of the plurality of unit pixels may include: a first dike disposed between the substrate and the first electrode; and a second dike disposed between the substrate and the second electrode. A light-emitting element may be disposed between the first dike and the second dike.

[0033] In the plan view, both the first and second dikes can have a spiral shape that winds in the same direction as the first and second electrodes while moving away from the center point.

[0034] Details of the various embodiments are included in the detailed description and accompanying drawings.

[0035] Beneficial effects

[0036] In various embodiments of this disclosure, the light-emitting element between the first electrode and the second electrode surrounding the first electrode can be radially disposed around the first electrode. Therefore, it is possible to prevent light emitted from the light-emitting element from concentrating in a specific direction and to provide a display device with a uniform light output distribution.

[0037] Furthermore, various embodiments of this disclosure can provide a display device in which both the first electrode and the second electrode include a center electrode, a peripheral electrode, and a connecting electrode, thereby improving the space between the light-emitting element and the second electrode, and increasing the display brightness of the display device.

[0038] Additionally, embodiments of this disclosure may provide a display device in which the first electrode and the second electrode have a spiral shape that winds in the same direction while moving away from the center point in a plan view, thereby improving the space in which the light-emitting element can be effectively disposed between the first electrode and the second electrode, and improving the display brightness of the display device.

[0039] The effects of this disclosure are not limited to the foregoing, and various other effects are anticipated herein. Attached Figure Description

[0040] Figure 1a and Figure 1b This is a perspective view showing the light-emitting element according to an embodiment.

[0041] Figure 2 This is a plan view showing a display device according to an embodiment.

[0042] Figures 3a to 3c Each of these is a circuit diagram showing a pixel according to an embodiment.

[0043] Figure 4 This is a circuit diagram illustrating pixels according to an embodiment.

[0044] Figure 5 This is a plan view showing the pixels according to an embodiment.

[0045] Figure 6 It is a planar view of a unit pixel according to an embodiment, and is shown Figure 5 An enlarged plan view of region Q1.

[0046] Figure 7 and Figure 8 It is a cross-sectional view of a unit pixel according to an embodiment, and is along... Figure 6 The sectional view taken by line A1-A1'.

[0047] Figure 9 It is a planar view of a unit pixel according to the embodiment.

[0048] Figures 10 to 13 It is a cross-sectional view of a unit pixel according to various embodiments, and is along... Figure 9 The sectional view taken by line A2-A2'.

[0049] Figure 14 It is a planar view of a unit pixel according to the embodiment.

[0050] Figure 15 It is a cross-sectional view of a unit pixel according to an embodiment, and is along... Figure 14 The sectional view taken by line A3-A3'.

[0051] Figure 16 It is a planar view of pixels according to the embodiment.

[0052] Figure 17 It is a planar view of a unit pixel according to an embodiment, and is shown Figure 16 An enlarged planar view of region Q2.

[0053] Figure 18 It is along Figure 17 The sectional view taken by line B1-B1'.

[0054] Figure 19 It is along Figure 17 The sectional view taken by line B2-B2'.

[0055] Figure 20 This is a cross-sectional view of a unit pixel according to an embodiment, and is related to... Figure 17 The sectional view corresponding to line B1-B1'.

[0056] Figure 21 It is a planar view of pixels according to the embodiment.

[0057] Figure 22 It is a planar view of a unit pixel according to an embodiment, and is shown Figure 21 An enlarged plan view of region Q3.

[0058] Figure 23 It is along Figure 22 The sectional view taken by line C1-C1'.

[0059] Figure 24 It is along Figure 22 The sectional view taken by line C2-C2'.

[0060] Figure 25 This is a cross-sectional view of a unit pixel according to an embodiment, and is related to... Figure 22 The sectional view corresponding to line C2-C2'. Detailed Implementation

[0061] The advantages and features of this disclosure, and its implementation methods, will become clear from the embodiments described in detail below and the accompanying drawings. However, the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art, and the invention will be defined only by the appended claims.

[0062] It will be understood that when an element or layer is referred to as being "on" another element or layer, that element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or one or more intermediate elements or layers may be present. The same reference numerals always denote the same elements. The shapes, sizes, proportions, angles, quantities, etc., of the components given in the drawings to describe embodiments are for illustrative purposes only, and this disclosure is not limited to the shapes, sizes, proportions, angles, quantities, etc., of the components shown in the drawings.

[0063] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, the first element discussed below may be named the second element without departing from the teachings of this disclosure. In this disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0064] Features of the various embodiments of this disclosure can be combined or integrated with each other in part or in whole, and can be interlocked and operated in various technical ways. Embodiments can be performed independently of each other or in relation to each other.

[0065] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals are used to indicate the same or similar elements.

[0066] Figure 1a and Figure 1bThis is a perspective view showing the light-emitting element according to an embodiment.

[0067] Reference Figure 1a and Figure 1b According to embodiments of the present disclosure, a light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD may be implemented as a stack formed by continuously stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0068] In embodiments of this disclosure, the light-emitting element (LD) may be arranged in the form of a rod extending in one direction. If the direction in which the light-emitting element LD extends is defined as the longitudinal direction, the light-emitting element LD may have a first end and a second end in the longitudinal direction.

[0069] In embodiments of this disclosure, one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed on the first end, and the remaining one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed on the second end.

[0070] In embodiments of this disclosure, the light-emitting element (LD) may be arranged in the form of a rod. Here, the term "rod-shaped" includes rod-like and bar-like shapes, such as cylindrical and prismatic shapes extending in the longitudinal direction (i.e., having an aspect ratio greater than 1). For example, the length of the light-emitting element LD may be greater than its diameter. However, this disclosure is not limited thereto. Furthermore, the light-emitting element LD may be a light-emitting element having a core-shell structure.

[0071] Light-emitting diodes (LDs) can be manufactured to have diameters and / or lengths corresponding to, for example, the micrometer or nanometer scale. For example, the diameter of an LD can be equal to or less than 600 nm, and the length can be equal to or less than 4 μm. However, the size of the LD is not limited to these dimensions. For example, the size of the LD can be changed to meet the requirements of the display device using the LD.

[0072] The first semiconductor layer 11 may include, for example, at least one N-type semiconductor layer. For instance, the first semiconductor layer 11 may include a semiconductor layer comprising any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first dopant such as Si, Ge, Se, or Sn. The materials forming the first semiconductor layer 11 are not limited to these; the first semiconductor layer 11 may be formed from various other materials.

[0073] The active layer 12 can be formed on the first semiconductor layer 11 and has a single quantum well structure or a multiple quantum well structure. When the active layer 12 includes a material with a multiple quantum well structure, the active layer 12 can have a structure formed by alternately stacking multiple quantum layers and multiple well layers.

[0074] If an electric field with a predetermined voltage or higher is applied to opposite ends of the light-emitting element LD, the light-emitting element LD can emit light through the recombination of electron-hole pairs in the active layer 12. Since the light emission of the light-emitting element LD can be controlled based on the above principle, the light-emitting element LD can be used as a light source for various light-emitting devices and a pixel for display devices.

[0075] The active layer 12 can emit light with wavelengths in the range of 400 nm to 900 nm. For example, when the active layer 12 emits light with a blue wavelength, the active layer 12 can include materials such as AlGaN or AlGaInN. Specifically, when the active layer 12 has a structure formed by alternately stacking quantum layers and well layers into a multi-quantum-well structure, the quantum layers can include materials such as AlGaN or AlGaInN, and the well layers can include materials such as GaN or AlInN. In an embodiment, the active layer 12 can include AlGaInN as the quantum layer material and AlInN as the well layer material. As described above, the active layer 12 can emit blue light with a central wavelength in the range of 450 nm to 495 nm.

[0076] However, this disclosure is not limited thereto. The active layer 12 may have a structure formed by alternately stacking semiconductor materials with large band gaps and semiconductor materials with small band gaps, and may include group III to group V semiconductor materials depending on the wavelength of the light to be emitted. The light emitted from the active layer 12 is not limited to light with a blue wavelength, and in some cases may be light with a red wavelength or a green wavelength.

[0077] Light emitted from the active layer 12 can be emitted not only toward the outer surface of the light-emitting element LD relative to the longitudinal direction, but also toward its opposite sidewall. The directionality of the light emitted from the active layer 12 is not limited to either direction.

[0078] The second semiconductor layer 13 may be disposed on the active layer 12 and may include a semiconductor layer of a different type than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one P-type semiconductor layer. Alternatively, the second semiconductor layer 13 may include a semiconductor layer comprising at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second dopant such as Mg, Zn, Ca, and Ba. The materials forming the second semiconductor layer 13 are not limited to these; the second semiconductor layer 13 may be formed from various other materials.

[0079] Although both the first semiconductor layer 11 and the second semiconductor layer 13 are formed as monolayers in the accompanying drawings, this disclosure is not limited thereto. For example, the number of layers included in each of the first semiconductor layer 11 and the second semiconductor layer 13 may be increased depending on the material of the active layer 12. For example, the first semiconductor layer 11 and the second semiconductor layer 13 may also include a cladding layer or a tensile strain barrier reduction (TSBR) layer.

[0080] In the embodiments of this disclosure, the light-emitting element LD may include not only a first semiconductor layer 11, an active layer 12 and a second semiconductor layer 13, but also another fluorescent layer, another active layer, another semiconductor layer and / or another electrode layer disposed on and / or under each layer.

[0081] In embodiments, the light-emitting element (LD) may further include at least one electrode layer disposed on one end of the second semiconductor layer 13 (e.g., the upper surface of the light-emitting element LD) or on one end of the first semiconductor layer 11 (e.g., the lower surface of the light-emitting element LD). For example, as Figure 1b As shown, the light-emitting element LD may further include an electrode layer 15 disposed on one end of the second semiconductor layer 13. The electrode layer 15 may be an ohmic electrode, but this disclosure is not limited thereto. For example, the electrode layer 15 may be a Schottky contact electrode. The electrode layer 15 may include a metal or a metal oxide. For example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), and their oxides or alloys may be used alone or in combination with each other. However, this disclosure is not limited thereto. In embodiments, the electrode layer 15 may be substantially transparent or translucent. Thus, light generated from the light-emitting element LD can be emitted from the light-emitting element LD after passing through the electrode layer 15.

[0082] The light-emitting element LD may also include an insulating film 14. However, in embodiments of this disclosure, the insulating film 14 may be omitted, or the insulating film 14 may be provided to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. For example, the insulating film 14 may be provided on portions of the light-emitting element LD other than its opposite ends, such that the opposite ends of the light-emitting element LD are exposed.

[0083] For the purpose of explanation, Figure 1a and Figure 1b The insulating film 14, which has been partially removed, is shown. In fact, the entire side surface of the light-emitting element LD can be surrounded by the insulating film 14.

[0084] In embodiments of this disclosure, the insulating film 14 may comprise a transparent insulating material. For example, the insulating film 14 may comprise at least one or more insulating materials selected from SiO2, Si3N4, Al2O3, and TiO2, but this disclosure is not limited thereto. In other words, various materials with insulating properties can be used.

[0085] The insulating film 14 prevents the active layer 12 from short-circuiting due to contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film 14 minimizes surface defects in the light-emitting element LD, thereby improving the LD's lifespan and efficiency. When multiple light-emitting elements LD are arranged in close contact with each other, the insulating film 14 prevents unwanted short circuits between the light-emitting elements LD.

[0086] The type, structure, shape, etc. of the light-emitting element LD according to the embodiments of this disclosure can be changed in various ways.

[0087] Figure 2 This is a plan view showing a display device according to an embodiment.

[0088] Reference Figures 1a to 2 The display device 1000 may include a substrate SUB and a plurality of pixels PXL disposed on the substrate SUB. Specifically, the display device 1000 (or the substrate SUB) may include a display area DA formed to display an image and a non-display area NDA other than the display area DA.

[0089] The display area DA can be the area in which the pixel PXL is set. The non-display area NDA can be the area in which the drivers EDV, SDV, and DDV configured to drive the pixel PXL are set, as well as various lines used to connect the pixel PXL to the drivers.

[0090] The display area DA can have various shapes. For example, the display area DA can be set in various forms, such as: a closed polygon with sides formed by straight lines; a circle or ellipse with sides formed by curves; and a semicircle or semi-ellipse with sides formed by both straight lines and curves.

[0091] When the display area DA comprises multiple regions, each region can be configured in various forms, such as a closed polygon including linear sides and a semicircle, semi-ellipse, etc., including sides formed by curves. The surface areas of the multiple regions can be the same or different from each other. In embodiments of this disclosure, an example in which the display area DA is configured as a single region having a rectangular shape including linear sides will be described.

[0092] The non-display area NDA can be disposed on at least one side of the display area DA. In embodiments of this disclosure, the non-display area NDA can surround the display area DA.

[0093] Pixel PXL can be disposed in display area DA located on substrate SUB. Each of the pixels PXL may include at least one light-emitting element LD, which is connected to scan lines and data lines and is configured to be driven in response to a corresponding scan signal and a corresponding data signal.

[0094] Each pixel PXL can emit light of any color among red, green, and blue, and this disclosure is not limited thereto. For example, each of the pixels PXL can emit light of any color among cyan, magenta, yellow, and white.

[0095] Specifically, a pixel PXL may include a first pixel PXL1 configured to emit light having a first color, a second pixel PXL2 configured to emit light having a second color different from the first color, and a third pixel PXL3 configured to emit light having a third color different from the first and second colors. At least one first pixel PXL1, at least one second pixel PXL2, and at least one third pixel PXL3 arranged adjacent to each other can form a pixel unit PXU capable of emitting light having various colors.

[0096] In an embodiment, the first pixel PXL1 can be a red pixel that emits red light, the second pixel PXL2 can be a green pixel that emits green light, and the third pixel PXL3 can be a blue pixel that emits blue light.

[0097] In an embodiment, each pixel PXL may be provided with a light-emitting element LD configured to emit light of the same color, and may include different color conversion layers disposed on each light-emitting element LD, enabling the emission of light of different colors. In an embodiment, each pixel PXL may include light-emitting elements LD configured to emit light of different colors. However, there are no specific limitations on the color, type, and / or number of each pixel PXL.

[0098] Pixel PXL can be arranged on the first direction DR1 and the second direction DR2 intersecting the first direction DR1. However, there are no specific restrictions on the arrangement of pixel PXL, and pixel PXL can be arranged in various forms.

[0099] The driver can provide signals to pixel PXL via corresponding lines (not shown), thereby controlling the operation of pixel PXL. For ease of explanation, in Figure 2 The line is omitted in the middle.

[0100] The driver may include: a scan driver SDV configured to provide scan signals to pixel PXL via scan lines; a transmit driver EDV configured to provide transmit control signals to pixel PXL via transmit control lines; a data driver DDV configured to provide data signals to pixel PXL via data lines; and a timing controller (not shown). The timing controller can control the scan driver SDV, the transmit driver EDV, and the data driver DDV. In an embodiment, the display device 1000 may not include the transmit driver EDV.

[0101] The scan driver (SDV) and transmit driver (EDV) can be disposed on one side of the substrate SUB and can be disposed in one direction (e.g., a second direction DR2). The scan driver (SDV) and transmit driver (EDV) can be mounted on the substrate SUB as separate components, but this disclosure is not limited thereto. For example, the scan driver (SDV) and transmit driver (EDV) can be formed directly on the substrate SUB. Furthermore, the scan driver (SDV) and transmit driver (EDV) can be located outside the substrate SUB and connected to the respective pixels (PXL) via separate connectors. The scan driver (SDV) and transmit driver (EDV) can be disposed on the same side of the substrate SUB, but this disclosure is not limited thereto; the scan driver (SDV) and transmit driver (EDV) can be disposed on different sides.

[0102] The data driver DDV can be positioned on one side of the substrate SUB and in a direction intersecting the directions of the scan driver SDV and the transmit driver EDV (e.g., in the first direction DR1). Alternatively, the data driver DDV can be mounted on the substrate SUB as a separate component, or it can be located outside the substrate SUB and connected to the individual pixels PXL via a separate connector.

[0103] In an embodiment, each of the pixels PXL may be formed by an active pixel. However, the type, structure, and / or driving scheme of the pixels PXL applicable to this disclosure are not specifically limited.

[0104] Figures 3a to 3c Each of these is a circuit diagram illustrating a pixel according to an embodiment. Specifically, Figures 3a to 3c An example of pixels forming an active emission display panel is shown.

[0105] Reference Figures 1a to 3a The pixel PXL may include at least one light-emitting element LD and a driving circuit DC connected to the light-emitting element LD and configured to drive the light-emitting element LD.

[0106] The first electrode (e.g., the anode electrode) of the light-emitting element (LD) can be connected to a first driving power supply VDD via a driving circuit DC. The second electrode (e.g., the cathode electrode) of the light-emitting element (LD) can be connected to a second driving power supply VSS. The light-emitting element (LD) can emit light with a brightness corresponding to the amount of driving current controlled by the driving circuit DC.

[0107] although Figure 3a Only one light-emitting element (LD) is shown, but this is only an exemplary configuration. In reality, a pixel PXL can include multiple light-emitting elements (LDs). Multiple light-emitting elements (LDs) can be connected in parallel and / or in series with each other.

[0108] The first driving power supply VDD and the second driving power supply VSS can have different potentials. For example, the second driving power supply VSS can have a potential that is equal to or greater than the threshold voltage of the light-emitting element (LD) than the potential of the first driving power supply VDD. In other words, the voltage applied to the first driving power supply VDD can be greater than the voltage applied to the second driving power supply VSS.

[0109] In embodiments of this disclosure, the driving circuit DC may include a first transistor M1, a second transistor M2, and a storage capacitor Cst.

[0110] The first electrode of the first transistor (driving transistor) M1 can be connected to the first driving power supply VDD, and its second electrode can be electrically connected to the first electrode (e.g., the anode electrode) of the light-emitting element LD. The gate electrode of the first transistor M1 can be connected to the first node N1. The first transistor M1 can control the amount of driving current to be supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0111] The first electrode of the second transistor (switching transistor) M2 can be connected to the data line DL, and its second electrode can be connected to the first node N1. Here, the first and second electrodes of the second transistor M2 can be different electrodes. For example, if the first electrode is the source electrode, then the second electrode is the drain electrode. The gate electrode of the second transistor M2 can be connected to the scan line SL.

[0112] When a scan signal with a voltage (e.g., gate on-state voltage) capable of turning on the second transistor M2 is supplied from the scan line SL, the second transistor M2 turns on, electrically connecting the data line DL and the first node N1. Here, the data signal of the corresponding frame is supplied to the data line DL, thereby allowing the data signal to be transmitted to the first node N1. The data signal transmitted to the first node N1 can be stored in the storage capacitor Cst.

[0113] One electrode of the storage capacitor Cst can be connected to the first drive power supply VDD, and the remaining electrode can be connected to the first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signal supplied to the first node N1, and the charged voltage is maintained until the data signal of a subsequent frame is supplied.

[0114] For ease of explanation, Figure 3a A driving circuit DC with a relatively simple structure is shown. The driving circuit DC includes a second transistor M2 configured to transmit data signals to the interior of each pixel PXL, a storage capacitor Cst configured to store data signals, and a first transistor M1 configured to supply driving current corresponding to the data signals to the light-emitting element LD.

[0115] However, this disclosure is not limited thereto, and the structure of the driving circuit DC can be changed in various ways. For example, the driving circuit DC may also include various transistors (such as a compensation transistor configured to compensate the threshold voltage of the first transistor M1, an initialization transistor configured to initialize the first node N1, and / or an emission control transistor configured to control the emission time of the light-emitting element LD) or other circuit elements (such as a boost capacitor configured to boost the voltage of the first node N1).

[0116] Furthermore, despite Figure 3a In the present invention, the transistors included in the drive circuit DC (e.g., the first transistor M1 and the second transistor M2) have been shown as being formed of P-type transistors, but this disclosure is not limited thereto. In other words, at least one of the first transistor M1 and the second transistor M2 included in the drive circuit DC may be changed to an N-type transistor.

[0117] For example, such as Figure 3bAs shown, each of the first transistor M1 and the second transistor M2 in the drive circuit DC can be formed by an N-type transistor. Except for the fact that the connection positions of some components change due to the change in the type of transistor, Figure 3b The configuration and operation of the DC drive circuit shown in the figure are similar to Figure 3a The configuration and operation of the DC drive circuit are similar. Therefore, a detailed description related to it will be omitted.

[0118] Alternatively, refer to Figure 3c The pixel PXL may also include a third transistor (sensing transistor) M3.

[0119] The gate electrode of the third transistor M3 can be connected to the sensing signal line SSL. The first electrode of the third transistor M3 can be connected to the sensing line SENL, and its second electrode can be connected to the anode electrode of the light-emitting element LD. In response to a sensing signal supplied to the sensing signal line SSL during a sensing period, the third transistor M3 can transmit the voltage value on the anode electrode of the light-emitting element LD to the sensing line SENL. The voltage value transmitted through the sensing line SENL can be provided to external circuitry (e.g., a timing controller). The external circuitry can extract information about the characteristics of pixel PXL (e.g., the threshold voltage of the first transistor M1, etc.) based on the provided voltage value. The extracted characteristic information can be used to convert image data to compensate for deviations in the characteristics of pixel PXL.

[0120] Figure 4 This is a circuit diagram illustrating pixels according to an embodiment.

[0121] Reference Figure 4 According to embodiments of the present disclosure, a pixel PXL may include a light-emitting element LD, a first transistor to a seventh transistor T1, T2, T3, T4, T5, T6 and T7, and a storage capacitor Cst.

[0122] The first electrode (e.g., the anode electrode) of the light-emitting element LD can be connected to the first transistor T1 via a sixth transistor T6. The second electrode (e.g., the cathode electrode) of the light-emitting element LD can be connected to a second driving power supply VSS. The light-emitting element LD can emit light with a predetermined brightness corresponding to the amount of driving current supplied from the first transistor T1.

[0123] The first electrode of the first transistor (driving transistor) T1 can be connected to the first driving power supply VDD via the fifth transistor T5, and its second electrode can be connected to the first electrode of the light-emitting element LD via the sixth transistor T6. The first transistor T1 can control the amount of current flowing from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD in response to the voltage of the first node N1, which is its gate electrode.

[0124] A second transistor (switching transistor) T2 can be connected between the data line DL and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to the first scan line SL. When a scan signal with a gate on-state voltage is supplied to the first scan line SL, the second transistor T2 can be turned on, allowing the data line DL to be electrically connected to the first electrode of the first transistor T1.

[0125] The third transistor T3 can be connected between the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 can be connected to the first scan line SL. When a scan signal with a gate on-state voltage is supplied to the first scan line SL, the third transistor T3 can be turned on, so that the second electrode of the first transistor T1 can be electrically connected to the first node N1.

[0126] A fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 can be connected to the second scan line SL-1. When a scan signal with a gate on-state voltage is supplied to the second scan line SL-1, the fourth transistor T4 is turned on, allowing the voltage of the initialization power supply Vint to be supplied to the first node N1. Here, the initialization power supply Vint can be set to a voltage lower than the voltage of the data signal. The scan signal applied to the second scan line SL-1 can have the same waveform as the scan signal of the first scan line to be supplied to the pixels of the previous stage.

[0127] The fifth transistor T5 can be connected between the first drive power supply VDD and the first electrode of the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the emitter control line EL. When an emitter control signal with a gate on-state voltage is supplied to the emitter control line EL, the fifth transistor T5 can be turned on, and can be turned off under other conditions.

[0128] The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the first electrode of the light-emitting element LD. The gate electrode of the sixth transistor T6 can be connected to the emitter control line EL. When an emitter control signal with a gate on-state voltage is supplied to the emitter control line EL, the sixth transistor T6 can be turned on, and can be turned off under other conditions.

[0129] A seventh transistor T7 can be connected between the initialization power supply Vint and the first electrode (e.g., the anode electrode) of the light-emitting element LD. The gate electrode of the seventh transistor T7 can be connected to the third scan line SL+1. When a scan signal with a gate on-state voltage is supplied to the third scan line SL+1, the seventh transistor T7 can be turned on, allowing the voltage of the initialization power supply Vint to be supplied to the first electrode of the light-emitting element LD. The scan signal applied to the third scan line SL+1 can have the same waveform as the scan signal of the first scan line to be supplied to subsequent pixels.

[0130] Figure 4 The illustration shows the seventh transistor T7 with its gate electrode connected to the third scan line SL+1. However, the spirit of this disclosure is not limited thereto. For example, in embodiments of this disclosure, the gate electrode of the seventh transistor T7 may be connected to either the first scan line SL or the second scan line SL-1. In this case, when a scan signal with a gate-on voltage is supplied to either the first scan line SL or the second scan line SL-1, the voltage of the initialization power supply Vint may be supplied to the anode electrode of the light-emitting element LD via the seventh transistor T7.

[0131] The storage capacitor Cst can be connected between the first drive power supply VDD and the first node N1. The storage capacitor Cst can store the voltage corresponding to both the data signal and the threshold voltage of the first transistor T1.

[0132] Despite Figure 4 In the present disclosure, the transistors included in the driving circuit DC (e.g., the first to seventh transistors T1, T2, T3, T4, T5, T6 and T7) have been shown as being formed of P-type transistors, but this disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 may be changed to N-type transistors.

[0133] Figure 5 This is a plan view showing the pixels according to an embodiment. Figure 6 It is a planar view of a unit pixel according to an embodiment, and is shown Figure 5 An enlarged plan view of region Q1. Figure 7 and Figure 8 It is a cross-sectional view of a unit pixel according to an embodiment, and is along... Figure 6 The sectional view taken by line A1-A1'.

[0134] For ease of explanation, each electrode will be simplified and shown hereinafter as being formed of a single electrode layer, but this disclosure is not limited thereto. Each electrode may be formed of multiple electrode layers. In embodiments of this disclosure, the phrase "components formed and / or disposed on the same layer" may mean that the components are formed by the same process and are made of the same material.

[0135] Furthermore, for the purpose of explanation, in Figure 5 The diagram omits the transistor connected to the light-emitting element and the signal lines connected to the transistor.

[0136] Reference Figures 5 to 8 The display device according to the embodiment may include a substrate SUB and a pixel PXLa disposed on the substrate SUB.

[0137] The substrate SUB can be a rigid substrate or a flexible substrate, and its material or properties are not specifically limited. For example, the substrate SUB can be a rigid substrate made of glass or tempered glass, or a flexible substrate formed from a thin film made of plastic or metal. Furthermore, the substrate SUB can be a transparent substrate, but this disclosure is not limited thereto. For example, the substrate SUB can be a translucent substrate, an opaque substrate, or a reflective substrate.

[0138] A pixel PXLa can include multiple unit pixels UPX1, UPX2, and UPX3. For example, multiple unit pixels UPX1, UPX2, and UPX3 can include a first unit pixel UPX1, a second unit pixel UPX2, and a third unit pixel UPX3.

[0139] First unit pixel UPX1, second unit pixel UPX2, and third unit pixel UPX3 can be arranged adjacent to each other to form a pixel PXLa. Each of unit pixels UPX1, UPX2, and UPX3 can be a group of the smallest components used to emit light and emit light of the same color. Furthermore, a pixel PXLa can be the smallest unit constructed to emit light of a predetermined color.

[0140] The structures of unit pixels UPX1, UPX2 and UPX3 included in pixel PXLa can be the same or similar to each other. Therefore, the following description will be based on the structure of the first unit pixel UPX1, and the description can also be applied to the second unit pixel UPX2 and the third unit pixel UPX3.

[0141] The first unit pixel UPX1 may include a pixel circuit layer PCL disposed on the substrate SUB and a display element layer DPL disposed on the pixel circuit layer PCL.

[0142] The pixel circuit layer (PCL) may include multiple circuit elements that form the pixel driving circuitry for each of the unit pixels UPX1, UPX2, and UPX3. Figure 7 The pixel circuit layer PCL is shown to include Figures 3a to 3c This is an example of the structure of the first transistor M1. However, the structure of the pixel circuit layer PCL is not limited to this and may also include... Figures 3a to 3b as well as Figure 4 Other circuit components.

[0143] The transistors included in the pixel circuit layer PCL can include substantially the same or similar cross-sectional structures. Furthermore, the structure of each transistor is not limited to... Figure 7 The structure shown.

[0144] The pixel circuit layer (PCL) may include multiple layers. For example, the pixel circuit layer (PCL) may include a buffer layer (BUF), a gate insulating layer (GI), an interlayer insulating layer (IL), a first via layer (VIA1), and a second via layer (VIA2) continuously stacked on a substrate (SUB). Each of the aforementioned layers may be an insulating layer comprising either an organic insulating material or an inorganic insulating material. Additionally, the pixel circuit layer (PCL) may include a first transistor (M1).

[0145] A buffer layer (BUF) prevents impurities from diffusing into each circuit element. While a buffer layer BUF can be a single-layer structure, it can also be a multi-layer structure with at least two or more layers. In the case of a multi-layer buffer layer BUF, the individual layers can be formed from the same material or different materials. Depending on the material or process conditions of the substrate SUB, the buffer layer BUF may be omitted.

[0146] The first transistor M1 can be disposed on the buffer layer BUF. The first transistor M1 may include an active layer ACT, a gate electrode GE, a first transistor electrode TET1, and a second transistor electrode TET2.

[0147] The active layer ACT can be disposed between the buffer layer BUF and the gate insulating layer GI. In the case where the pixel circuit layer PCL does not include the buffer layer BUF, the active layer ACT can be disposed between the substrate SUB and the gate insulating layer GI. The active layer ACT may include a first region contacting the first transistor electrode TET1, a second region connected to the second transistor electrode TET2, and a channel region disposed between the first region and the second region. One of the first region and the second region can be a source region, and the other can be a drain region.

[0148] The active layer ACT can be a semiconductor pattern formed from polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The channel region of the active layer ACT can be an intrinsic semiconductor of an undoped semiconductor pattern. Each of the first and second regions of the active layer ACT can be a semiconductor pattern doped with a predetermined impurity.

[0149] The gate electrode GE can be disposed between the gate insulating layer GI and the interlayer insulating layer IL, and at least partially stacked with the active layer ACT. The gate electrode GE can be insulated from the active layer ACT through the gate insulating layer GI.

[0150] The first transistor electrode TET1 and the second transistor electrode TET2 can be disposed on the interlayer insulating layer IL. The first transistor electrode TET1 and the second transistor electrode TET2 can be electrically connected to the active layer ACT. For example, the first transistor electrode TET1 and the second transistor electrode TET2 can contact the first region and the second region of the active layer ACT respectively through contact holes passing through the gate insulating layer GI and the interlayer insulating layer IL.

[0151] The first bridge wire BRE1 can be disposed on the same layer as the first transistor electrode TET1 and the second transistor electrode TET2. In the plan view, the first bridge wire BRE1 can extend in the second direction DR2. Although not shown in the figure, the first bridge wire BRE1 can be electrically connected to the second electrode RFE2, which will be described below, via a contact hole or a separate connector. The first bridge wire BRE1 can be connected to a second drive power supply ( Figure 3a The voltage of the second drive power supply VSS is supplied to the second electrode RFE2.

[0152] The first transistor electrode TET1 of the first transistor M1 can be electrically connected to the second bridge wire BRE2 disposed on the first via layer VIA1 through a contact hole disposed on the first transistor electrode TET1.

[0153] The second bridge wire BRE2 can be connected to the first electrode RFE1 through a contact hole CTH passing through at least a portion of the second via layer VIA2 and the first via layer VIA1, and transmits the drive current supplied by the first transistor M1 to the first electrode RFE1. The second bridge wire BRE2 can be widely disposed on the first via layer VIA1, such that it is at least partially superimposed on the light-emitting element LD of the display element layer DPL. In this case, voltage drop of the drive voltage supplied to the light-emitting element LD can be prevented, thereby improving the display quality of the display device.

[0154] The connection structure of the first bridge wiring BRE1 and the second bridge wiring BRE2 is not limited to this. For example, as Figure 8As shown, the first bridge wire BRE1' can be electrically connected to the first electrode RFE1' through the contact hole CTH, so that the voltage of the second drive power supply VSS can be provided to the first electrode RFE1'. In addition, the second bridge wire BRE2' can be electrically connected to the second electrode RFE2' through the contact hole, so that the drive current provided from the first transistor M1 can be provided to the second electrode RFE2'.

[0155] In the foregoing embodiments, an example has been described in the plan view that includes a pixel circuit layer PCL in pixel PXLa (or the first unit pixel UPX1) disposed below the display element layer DPL, but this disclosure is not limited thereto. In embodiments, the pixel circuit layer PCL may be disposed below the display element layer DPL and in an area that does not overlap with the display element layer DPL.

[0156] The display element layer (DPL) will be described below. The display element layer (DPL) may be disposed above the pixel circuit layer (PCL) (or the second via layer (VIA2)) and includes multiple light-emitting elements (LDs).

[0157] In detail, the display element layer DPL may include a first electrode RFE1 and a second electrode RFE2, a light-emitting element LD, a fixing layer INSA, a third electrode CTE1 and a fourth electrode CTE2, and a passivation layer PSV. In an embodiment, a pixel PXLa may also include a partition wall PW surrounding each unit pixel UPX1, UPX2 and UPX3.

[0158] The first electrode RFE1 and the second electrode RFE2 can be positioned at a distance from each other. The second electrode RFE2 can be configured to surround at least a portion of the first electrode RFE1.

[0159] The first electrode RFE1 (or the first reflective electrode) may be located in the center portion of the first unit pixel UPX1 and formed in a circular shape. The shape of the first electrode RFE1 is not limited to a circular shape, and may be formed in various shapes having annular curved structures.

[0160] As described above, the first electrode RFE1 can be electrically connected to the second bridge wire BRE2 of the pixel circuit layer PCL through the contact hole CTH, and is supplied with drive current through the second bridge wire BRE2.

[0161] In a plan view, the second electrode RFE2 (or the second reflective electrode) can be configured to surround the first electrode RFE1. In the plan view, the second electrode RFE2 can be formed in various shapes such as rectangular, circular, and elliptical, and has an opening in which the first electrode RFE1 can be disposed. The shape of the opening included in the second electrode RFE2 can be the same as or similar to the shape of the first electrode RFE1, and the shape of the opening is not limited, as long as the first electrode RFE1 and the second electrode RFE2 can be positioned at a distance from each other. For example, Figure 6 A structure is shown in which a first electrode RFE1 of a first unit pixel UPX1 has a circular shape, a second electrode RFE2 has a rectangular shape, and the second electrode RFE2 includes an opening having a shape corresponding to and larger than that of the first electrode RFE1.

[0162] The second electrodes RFE2 of each unit pixel UPX1, UPX2 and UPX3 can be connected to each other through a connection pattern CNE, but this disclosure is not limited thereto. For example, the second electrodes RFE2 can be formed in each of the unit pixels UPX1, UPX2 and UPX3 respectively and connected to the lines of the pixel circuit layer PCL.

[0163] Although not shown in the accompanying drawings, the second electrode RFE2 can be electrically connected to the first bridge terminal BRE1 and is supplied with the voltage of the second drive power supply. Figure 3a (VSS).

[0164] Either the first electrode RFE1 or the second electrode RFE2 can be an anode electrode, and the other electrode can be a cathode electrode. For example, the first electrode RFE1 can be an anode electrode, and the second electrode RFE2 can be a cathode electrode, but this disclosure is not limited thereto.

[0165] The first electrode RFE1 and the second electrode RFE2 can be formed of a conductive material. The conductive material may include metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti and their alloys, but this disclosure is not limited thereto.

[0166] Each of the first electrode RFE1 and the second electrode RFE2 may be formed from a single layer, but this disclosure is not limited thereto; each of the first electrode RFE1 and the second electrode RFE2 may also be formed from multiple layers. For example, both the first electrode RFE1 and the second electrode RFE2 may further include a cover layer (not shown) formed of a transparent conductive material. The cover layer may be configured to cover the first electrode RFE1 and the second electrode RFE2, thereby preventing the first electrode RFE1 and the second electrode RFE2 from being damaged during the manufacturing process of the display device.

[0167] The materials of the first electrode RFE1 and the second electrode RFE2 are not limited to those described above. For example, the first electrode RFE1 and the second electrode RFE2 can be made of a conductive material with a constant reflectivity. When the first electrode RFE1 and the second electrode RFE2 are made of a conductive material with a constant reflectivity, the light emitted from the light-emitting element LD can be reflected by the first electrode RFE1 and the second electrode RFE2, and then travel in the display direction (e.g., the third direction DR3).

[0168] The spacing between the first electrode RFE1 and the second electrode RFE2 can be substantially uniform. Therefore, the light-emitting elements (LDs) arranged between the first electrode RFE1 and the second electrode RFE2 can be arranged more uniformly.

[0169] The light-emitting elements (LDs) can be disposed on the first electrode RFE1 and the second electrode RFE2. The LDs can be arranged radially (centripetally) around the first electrode RFE1. The distances between the LDs can vary, but this disclosure is not limited thereto. The LDs can also be configured to have the same distance between them.

[0170] The light-emitting elements LD disposed on the first electrode RFE1 and the second electrode RFE2 can form a parallel connection structure, but this disclosure is not limited thereto.

[0171] Each light-emitting element (LD) may include a first terminal EP1 and a second terminal EP2. The first terminal EP1 may be stacked with a first electrode RFE1. The second terminal EP2 may be stacked with a second electrode RFE2. See also... Figure 1a The second semiconductor layer 13 can be disposed on the first end EP1, and the first semiconductor layer 11 can be disposed on the second end EP2.

[0172] The light-emitting element (LD) can be supplied with a driving current (or driving signal) from the first electrode RFE1 and the second electrode RFE2, and emits light with a predetermined brightness corresponding to the supplied driving current.

[0173] A fixing layer INSA can be disposed on the light-emitting element LD to stably support and fix the light-emitting element LD. The fixing layer INSA can be formed of an inorganic insulating layer including inorganic materials or an organic insulating layer including organic materials. The fixing layer INSA can be disposed such that the space between the light-emitting element LD and the second via layer VIA2 is filled with the fixing layer INSA. The fixing layer INSA can cover at least a portion of the outer peripheral surface of each of the light-emitting elements LD, and is formed such that the first end EP1 and the second end EP2 of the light-emitting element LD are exposed. Therefore, the fixing layer INSA can stably support and fix the light-emitting element LD, thereby preventing the light-emitting element LD from being removed from the display element layer DPL. The fixing layer INSA can be omitted depending on the process conditions of the display element layer DPL.

[0174] The third electrode CTE1 and the fourth electrode CTE2 can be set on the first electrode RFE1, the second electrode RFE2 and the light-emitting element LD.

[0175] In the plan view, the third electrode CTE1 (or the first contact electrode) can be formed in a circular shape and is configured to cover and stack with the first electrode RFE1. The first end EP1 of the light-emitting element LD can be disposed between the first electrode RFE1 and the third electrode CTE1. The third electrode CTE1 can contact the first electrode RFE1 and the first end EP1 of the light-emitting element LD. In other words, the first electrode RFE1 can be electrically connected to the first end EP1 of the light-emitting element LD through the third electrode CTE1.

[0176] In the plan view, the fourth electrode CTE2 (or the second contact electrode) can be formed in a ring shape and is arranged to overlap with the second electrode RFE2. The second end EP2 of the light-emitting element LD can be located between the second electrode RFE2 and the fourth electrode CTE2. The fourth electrode CTE2 can contact the second electrode RFE2 and the second end EP2 of the light-emitting element LD. In other words, the second electrode RFE2 can be electrically connected to the second end EP2 of the light-emitting element LD through the fourth electrode CTE2.

[0177] However, the shapes of the third electrode CTE1 and the fourth electrode CTE2 are not limited to those shown in the figures and can be changed in various ways. Furthermore, the third electrode CTE1 and the fourth electrode CTE2 can be formed in the same layer, but this disclosure is not limited thereto; the third electrode CTE1 and the fourth electrode CTE2 can be formed in different layers.

[0178] Each of the third electrode CTE1 and the fourth electrode CTE2 can be formed of a transparent conductive material. For example, the transparent conductive material may include indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). When the third electrode CTE1 and the fourth electrode CTE2 are formed of a transparent conductive material, the loss of light emitted from the light-emitting element LD and traveling on the third-party DR3 can be reduced. The materials of the third electrode CTE1 and the fourth electrode CTE2 are not limited to those described above.

[0179] A passivation layer PSV can be disposed on the third electrode CTE1 and the fourth electrode CTE2. The passivation layer PSV can be formed on the outermost portion of the display element layer DPL and cover the other components of the display element layer DPL. The passivation layer PSV can also serve as an encapsulation layer to prevent damage to the first electrode RFE1, the second electrode RFE2, the third electrode CTE1, the fourth electrode CTE2, and the light-emitting element LD during the manufacturing process of the display device, and to prevent oxygen and / or water from penetrating the display element layer DPL.

[0180] The passivation layer PSV can be formed from an inorganic insulating layer comprising inorganic materials. The passivation layer PSV can be formed as a single layer, but this disclosure is not limited thereto; the passivation layer PSV can include a multilayer structure. In the case where the passivation layer PSV has a multilayer structure, the passivation layer PSV can further include an organic insulating layer comprising organic materials, and has a structure formed by alternating organic insulating layers and inorganic insulating layers.

[0181] Although not shown in the accompanying drawings, in some embodiments, a planarization layer (not shown) may also be provided on the passivation layer PSV. The planarization layer can mitigate step differences caused by various components disposed beneath it. The planarization layer may include an organic insulating layer, but this disclosure is not limited thereto; the planarization layer may include an inorganic insulating layer.

[0182] Pixel PXLa may also include a partition wall PW disposed around unit pixels UPX1, UPX2, and UPX3. The partition wall PW may be configured to surround unit pixels UPX1, UPX2, and UPX3. The partition wall PW may be disposed on the pixel circuit layer PCL, but this disclosure is not limited thereto. The partition wall PW may be a pixel defining layer configured to define the emission region of pixel PXLa.

[0183] The partition wall (PW) may include at least one light-shielding material and / or reflective material, thus preventing light leakage defects that occur between adjacent pixels. Furthermore, during the process of aligning the light-emitting elements (LDs), the partition wall (PW) can prevent the solution including the LDs from leaking into adjacent pixels. The partition wall (PW) may be omitted depending on the process conditions of the display device.

[0184] According to the foregoing embodiment, the pixel PXLa of the display device may include a plurality of unit pixels UPX1, UPX2, and UPX3, and each of the unit pixels UPX1, UPX2, and UPX3 may include a first electrode RFE1 and a second electrode RFE2 provided to surround the first electrode RFE1. The light emitting elements LD disposed between the first electrode RFE1 and the second electrode RFE2 may be radially disposed (or arranged) around the first electrode RFE1. In this case, the light emitting elements LD of each of the unit pixels UPX1, UPX2, and UPX3 may be disposed (or arranged) so as not to be biased in a specific direction. Therefore, light emitted from each of the light emitting elements LD can be prevented from being concentrated in a specific direction. Accordingly, the amount (or intensity) of light emitted from the pixel PXLa can be substantially the same as or similar to the amount (or intensity) of light emitted from an adjacent pixel. Therefore, the display device according to the embodiment of the present disclosure can have a uniform emission distribution over the entire area thereof.

[0185] Figure 9 is a plan view of a unit pixel according to an embodiment. Figures 10 to 13 is a cross-sectional view of a unit pixel according to various embodiments, taken along Figure 9 the cross-section taken along line A2-A2'.

[0186] Figures 9 to 13 the embodiment shown in differs from the foregoing embodiment of Figures 5 to 8 in that the display element layer DPL further includes a first bank BNK1 and a second bank BNK2, and other components thereof are Figures 5 to 8 substantially the same as or similar to the components of the embodiment of. A detailed description of components that are the same as or similar to the components of the embodiment of Figures 5 to 8 (e.g., the pixel circuit layer PCL) will be omitted.

[0187] Referring to Figures 9 to 10 , the display element layer DPL of the first unit pixel UPX1a may include a first bank BNK1, a second bank BNK2, a first electrode RFE1, a second electrode RFE2, an insulating layer INSL, a light emitting element LD, a fixing layer INSA, a third electrode CTE1 and a fourth electrode CTE2, and a passivation layer PSV. In addition, a partition wall PW may be formed around the first unit pixel UPX1a.

[0188] The first dam BNK1 and the second dam BNK2 can be disposed on the pixel circuit layer PCL. The space where the light-emitting element LD is disposed can be located between the first dam BNK1 and the second dam BNK2. In an embodiment, the first dam BNK1 and the second dam BNK2 can be spaced apart from each other on the substrate SUB by a distance equal to or greater than the length of the light-emitting element LD. The first dam BNK1 and the second dam BNK2 can be disposed on the same layer and have the same height, but this disclosure is not limited thereto.

[0189] In the plan view, the first dam BNK1 can be stacked with the first electrode RFE1 and has an annular shape. The first dam BNK1 may not be stacked with the contact hole CTH, but this disclosure is not limited thereto.

[0190] The second dam BNK2 can be configured to surround the first dam BNK1. The second dam BNK2 can be formed in a shape substantially the same as the shape of the second electrode RFE2. For example, the second dam BNK2 can be formed in a rectangular shape in a plan view, and has an opening therein. The shape of the second dam BNK2 is not limited to this; the second dam BNK2 can be formed in an annular shape surrounding the first dam BNK1.

[0191] The first barrier BNK1 and the second barrier BNK2 may comprise an organic insulating layer formed of an organic material or an inorganic insulating layer formed of an inorganic material, but the materials of the first barrier BNK1 and the second barrier BNK2 are not limited thereto. Furthermore, both the first barrier BNK1 and the second barrier BNK2 may be formed from a single layer, but this disclosure is not limited thereto; the first barrier BNK1 and the second barrier BNK2 may be formed from multiple layers. In this case, both the first barrier BNK1 and the second barrier BNK2 may have a structure formed by stacking at least one organic insulating layer and at least one inorganic insulating layer.

[0192] The first dike BNK1 and the second dike BNK2 may have a trapezoidal shape in which their sidewalls are inclined at a predetermined angle, but the shape of the first dike BNK1 and the second dike BNK2 is not limited to this, and may have various shapes such as semi-elliptical shape, circular shape and rectangular shape.

[0193] The first electrode RFE1 and the second electrode RFE2 can be disposed on the first embankment BNK1 and the second embankment BNK2. In an embodiment, the first electrode RFE1 can be disposed on the first embankment BNK1, and the second electrode RFE2 can be disposed on the second embankment BNK2. In other words, the first electrode RFE1 and the second electrode RFE2 can be disposed on the same plane and have the same height. If the first electrode RFE1 and the second electrode RFE2 have the same height, the light-emitting element LD can be more reliably connected to each of the first electrode RFE1 and the second electrode RFE2.

[0194] The first electrode RFE1 and the second electrode RFE2 can be configured to have substantially uniform thickness along the surfaces of the first embankment BNK1 and the second embankment BNK2. The first electrode RFE1 and the second electrode RFE2 can be configured to have shapes corresponding to the shapes of the first embankment BNK1 and the second embankment BNK2. For example, the first electrode RFE1 can have a shape corresponding to the inclination of the first embankment BNK1, and the second electrode RFE2 can have a shape corresponding to the inclination of the second embankment BNK2.

[0195] As described above, the first electrode RFE1 and the second electrode RFE2 may comprise a conductive material with a constant reflectivity. When the first electrode RFE1 and the second electrode RFE2 have shapes corresponding to the shapes of the first dam BNK1 and the second dam BNK2, the first electrode RFE1 and the second electrode RFE2 may also have predetermined angles in the same manner as the first dam BNK1 and the second dam BNK2. Light emitted from opposite ends of each of the light-emitting elements LD can be reflected by the first electrode RFE1 and the second electrode RFE2, thus traveling more reliably on the third-direction DR3. Therefore, the light output efficiency of the display device can be improved.

[0196] An insulating layer INSL can be disposed on the first electrode RFE1 and the second electrode RFE2. The insulating layer INSL can be disposed on the entire surface of the pixel circuit layer PCL, covering the first barrier BNK1, the second barrier BNK2, and the first electrode RFE1 and the second electrode RFE2. Alternatively, the insulating layer INSL can be disposed along the surface of the pixel circuit layer PCL (or the substrate SUB) where the first barrier BNK1 and the second barrier BNK2, and the first electrode RFE1 and the second electrode RFE2 are not disposed.

[0197] In an embodiment, the insulating layer INSL may comprise an inorganic insulating layer formed of an inorganic material. In this case, the insulating layer INSL may be configured to have a uniform thickness along the surface of the pixel circuit layer PCL and the first electrode RFE1 and the second electrode RFE2. At least some space may be formed between the insulating layer INSL and the light-emitting element LD disposed on the insulating layer INSL.

[0198] The insulating layer INSL may include a first opening OP1 and a second opening OP2. The first opening OP1 and the second opening OP2 may expose at least corresponding portions of the first electrode RFE1 and the second electrode RFE2.

[0199] The first opening OP1 and the second opening OP2 can be formed to be superimposed on the corresponding first electrode RFE1 and second electrode RFE2, respectively. For example, the first opening OP1 can be superimposed on the first electrode RFE1. The second opening OP2 can be superimposed on the second electrode RFE2.

[0200] Both the first opening OP1 and the second opening OP2 can have a thickness and / or depth corresponding to the thickness of the insulating layer INSL. In other words, both the first opening OP1 and the second opening OP2 can completely penetrate the insulating layer INSL in their respective regions. Therefore, the first electrode RFE1 and the second electrode RFE2 can be exposed to the outside and thus contact the third electrode CTE1 and the fourth electrode CTE2.

[0201] The light-emitting element (LD) can be disposed on the insulating layer INSL. The LD can be stably disposed in the space defined by the first dike BNK1 and the second dike BNK2. The LD can be electrically connected to the first electrode RFE1 and the second electrode RFE2 through the third electrode CTE1 and the fourth electrode CTE2.

[0202] A fixing layer INSA can be disposed on each light-emitting element LD. As described above, the fixing layer INSA can cover at least a portion of the outer peripheral surface of each of the light-emitting elements LD, and is formed such that the first end EP1 and the second end EP2 of the light-emitting element LD are exposed. In the case where the fixing layer INSA comprises an organic insulating layer formed of an organic material, such as... Figure 10 As shown, the fixing layer INSA can be filled into the space between the light-emitting element LD and the insulating layer INSL and support the light-emitting element LD. On the other hand, when the fixing layer INSA includes an inorganic insulating layer formed of inorganic material, the void VD can be formed at least partially between the light-emitting element LD and the insulating layer INSL, as shown in the first unit pixel UPX1b. Figure 11 As shown in the figure. Although the void VD is formed by an air layer, this disclosure is not limited thereto.

[0203] As shown in the first unit pixel UPX1c Figure 12 As shown, when the insulating layer INSL' is uniformly formed in the area where the light-emitting element LD is disposed, no other material or component may be formed between the light-emitting element LD and the insulating layer INSL', and the light-emitting element LD may be directly disposed on the insulating layer INSL'.

[0204] Refer again Figure 10 The third electrode CTE1 and the fourth electrode CTE2 can be formed on the light-emitting element LD and the insulating layer INSL. The third electrode CTE1 can contact the first end EP1 of the light-emitting element LD and contact the first electrode RFE1 through the first opening OP1. In addition, the fourth electrode CTE2 can contact the second end EP2 of the light-emitting element LD and contact the second electrode RFE2 through the second opening OP2.

[0205] As described above, the third electrode CTE1 and the fourth electrode CTE2 can be disposed on the same layer, but in another embodiment, the third electrode CTE1 and the fourth electrode CTE2 can be disposed on different layers.

[0206] For example, as shown in the first unit pixel UPX1d Figure 13 As shown, the insulating pattern INSP can be disposed between the third electrode CTE1 and the fourth electrode CTE2.

[0207] The insulating pattern INSP may include an inorganic insulating layer formed of inorganic material. The insulating pattern INSP may be configured to cover one of the third electrode CTE1 and the fourth electrode CTE2, and the other electrode may be disposed on the insulating pattern INSP. For example, the insulating pattern INSP may be disposed on and cover the fourth electrode CTE2. The third electrode CTE1 may be disposed on the insulating pattern INSP. In other words, the third electrode CTE1 and the fourth electrode CTE2 can be electrically separated from each other through the insulating pattern INSP.

[0208] As described above, when a unit pixel includes a first wall BNK1 and a second wall BNK2, the light-emitting element LD is stably disposed in the space formed between the first wall BNK1 and the second wall BNK2, thereby improving the reliability of the display device and the yield of its manufacturing process. Furthermore, light emitted from the light-emitting element LD can be effectively emitted to the outside through the inclined sidewalls of the first wall BNK1 and the second wall BNK2, thereby improving the display quality and brightness of the display device.

[0209] Figure 14 It is a planar view of a unit pixel according to the embodiment. Figure 15 It is a cross-sectional view of a unit pixel according to an embodiment, and is along... Figure 14 The sectional view taken by line A3-A3'.

[0210] Figure 14 and Figure 15 The embodiments are the same as those described above. Figure 9 and Figure 10 The difference in the embodiment is that the second embankment BNK2' extends outward and partially overlaps with the partition wall PW, and their other components are... Figure 9 and Figure 10 The components of the embodiments are substantially the same or similar. Hereinafter, the focus will be on the differences from the foregoing embodiments.

[0211] Reference Figure 14 and Figure 15In the plan view, the first unit pixel UPX1e may include a second embankment BNK2' that extends further outward. Here, the term "outward" may refer to the direction from the first embankment BNK1 towards the second embankment BNK2'. Therefore, at least a portion of the second embankment BNK2' may be superimposed on the partition wall PW disposed in the peripheral portion of the first unit pixel UPX1e.

[0212] When a space is formed between the second bank BNK2' and the partition wall PW, during the process of setting (or arranging) the light-emitting element (LD), the LD may be positioned between the second bank BNK2' and the partition wall PW instead of between the first bank BNK1 and the second bank BNK2'. Because the driving current cannot be properly supplied to the LD, the LD positioned between the second bank BNK2' and the partition wall PW cannot emit light. With such a LD present, the display brightness of the display device will decrease.

[0213] As shown in this embodiment, when the second dam BNK2' extends further outward, the space between the second dam BNK2' and the partition wall PW is removed, thus preventing defects such as the light-emitting element LD being placed in an undesirable location. Therefore, since the number of light-emitting elements LD disposed between the first dam BNK1 and the second dam BNK2' can be increased, the display quality and display brightness of the display device can be improved.

[0214] In the following description, pixels and other embodiments of display devices including such pixels will be described. In the following embodiments, the same reference numerals are used to indicate components that are the same as or similar to those in the above embodiments, and their descriptions will be omitted or simplified, focusing on the differences.

[0215] Figure 16 It is a planar view of pixels according to the embodiment. Figure 17 It is a planar view of a unit pixel according to an embodiment, and is shown Figure 16 An enlarged planar view of region Q2. Figure 18 It is along Figure 17 The sectional view taken by line B1-B1'. Figure 19 It is along Figure 17 The sectional view taken by line B2-B2'. Figure 20 This is a cross-sectional view of a unit pixel according to an embodiment, and is related to... Figure 17 The sectional view corresponding to line B1-B1'.

[0216] Reference Figures 16 to 20 The display device according to the embodiment may include a substrate SUB and a pixel PXLb disposed on the substrate SUB.

[0217] Pixel PXLb may include multiple unit pixels UPX1_1, UPX2_1, and UPX3_1. For example, multiple unit pixels UPX1_1, UPX2_1, and UPX3_1 may include a first unit pixel UPX1_1, a second unit pixel UPX2_1, and a third unit pixel UPX3_1. The structures of the unit pixels UPX1_1, UPX2_1, and UPX3_1 included in pixel PXLb may be the same or similar to each other. Therefore, the following description will be based on the structure of the first unit pixel UPX1_1, and the description can also be applied to the second unit pixel UPX2_1 and the third unit pixel UPX3_1.

[0218] The first unit pixel UPX1_1 may include a pixel circuit layer PCL disposed on the substrate SUB and a display element layer DPL disposed on the pixel circuit layer PCL.

[0219] The display element layer (DPL) may include a first electrode RFE1_1, a second electrode RFE2_1, a light-emitting element (LD), a third electrode CTE1_1, and a fourth electrode CTE2_1.

[0220] In the plan view, the first electrode RFE1_1 and the second electrode RFE2_1 can be positioned at a distance from each other. The second electrode RFE2_1 can be configured to surround at least a portion of the first electrode RFE1_1.

[0221] In detail, the first electrode RFE1_1 may include a first center electrode RFE1A, a first peripheral electrode RFE1C, and a first connecting electrode RFE1B configured to connect the first center electrode RFE1A and the first peripheral electrode RFE1C to each other.

[0222] In the planar view, the first center electrode RFE1A can be disposed in the center portion of the first unit pixel UPX1_1 and formed into a circular shape. The first center electrode RFE1A can be disposed superimposed on the contact hole CTH.

[0223] The first peripheral electrode RFE1C can be configured to surround at least a portion of the first central electrode RFE1A. In a plan view, the first peripheral electrode RFE1C can be formed as an annular shape with an opening on one side. For example, the first peripheral electrode RFE1C typically has an annular shape with an opening based on the first central electrode RFE1A in a direction opposite to the first direction DR1. For example, the annular shape with an opening on one side can be a Corbino disk shape or a Landolt ring shape. However, the shape of the first peripheral electrode RFE1C is not limited to this, and there can be two or more opening regions.

[0224] The first connecting electrode RFE1B can be an electrode configured to connect the first center electrode RFE1A and the first peripheral electrode RFE1C to each other. The first connecting electrode RFE1B can extend in a first direction DR1 and is positioned based on the first center electrode RFE1A in the first direction DR1. In other words, the location forming the first connecting electrode RFE1B can be opposite to the opening region of the first peripheral electrode RFE1C. However, the location and shape of the first connecting electrode RFE1B are not limited to this. For example, the first connecting electrode RFE1B can extend in a second direction DR2 between the first center electrode RFE1A and the first peripheral electrode RFE1C. Furthermore, the first connecting electrode RFE1B can have a curved or serrated shape instead of a linear shape.

[0225] The second electrode RFE2_1 may include a second center electrode RFE2A, a second peripheral electrode RFE2C, and a second connecting electrode RFE2B configured to connect the second center electrode RFE2A and the second peripheral electrode RFE2C to each other.

[0226] The second center electrode RFE2A can typically have an annular shape and is configured to surround at least a portion of the first center electrode RFE1A. In a plan view, the second center electrode RFE2A may not overlap with the first connecting electrode RFE1B and has an opening region at the location where the first connecting electrode RFE1B is disposed. In other words, in a plan view, the second center electrode RFE2A can have an annular shape with an opening on one side.

[0227] The second peripheral electrode RFE2C can be configured to surround the first peripheral electrode RFE1C. In other words, the second peripheral electrode RFE2C can be configured to surround the first central electrode RFE1A and the second central electrode RFE2A.

[0228] The second connecting electrode RFE2B can be an electrode configured to connect the second central electrode RFE2A and the second peripheral electrode RFE2C to each other. The second connecting electrode RFE2B can be disposed in the opening region of the first peripheral electrode RFE1C. In other words, in a plan view, the second connecting electrode RFE2B can be spaced apart from the first peripheral electrode RFE1C. The second connecting electrode RFE2B can extend in the first direction DR1 in the same manner as the first connecting electrode RFE1B, but this disclosure is not limited thereto. For example, the second connecting electrode RFE2B can be formed in a region corresponding to the location of the opening region of the first peripheral electrode RFE1C. The second connecting electrode RFE2B can have various shapes, and can have a curved or serrated shape instead of a linear shape.

[0229] The light-emitting element (LD) can be disposed on the first electrode RFE1_1 and the second electrode RFE2_1. Specifically, the light-emitting element (LD) can be disposed between the first central electrode RFE1A and the second central electrode RFE2A, between the second central electrode RFE2A and the first peripheral electrode RFE1C, and between the first peripheral electrode RFE1C and the second peripheral electrode RFE2C. Furthermore, some light-emitting elements (LDs) can also be disposed between the first connecting electrode RFE1B and the second central electrode RFE2A, and between the second connecting electrode RFE2B and the first peripheral electrode RFE1C.

[0230] The light-emitting elements (LDs) can be radially arranged around the first central electrode RFE1A along the shape of the first electrode RFE1_1 and the second electrode RFE2_1. The distances between the light-emitting elements (LDs) can be different from each other, but this disclosure is not limited thereto.

[0231] The light-emitting element LD, positioned between the first electrode RFE1_1 and the second electrode RFE2_1, can emit light with a predetermined brightness corresponding to the driving current provided through the first electrode RFE1_1 and the second electrode RFE2_1.

[0232] The third electrode CTE1_1 and the fourth electrode CTE2_1 can be disposed above the first electrode RFE1_1, the second electrode RFE2_1, and the light-emitting element LD. The third electrode CTE1_1 and the fourth electrode CTE2_1 can be stacked on top of the first electrode RFE1_1 and the second electrode RFE2_1, and have a similar shape. In a planar view, the third electrode CTE1_1 and the fourth electrode CTE2_1 can be formed at positions spaced apart from each other.

[0233] For example, the third electrode CTE1_1 may include a third center electrode CTE1A, a third connecting electrode CTE1B, and a third peripheral electrode CTE1C. The fourth electrode CTE2_1 may include a fourth center electrode CTE2A, a fourth connecting electrode CTE2B, and a fourth peripheral electrode CTE2C.

[0234] The third center electrode CTE1A, the third connecting electrode CTE1B, and the third peripheral electrode CTE1C of the third electrode CTE1_1 can be configured to be superimposed on the first center electrode RFE1A, the first peripheral electrode RFE1C, and the first connecting electrode RFE1B of the first electrode RFE1_1, respectively, and have a similar shape. Furthermore, the fourth center electrode CTE2A, the fourth connecting electrode CTE2B, and the fourth peripheral electrode CTE2C of the fourth electrode CTE2_1 can be configured to be superimposed on the second center electrode RFE2A, the second peripheral electrode RFE2C, and the second connecting electrode RFE2B of the second electrode RFE2_1, respectively, and have a similar shape.

[0235] The third electrode CTE1_1 can contact the first end EP1 of the light-emitting element LD and the first electrode RFE1_1, and the fourth electrode CTE2_1 can contact the second end EP2 of the light-emitting element LD and the second electrode RFE2_1, so that the driving current provided from the first electrode RFE1_1 and the second electrode RFE2_1 can be transmitted to the light-emitting element LD.

[0236] The first unit pixel UPX1_1 may further include a first barrier BNK1_1 disposed between the first electrode RFE1_1 and the pixel circuit layer PCL, and a second barrier BNK2_1 disposed between the second electrode RFE2_1 and the pixel circuit layer PCL.

[0237] The first dam BNK1_1 and the second dam BNK2_1 can be positioned at a distance spaced apart from each other. The first dam BNK1_1 and the second dam BNK2_1 can be spaced apart by a distance equal to or greater than the length of the light-emitting element LD, in order to provide space in which the light-emitting element LD can be placed. The first dam BNK1_1 and the second dam BNK2_1 can be covered by the first electrode RFE1_1 and the second electrode RFE2_1, and have similar planar shapes.

[0238] However, the shapes of the first dam BNK1_1 and the second dam BNK2_1 are not limited to those described above. For example, as shown in the diagram of the first unit pixel UPX1_1a... Figure 20 As shown, the second dam BNK2_1a, which is formed to be stacked with the second peripheral electrode RFE2C, can extend further outward. Therefore, at least a portion of the second dam BNK2_1a can be stacked with the partition wall PW. (Refer to the above...) Figure 20 In the case where the second embankment BNK2_1a is formed to be stacked with the partition wall PW, defects in which the light-emitting element LD is abnormally set during the manufacturing process of the display device can be prevented, and the display quality and brightness of the display device can be improved.

[0239] According to the foregoing embodiments, the pixel PXLb of the display device may include a plurality of unit pixels UPX1_1, UPX2_1, and UPX3_1, and each of the unit pixels UPX1_1, UPX2_1, and UPX3_1 may include a first electrode RFE1_1 and a second electrode RFE2_1. Here, the first electrode RFE1_1 may include a first center electrode RFE1A, a first peripheral electrode RFE1C, and a first connecting electrode RFE1B. The second electrode RFE2_1 may include a second center electrode RFE2A, a second peripheral electrode RFE2C, and a second connecting electrode RFE2B. The second center electrode RFE2A may surround at least a portion of the first center electrode RFE1A. The first peripheral electrode RFE1C may surround at least a portion of the second center electrode RFE2A. The second peripheral electrode RFE2C may surround at least a portion of the first peripheral electrode RFE1C. Due to the foregoing structure, the area of ​​the space in which the light-emitting element LD is effectively disposed between the first electrode RFE1_1 and the second electrode RFE2_1 can be increased, and the number of light-emitting elements LD disposed in each unit pixel can be increased. Therefore, the display brightness of the display device can be improved.

[0240] Furthermore, the light-emitting element LD disposed between the first electrode RFE1_1 and the second electrode RFE2_1 can be radially arranged based on the first center electrode RFE1A. In other words, it is possible to prevent the light-emitting elements LD from being set (or arranged) to be biased in a specific direction. Therefore, it is possible to prevent the light emitted from each of the light-emitting elements LD from being concentrated in a specific direction. Therefore, the amount (or intensity) of light emitted from pixel PXLb can be substantially the same or similar to the amount (or intensity) of light emitted from adjacent pixels. Therefore, the display device according to the embodiments of this disclosure can have a uniform emission distribution throughout its entire area.

[0241] Figure 21 It is a planar view of pixels according to the embodiment. Figure 22 It is a planar view of a unit pixel according to an embodiment, and is shown Figure 21 An enlarged plan view of region Q3. Figure 23 It is along Figure 22 The sectional view taken by line C1-C1'. Figure 24 It is along Figure 22 The sectional view taken by line C2-C2'. Figure 25 This is a cross-sectional view of a unit pixel according to an embodiment, and is related to... Figure 22 The sectional view corresponding to line C2-C2'.

[0242] Reference Figures 21 to 25 The display device according to the embodiment may include a substrate SUB and a pixel PXLc disposed on the substrate SUB.

[0243] Pixel PXLc may include multiple unit pixels UPX1_2, UPX2_2, UPX3_2, and UPX4_2. For example, the multiple unit pixels UPX1_2, UPX2_2, UPX3_2, and UPX4_2 may include a first unit pixel UPX1_2, a second unit pixel UPX2_2, a third unit pixel UPX3_2, and a fourth unit pixel UPX4_2. The structures of the unit pixels UPX1_2, UPX2_2, UPX3_2, and UPX4_2 included in pixel PXLc may be the same or similar to each other. Therefore, the following description will be based on the structure of the first unit pixel UPX1_2, and the description can also be applied to the second unit pixel UPX2_2, the third unit pixel UPX3_2, and the fourth unit pixel UPX4_2.

[0244] The first unit pixel UPX1_2 may include a pixel circuit layer PCL disposed on the substrate SUB and a display element layer DPL disposed on the pixel circuit layer PCL.

[0245] The display element layer (DPL) may include a first electrode RFE1_2, a second electrode RFE2_2, a light-emitting element (LD), a third electrode CTE1_2, and a fourth electrode CTE2_2.

[0246] In the plan view, the first electrode RFE1_2 and the second electrode RFE2_2 can be positioned at intervals from each other. Furthermore, both the first electrode RFE1_2 and the second electrode RFE2_2 can have a spiral shape that winds (or extends) clockwise or counterclockwise while moving away from the center point CP. The first electrode RFE1_2 and the second electrode RFE2_2 can be wound in the same direction.

[0247] Specifically, the first electrode RFE1_2 may include a first spiral electrode RFE1_2A and a first connecting electrode RFE1_2B.

[0248] The first helical electrode RFE1_2A can have a helical shape that winds counterclockwise while moving away from the center point CP.

[0249] The first connecting electrode RFE1_2B may be an electrode configured to connect the first helical electrode RFE1_2A and the first connecting line CNL1 to each other, and may be a linear electrode extending in the first direction DR1.

[0250] The first connection line CNL1 can be connected to the second bridge connection BRE2 and the first transistor M1 disposed on the pixel circuit layer PCL through the contact hole CTH_2. The first connection line CNL1 can be supplied with driving current from the first transistor M1, and the supplied driving current is provided to the respective first electrodes RFE1_2 of unit pixels UPX1_2, UPX2_2, and UPX3_2. In other words, the respective first electrodes RFE1_2 of unit pixels UPX1_2, UPX2_2, and UPX3_2 can be connected to each other through the first connection line CNL1 and are supplied with the same driving current.

[0251] The second electrode RFE2_2 may include a second spiral electrode RFE2_2A and a second connecting electrode RFE2_2B.

[0252] The second helical electrode RFE2_2A can have a helical shape that winds counterclockwise in the same manner as the first helical electrode RFE1_2A while moving away from the center point CP. In this case, the second helical electrode RFE2_2A can be spaced apart from the first helical electrode RFE1_2A, and the first and second helical electrodes RFE1_2A can form a helical shape in which the first and second helical electrodes RFE1_2A engage and wind around each other. For example, the second helical electrode RFE2_2A can be point-symmetric to the first helical electrode RFE1_2A based on the center point CP, but this disclosure is not limited thereto.

[0253] The second connecting electrode RFE2_2B can be an electrode configured to connect the second spiral electrode RFE2_2A and the second connecting line CNL2 to each other. The second connecting line CNL2 can extend in the second direction DR2 and is supplied with a voltage of the second driving power supply through a contact hole formed outside the pixel PXLc or a separate connector. Figure 3a (VSS). However, this disclosure is not limited thereto, and voltage can be supplied to it via contact holes formed inside the pixel PXLc or a separate connector.

[0254] Insulating layer INSL_2 can be disposed on the first electrode RFE1_2 and the second electrode RFE2_2. Opening ( Figure 10 OP1 and OP2 can be formed in the insulating layer INSL_2 to expose at least a portion of the first electrode RFE1_2 and the second electrode RFE2_2. The openings in the insulating layer INSL_2 can also be formed in a spiral shape corresponding to the openings of the first electrode RFE1_2 and the second electrode RFE2_2.

[0255] The light-emitting element LD can be disposed on the insulating layer INSL_2. The light-emitting element LD can be formed between the first electrode RFE1_2 and the second electrode RFE2_2, and is arranged in a shape corresponding to the spiral shape of the first electrode RFE1_2 and the second electrode RFE2_2. The light-emitting element LD can be disposed generally radially around the center point CP, but this disclosure is not limited thereto.

[0256] The fixing layer INSA_2 can be disposed on the light-emitting element LD. The fixing layer INSA_2 can also be formed in a shape corresponding to the spiral shape between the first electrode RFE1_2 and the second electrode RFE2_2. The fixing layer INSA_2 can be disposed along the area where the light-emitting element LD is disposed and fix the light-emitting element LD, so that the light-emitting element LD can be stably disposed on the first electrode RFE1_2 and the second electrode RFE2_2.

[0257] The third electrode CTE1_2 and the fourth electrode CTE2_2 can be disposed above the first electrode RFE1_2, the second electrode RFE2_2, and the light-emitting element LD. The third electrode CTE1_2 and the fourth electrode CTE2_2 can be stacked with the first electrode RFE1_2 and the second electrode RFE2_2, and have a similar shape. In other words, the third electrode CTE1_2 and the fourth electrode CTE2_2 can both have a spiral shape wound counterclockwise. Furthermore, in a planar view, the third electrode CTE1_2 and the fourth electrode CTE2_2 can be formed at positions spaced apart from each other.

[0258] The third electrode CTE1_2 can contact the first end EP1 and the first electrode RFE1_2 of the light-emitting element LD, and the fourth electrode CTE2_2 can contact the second end EP2 and the second electrode RFE2_2 of the light-emitting element LD, so that the driving current provided from the first electrode RFE1_2 and the second electrode RFE2_2 can be transmitted to the light-emitting element LD.

[0259] The first unit pixel UPX1_2 may also include a first barrier BNK1_2 disposed between the first electrode RFE1_2 and the pixel circuit layer PCL, and a second barrier BNK2_2 disposed between the second electrode RFE2_2 and the pixel circuit layer PCL.

[0260] The first dam BNK1_2 and the second dam BNK2_2 can be positioned at a distance spaced apart from each other. The first dam BNK1_2 and the second dam BNK2_2 can be spaced apart from each other by a distance equal to or greater than the length of the light-emitting element LD, in order to provide space in which the light-emitting element LD can be disposed. The first dam BNK1_2 and the second dam BNK2_2 can be covered by the first electrode RFE1_2 and the second electrode RFE2_2, and have a planar shape similar to the shape of the first electrode RFE1_2 and the second electrode RFE2_2.

[0261] However, the shapes of the first dam BNK1_2 and the second dam BNK2_2 are not limited to those described above. For example, as shown in the diagram of the first unit pixel UPX1_2a... Figure 25 As shown, at least a portion of the first dam BNK1_2 and the second dam BNK2_2 can extend further outward. Here, the area where the dams extend can be a region between the first dam BNK1_2 and the second dam BNK2_2 where no light-emitting element LD is disposed. In other words, the portions of the first dam BNK1_2 and the second dam BNK2_2 disposed in the periphery of the first unit pixel UPX1_2a can extend outward.

[0262] For example, such as Figure 24 As shown, the width WBNK of the first embankment BNK1_2 can be smaller than the width WRFE of the first electrode RFE1_2. Optionally, as... Figure 25 As shown, the first dam BNK1_2 may extend outward (or in a direction opposite to the fifth direction DR5). The first electrode RFE1_2a and the insulating layer INSL_2a may cover at least a portion of the extended first dam BNK1_2. In other words, the width WBNKa of the first dam BNK1_2 may be greater than the width WRFE of the first electrode RFE1_2a.

[0263] With the first dike BNK1_2 and the second dike BNK2_2 extending outward, defects in which the light-emitting element LD is abnormally set during the manufacturing process of the display device can be prevented, and the display quality and brightness of the display device can be improved.

[0264] like Figure 21 and Figure 22 As shown, the winding directions of the electrodes of adjacent unit pixels can be different from each other. For example, the first electrode RFE1_2 and the second electrode RFE2_2 of the first unit pixel UPX1_2 can both have a spiral shape that winds counterclockwise while moving away from the center point CP. On the other hand, the first electrode RFE1_2 and the second electrode RFE2_2 of the second unit pixel UPX2_2 adjacent to the first unit pixel UPX1_2 can both have a spiral shape that winds clockwise while moving away from the center point CP.

[0265] The first electrode RFE1_2 and the second electrode RFE2_2 of the first unit pixel UPX1_2 can be symmetrical with the first electrode RFE1_2 and the second electrode RFE2_2 of the second unit pixel UPX2_2 based on the symmetry line SML. Therefore, the second electrode RFE2_2 of the first unit pixel UPX1_2 can face the second electrode RFE2_2 of the second unit pixel UPX2_2.

[0266] For example, when the first electrode RFE1_2 and the second electrode RFE2_2 of the first unit pixel UPX1_2 are wound in the same direction as the first electrode RFE1_2 and the second electrode RFE2_2 of the second unit pixel UPX2_2, the different electrodes can face each other. For example, the second electrode RFE2_2 of the first unit pixel UPX1_2 and the first electrode RFE1_2 of the second unit pixel UPX2_2 can face each other.

[0267] During the arrangement (or placement) of light-emitting elements (LDs), the polarities of the arrangement voltages applied to different electrodes can be different. Due to the electric field formed between the second electrode RFE2_2 of the first unit pixel UPX1_2 and the first electrode RFE1_2 of the second unit pixel UPX2_2, some LDs are placed between the first unit pixel UPX1_2 and the second unit pixel UPX2_2. In this case, the LDs placed between the first unit pixel UPX1_2 and the second unit pixel UPX2_2 cannot be properly supplied with driving current and therefore cannot emit light. As the number of such LDs increases, the display quality and brightness of the display device deteriorate.

[0268] Therefore, in this embodiment, the electrodes of adjacent unit pixels can be wound in different directions, such that the same polarity among unit pixels UPX1_2, UPX2_2, UPX3_2, and UPX4_2 faces each other. This prevents the light-emitting elements (LDs) from being abnormally aligned (or positioned) during the process of arranging (or setting) the LDs. Consequently, the display quality and brightness of the display device can be improved.

[0269] According to the foregoing embodiments, the pixel PXLc of the display device may include a plurality of unit pixels UPX1_2, UPX2_2, UPX3_2, and UPX4_2, and each of the unit pixels UPX1_2, UPX2_2, UPX3_2, and UPX4_2 may include a first electrode RFE1_2 and a second electrode RFE2_2. Here, both the first electrode RFE1_2 and the second electrode RFE2_2 may have a spiral shape that winds (or extends) in a clockwise or counterclockwise direction while moving away from the center point CP. Due to the structure in which the first electrode RFE1_2 and the second electrode RFE2_2 are joined and wound around each other, the area of ​​the space in which the light-emitting element LD is effectively disposed between the first electrode RFE1_2 and the second electrode RFE2_2 can be increased, and the number of light-emitting elements LD disposed in each of the unit pixels can be increased. Therefore, the display brightness of the display device can be improved.

[0270] Furthermore, the light-emitting elements LD disposed between the first electrode RFE1_2 and the second electrode RFE2_2 can be arranged radially based on the center point CP. In other words, it is possible to prevent the light-emitting elements LD from being set (or arranged) to be biased in a specific direction. Therefore, it is possible to prevent the light emitted from each of the light-emitting elements LD from being concentrated in a specific direction. Therefore, the amount (or intensity) of light emitted from pixel PXLc can be substantially the same or similar to the amount (or intensity) of light emitted from adjacent pixels. Therefore, the display device according to the embodiments of this disclosure can have a uniform emission distribution throughout its entire area.

[0271] It is possible to prevent the light-emitting elements (LDs) from being configured (or arranged) to be biased in a specific direction. Therefore, it is possible to prevent light emitted from each of the light-emitting elements (LDs) from being concentrated in a specific direction. Thus, the amount (or intensity) of each of unit pixels UPX1, UPX2, and UPX3 can be substantially the same or similar to the amount (or intensity) of light emitted from adjacent pixels. Therefore, the display device according to embodiments of this disclosure can have a uniform emission distribution throughout its entire area.

[0272] Although embodiments of this disclosure have been disclosed, those skilled in the art will understand that this disclosure may be implemented in other specific forms without departing from the scope and spirit of this disclosure as disclosed in the appended claims. Therefore, it should be understood that exemplary embodiments are for illustrative purposes only and do not limit the scope of this disclosure.

Claims

1. A display device, the display device comprising: Base; as well as Multiple unit pixels are disposed on the substrate. Each of the plurality of unit pixels includes: First electrode; The second electrode is spaced apart from the first electrode and surrounds the periphery of the first electrode; A light-emitting element is disposed between the first electrode and the second electrode, and each includes a first end and a second end; A third electrode is stacked on top of the first electrode and the first end of the light-emitting element, and contacts the first electrode and the first end of the light-emitting element; and The fourth electrode is stacked on top of the second electrode and the second end of the light-emitting element, and contacts the second electrode and the second end of the light-emitting element. The light-emitting elements are radially arranged around the first electrode. The display device further includes: an insulating layer disposed on the first electrode and the second electrode, wherein the insulating layer includes: a first opening formed to expose at least a portion of the first electrode; and a second opening formed to expose at least a portion of the second electrode, wherein the third electrode contacts the first electrode through the first opening, and wherein the fourth electrode contacts the second electrode through the second opening; and The display device further includes: a fixing layer disposed on the insulating layer and the light-emitting elements, wherein the fixing layer contacts at least a portion of the outer peripheral surface of each of the light-emitting elements and allows exposure of the first end and the second end, wherein the fixing layer comprises an inorganic material and voids are formed at least partially between the light-emitting elements and the insulating layer.

2. The display device according to claim 1, wherein, The first electrode includes: The first central electrode is formed in a circular shape in the plan view; A first peripheral electrode, surrounding at least a portion of the first central electrode; and The first connecting electrode connects the first center electrode and the first peripheral electrode to each other.

3. The display device according to claim 2, wherein, The second electrode includes: The second center electrode surrounds at least a portion of the first center electrode; The second peripheral electrode surrounds at least a portion of the second central electrode; and The second connecting electrode connects the second center electrode and the second peripheral electrode to each other.

4. The display device according to claim 3, wherein, In the plan view, the second central electrode is formed as an annular shape with an opening on at least one side.

5. The display device according to claim 3, wherein, In the plan view, the first peripheral electrode surrounds at least a portion of the second central electrode and is formed as an annular shape with an opening on at least one side.

6. The display device according to claim 3, wherein, The second peripheral electrode is disposed outside the first peripheral electrode.

7. The display device according to claim 3, wherein, The light-emitting element is disposed in at least one of the regions between the first central electrode and the second central electrode, between the second central electrode and the first peripheral electrode, and between the first peripheral electrode and the second peripheral electrode.

8. The display device according to claim 1, wherein, Each of the plurality of unit pixels also includes: A first dam is disposed between the substrate and the first electrode; and A second dam is disposed between the substrate and the second electrode. The light-emitting element is disposed between the first dike and the second dike.

9. The display device according to claim 8, further comprising: A partition wall surrounds at least some of the plurality of unit pixels and is disposed on the insulating layer. At least a portion of the second dike overlaps with the partition wall.

10. The display device according to claim 1, wherein, The fourth electrode is spaced apart from the third electrode and is configured to surround the periphery of the third electrode.

11. The display device according to claim 10, further comprising: An insulating pattern is disposed between the third electrode and the fourth electrode. The insulating pattern is disposed on one of the third electrode and the fourth electrode, and The remaining one of the third electrode and the fourth electrode is disposed on the insulating pattern.

12. The display device according to claim 1, further comprising: A driving transistor is disposed between the substrate and the plurality of unit pixels and is electrically connected to the light-emitting element. The driving transistor includes: A semiconductor pattern is disposed on the substrate; A gate electrode is disposed on the semiconductor pattern; and The first transistor electrode and the second transistor electrode are disposed on the gate electrode. The semiconductor pattern includes: a first region contacting the first transistor electrode; a second region spaced apart from the first region and contacting the second transistor electrode; and a channel region disposed between the first region and the second region. Wherein, the first transistor electrode is electrically connected to a first bridge wire disposed on a layer different from the first transistor electrode, and The first bridging wire is electrically connected to one of the first electrode and the second electrode.

13. The display device according to claim 12, wherein, The first bridging wire contacts the first electrode through a contact hole that overlaps with the first electrode.

14. The display device according to claim 12, in, The first transistor electrode is electrically connected to a second bridge wire disposed on the same layer as the first transistor electrode. Wherein, the second bridge wire is electrically connected to the first electrode, and The first bridging wire is electrically connected to the second electrode.

15. A display device, the display device comprising: Base; as well as Multiple unit pixels are disposed on the substrate. Each of the plurality of unit pixels includes: The first electrode, in a planar view, has a spiral shape that winds clockwise or counterclockwise while moving away from the center point; The second electrode, in the plan view, has a spiral shape that winds in the same direction as the first electrode while moving away from the center point, and is spaced apart from the first electrode; A light-emitting element is disposed between the first electrode and the second electrode, wherein each light-emitting element includes a first end and a second end; The third electrode is stacked on top of the first end of the light-emitting element and the first electrode, and contacts the first electrode and the first end of the light-emitting element; and The fourth electrode is stacked on top of and in contact with the second end of the light-emitting element and the second electrode, and is spaced apart from the third electrode. The display device further includes: an insulating layer disposed on the first electrode and the second electrode, wherein the insulating layer includes: a first opening formed to expose at least a portion of the first electrode; and a second opening formed to expose at least a portion of the second electrode, wherein the third electrode contacts the first electrode through the first opening, and wherein the fourth electrode contacts the second electrode through the second opening; and The display device further includes: a fixing layer disposed on the insulating layer and the light-emitting elements, wherein the fixing layer contacts at least a portion of the outer peripheral surface of each of the light-emitting elements and allows exposure of the first end and the second end, wherein the fixing layer comprises an inorganic material and voids are formed at least partially between the light-emitting elements and the insulating layer.

16. The display device according to claim 15, in, The plurality of unit pixels includes a first unit pixel and a second unit pixel adjacent to the first unit pixel. Wherein, the direction in which the first electrode and the second electrode of the first unit pixel are wound is different from the direction in which the first electrode and the second electrode of the second unit pixel are wound.

17. The display device according to claim 15, wherein, The light-emitting elements are arranged radially around the center point.

18. The display device according to claim 15, wherein, In the plan view, both the third electrode and the fourth electrode have a spiral shape that winds in the same direction as the first electrode and the second electrode while moving away from the center point.

19. The display device according to claim 15, wherein, Each of the plurality of unit pixels includes: A first dam is disposed between the substrate and the first electrode; and A second dam is disposed between the substrate and the second electrode. The light-emitting element is disposed between the first dike and the second dike.

20. The display device according to claim 19, wherein, In the plan view, both the first and second dikes have a spiral shape that winds in the same direction as the first and second electrodes while moving away from the center point.

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