Semiconductor device

Abstract

This invention provides a semiconductor device having a gate trench and a dummy trench adjacent to the gate trench. The semiconductor device may include: a drift region of a first conductivity type disposed on a semiconductor substrate; a base region of a second conductivity type disposed above the drift region; an emitter region of the first conductivity type disposed above the base region, and having a higher doping concentration than the drift region; and a contact region of the second conductivity type disposed above the base region, and having a higher doping concentration than the base region. In the mesa section between the gate trench and the dummy trench, the contact region may be disposed below the lower end of the emitter region on the side adjacent to the dummy trench.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Patent document 1 describes "improving characteristics such as saturation current in semiconductor devices".

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-195798

[0006] Patent Document 2: International Publication No. 2018 / 052098 Summary of the Invention

[0007] Technical issues

[0008] A semiconductor device is provided to improve latch-up tolerance during switching.

[0009] Technical solution

[0010] In a first aspect of the present invention, a semiconductor device is provided having a gate trench portion and a first trench portion adjacent to the gate trench portion. The semiconductor device may include: a drift region of a first conductivity type disposed on a semiconductor substrate; a base region of a second conductivity type disposed above the drift region; an emitter region of the first conductivity type disposed above the base region, and having a higher doping concentration than the drift region; and a contact region of the second conductivity type disposed above the base region, and having a higher doping concentration than the base region. In the mesa section between the gate trench portion and the first trench portion, the contact region may be disposed below the lower end of the emitter region.

[0011] The contact area can contact the first groove portion.

[0012] On the face of the gate, the contact area can be separated from the gate trench.

[0013] In the trench arrangement direction, the contact area can be separated from the gate trench by more than 0.6 μm.

[0014] The contact area can be disposed on the front side of the semiconductor substrate on the sidewall of the first trench.

[0015] The semiconductor device may include an interlayer insulating film disposed above a semiconductor substrate. The emitter region may be electrically connected to the emitter via a contact hole that penetrates the interlayer insulating film.

[0016] The emitter region can extend from the gate trench portion across the contact hole and toward the first trench portion side in the trench arrangement direction.

[0017] A semiconductor device may have an accumulation region of a first conductivity type between the drift region and the base region, where the doping concentration is higher than that of the drift region.

[0018] A semiconductor device may have multiple gate trenches and multiple first trenches. The ratio of the number of gate trenches to the number of first trenches may be 1:1.

[0019] A semiconductor device may have multiple gate trenches and multiple first trenches. The ratio of the number of gate trenches to the number of first trenches may be 1:2.

[0020] The emitter region can extend from the gate trench portion to the first trench portion in the trench arrangement direction. The emitter region may terminate before reaching the first trench portion.

[0021] The emitter region can extend from the gate trench portion to the first trench portion in the trench arrangement direction.

[0022] The contact area and the emitter area can be configured to alternately contact the front side of the semiconductor device relative to the trench extension direction of the gate trench portion.

[0023] The first trench portion can be set as the emitter potential.

[0024] The first trench portion can be set to the gate potential.

[0025] The first trench portion can be a dummy trench. The emitter region can be located on the mesa portion, in contact with the gate trench portion, and separated from the first trench portion. The contact region can be located on the mesa portion, below the lower end of the emitter region on the side closest to the first trench portion.

[0026] The first trench portion may include a dummy gate trench portion that is set to the gate potential and does not contact the emitter region.

[0027] The first trench portion may include a dummy trench portion set to the emitter potential.

[0028] The emitter region may have a first emitter region, which is in contact with the gate trench portion on the mesa portion and is separated from the first trench portion.

[0029] The contact area can be located on the lower end of the first launch area near the first groove portion on the platform surface.

[0030] The emitter region may also have a second emitter region, which is in contact with the first trench portion on the mesa portion and is separated from the gate trench portion.

[0031] The contact area can also be located on the lower end of the second emitter region near the gate trench portion on the platform surface.

[0032] In the trench extension direction of the gate trench portion, the first emitter region and the second emitter region can be alternately arranged.

[0033] It should be noted that the above description of the invention does not list all the essential features of the invention. Furthermore, sub-combinations of these feature groups can also constitute separate inventions. Attached Figure Description

[0034] Figure 1A A top view of the semiconductor device 100 is shown.

[0035] Figure 1B yes Figure 1A An example of the a-a' section diagram.

[0036] Figure 1C yes Figure 1A An example of a b-b' section diagram.

[0037] Figure 2 An example of an enlarged cross-sectional view of the platform surface 71 is shown.

[0038] Figure 3 An example of a top view of a semiconductor device 100 with an unopened portion having a contact hole 54 is shown.

[0039] Figure 4A An example of simulation results showing the static characteristics of semiconductor device 100 is presented.

[0040] Figure 4B An example of simulation results showing the conduction characteristics of semiconductor device 100 is presented.

[0041] Figure 4C An example of simulation results showing the turn-off characteristics of semiconductor device 100 is presented.

[0042] Figure 5A An example of a top view of a semiconductor device 100 is shown.

[0043] Figure 5B yes Figure 5A An example of a c-c' cross-sectional view.

[0044] Figure 6A An example of a top view of a semiconductor device 100 is shown.

[0045] Figure 6B yes Figure 6A An example of a d-d' section diagram.

[0046] Figure 7A An example of a top view of a semiconductor device 100 as a variant is shown.

[0047] Figure 7B yes Figure 7AAn example of the e-e' section diagram.

[0048] Figure 8A An example of a top view of a semiconductor device 100 is shown.

[0049] Figure 8B yes Figure 8A An example of the f-f' section diagram.

[0050] Figure 9A An example of a top view of a semiconductor device 100 is shown.

[0051] Figure 9B yes Figure 9A An example of a g-g' cross-sectional diagram.

[0052] Figure 10A An example of a top view of a semiconductor device 100 is shown.

[0053] Figure 10B yes Figure 10A An example of an h-h' cross-sectional diagram.

[0054] Figure 10C yes Figure 10A Other examples of h-h' cross-sectional diagrams.

[0055] Figure 11A An example of a top view of a semiconductor device 100 is shown.

[0056] Figure 11B yes Figure 11A An example of the i-i' section diagram.

[0057] Figure 12A An example of a top view of a semiconductor device 100 is shown.

[0058] Figure 12B yes Figure 12A An example of a j-j' section diagram.

[0059] Figure 13A An example of a top view of a semiconductor device 100 is shown.

[0060] Figure 13B yes Figure 13A An example of a k-k' section diagram.

[0061] Symbol Explanation

[0062] 10. Semiconductor substrate; 12. Emitter region; 13. Bottom end; 14. Base region; 15. Contact region; 16. Accumulation region; 17. Well region; 18. Drift region; 19. Trench bottom region; 20. Buffer zone; 21. Front side; 22. Collector region; 23. Back side; 24. Collector; 25. Connector; 30. Dummy trench; 31. Extension; 32. Dummy insulating film; 33. Connector; 34. Dummy conductive part; 38. Interlayer insulating film; 40. Gate trench; 41. Extension; 42. Gate insulating film; 43. ··Connection portion, 44···Gate conductive portion, 50···Gate metal layer, 52···Emitter, 54···Contact hole, 55···Contact hole, 56···Contact hole, 58···Contact hole, 59···Non-connection area, 60···Contact trench portion, 62···Plug, 64···Barrier metal layer, 70···Transistor portion, 71···Mesa portion, 80···Diode portion, 81···Mesa portion, 82···Cathode region, 92···Surface region, 94···Lower region, 100···Semiconductor device, 130···Dummy gate trench portion, 132···Second gate insulating film, 134···Second gate conductive portion Detailed Implementation

[0063] The present invention will now be described through embodiments thereof, but these embodiments do not limit the scope of the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the technical solution of the invention.

[0064] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper" and the other side as "lower". Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the front surface and the other as the back surface. The directions of "upper", "lower", "front", and "back" are not limited to the direction of gravity or the actual mounting direction towards the substrate, etc., when the semiconductor device is mounted.

[0065] In this specification, orthogonal coordinate axes of X, Y, and Z are sometimes used to explain technical matters. In this specification, the surface parallel to the front side of the semiconductor substrate is designated as the XY plane, and the direction forming a right-hand rule with the X and Y axes and parallel to the depth direction of the semiconductor substrate is designated as the Z axis.

[0066] In various embodiments, examples are shown where the first conductivity type is N-type and the second conductivity type is P-type; however, it is also possible to set the first conductivity type to P-type and the second conductivity type to N-type. In this case, the conductivity types of the substrate, layer, region, etc., in each embodiment are opposite polarities.

[0067] In this specification, layers or regions prefixed with N or P indicate that electrons or holes are the majority carriers, respectively. Additionally, the + and - markings on N or P indicate that the impurity concentration is higher and lower than that of layers or regions not marked with + or -, respectively.

[0068] Figure 1A This example shows a top view of a semiconductor device 100. The semiconductor device 100 in this example is a semiconductor chip including a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a trench-gate RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) with a plurality of trench sections arranged thereon. In this example, the plurality of trench sections are arranged along the X-axis and extend along the Y-axis.

[0069] Transistor section 70 is in Figure 1B The collector region 22, which is disposed on the back side of the semiconductor substrate 10 and described later, is the area obtained by projecting it onto the upper surface of the semiconductor substrate 10. The collector region 22 has a second conductivity type. As an example, the collector region 22 in this example is P+ type. The transistor section 70 includes transistors such as IGBTs.

[0070] Diode 80 is in Figure 1B The cathode region 82, which is disposed on the back side of the semiconductor substrate 10 and described later, is the area obtained by projecting it onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. As an example, the cathode region 82 in this example is N+ type. The diode section 80 includes a diode such as a freewheeling diode disposed adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0071] exist Figure 1A The diagram shows the area surrounding the chip end, which is the edge side of the semiconductor device 100; other areas are omitted. For example, in this example, an edge termination structure is provided in the region on the negative side of the Y-axis direction in the semiconductor device 100. The edge termination structure alleviates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure may include, for example, a protective ring, a field plate, a surface electric field reducing element, and a structure combining these. It should be noted that although the edge on the negative side of the Y-axis direction is described in this example for convenience, the same applies to the other edges of the semiconductor device 100.

[0072] The semiconductor substrate 10 can be a silicon substrate, a silicon carbide substrate, or a gallium nitride or other nitride semiconductor substrate. In this example, the semiconductor substrate 10 is a silicon substrate.

[0073] In this example, the semiconductor device 100 has a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front side of the semiconductor substrate 10. In addition, the semiconductor device 100 in this example has an emitter 52 and a gate metal layer 50 disposed on the upper part of the front side of the semiconductor substrate 10.

[0074] The emitter 52 is disposed above the trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. Additionally, the gate metal layer 50 is disposed above the gate trench portion 40 and the well region 17.

[0075] The emitter 52 and the gate metal layer 50 are formed of a metal-containing material. For example, at least a portion of the emitter 52 is formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may also be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter 52 and the gate metal layer 50 may have a barrier metal formed of titanium or a titanium compound beneath the regions formed of aluminum or the like. The emitter 52 and the gate metal layer 50 are disposed separately from each other.

[0076] The emitter 52 and the gate metal layer 50 are disposed above the semiconductor substrate 10, separated by an interlayer insulating film 38. The interlayer insulating film 38... Figure 1A The middle part is omitted. Contact holes 54, 55 and 56 are provided through the interlayer insulating film 38.

[0077] The contact hole 55 connects the gate metal layer 50 to the gate conductive portion within the gate trench portion 40 of the transistor portion 70. A plug made of tungsten or the like may also be formed inside the contact hole 55.

[0078] The contact hole 56 connects the emitter 52 to the dummy conductive part within the dummy trench portion 30. A plug made of tungsten or the like may also be formed inside the contact hole 56.

[0079] The connection portion 25 electrically connects the front-side electrode, such as the emitter 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is disposed between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also disposed between the emitter 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. Here, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is disposed on the upper surface of the front side of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0080] The gate trench portions 40 are arranged at predetermined intervals along a predetermined trench arrangement direction (the X-axis direction in this example). As an example, the gate trench portions 40 are arranged with a trench interval of 1.5 μm, but the trench interval is not limited to this interval. The gate trench portions 40 in this example may have two extension portions 41 extending along a trench extension direction (the Y-axis direction in this example) that is parallel to the front side of the semiconductor substrate 10 and perpendicular to the trench arrangement direction, and a connecting portion 43 that connects the two extension portions 41.

[0081] The connection portion 43 is preferably at least partially formed in a curved shape. By connecting the ends of the two extension portions 41 in the gate trench portion 40, the electric field concentration at the ends of the extension portions 41 can be alleviated. In the connection portion 43 of the gate trench portion 40, the gate metal layer 50 can be connected to the gate conductive portion.

[0082] In this example, the dummy trench portion 30 is electrically connected to the emitter 52 and is set to the emitter potential. The dummy trench portion 30, like the gate trench portion 40, is arranged at predetermined intervals along a predetermined trench arrangement direction (the X-axis direction in this example). For example, the dummy trench portions 30 are arranged with a trench interval of 1.5 μm, but the trench interval is not limited to this interval. Specifically, the trench interval of the dummy trench portion 30 can be set to be different from the trench interval of the gate trench portion 40. In this example, the dummy trench portion 30, like the gate trench portion 40, has a U-shape on the front side of the semiconductor substrate 10. That is, the dummy trench portion 30 can have two extension portions 31 extending along the trench extension direction, and a connecting portion 33 connecting the two extension portions 31. The dummy trench portion 30 can also be set to a floating potential. The dummy trench portion 30 is an example of a first trench portion adjacent to the gate trench portion 40.

[0083] The transistor section 70 in this example has a structure in which two gate trench sections 40 having a connection portion 43 and two dummy trench sections 30 without a connection portion are repeatedly arranged. That is, the arrangement ratio of the gate trench sections 40 and the dummy trench sections 30 can be set to a predetermined desired arrangement ratio. In the transistor section 70 of this example, the ratio of the number of gate trench sections 40 to the number of dummy trench sections 30 is 1:1. The transistor section 70 of this example has dummy trench sections 30 between two extension sections 41 connected by the connection portion 43. It should be noted that the number of gate trench sections 40 can be the same as the number of extension sections 41. The number of dummy trench sections 30 can be the same as the number of extension sections 31.

[0084] The ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio can be 2:3 or 2:4. By increasing the number of dummy trench portions 30 relative to the gate trench portion 40, the electric field concentration at the mesa 71 can be alleviated, and the voltage and current tolerance of the semiconductor device 100 can be increased. Furthermore, by adjusting the ratio of the gate trench portion 40 to the dummy trench portion 30, the gate capacitance used to drive the semiconductor device 100 can be adjusted. If the dummy trench portion 30 is increased relative to the gate trench portion 40, the gate capacitance increases, and the saturation current decreases. Alternatively, a so-called all-gate structure can be constructed where the transistor portion 70 is entirely composed of gate trench portions 40 and no dummy trench portions 30 are provided. It should be noted that the ratio of the gate trench portion 40 to the dummy trench portion 30 disclosed in this specification can be rewritten as the ratio of the gate trench portion 40 to the dummy trench portion. Dummy trenches, such as dummy trench portion 30 or dummy gate trench portion 130 described later, include trenches in which no channels are formed on the sidewalls.

[0085] Well region 17 is a region of the second conductivity type disposed on the front side of the semiconductor substrate 10, which is closer to the drift region 18 described later. Well region 17 is an example of a well region disposed on the edge side of the semiconductor device 100. As an example, well region 17 is P+ type. Well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is disposed. The diffusion depth of well region 17 can be deeper than the depth of gate trench portion 40 and dummy trench portion 30. A portion of the gate trench portion 40 and dummy trench portion 30 on the side near the gate metal layer 50 is formed in well region 17. The bottom of the end of the trench extension direction of gate trench portion 40 and dummy trench portion 30 can be covered by well region 17.

[0086] In the transistor section 70, contact holes 54 are formed above the emitter region 12 and the contact region 15. The emitter region 12 and the contact region 15 are exposed within the contact holes 54. The contact holes 54 are not positioned above the well region 17, which is located at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 can be provided extending along the trench extension direction.

[0087] Mesa-face 71 and mesa-face 81 are mesa-faces disposed adjacent to the trench portions in a plane parallel to the front surface of the semiconductor substrate 10. A mesa-face refers to the portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and can extend from the front surface of the semiconductor substrate 10 to the deepest bottom of each trench portion. An extension portion of each trench portion can be defined as a single trench portion. That is, the area sandwiched between two extension portions can be defined as a mesa-face.

[0088] In the transistor section 70, the mesa section 71 is disposed adjacent to at least one of the dummy trench section 30 or the gate trench section 40. The mesa section 71 has a well region 17, an emitter region 12, a base region 14 and a contact region 15 on the front side of the semiconductor substrate 10.

[0089] On the other hand, in the diode section 80, the mesa portion 81 and the dummy trench portion 30 are provided adjacent to each other. The trench portion in the mesa portion 81 can be electrically connected to the emitter 52 through the contact hole 56 and is set to the emitter potential. That is, the trench portion provided in the diode section 80 can be the dummy trench portion 30.

[0090] The mesa 81 has a well region 17 and a base region 14 on the front side of the semiconductor substrate 10. It should be noted that an emitter 52 is also disposed on the upper surface of the mesa 81. That is, the metal layer of the emitter 52 can function as the anode in the diode section 80.

[0091] The base region 14 is a region of a second conductivity type disposed on the front side of the semiconductor substrate 10 in the transistor section 70. As an example, the base region 14 is P-type. The base region 14 can be disposed at both ends of the mesa 71 in the Y-axis direction on the front side 21 of the semiconductor substrate 10. It should be noted that... Figure 1A Only one end of the base region 14 in the Y-axis direction is shown.

[0092] Emitter region 12 is the doping concentration ratio Figure 1B The drift region 18, described later, is a region of the first conductivity type with a high doping concentration. As an example, the emitter region 12 in this example is N+ type. For example, the dopant of the emitter region 12 is phosphorus (P) or arsenic (As). The emitter region 12 is disposed on the front side of the mesa 71, in contact with the gate trench portion 40. The emitter region 12 can be configured to extend along the X-axis from one of the two trench portions of the mesa 71 to the other. The emitter region 12 is also disposed below the contact hole 54.

[0093] The emission region 12 may extend to and contact the dummy trench 30. Alternatively, the emission region 12 may terminate before reaching the dummy trench 30, thus avoiding contact with it. In this example, the emission region 12 does not contact the dummy trench 30.

[0094] Contact region 15 is a region of the second conductivity type with a higher doping concentration than the base region 14. As an example, contact region 15 in this example is P+ type. An example of the dopant in contact region 15 is boron (B). In this example, contact region 15 is disposed on the front side 21 of the mesa 71. Contact region 15 can be disposed from one of the two trench portions of the mesa 71 along the X-axis to the other. Specifically, contact region 15 may separate from the gate trench portion 40 below the emitter region 12 at the portion where the emitter region 12 contacts the gate trench portion 40.

[0095] Contact area 15 may or may not contact the gate trench portion 40. Additionally, contact area 15 may or may not contact the dummy trench portion 30. In this example, contact area 15 contacts both the dummy trench portion 30 and the gate trench portion 40. Contact area 15 is also located below contact hole 54. It should be noted that contact area 15 may also be located on mesa portion 81.

[0096] Figure 1B yes Figure 1A This is an example of an a-a' cross-sectional view. The a-a' cross-section extends from the transistor section 70 to the diode section 80, passing through the XZ plane of the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter 52, and a collector 24 in the a-a' cross-section. The emitter 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0097] Drift region 18 is a region of a first conductivity type disposed on semiconductor substrate 10. As an example, drift region 18 in this example is N-type. Drift region 18 can be a region remaining in semiconductor substrate 10 where no other doped regions have been formed. That is, the doping concentration of drift region 18 can be the doping concentration of semiconductor substrate 10.

[0098] Buffer 20 is a region of the first conductivity type disposed below drift region 18. As an example, buffer 20 in this example is N-type. The doping concentration of buffer 20 is higher than that of drift region 18. Buffer 20 can function as a field cutoff layer to prevent the depletion layer extending from the lower surface side of base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0099] In the transistor section 70, the collector region 22 is disposed below the buffer zone 20. The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal.

[0100] The base region 14 is a second conductivity type region disposed above the drift region 18 in the mesa 71 and mesa 81. The base region 14 is disposed in contact with the gate trench portion 40. The base region 14 may be disposed in contact with the dummy trench portion 30.

[0101] In the mesa 71, the emitter region 12 is disposed between the base region 14 and the front surface 21. The emitter region 12 is disposed in contact with the gate trench portion 40. The emitter region 12 may or may not contact the dummy trench portion 30.

[0102] One or more gate trench portions 40 and one or more dummy trench portions 30 are disposed on the front side 21. Each trench portion extends from the front side 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, and contact region 15 is disposed, each trench portion also extends through these regions to reach the drift region 18. The trench portion extending through the doped region is not limited to the order in which the trench portion is formed after the doped region is formed. The case where the doped region is formed between the trench portions after the trench portion is formed is also included in the case where the trench portion extends through the doped region.

[0103] The gate trench portion 40 has a gate trench formed on the front side 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed by covering the inner wall of the gate trench. The gate insulating film 42 can be formed by semiconductor oxidation or nitriding of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench at a position further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front side 21 by an interlayer insulating film 38. The potential of the gate electrode such as an IGBT is applied to the gate conductive portion 44.

[0104] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that is separated by a gate insulating film 42 and faces the base region 14 adjacent to the mesa 71 side. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in the base region 14 that contacts the gate trench.

[0105] The dummy trench portion 30 can have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front side 21. The dummy insulating film 32 is formed by covering the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed at a position further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front side 21 by an interlayer insulating film 38. The potential of the emitter, such as that of an IGBT, is applied to the dummy conductive portion 34. The dummy conductive portion 34 can also be configured as a floating potential.

[0106] An interlayer insulating film 38 is disposed on the front side 21. An emitter 52 is disposed above the interlayer insulating film 38. One or more contact holes 54 are provided on the interlayer insulating film 38 for electrically connecting the emitter 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be disposed through the interlayer insulating film 38.

[0107] The lower end 13 is the lower end of the launch area 12 in the platform 71 on the side near the dummy groove 30. When the launch area 12 reaches the dummy groove 30, the lower end 13 contacts the dummy groove 30.

[0108] At least a portion of the contact area 15 is disposed below the lower end 13 on the platform surface 71. That is, the contact area 15 is disposed deeper than the emitter area 12 and is disposed to partially overlap with the emitter area 12. In this example, the contact area 15 is disposed such that it extends from the dummy trench portion 30 to below the lower end 13 of the emitter area 12 in the trench arrangement direction. As a result, holes below the emitter area 12 are difficult to be directly extracted through the emitter area 12, and hole current is easily extracted from the contact area 15. As a result, the NPNP type parasitic thyristor from the emitter area 12 to the collector area 22 becomes difficult to conduct, and latch-up of the semiconductor device 100 can be suppressed.

[0109] In the cross-section of this example, the contact region 15 is separated from the gate trench portion 40 at the mesa 71. As a result, the contact region 15 does not hinder the formation of the inversion layer on the side of the gate trench portion 40, and the semiconductor device 100 operates stably.

[0110] In this example, the contact area 15 is provided so as to span both sides of the dummy trench portion 30 in the X-axis direction. In the manufacturing process of the contact area 15 in this example, a photoresist can be provided on the semiconductor substrate 10, and the contact area 15 can be provided by ion implantation, which spans the area where the trench portion is provided. The dummy trench portion 30 can be provided by etching the semiconductor substrate 10 after the contact area 15 is provided.

[0111] In recent years, for the purpose of miniaturizing semiconductor devices 100, so-called process pitch reduction, which shortens the spacing of mesa 71, has been carried out. For example, when a diffusion region is provided on a silicon semiconductor substrate 10 by ion implantation, dopants tend to diffuse within a certain range. With the structure of the contact region 15 in this example, even when the process pitch has been miniaturized, it is easy to manufacture a contact region 15 that extends below the lower end 13 of the emitter region 12 and is separated from the gate trench portion 40. As a result, it does not have a significant impact on electrical characteristics, and a semiconductor device 100 with high latch-up resistance can be provided. The contact region 15 can achieve the effect of suppressing latch-up as long as it is provided in a manner connected in the trench extension direction, and is not limited to the way the contact region 15 contacts the dummy trench portion 30.

[0112] In the diode section 80, a buffer zone 20 is deposited above the cathode region 82, and a drift region 18 is deposited above the buffer zone 20. In the mesa section 81, a base region 14 is deposited above the drift region 18, and a PN junction is formed between the base region 14 and the drift region 18. The base region 14 is electrically connected to the emitter 52 via a contact hole 54.

[0113] Figure 1C yes Figure 1A This is an example of a b-b' cross-sectional view. The b-b' cross-section is the XZ plane in the transistor section 70 that does not pass through the emitter region 12. In this example, the mesa 71 in the transistor section 70 has a base region 14 and a contact region 15 above the drift region 18. In the diode section 80, the mesa 81 has the same... Figure 1B The examples in the text have the same structure.

[0114] The contact region 15 extends from the gate trench portion 40 to the dummy trench portion 30. A contact hole 54 is provided above the contact region 15. Holes are extracted from the contact region 15 through the contact hole 54.

[0115] In this example, when the contact area 15 in the cross-section and the contact area 15 located below the emission area 12 are configured using the same process, the depths of these contact areas 15 are the same. In this case, the contact area 15 is deeper than the emission area 12. Alternatively, the contact area 15 may be located below the emission area 12 and in other areas at different depths.

[0116] Figure 2 An example of an enlarged cross-sectional view of the mesa 71 is shown. In this example, the XZ plane passing through the emitter region 12 in the transistor section 70 is shown.

[0117] The emitter region 12 extends from the gate trench portion 40, across the contact hole 54, and into the dummy trench portion 30 in the trench arrangement direction. This facilitates current conduction from the emitter region 12 through the contact hole 54, resulting in improved electrical characteristics of the semiconductor device 100. In this example, the emitter region 12 extends from the gate trench portion 40 into the dummy trench portion 30 in the trench arrangement direction, but terminates before reaching the dummy trench portion 30. Alternatively, the emitter region 12 may be configured to extend from the gate trench portion 40 to the dummy trench portion 30 in the trench arrangement direction.

[0118] The contact area 15 is disposed on the sidewall of the dummy trench portion 30 on the front surface 21 of the semiconductor substrate 10. The contact area 15 includes a surface area 92 and a lower area 94.

[0119] Surface region 92 is a region in the semiconductor substrate 10 having the same depth as emitter region 12. For example, the depth of surface region 92 is 0.5 μm. However, the depth of surface region 92 can also be set to different depths. When emitter region 12 extends from gate trench portion 40 to dummy trench portion 30 and reaches dummy trench portion 30, surface region 92 is not provided at the cross-section exposed on the front side 21 of semiconductor substrate 10 by emitter region 12. Furthermore, the impurity concentration of surface region 92 can be in the range of 5E19 / cm3 or higher and 2E20 / cm3 or lower.

[0120] The lower region 94 is disposed in the semiconductor substrate 10 in a region deeper than the emitter region 12. The lower region 94 extends beyond the lower end 13 of the emitter region 12, which extends from the gate trench portion 40 to the dummy trench portion 30, and extends toward the gate trench portion 40. In addition, the impurity concentration of the lower region 94 can be in the range of 1E19 / cm3 or more and 1E20 / cm3 or less.

[0121] The width Wc is the width of the contact area 15 in the trench arrangement direction. The width Wc is measured from the center of the dummy trench portion 30 to the lower end of the emitter region 12 on the dummy trench portion 30 side. That is, the width Wc corresponds to the maximum reach position of the lower region 94 on the gate trench portion 40 side, measured from the center of the dummy trench portion 30. The width Wc can be 1.2 μm or less, or 1.1 μm or less. Here, the width of the surface region 92 in the trench arrangement direction can be in the range of 15% or more and 40% or less relative to the distance between adjacent trenches. The width of the lower region 94 in the trench arrangement direction can be in the range of 30% or more and 70% or less relative to the distance between adjacent trenches. Furthermore, the width of the portion of the lower region 94 overlapping with the emitter region 12 in the trench arrangement direction can be in the range of 0% or more and 30% or less relative to the distance between adjacent trenches, more preferably in the range of 10% or more and 20% or less.

[0122] Thickness Dc is the thickness of the contact region 15 in the depth direction of the semiconductor substrate 10. Thickness Dc is thicker than the depth of the lower end 13 of the emitter region 12 and less than the depth of the base region 14. For example, thickness Dc is 0.5 μm or more and 2.0 μm or less. The thickness of the surface region 92 can be in the range of 0.3 μm or more and 0.8 μm or less. Furthermore, the thickness of the lower region 94 can be in the range of 0.3 μm or more and 1.1 μm or less.

[0123] The width Ws is the distance between the contact area 15 and the gate trench portion 40 in the trench arrangement direction. The width Ws can be set in such a way that a channel can be formed at the end of the gate trench portion 40. That is, the width Ws is equivalent to the spacing distance between the contact area 15 and the gate trench portion 40. In one example, the width Ws is 0.6 μm or more. Furthermore, the width Ws in the trench arrangement direction relative to the distance between adjacent trenches can be in the range of 30% or more and 70% or less.

[0124] Figure 3 An example of a top view of a semiconductor device 100 with an unopened portion having a contact hole 54 is shown. Figure 3 This is an example of an enlarged view of the upper surface of the semiconductor device 100.

[0125] The non-connection region 59 is the area on the front side 21 where the emitter 52 is not electrically connected to the contact region 15. For example, the non-connection region 59 is an unopened area on the interlayer insulating film 38 where contact holes 54 are not formed due to poor oxide film etching caused by particles or foreign matter. Alternatively, the non-connection region 59 may be an area on the front side 21 where contact regions 15 are not formed due to resist residues, etc.

[0126] In this example, the hole current that should be extracted in the non-connection region 59 flows through the contact region 15 and is extracted via the contact hole 54 above other adjacent contact regions 15. That is, since the hole current does not flow through the base region 14 below the emitter region 12, but flows through the contact region 15, which has a lower resistance than the base region 14 relative to holes, latch-up can be suppressed. Thus, switching failure caused by process defects is suppressed. Therefore, a semiconductor device 100 with a device structure that has strong redundancy against process defects is provided.

[0127] Figure 4AAn example of simulation results for the static characteristics of semiconductor device 100 is shown. This example illustrates the change in static characteristics relative to the width Wc of the contact region 15. Specifically, this example shows a case where the width of the mesa 71 between the dummy trench 30 and the gate trench 40 is 1.5 μm. It should be noted that, to illustrate the qualitative properties in the simulation results, the vertical axis values ​​in this example are scaled to a value normalized to 1, corresponding to an initial value of Wc = 0 for the contact region width. The units of each normalized value can be appropriate units with dimensions corresponding to the respective physical quantities.

[0128] The diagram illustrates the relationships between the collector-emitter saturation voltage Vce and the width Wc when the semiconductor device 100 is driven, the collector-emitter saturation current and the width Wc when the semiconductor device 100 is driven, and the threshold voltage Vth of the semiconductor device 100 and the width Wc. When the width Wc is 1.2 μm or less, the influence of the contact region 15 on the channel formation of the base region 14 is small. Therefore, when the width Wc is within this range, the influence on all these static characteristic values ​​can be kept within a small range.

[0129] Figure 4B An example of simulation results showing the conduction characteristics of semiconductor device 100 is presented. This example shows the variation of the conduction characteristics with respect to the width Wc of contact region 15. It should be noted that the vertical axis values ​​in this example have been scaled to normalized values.

[0130] The diagram shows the relationship between the maximum time-varying value of the collector-emitter voltage Vce (Normalized) and Wc when the semiconductor device 100 is driven, the relationship between the maximum time-varying value of the collector-emitter current di (Normalized) and Wc when the semiconductor device 100 is driven, and the relationship between the conduction loss Eon (Normalized) of the semiconductor device 100 and Wc. When the width Wc is 1.2 μm or less, the influence of the contact region 15 on the channel formation of the base region 14 is small. Therefore, when the width Wc is within this range, the influence on all these conduction characteristic values ​​can be kept within a small range.

[0131] Figure 4C An example of simulation results for the turn-off characteristics of semiconductor device 100 is shown. This example illustrates the change in turn-off characteristics relative to the width Wc of contact region 15. It should be noted that the vertical axis values ​​in this example are calibrated to normalized values.

[0132] The diagram shows the relationship between the maximum time-varying value of the collector-emitter voltage Vce (Normalized) and Wc when the semiconductor device 100 is driven, the relationship between the maximum time-varying value of the collector-emitter current di (Normalized) and Wc when the semiconductor device 100 is driven, and the relationship between the turn-off loss Eoff (Normalized) of the semiconductor device 100 and Wc. When the width Wc is less than 1.2 μm, the influence of the contact region 15 on the channel formation of the base region 14 is small. Therefore, when the width Wc is within this range, the influence on all these turn-off characteristic values ​​can be kept within a small range.

[0133] like Figure 4B and Figure 4C The simulation results show that the semiconductor device 100 in this example, through the structure of the contact region 15, does not affect the dynamic electrical characteristics. Therefore, as Figures 4A to 4C The simulation results show that the semiconductor device 100 in this example does not significantly affect the electrical characteristics in either static or dynamic aspects. The semiconductor device 100 in this example improves latch-up tolerance without altering the electrical characteristics.

[0134] Figure 5A An example top view of a semiconductor device 100 is shown. In this example, with... Figure 1A The difference lies in that the launch area 12 is positioned in contact with the dummy groove portion 30. In this example, for... Figure 1A Different points will be explained in detail.

[0135] In this example, the emitter region 12 extends from the gate trench portion 40 to the dummy trench portion 30 in the trench arrangement direction. The emitter region 12 and the contact region 15 are configured to alternately contact each gate trench portion 40 and dummy trench portion 30 on the front side 21 of the semiconductor substrate 10, relative to the trench extension direction.

[0136] Figure 5B yes Figure 5A An example of a c-c' cross-sectional view. The c-c' cross-section extends from the transistor section 70 to the diode section 80, passing through the XZ plane of the emitter region 12 in the transistor section 70. It should be noted that the XZ cross-section extending from the transistor section 70 to the diode section 80, passing through the contact region 15 in the transistor section 70, is... Figure 1C same.

[0137] In this example, the surface area 92 of the contact area 15 is not provided in the c-c' section. In this example, the contact area 15 has a relationship with the lower region 94. Figure 1BThe example uses the same structure. That is, at least a portion of the contact area 15 is disposed in the platform 71 below the lower end 13. As a result, holes below the emitter area 12 are difficult to be directly extracted through the emitter area 12, and hole current can be extracted from the contact area 15 to suppress latch-up.

[0138] Figure 6A An example of a top view of a semiconductor device 100 is shown. In this example, the ratio of the number of gate trench portions 40 to the number of dummy trench portions 30 is 1:2. The semiconductor device 100 in this example can improve its tolerance to defects by increasing the ratio of dummy trench portions 30.

[0139] In this example, on the transistor portion 70 on the front side of the semiconductor substrate 10, there are U-shaped gate trench portions 40 and two I-shaped dummy trench portions 30 arranged together. The structures of the gate trench portions 40 and dummy trench portions 30 are not limited to this, as long as the arrangement ratio of the gate trench portions 40 to the dummy trench portions 30 can be maintained at 1:2. As an example, the dummy trench portions 30 may also have a U-shaped structure, and the area within the dummy trench portions may also be a floating region.

[0140] Figure 6B yes Figure 6A An example of a d-d' cross-sectional view. The d-d' cross-section extends from the transistor section 70 to the diode section 80, passing through the XZ plane of the emitter region 12 in the transistor section 70.

[0141] The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter 52, and a collector 24 in the d-d' cross section. The emitter 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38. In addition, the semiconductor device 100 of this example has an accumulation region 16 between the drift region 18 and the base region 14.

[0142] The accumulation region 16 is a first conductivity type region disposed between the base region 14 and the drift region 18. As an example, the accumulation region 16 in this example is N+ type. The accumulation region 16 is disposed in the transistor section 70 and the diode section 80. As a result, the semiconductor device 100 can avoid mask shift of the accumulation region 16.

[0143] Additionally, the accumulation region 16 is disposed in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than that of the drift region 18. The ion implantation dose of the accumulation region 16 can be 1E12cm⁻¹. -2 Above and 1E13cm -2 The following. Additionally, the ion implantation dose in accumulation region 16 can be 3E12cm. -2 Above and 6E12cm -2The following describes how, by setting the accumulation region 16, the carrier injection enhancement effect can be improved, and the turn-on voltage of the transistor section 70 can be reduced. It should be noted that E refers to a power of 10, for example, 1E12cm. -2 It refers to 1×10 12 cm -2 .

[0144] In this example, the contact area 15 is also located below the emitter area 12, and adjacent contact areas 15 are electrically connected to each other. Regardless of whether there is an accumulation area 16 and the arrangement ratio of the gate trench portion 40 and the dummy trench portion 30, the semiconductor device 100 can use the structure of the contact area 15 to suppress latch-up.

[0145] Figure 7A An example of a top view of a semiconductor device 100 as a variation is shown. In this example, particular attention is paid to... Figure 1A The differences will be explained below. In this example, the semiconductor device 100 has a dummy gate trench portion 130 that does not contact the emitter region 12 instead of the dummy trench portion 30. The dummy gate trench portion 130 is an example of a first trench portion adjacent to the gate trench portion 40.

[0146] The dummy gate trench 130 is a trench portion set to the gate potential and not in contact with the emitter region 12. That is, the dummy gate trench 130 is a trench portion that, although set to the gate potential, does not drive transistors in the adjacent mesa 71, and is an example of a dummy trench portion different from the dummy trench 30. To set the dummy gate trench 130 to the gate potential, the dummy gate trench 130 extends along the Y-axis to the region where the gate metal layer 50 is disposed. The dummy gate trench 130 is connected to the gate metal layer 50 via a contact hole 58 and is set to the gate potential.

[0147] Although the dummy gate trench 130 is set to the gate potential, it does not contact the emitter region 12. Therefore, no channel formed by the inversion layer of the first conductivity type is formed on the sidewall of the dummy gate trench 130. Since the dummy gate trench 130 easily attracts charge carriers to the mesa 71, its properties differ from those of the gate capacitor, etc. Therefore, by combining the dummy gate trench 130 and the dummy trench 30, it is possible to adjust the threshold voltage, saturation current, electric field concentration, and gate capacitance in the semiconductor device 100.

[0148] On the front side of the semiconductor substrate 10, the gate trench portion 40 in this example has a U-shaped structure, and the dummy gate trench portion 130 has an I-shaped structure. The structures of the gate trench portion 40 and the dummy gate trench portion 130 are not limited to these structures as long as the desired alignment ratio can be achieved.

[0149] In this example, the dummy gate trench portion 130 in the diode portion 80 and Figure 1A The structure is the same. That is, the dummy gate trench portion 130 is connected to the emitter 52 via the contact hole 56 and is set to the emitter potential.

[0150] Figure 7B yes Figure 7A An example of an e-e' cross-sectional view. The e-e' cross-section extends from the transistor section 70 to the diode section 80, passing through the XZ plane of the emitter region 12 in the transistor section 70. The dummy gate trench section 130 has a second gate insulating film 132 and a second gate conductive section 134.

[0151] In this example, in addition to the dummy gate trench portion 130 of the semiconductor device 100 having an emitter potential, it also has a potential related to... Figure 1B The configuration is the same as the cross-sectional view in this example. That is, in this example, the contact region 15 is also below the emitter region 12, and adjacent contact regions 15 are electrically connected to each other. Therefore, regardless of the potential of the dummy gate trench, the semiconductor device 100 can use the structure of the contact region 15 to suppress latch-up.

[0152] Figure 8A An example of a top view of a semiconductor device 100 is shown. In this example, the semiconductor device 100 includes a contact trench portion 60.

[0153] The contact trench portion 60 is provided extending from the front side 21 into the depth direction of the semiconductor substrate 10. The contact trench portion 60 electrically connects the emitter 52 to the semiconductor substrate 10. The contact trench portion 60 is provided extending along the trench extension direction. In this example, the contact trench portion 60 is configured in a stripe shape along the gate trench portion 40 and the dummy trench portion 30.

[0154] Contact trench portions 60 are formed in transistor portions 70 above the emitter region 12 and contact region 15. Contact trench portions 60 are formed in diode portions 80 above the base region 14. Contact trench portions 60 are not disposed above the well region 17, which is located at both ends in the Y-axis direction. One or more contact trench portions 60 may extend along the trench extension direction.

[0155] In the mesa 71 between the gate trench portion 40 and the contact trench portion 60, the emitter region 12 and the contact region 15 can be alternately arranged along the trench extension direction. In the trench extension direction, the width of the emitter region 12 can be greater than the width of the contact region 15. The width of the emitter region 12 in the trench extension direction can be 0.6 μm or more and 1.6 μm or less. By appropriately controlling the ratio of the emitter region 12 to the contact region 15, latch-up can be easily suppressed.

[0156] Figure 8B yes Figure 8A An example of the f-f' cross-sectional view. In this example, the contact groove 60 is formed to be shallower than the emission region 12.

[0157] The contact trench 60 extends from the front side 21 toward the back side 23 of the semiconductor substrate 10. In this example, the lower end of the contact trench 60 is shallower than the lower end of the emitter region 12. Emitter regions 12 are provided at both ends of the contact trench 60 in the trench arrangement direction. The contact trench 60 has a plug 62 and a blocking metal layer 64.

[0158] The plug 62 is a conductive material disposed inside the contact groove 60. The plug 62 can be the same material as the emitter 52, or it can be a different material. The plug 62 can include materials such as tungsten.

[0159] A barrier metal layer 64 is disposed below the plug 62. In this example, the barrier metal layer 64 is disposed between the plug 62 and the emission region 12. The barrier metal layer 64 may contain materials such as titanium nitride.

[0160] The emitter region 12 is disposed in contact with the gate trench portion 40. The emitter region 12 may or may not contact the dummy trench portion 30. In this example, the emitter region 12 is disposed such that it extends further toward the dummy trench portion 30 than the contact trench portion 60 in the trench arrangement direction. That is, the lower end 13 is disposed between the dummy trench portion 30 and the contact trench portion 60 in the trench arrangement direction.

[0161] At least a portion of the contact area 15 is disposed below the lower end 13 on the platform surface 71. In this example, the contact area 15 is disposed such that it extends from the dummy groove portion 30 to below the lower end 13 of the emission area 12 in the groove arrangement direction. The contact area 15 may extend beyond the contact groove portion 60 from the dummy groove portion 30 in the groove arrangement direction, or it may not extend beyond the contact groove portion 60. In this example, the contact area 15 is disposed between the dummy groove portion 30 and the contact groove portion 60 in the groove arrangement direction.

[0162] The trench bottom region 19 is a second conductivity type region disposed below the dummy trench portion 30 and the gate trench portion 40. In this example, the trench bottom region 19 covers the lower ends of the dummy trench portion 30 and the gate trench portion 40. The doping concentration of the trench bottom region 19 can be lower than the doping concentration of the base region 14. The trench bottom region 19 is disposed between the drift region 18a and the drift region 18b. The avalanche tolerance is improved by providing the trench bottom region 19. It should be noted that sometimes embodiments of the semiconductor device 100 having the trench bottom region 19 are described, but the trench bottom region 19 may also be omitted.

[0163] Drift region 18a is disposed in mesa 71 and mesa 81 between base region 14 and trench bottom region 19. Drift region 18b is disposed below trench bottom region 19. The doping concentration of drift region 18a and drift region 18b can be the same.

[0164] Figure 9A An example top view of a semiconductor device 100 is shown. In this example, the arrangement of the emitter region 12 and contact region 15 in the front side 21 of the semiconductor device 100 is similar to... Figure 8A The implementation methods differ. In this example, the specific implementation method is different from that of... Figure 8A The differences in implementation methods will be explained. In this example, compared to... Figure 8A The difference in the implementation method is that an emission area 12 is provided on one side of the contact groove portion 60.

[0165] The emitter region 12 is disposed in contact with the gate trench portion 40. The emitter region 12 is disposed such that it extends from the gate trench portion 40 to the sidewall of the contact trench portion 60 in the trench arrangement direction. The emitter region 12 may not be disposed between the dummy trench portion 30 and the contact trench portion 60.

[0166] Figure 9B yes Figure 9A An example of a g-g' cross-sectional view. In this example, the contact groove portion 60 is formed more... Figure 8B The contact groove portion 60 of the embodiment is deeper.

[0167] The contact trench 60 is provided such that it extends further toward the back surface 23 of the semiconductor substrate 10 than the emitter region 12. That is, in this example, the lower end of the contact trench 60 is deeper than the lower end of the emitter region 12. In this example, the lower end of the contact trench 60 is shallower than the lower end of the contact region 15.

[0168] The emitter region 12 is provided in such a way that it extends from the gate trench portion 40 to the sidewall of the contact trench portion 60 in the trench arrangement direction. Therefore, the lower end 13 is located between the gate trench portion 40 and the contact trench portion 60 in the trench arrangement direction and is located on the sidewall of the contact trench portion 60.

[0169] Figure 10A An example top view of a semiconductor device 100 is shown. The semiconductor device 100 in this example is... Figure 8A The difference in the implementation method is that it does not have a diode section 80.

[0170] Figure 10B yes Figure 10A An example of the h-h' cross-sectional view. In this example, the contact groove portion 60 is formed more... Figure 8B The contact groove portion 60 of the embodiment is deeper.

[0171] The contact trench portion 60 is provided such that it extends further toward the back surface 23 of the semiconductor substrate 10 than the emitter region 12. In this example, the lower end of the contact trench portion 60 is deeper than the lower end of the emitter region 12, but shallower than the lower end of the contact region 15. The emitter regions 12 are provided at both ends of the contact trench portion 60 in the trench arrangement direction.

[0172] The transmitting region 12 is provided to extend further toward the dummy groove portion 30 than the contact groove portion 60 in the groove arrangement direction. That is, the lower end 13 is provided between the dummy groove portion 30 and the contact groove portion 60 in the groove arrangement direction.

[0173] Figure 10C yes Figure 10A Other examples of the h-h' cross-sectional diagram. In this example, the depth of the contact groove 60 is... Figure 10B The implementation methods differ. In this example, the contact groove portion 60 is formed to be shallower than the emission region 12. That is, the lower end of the contact groove portion 60 in this example is shallower than the lower end of the emission region 12.

[0174] As described above, the depth of the contact trench portion 60 is not limited to the embodiment and can be appropriately modified. Furthermore, the emitter region 12 can be disposed at both ends in the trench arrangement direction of the contact trench portion 60, or it can be disposed on one side of the contact trench portion 60. Additionally, in each embodiment, the semiconductor device 100 may or may not include a trench bottom region 19.

[0175] Figure 11A An example of a top view of a semiconductor device 100 is shown. In this example, the semiconductor device 100 includes a dummy trench portion 30 disposed adjacent to the gate trench portion 40, and a dummy gate trench portion 130 disposed adjacent to the gate trench portion 40.

[0176] The dummy gate trench 130 is a trench portion that is set to the gate potential and does not contact the emitter region 12. In this example, the dummy gate trench 130 is connected to the extension portion 41 via the connecting portion 43.

[0177] The emitter region 12 is configured such that it is in contact with the gate trench 40 and separated from the dummy gate trench 130 on the mesa 71 between the gate trench 40 and the dummy gate trench 130.

[0178] In addition, the emitter region 12 is configured such that it is in contact with the gate trench 40 and separated from the dummy trench 30 at the mesa 71 between the gate trench 40 and the dummy trench 30.

[0179] Figure 11B yes Figure 11AThis is an example of an i-i' cross-sectional view. The semiconductor device 100 in this example has a contact trench 60 that is shallower than the emitter region 12, and emitter regions 12 disposed at both ends of the contact trench 60 in the trench arrangement direction, but is not limited thereto. The dummy gate trench 130 is also a dummy trench, just like the dummy trench 30. Therefore, a portion of the dummy gate trench 130 can be replaced with a dummy trench 30 at the emitter potential. This allows adjustment of the gate capacitance, thus enabling the achievement of the most appropriate switching speed.

[0180] The contact region 15 is disposed in the mesa 71 between the gate trench portion 40 and the dummy gate trench portion 130, below the lower end 13 of the emitter region 12 on the side of the dummy gate trench portion 130. Additionally, the contact region 15 is disposed in the mesa 71 between the gate trench portion 40 and the dummy trench portion 30, below the lower end 13 of the emitter region 12 on the side of the dummy trench portion 30.

[0181] Figure 12A This shows an example of a top view of a semiconductor device 100. In this example, the semiconductor device 100 is a case where the first trench portion adjacent to the gate trench portion 40 is the gate trench portion 40. Figure 11A The difference in the implementation method lies in the presence of an interleaved structure. The semiconductor device 100 has a plurality of gate trench portions 40 disposed adjacently. The plurality of gate trench portions 40 disposed adjacently can be connected to each other via a connecting portion 43.

[0182] Multiple adjacent gate trench portions 40 contact the emitter region 12 at different positions in the trench extension direction. That is, the semiconductor device 100 has an interleaved structure and emitter regions 12 arranged in a staggered manner. In this case, adjacent gate trench portions 40 each simultaneously have a portion that serves as a gate trench portion and a portion that serves as a first trench portion. That is, on the mesa between adjacent gate trench portions 40, there is an emitter region 12 (first emitter region) that contacts one gate trench portion 40 and is separated from the other gate trench portion 40, and an emitter region 12 (second emitter region) that is separated from one gate trench portion 40 and contacts the other gate trench portion 40. Moreover, a contact region 15 is provided below the lower end 13 of the first emitter region on the side of the other gate trench portion 40, and below the lower end 13 of the second emitter region on the side of one gate trench portion 40. In addition, in the trench extension direction of the gate trench portions 40, the first emitter region and the second emitter region are alternately provided with the contact region 15 between them.

[0183] Figure 12B yes Figure 12AThis is an example of a j-j' cross-sectional view. The semiconductor device 100 in this example has a contact trench 60 that is shallower than the emitter region 12, and emitter regions 12 disposed at both ends of the contact trench 60 in the trench arrangement direction, but is not limited thereto. That is, the semiconductor device 100 may have a contact trench 60 that is deeper than the emitter region 12, or it may have an emitter region 12 disposed on only one side of the contact trench 60. The semiconductor device 100 may or may not have a trench bottom region 19.

[0184] Figure 13A An example top view of a semiconductor device 100 is shown. In this example of the semiconductor device 100, with... Figure 12A The difference in the implementation method is that the dummy trench portion 30 is not provided, but only the gate trench portion 40 is provided. Figure 12A Similarly, in this embodiment, the semiconductor device 100 has an interleaved structure in which the emitter regions 12 are arranged in a staggered manner. Figure 12A Compared to the previous implementation, the ratio of the emitter region 12 in the front side 21 of the semiconductor device 100 in this example is larger. For the semiconductor device 100 in this example, even with the increased ratio of the emitter region 12 in the front side 21, latch-up of the semiconductor device 100 can be suppressed because a portion of the emitter region 12 is separated from the gate trench portion 40.

[0185] Figure 13B yes Figure 13A This is an example of a k-k' cross-sectional view. The semiconductor device 100 in this example includes a contact trench 60 shallower than the emitter region 12, and emitter regions 12 disposed at both ends of the contact trench 60 in the trench arrangement direction, but is not limited thereto. In this example, the emitter regions 12 are disposed at both ends in the trench arrangement direction, separated by the gate trench 40. In this case, by patterning the adjacent emitter regions 12 separated by the gate trench 40 together, process reliability can be maintained even when the mesa width is reduced.

[0186] While the present invention has been described above using embodiments, its technical scope is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. As can be seen from the claims, such modifications or improvements can also be included within the technical scope of the present invention. For example, although an RC-IGBT has been described as an example in this case, it can also be applied to IGBTs and MOSFETs.

[0187] It should be noted that the execution order of actions, processes, steps, and stages in the apparatus, system, program, and method shown in the claims, specification, and drawings can be implemented in any order, unless specifically stated as "earlier than" or "before," and unless the results of previous processes are used in subsequent processes. Even if the flow of actions in the claims, specification, and drawings is described using terms such as "firstly" or "next" for convenience, it does not mean that they must be implemented in that order.

Claims

1. A semiconductor device, characterized by comprising: It has a gate trench portion and a first trench portion. The semiconductor device includes: A drift region of the first conductivity type is disposed in the semiconductor substrate; The base region of the second conductivity type is disposed above the drift region; The emitter region of the first conductivity type is disposed above the base region and has a higher doping concentration than the drift region; as well as A second conductivity type contact region is disposed above the base region, and has a higher doping concentration than the base region. In the mesa-shaped section between the gate trench portion and the first trench portion, the contact area is disposed below the lower end of the emitter region in a cross-section parallel to the trench arrangement direction, and extends from below the lower end towards the gate trench portion in the trench arrangement direction, terminating before reaching the gate trench portion. The first trench portion is a dummy trench portion or a dummy gate trench portion. The gate trench portion includes adjacent gate trench portions disposed adjacent to each other in a manner that does not clamp the first trench portion. In the mesa portion between the adjacent gate trench portions, the emitter region has a first emitter region and a second emitter region. The first emitter region is in contact with one of the adjacent gate trench portions and is separated from the other of the adjacent gate trench portions. The second emitter region is in contact with the other of the adjacent gate trench portions and is separated from one of the adjacent gate trench portions. On the mesa between adjacent gate trench portions, the first emitter region and the second emitter region are not opposite to each other in the trench arrangement direction of the gate trench portion, and are alternately arranged in the trench extension direction of the gate trench portion.

2. The semiconductor device according to claim 1, characterized in that, The contact area contacts the first groove portion.

3. The semiconductor device according to claim 1 or 2, characterized in that, On the platform surface, the contact area contacts the lower surface of the emission area.

4. The semiconductor device according to claim 3, characterized in that, The contact area is separated from the gate trench by more than 0.6 μm in the trench arrangement direction.

5. The semiconductor device according to claim 1 or 2, characterized in that, The contact area is located on the front side of the semiconductor substrate on the sidewall of the first trench.

6. The semiconductor device according to claim 1 or 2, characterized in that, The semiconductor device includes an interlayer insulating film disposed above the semiconductor substrate. The emitting region is electrically connected to the emitting electrode via a contact hole that penetrates the interlayer insulating film.

7. The semiconductor device according to claim 6, characterized in that, The emitter region extends from the gate trench portion across the contact hole toward the first trench portion side in the trench arrangement direction.

8. The semiconductor device according to claim 1 or 2, characterized in that, Between the drift region and the base region, there is an accumulation region of a first conductivity type with a higher doping concentration than that of the drift region.

9. The semiconductor device according to claim 1 or 2, characterized in that, The emitter region extends from the gate trench portion toward the first trench portion in the trench arrangement direction and terminates before reaching the first trench portion.

10. The semiconductor device according to claim 1, characterized in that, The contact area and the emitter area are configured to alternately contact the front side of the semiconductor device relative to the trench extension direction of the gate trench portion.

11. The semiconductor device according to claim 1 or 2, characterized in that, The first trench portion has a first trench insulating film and a first trench conductive portion. The first trench conductive portion is set to an emitter potential or a floating potential.

12. The semiconductor device according to claim 1 or 2, characterized in that, The first trench portion has a first trench insulating film and a first trench conductive portion. The first trench conductive portion is set to the gate potential.

13. The semiconductor device according to claim 1, characterized in that, A third emitter region is located on the mesa between the other of the adjacent gate trenches and the first trench. The third emitter region is in contact with the other of the adjacent gate trenches on the mesa between the first trench and the other of the adjacent gate trenches.

14. The semiconductor device according to claim 1, characterized in that, In the trench arrangement direction, the contact area extends from the lower end of the second emitter region on the side of one of the adjacent gate trenches toward the other of the adjacent gate trenches, and terminates before reaching the other of the adjacent gate trenches.

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