Self-aligned edge passivation for robust resistive random access memory connections

Abstract

A resistive random access memory (RRAM) structure includes a top electrode and a bottom electrode (106, 108) electrically coupled to a first metal connection line and a second metal connection line, respectively, the first and second metal connection lines providing electrical connections to the RRAM structure. A layer of a resistance-switching material (106) is disposed between the top and bottom electrodes (106, 108) of the RRAM structure. The resistance-switching material (106) exhibits a measurable change in electrical resistance under the influence of at least an electric field and / or heat. A dielectric spacer (324) is formed on at least sidewalls of the bottom electrode of the RRAM structure. The RRAM structure further includes a passivation layer (326) formed on an upper surface of the dielectric spacer (324) and covering at least a portion of the sidewalls of the top electrode (110). The passivation layer (326) is self-aligned to the first metal connection line.

Description

Technical Field

[0001] This invention generally relates to the electrical, electronic and computer fields, and more particularly to resistive random access memory. Background Technology

[0002] Resistive random access memory (RRAM or ReRAM) is considered a promising technology for more scalable, high-density, and high-performance non-volatile memory solutions. RRAM is particularly advantageous for use as electronic synaptic devices or memristors in neuromorphic computing. Neuromorphic engineering draws inspiration from multiple technological fields, including biology, physics, mathematics, computer science, and electrical engineering, to construct artificial neural systems whose physical architecture and design principles are based on biological neural systems. In neuromorphic computing applications, resistive memory devices can be used as connections (i.e., synapses) between preneurons and postneurons, with connection weights represented as device components.

[0003] In artificial neural system applications, multiple preneurons and postneurons can be connected via a crossbar array of Resonant RAMs (RRAMs), which naturally represent fully connected neural networks. To fabricate large-scale crossbar arrays, it is desirable to minimize line resistance to reduce voltage drop across the lines. Therefore, copper wires are preferred. However, integrating copper wires with RRAM pillars has presented significant design and reliability challenges.

[0004] RRAM pillars / stacks typically include titanium nitride (TiN) electrodes for compatibility with complementary metal-oxide-semiconductor (CMOS) process flows. Incorporating RRAM devices into copper damascene processes requires an additional metal mask layer (e.g., tantalum nitride (TaN)) on top of the RRAM stack to protect the stack during TiN hard mask removal. Additionally, sidewall protection is often required because the size of copper vias in the cross-switch array is typically larger than the size of copper vias in the RRAM stack pillars. Conventional spacers are frequently damaged during via opening, thus introducing undesirable weaknesses for subsequent TiN wet etching. Therefore, there is a need in the art to address these issues. Summary of the Invention

[0005] From a first aspect, the present invention provides a resistive random access memory (RRAM) structure comprising: top and bottom electrodes electrically coupled to first and second metal interconnects, the first and second metal interconnects providing electrical connections to the RRAM structure; a layer of resistive switching material disposed between the top and bottom electrodes, the resistive switching material exhibiting a measurable resistance change under the influence of at least one of an electric field and heat; a dielectric spacer formed on at least the sidewall of the bottom electrode; and a passivation layer formed on the upper surface of the dielectric spacer and covering at least a portion of the sidewall of the top electrode, the passivation layer being self-aligned with the first metal interconnect.

[0006] From a first aspect, the present invention provides a method for forming a resistive random access memory (RRAM) structure, the method comprising: forming a bottom electrode on an upper surface of a first metal interconnect; forming a layer of resistive conversion material on at least a portion of the upper surface of the bottom electrode, the resistive conversion material exhibiting a measurable resistance change under the influence of at least one of an electric field and heat; forming a top electrode on the upper surface of the resistive conversion material layer; forming a dielectric spacer formed on at least a sidewall of the bottom electrode; and forming a passivation layer on the upper surface of the dielectric spacer, the passivation layer covering at least a portion of the sidewall of the top electrode, the passivation layer being self-aligned with a second metal interconnect electrically connected to the top electrode.

[0007] As shown in one or more embodiments, the present invention advantageously provides a resistive random access memory (RRAM) structure and a method for manufacturing the RRAM structure, which provides reduced connection resistance, particularly advantageous for use in crossbar switch arrays. In one or more embodiments, the RRAM structure includes a self-aligned passivation feature surrounding at least the bottom electrode of the RRAM structure. The passivation feature advantageously prevents the upper metal line from short-circuiting to the bottom electrode, although erosion of the RRAM sidewall spacers may occur during deep etching for forming vias for connecting the upper and lower metal lines in the crossbar switch array.

[0008] According to an embodiment of the present invention, the RRAM structure includes top and bottom electrodes electrically coupled to first and second metal interconnects, respectively, which provide electrical connections to the RRAM structure. A layer of resistivity-converting material is disposed between the top and bottom electrodes of the RRAM structure. The resistivity-converting material exhibits a measurable change in resistance under the influence of at least an electric field and / or heat. A dielectric spacer is formed on the sidewall of at least the bottom electrode of the RRAM structure. The RRAM structure also includes a passivation layer formed on the upper surface of the dielectric spacer and covering at least a portion of the sidewall of the top electrode. The passivation layer is self-aligned with the first metal interconnect.

[0009] According to an embodiment of the present invention, a method for forming an RRAM structure includes: forming a bottom electrode on an upper surface of a first metal interconnect; forming a layer of resistivity conversion material on at least a portion of the upper surface of the bottom electrode, the resistivity conversion material exhibiting a measurable resistance change under the influence of at least one of an electric field and heat; forming a top electrode on the upper surface of the resistivity conversion material layer; forming a dielectric spacer formed on at least the sidewall of the bottom electrode; and forming a passivation layer on the upper surface of the dielectric spacer, the passivation layer covering at least a portion of the sidewall of the top electrode, the passivation layer being self-aligned with a second metal interconnect electrically connected to the top electrode.

[0010] As used herein, an "facilitating" action includes performing an action, making an action easier, assisting in performing an action, or causing an action to be performed. Therefore, by way of example and not limitation, in the context of a semiconductor manufacturing method, a step performed by one entity can facilitate an action performed by another entity to induce or assist in the performance of one or more desired actions. To avoid confusion, in cases where an actor facilitates an action by performing an action other than the action itself, that action is still performed by an entity or combination of entities.

[0011] The technology of this invention can provide substantially beneficial technical effects. As an example only and not a limitation, the RRAM structure and / or method of manufacturing the RRAM structure according to embodiments of the present invention can provide one or more of the following advantages:

[0012] Reduce the connection resistance between the RRAM structure and the corresponding metal interconnects;

[0013] Reduce the possibility of electrical short circuits between the electrodes and corresponding metal interconnects in the RRAM structure;

[0014] Facilitates the integration of RRAM structures formed using CMOS processes with copper damascene processing for forming metal interconnects in cross-switch arrays;

[0015] This allows the size of the RRAM pillar to be scaled down to below the size of the corresponding contact body.

[0016] These and other features and advantages of the invention will become apparent from the following detailed description of illustrative embodiments of the invention, which are read in conjunction with the accompanying drawings. Attached Figure Description

[0017] The following figures are presented by way of example only and not as a limitation, wherein, in all the views, the same reference numerals (where used) indicate the corresponding elements, and wherein:

[0018] Figure 1 is a perspective view depicting at least a portion of a standard resistive random access memory (RRAM) cell;

[0019] Figure 2 It is a perspective view depicting at least a portion of a crossbar switch array comprising a plurality of RRAM cells in which aspects of the present invention may be employed;

[0020] Figure 3 This is a cross-sectional view according to an embodiment of the present invention, showing at least a portion of an exemplary RRAM post integrated with a corresponding copper wire;

[0021] Figures 4 to 26 This is a cross-sectional view depicting exemplary processing steps / stages in the fabrication of an exemplary RRAM structure that provides reduced connection resistance, according to an embodiment of the present invention; and

[0022] Figure 27 This is a cross-sectional view of at least a portion of an exemplary RRAM pillar integrated with a corresponding copper wire, according to an alternative embodiment of the present invention.

[0023] It should be understood that the elements in the accompanying drawings are shown for simplicity and clarity. Common but well-known elements that may be useful or necessary in commercially feasible embodiments may not be shown in order to facilitate a more unobstructed observation of the illustrated embodiments. Detailed Implementation

[0024] As shown in one or more embodiments of the invention, the principles of the invention will be described herein in the context of exemplary resistive random access memory (RRAM or ReRAM) structures and methods for manufacturing such structures, which have self-aligned edge passivation for reducing connection resistance, particularly when the RRAM structure is used, for example, in a crossbar switch array. However, it should be understood that the invention is not limited to the specific structures and / or methods illustrated and described herein. Rather, it will be apparent to those skilled in the art, based on the teachings given herein, that many modifications can be made to the illustrated embodiments, all of which are within the scope of the claimed invention. That is, no limitation is intended or should be inferred with respect to the embodiments shown and described herein.

[0025] Figure 1 is a perspective view depicting at least a portion of a basic RRAM cell 100. The RRAM cell 100 is disposed between a bottom conductor 102, which may be a word line, and a top conductor 104, which may be a bit line. The RRAM cell 100 includes a junction having a thin resistive switching material 106 sandwiched between a bottom electrode 108 and a top electrode 110 of the RRAM cell. Titanium nitride (TiN) is typically used for the bottom electrode 108 and the top electrode 110, and a metal oxide (e.g., hafnium oxide (HfO)) is typically used as the resistive switching material 106. The switching effect of the RRAM involves the creation of defects in the switching material 106, which may be referred to as oxygen vacancies (i.e., oxide binding sites where oxygen has been removed), which can be charged and drifted under the influence of an electric field, which may be generated by an applied bias voltage 112 or heat. This applied electric field or heat causes oxygen ions and vacancies in the switching material 106 to move in a manner consistent with the movement of electrons and holes in a semiconductor, which in turn causes a measurable change in the resistance of the device.

[0026] Figure 2 This is a perspective view showing at least a portion of a cross-switch array 200 in which aspects of the present invention may be employed. The cross-switch array 200 includes a plurality of RRAM cells 202, each RRAM cell being disposed between a corresponding bottom conductor 204, which may be a word line, and a top conductor 206, which may be a bit line, in a single intersection. Although not explicitly shown (but implied), cell selection devices (e.g., transistors or diodes) are typically connected in series between each RRAM cell 202 and either the corresponding top or bottom conductor 206, 204, and are used for selective access to the individual cells. The bottom conductor 204 is preferably disposed on a substrate 208, such as an interlayer dielectric (ILD) layer.

[0027] As previously mentioned, in order to fabricate large-scale cross-switch arrays, it is desirable to reduce the line resistance in the array to minimize the voltage drop across the lines. To achieve this, copper is preferably used, for example, by employing a copper damascene process to form the bottom and top conductors (e.g., 204, 206) in the cross-switch array. However, the integration of RRAM with the copper damascene process presents several challenges that have a significant impact on the reliability and cost of RRAM devices.

[0028] As mentioned earlier, RRAM pillars typically include TiN electrodes for compatibility with CMOS process flows. Copper damascene processes use TiN as a mask, so when the TiN mask is selectively removed during the copper damascene process, the TiN electrodes of the RRAM pillars are also etched. Therefore, incorporating RRAM into a copper damascene process usually requires forming an additional metal barrier layer on top of the RRAM pillars to protect the top electrodes from etching during the removal of the copper damascene TiN hard mask.

[0029] Another challenge in integrating RRAM with copper damascene technology is that, since the upper copper traces are typically much larger than the RRAM pillars, they tend to extend beyond the pillars and wrap around their sides, increasing the likelihood of electrical short circuits between the upper copper traces and the bottom electrode of the RRAM pillar. Therefore, dielectric spacers are typically formed on the sidewalls of the RRAM pillars to prevent electrical contact between the upper copper traces and the bottom electrode. However, conventional sidewall spacers are often damaged during the etching process used to form via openings, creating undesirable weaknesses in TiN wet etching. This results in yield losses for the RRAM cross-switch array.

[0030] Embodiments of the present invention provide a novel RRAM pillar structure that advantageously eliminates at least the aforementioned challenges of integrating RRAM with copper damascene processes. Reference now is made to... Figure 3 According to an embodiment of the invention, a cross-sectional view illustrates at least a portion of an exemplary RRAM pillar structure 300 integrated with corresponding copper wires. The RRAM pillar structure 300 may, for example, be disposed in the RRAM region of a cross-connected switch array. The RRAM pillar structure 300 includes a lower metal line (F2) 302 containing copper in one or more embodiments, an upper metal line (F3) 304 also containing copper in one or more embodiments, and RRAM pillars (i.e., stacks) disposed between the lower and upper metal lines as shown. The lower metal line 302 and upper metal line 304, which may be formed using a copper damascene process, are surrounded by a dielectric layer 306, which, in one or more embodiments, is an interlayer dielectric (ILD) layer. The dielectric layer 306 may comprise, for example, silicon dioxide or an alternative low-k material.

[0031] In the case of a copper damascene process, each of the lower metal line 302 and the upper metal line 304 is preferably surrounded by barrier layers 308 and 310, respectively, to prevent copper from diffusing into the surrounding dielectric layer 306. The barrier layers 308 and 310 preferably include, for example, tantalum (Ta), tantalum nitride (TaN), TiN, etc., although embodiments of the invention are not limited to any particular barrier material.

[0032] A packaging layer 312 (e.g., silicon nitride (SiN)) is deposited on the lower metal line 302, and although in Figure 3 Not explicitly shown, but preferably extending laterally across the structure. An opening through the encapsulation layer 312 is then etched in a designated area to expose the underlying lower metal line 302. RRAM pillars are formed on top of corresponding openings in the encapsulation layer 312 on at least a portion of the upper surface of the lower metal line 302.

[0033] In one or more embodiments, the RRAM pillar includes a multilayer bottom electrode and a multilayer top electrode. In some preferred embodiments, the top and bottom electrodes of the RRAM pillar are double-layer electrodes, although embodiments of the invention are not limited to electrodes with two layers. Specifically, the bottom electrode of the RRAM pillar includes: a first metal or metal nitride layer 314, which in this example may be TaN, formed directly on the upper surface of the lower metal line 302, and a second metal / metal nitride layer 316, which in this example may be TiN, formed on the upper surface of the first metal nitride layer. Similarly, in this exemplary embodiment, the top electrode of the RRAM pillar includes: a first metal or metal nitride layer 318, which in this example may be TiN, and a second metal / metal nitride layer 320, which in this example may be TaN. The second metal / metal nitride (TaN) layer 320 is in direct electrical contact with the upper metal line 304. It should be understood that all material layers forming the top and bottom electrodes of the RRAM pillar do not need to include metal nitrides. For example, in one or more embodiments, at least one of the layers forming the top electrode comprises TiN, and another layer of the top electrode comprises a metal, such as tungsten (W), iridium (Ir), etc.

[0034] The RRAM pillar also includes a metal oxide layer 322 disposed between the bottom electrode and the top electrode. More specifically, the metal oxide layer 322 is formed on at least a portion of the upper surface of the second metal nitride layer 316 of the bottom electrode, and the first metal nitride layer 318 of the top electrode is formed on at least a portion of the upper surface of the metal oxide layer 322. In one or more embodiments, the metal oxide layer 322 used as the resistivity conversion material includes hafnium oxide (HfO), but embodiments of the invention are not limited to this particular resistivity conversion material.

[0035] The dielectric spacer 324 is preferably formed on the sidewall of the RRAM pillar, at least covering the TiN layer 316 of the bottom electrode of the RRAM pillar. In one or more embodiments, the sidewall spacer 324 comprising silicon nitride (SiN) may not adequately protect the RRAM pillar during the formation of the upper metal line 304. Therefore, a passivation layer 326 is formed on the sidewall spacer 324, covering at least a portion of the multilayer top electrodes 318, 320. The sidewall spacer 324 is configured such that the passivation layer 326 does not contact the metal oxide layer 322 of the RRAM pillar or the multilayer bottom electrodes 314, 316 (i.e., electrically isolated).

[0036] As shown in region of interest 328, the passivation layer 326 is self-aligned with the upper metal line 304, such that the edge of the upper metal line cannot extend beyond the passivation layer and surround the RRAM pillar, thereby creating an electrical short circuit with the bottom electrode of the RRAM pillar. In one or more embodiments, the self-aligned passivation layer 326 comprises a dielectric material. In another embodiment, since the passivation layer 326 does not make electrical contact with the metal oxide layer 322 of the RRAM pillar or the multilayer bottom electrodes 314, 316, the passivation layer may comprise a metal or another conductive material. The upper metal line 304 is formed on and self-aligned with the passivation layer 326 and is located on the upper surface of the second metal nitride layer 320 of the multilayer top electrode of the RRAM pillar.

[0037] Therefore, compared to conventional RRAM device manufacturing methods, the RRAM pillar structure 300 according to one or more embodiments of the present invention advantageously provides a self-aligned passivation layer, formed after via photolithography and etching (for connecting the lower and upper metal lines in the peripheral region of the wafer in which the RRAM structure is formed), protecting the bottom electrodes 314, 316 of the RRAM pillar from electrical contact with the upper metal line 304. This unique arrangement advantageously allows the size of the RRAM pillar to be scaled down to less than the size of the upper metal contact without the risk of electrical short circuits.

[0038] This is merely an example and not a limitation. Figures 4 to 26This is a cross-sectional view depicting illustrative process steps / stages in the fabrication of an exemplary RRAM structure providing reduced connection resistance according to an embodiment of the invention. While the overall fabrication method and the resulting structure are entirely novel, certain individual process steps required to implement this method can be combined with conventional semiconductor fabrication techniques and tools. These techniques and tools are already familiar to those skilled in the art given the teachings herein. Furthermore, many process steps and tools used for fabricating semiconductor devices are described in numerous readily available publications, including, for example: P.H. Holloway et al., *Compound Semiconductor Handbook: Growth, Processing, Characterization, and Equipment*, Cambridge University Press, 2008; and R.K. Willardson et al., *Processing and Properties of Compound Semiconductors*, Academic Press, 2001. It should be emphasized that while some individual process steps are illustrated herein, these are merely illustrative, and those skilled in the art will recognize several equally suitable alternatives that will also fall within the scope of this invention.

[0039] It should be understood that the various layers and / or regions shown in the accompanying drawings may not be drawn to scale. Furthermore, for clarity, one or more semiconductor layers of a type typically used in such integrated circuit devices may not be explicitly shown in a given figure. This does not imply that un-explicitly shown semiconductor layers are omitted in actual integrated circuit devices.

[0040] Figure 4 This is a cross-sectional view depicting at least a portion of an exemplary semiconductor structure 400 in which lower metal lines are formed. Specifically, structure 400 includes a dielectric layer 402, which is preferably a low-k ILD layer. Lower metal lines 404 and 406 are formed in ILD layer 402, for example, using standard photolithographic patterning and etching processes. In this illustration, structure 400 is divided into various regions, including a first (e.g., KW) alignment mark region, a D2 alignment mark region, a base technology region (where peripheral circuitry is primarily formed), and a memory region (where RRAM cells are formed). In one or more embodiments of the invention, lower metal lines 404, 406 comprise copper, as can be formed by a copper damascene process. In the case of a copper damascene process, a barrier layer is typically formed around copper lines 404, 406 to prevent copper from diffusing into the surrounding ILD layer 402.

[0041] Figure 5A capping (i.e., encapsulation) layer 502 is shown formed on at least a portion of the upper surface of structure 400, which includes SiN in one or more embodiments. Specifically, the capping layer 502 is preferably formed on at least a portion of the upper surfaces of the lower copper lines 404, 406 and the upper surface of the ILD layer 402 using a deposition process (e.g., chemical vapor deposition (CVD)), although embodiments of the invention are not limited to any particular process for forming the capping layer.

[0042] exist Figure 6 In this embodiment, an organic dielectric layer (ODL) 602 is formed on at least a portion of the upper surface of the capping layer 502. In one or more embodiments, a standard deposition process, such as chemical vapor deposition (CVD), is used to form the organic dielectric layer 602 with a thickness of about 135 nanometers (nm), although embodiments of the invention are not limited to any deposition process or any particular thickness used to form the organic dielectric layer 602. An anti-reflective coating (ARC) 604 is formed on at least a portion of the upper surface of the organic dielectric layer 602. A photoresist mask 606 is formed on at least a portion of the upper surface of the ARC layer 604. The structure 400 is then subjected to an optical lithography process, thereby transferring a defined pattern to the photoresist mask 606 by exposure or exposure to another light source. One or more openings 608 and 610 are then formed in the photoresist mask 606 (e.g., by etching) to define areas of the structure 400 to be subsequently removed. One opening 608 is formed on a D2 alignment mark area, while another opening 610 is formed on a memory region and aligned with the lower copper line 406. Then, selective etching is performed to remove portions of the cover layer 502 located directly beneath openings 608 and 610.

[0043] Now refer to Figure 7 The openings 702 and 704 are etched through the SiN capping layer 502. In the D2 alignment mark region, the first of the openings 702 is etched through the ARC layer 604, the organic dielectric layer 602, and at least partially into the ILD layer 402 to expose the underlying ILD layer 402. Similarly, in the memory region, the second of the openings 704 is etched through the ARC layer 604, the organic dielectric layer 602, and at least partially into the lower copper trace 406 to expose the underlying lower copper trace; in this example, the lower copper trace 406 serves as a landing pad for the RRAM pillar subsequently formed thereon. In one or more embodiments, reactive ion etching (RIE) is used to etch the openings 702 and 704, although the invention is not limited to RIE. After forming the openings 702 and 704, the photoresist mask 606, the ARC layer 604, and the organic dielectric layer 602 are removed, for example, by wet etching.

[0044] like Figure 8As shown, a metal nitride liner 802 is formed in openings 702, 704 on the upper surface of structure 400. In one or more embodiments, the metal nitride liner 802 comprises TaN, although embodiments of the invention are not limited to TaN. The metal nitride liner 802 is preferably formed using a deposition process, such as, but not limited to, plasma vapor deposition (PVD). Figure 9 In this process, the upper surface of structure 400 is planarized using, for example, chemical mechanical planarization (CMP), such that a portion of the metal nitride liner 802 outside the openings 702, 704 on the upper surface of the capping layer 502 is removed to form metal nitride plugs 902 and 904. The metal nitride plug 904 is in direct electrical contact with the underlying lower copper wire 406 and will become one layer in the multilayer bottom electrode of the RRAM pillar subsequently formed on top of the lower copper wire 406, as will be described in further detail below.

[0045] Figure 10 The steps of forming a second metal nitride layer 1002 on at least a portion of the upper surface of structure 400 are described, including forming it on a capping layer 502 and metal nitride plugs 902 and 904. In one or more embodiments, the second metal nitride layer 1002 comprises TiN, although embodiments of the invention are not limited to TiN. The second metal nitride layer 1002, together with the metal nitride plug 904, will form the bottom electrode of the subsequently formed RRAM pillar structure.

[0046] Figure 11-13 Exemplary semiconductor manufacturing steps for optionally forming a notch alignment structure are described. References Figure 11 Preferably, a hard mask layer 1102 is deposited on at least a portion of the upper surface of the second metal nitride layer 1002 using, for example, a CVD process. Figure 12In this embodiment, an organic dielectric layer (ODL) 1202 is formed on at least a portion of the upper surface of the hard mask layer 1102. In one or more embodiments, a standard deposition process, such as CVD, is used to form the organic dielectric layer 1202 with a thickness of about 100 nm; however, embodiments of the invention are not limited to any deposition process or any specific thickness used to form the organic dielectric layer 1202. Next, on at least a portion of the upper surface of the organic dielectric layer 1202, an ARC layer 1204 corresponding to the alignment marks in another layer is formed, for example, by utilizing a standard CVD or similar process. A photoresist layer 1206 is formed on at least a portion of the upper surface of the ARC layer 1204. The photoresist layer 1206 is patterned, for example, using a standard photolithography process, and (e.g., using RIE) etched such that only a portion of the photoresist remains in the KW alignment mark region of structure 400. After selectively etching down to the second metal nitride layer 1002 and (e.g., using plasma or wet etching) removing the photoresist layer 1206, ARC layer 1204, and organic dielectric layer 1202, the photoresist layer ( Figure 12 The hard mask structure 1302 below 1206 (which is) Figure 12 A portion of the hard mask layer 1102 shown will remain in the KW alignment mark area of ​​structure 400, as... Figure 13 As shown in the image.

[0047] Figure 14 The process for forming the remaining layers of the RRAM pillar is illustrated. More specifically, a metal oxide layer 1402 is formed on at least a portion of structure 400, including the upper surface of a second metal nitride layer 1002 forming the bottom electrode of the RRAM pillar, and surrounding the hard mask structure 1302. In one or more embodiments, the metal oxide layer 1402, used as the resistivity conversion material for the RRAM pillar, comprises HfO, but embodiments of the invention are not limited to this particular resistivity conversion material. A third metal nitride layer 1404 is formed on at least a portion of the upper surface of the metal oxide layer 1402, and a fourth metal nitride layer 1406 is formed on at least a portion of the upper surface of the third metal nitride layer 1404. In one or more embodiments, the third and another metal nitride layers 1404 and 1406, comprising TiN and TaN respectively, will form the multilayer top electrode of the RRAM pillar. The metal oxide layer 1402 and the third and other metal nitride layers can be formed using standard deposition processes, such as CVD.

[0048] Continue to refer to Figure 14 A second hard mask layer 1408 is formed above the upper surface of structure 400. Similar to the first hard mask layers 502 / 1302, in one or more embodiments, the second hard mask layer 1408 comprises SiN, but embodiments of the invention are not limited to this particular material. Figure 14It is evident that the presence of the first hard mask structure 1302 produces a stepped cross-sectional profile in the KW alignment mask region of structure 400; in one or more embodiments, this morphology is used for alignment.

[0049] Figure 15 and 16 Exemplary steps in the formation of an RRAM column according to an embodiment of the present invention are described. Figure 15 As shown, a third organic dielectric layer 1502 is formed on at least a portion of the upper surface of the second hard mask layer 1408, for example, using standard deposition processes (e.g., CVD, PVD, plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.). In one or more embodiments, the third organic dielectric layer 1502 is formed to have a cross-sectional thickness of about 200 nm, but embodiments of the invention are not limited to any particular thickness. Preferably, CMP or the like is performed on the third organic dielectric layer 1502 to planarize the upper surface of the structure 400. Then, a third ARC layer 1504 is formed on at least a portion of the upper surface of the third organic dielectric layer 1502 using, for example, a standard deposition process.

[0050] A photoresist layer is deposited on the upper surface of the third ARC layer 1504. This photoresist layer is then patterned using a photolithography process and etched to form photoresist structures 1506 and 1508. Photoresist structures 1506 and 1508 are aligned with the underlying metal nitride plugs 902 and 904, respectively.

[0051] exist Figure 16 In the process, selective etching, such as RIE, is performed to form RRAM pillars 1602 in the memory region and alignment structures 1604 and 1606 in the D2 alignment mark and KW alignment mark regions, respectively. Specifically, in one or more embodiments, RIE is performed to etch through the third ARC layer 1504, the third organic dielectric layer 1502, the second hard mask layer 1408, the fourth metal nitride layer 1406, the third metal nitride layer 1404, the metal oxide layer 1402, and the second metal nitride layer 1002. Figure 16 The image shows the process after removing the remaining photoresist structures 1506 and 1508, the third ARC layer 1504, and the third organic dielectric layer 1502 (see [link]). Figure 15 The RRAM pillar 1602 and alignment structures 1604 and 1606 were obtained afterward.

[0052] like Figure 17As shown, an encapsulation layer 1702 is formed on structure 400, including the top surface and sidewalls of RRAM pillars 1602 and the top surface and sidewalls of alignment structures 1604 and 1606. In one or more embodiments, the encapsulation layer 1702 comprises SiN, although embodiments of the invention similarly contemplate other insulating (i.e., dielectric) materials for forming the encapsulation layer. Selective etching, such as RIE, is then performed to remove the encapsulation layer 1702 disposed on the horizontal surface of structure 400, including the top surfaces of the RRAM pillars 1602, alignment structures 1604 and 1606, and the upper surface of the overlay layer 502 between adjacent structures, as shown. Figure 18 As shown. Therefore, the encapsulation layer 1702 will only remain on the vertical sidewalls of the RRAM pillar 1602 and the alignment structures 1604, 1606 to form sidewall spacers.

[0053] exist Figure 19 In this configuration, a dielectric layer 1902 is deposited on at least a portion of the upper surface of structure 400, including the upper surface of capping layer 502 and surrounding RRAM pillars 1602 and alignment structures 1604, 1606. In one or more embodiments, dielectric layer 1902 is a low-k ILD layer. A CMP or alternative planarization process is then performed to planarize the upper surface of dielectric layer 1902. Subsequently, upper metallized wiring (F3) is formed in dielectric layer 1902, as will be described in further detail below.

[0054] like Figure 20 As shown, during the formation of the upper metal wiring layer (F3), a sacrificial SiN layer 2002 is deposited on the upper surface of the dielectric layer 1902. Then, a metal nitride (e.g., TiN) hard mask layer 2004 is deposited on the upper surface of the sacrificial SiN layer 2002, and a tetraethyl orthosilicate (TEOS) layer 2006 is deposited on the upper surface of the TiN hard mask layer. One or more of the SiN layer 2002, TiN hard mask layer 2004, and TEOS layer 2006 can be deposited using, for example, CVD or PECVD processes. Figure 21 In this process, the TEOS layer 2006 is patterned, and using standard photolithography and etching, openings 2102 and 2104 are formed in the TiN hard mask layer 2004 to expose a portion of the sacrificial SiN layer 2002. The first of the openings 2102 is vertically aligned with the underlying lower metal line 404, and the second of the openings 2104 is vertically aligned with the underlying RRAM pillar 1602.

[0055] Now for reference Figure 22Deep RIE or similar selective etching is performed to form trenches 2202 and 2204. Trench 2202 is etched through the sacrificial SiN layer 2002, the low-k dielectric layer 1902, and the capping layer 502 to expose at least a portion of the lower copper line 404. This trench 2202 will form a via that electrically connects the lower copper line 404 to a corresponding upper copper line to be formed in the base technology region of structure 400. Similarly, trench 2204 is etched through the sacrificial SiN layer 2002 and partially through the low-k dielectric layer 1902 to expose the top electrodes of the RRAM pillars in the memory region of structure 400, which are respectively composed of a third and another metal nitride layer 1404 and 1406.

[0056] Due to the deep RIE used to form trench 2202, there will be significant over-etching in trench 2204, which can significantly erode the encapsulation layer 1702 that forms the sidewall isolators protecting the RRAM pillars. Etching of the encapsulation layer 1702 protecting the RRAM pillars is shown in region 2206. This erosion creates a high risk of electrical short circuits between the corresponding unformed upper copper traces and the metal oxide conversion layer 1402 and the bottom electrode of the RRAM pillar, which includes a second metal nitride layer 1002.

[0057] To eliminate or at least substantially reduce the risk of short circuits between the upper copper traces and the bottom electrode of the RRAM pillar, a conformal dielectric pad (i.e., passivation layer) 2302 is deposited on the upper surface of structure 400, including on the upper surface of at least a portion of the TiN hard mask layer 2004, on the sidewalls of trenches 2202 and 2204, and around at least a portion of the RRAM pillar, as shown below. Figure 23 As shown. It should be understood that the small space of the encapsulation layer 1702, which is closest to the sidewall isolator forming the RRAM pillar, will also be completely filled by the dielectric pad 2302. The dielectric pad 2302 may include, for example, silicon carbide (SiC), silicon carbonate (SiCO), SiO2, etc., although embodiments of the present invention are limited to any particular dielectric pad material.

[0058] Figure 24 An exemplary structure 400 following isotropic etchback of a conformal dielectric pad 2302, according to one or more embodiments of the present invention, is shown. Figure 24As can be clearly seen, the isotropic etching back process removes the conformal dielectric pad 2302 from the upper surface of the hard mask layer 2004, the sidewalls and bottom of the trench 2202, and the opening regions on at least a portion of the sidewalls of the trench 2204. The conformal dielectric pad 2302 is retained in the pinched-off region between the RRAM pillar and the trench 2204, leaving only a portion of the fourth metal nitride layer 1406, forming the upper surface of the top electrode of the RRAM pillar exposed in the trench. This conformal dielectric pad 2302 protects the RRAM pillar conversion material and the bottom electrode from short-circuiting with the upper copper traces to be formed in the trench 2204. After the isotropic etching back process, at least a portion of the upper surface of the top electrode 1406 of the RRAM pillar is exposed in the trench through the recessed conformal dielectric pad 2302. In one or more embodiments, isotropic etching back is performed by atomic layer etching (ALE) to achieve precise etching control, although embodiments of the invention substantially cover any isotropic dry or wet etching process.

[0059] exist Figure 25 In the middle, the sacrificial TiN hard mask layer is removed ( Figure 24 (2004). In one or more embodiments, selective etching, such as diluted hydroperoxide or SC1 chemicals, is used to remove the sacrificed TiN hard mask layer. During TiN hard mask removal, the TiN used to form the top and bottom electrodes of the RRAM pillars is advantageously protected from damage by a self-aligned conformal dielectric pad 2302; this dielectric pad material clamps the lower edge of the RRAM pillars and seals any exposed TiN. Figure 26 The upper layer (F3) metallization process is illustrated, whereby, in one or more embodiments, copper is deposited to fill trenches 2202 and 2204, thereby forming upper copper lines 2602 and 2604, respectively. A planarization process (e.g., CMP) is then performed to planarize the upper copper lines 2602 and 2604 and remove the sacrificial SiN layer (…). Figure 25 (2002) up to the low-k dielectric layer 1902. As previously mentioned, adding a conformal dielectric pad 2302 that is self-aligned with the bottom of the upper copper line 2604 helps to prevent damage to the RRAM pillar by the TiN electrode, as highlighted in region 2606, and also prevents electrical short circuits between the upper copper line 2604 and the bottom electrode of the RRAM pillar, as highlighted in region 2608.

[0060] In an alternative embodiment of the invention, reference is made to Figure 27 If the metal used to form trenches 2202 and 2204 is not over-etched too deeply, such that the bottom of trench 2204 does not recede below the top electrode of the RRAM pillar, then the self-aligned conformal pad 2302 may comprise a metal or similar conductive material. Figure 27As shown, a conformal pad 2302 is formed on the upper surface of the encapsulation layer 1702, forming a sidewall spacer for protecting the RRAM pillars, as shown in region 2702. In this embodiment, the conformal pad 2302 preferably comprises, for example, TaN, ruthenium, etc. In this way, the metal pad 2302 is again self-aligned with the bottom of the upper copper line 2604, not only preventing damage to the TiN electrode below the RRAM pillar, but also providing a low-resistance connection between the top electrode of the RRAM pillar and the upper copper line 2604, because the connection joint will have a large surface area.

[0061] At least a portion of the technology of this invention can be implemented in integrated circuits. In forming integrated circuits, identical dies are typically fabricated on the surface of a semiconductor wafer in a repeating pattern. Each die includes the devices described herein and may include other structures and / or circuitry. Individual dies are diced or sliced ​​from the wafer and then packaged into integrated circuits. Those skilled in the art will know how to diced wafers and packaged dies to produce integrated circuits. Any exemplary structures or portions thereof shown in the figures may be part of an integrated circuit. Integrated circuits thus manufactured are considered part of this invention.

[0062] Those skilled in the art will understand that the above exemplary structures can be distributed as bare chips in their original form (i.e., a single wafer having multiple unpackaged chips), distributed in a packaged form, or incorporated as part of an intermediate or final product that benefits from having RRAM devices formed according to one or more embodiments of the present invention.

[0063] The integrated circuits according to aspects of this disclosure can be used in virtually any application and / or electronic system involving RRAM, such as, but not limited to, crossbar switch arrays. Suitable systems for implementing embodiments of the invention may include, but are not limited to, neuromorphic computing systems. Systems incorporating such integrated circuits are considered part of this invention. Given the teachings of this disclosure provided herein, those skilled in the art will be able to conceive of other implementations and applications of embodiments of the invention.

[0064] The description of embodiments of the invention described herein is intended to provide a general understanding of various embodiments and is not intended to serve as a complete description of all elements and features of devices and systems that may utilize the structures and semiconductor manufacturing methods described herein. Many other embodiments will become apparent to those skilled in the art based on the teachings herein; other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of the invention. The accompanying drawings are also merely representative and are not drawn to scale. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0065] Embodiments of the present invention are referred to herein individually and / or collectively by the term "embodiment," which is merely for convenience and not intended to limit the scope of this application to any single embodiment or inventive concept, if more than one is actually shown. Therefore, although specific embodiments have been illustrated and described herein, it should be understood that arrangements for achieving the same purpose may be substituted for the specific embodiments(s) shown; that is, this disclosure is intended to cover any and all modifications or variations of the various embodiments. Combinations of the foregoing embodiments, as well as other embodiments not specifically described herein, will become apparent to those skilled in the art from the teachings herein.

[0066] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “including”, when used in this specification, designate the presence of stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Terms such as “above,” “below,” “upper,” “lower,” “top,” and “bottom,” as may be used herein, are intended to indicate the relative positioning of elements or structures to each other rather than their absolute positioning.

[0067] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent for performing a function in combination with other claimed elements as specifically claimed. Various embodiments have been described for purposes of illustration and description, but are not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, and to enable others skilled in the art to understand the various embodiments with various modifications suitable for the particular purpose contemplated.

[0068] Furthermore, as can be seen from the foregoing detailed description, various features have been grouped together in a single embodiment to facilitate the flow of this disclosure. This approach to disclosure should not be construed as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as reflected in the appended claims, the inventive subject matter lies in fewer than all features of a single embodiment. Therefore, the following claims are thus incorporated into the detailed description, with each claim independently as a separately claimed subject matter.

[0069] Given the teachings of the embodiments of the invention provided herein, those skilled in the art will be able to conceive of other implementations and applications of the technology of the embodiments of the invention. Although illustrative embodiments of the invention have been described herein with reference to the accompanying drawings, it should be understood that the embodiments of the invention are not limited to these precise embodiments, and various other changes and modifications can be made therein by those skilled in the art without departing from the scope of the appended claims.

Claims

1. A resistive random access memory (RRAM) structure, comprising: The top electrode and the bottom electrode are electrically coupled to a first metal connection line and a second metal connection line, respectively, which provide electrical connections to the RRAM structure. A layer of resistivity conversion material disposed between the top electrode and the bottom electrode, the resistivity conversion material exhibiting a measurable change in resistance under the influence of at least one of an electric field and heat; A dielectric spacer formed on at least the sidewall of the bottom electrode; A passivation layer is formed on the upper surface of the dielectric spacer and covers at least a portion of the sidewall of the top electrode, the passivation layer being self-aligned with the first metal connection line; The passivation layer comprises a conductive material, and the dielectric spacer is formed on the sidewalls of the resistivity conversion material layer and the sidewalls of the bottom electrode and is configured to electrically isolate the resistivity conversion material and the bottom electrode from the passivation layer.

2. The RRAM structure according to claim 1, wherein at least one of the top electrode and the bottom electrode comprises a multilayer electrode.

3. The RRAM structure according to claim 2, wherein at least one of the top electrode and the bottom electrode comprises a first metal nitride layer and at least one of a second metal nitride layer and a first metal layer formed on the upper surface of the first metal nitride layer.

4. The RRAM structure according to claim 3, wherein one of the first metal nitride layer and the second metal nitride layer comprises titanium nitride, and the other of the first metal nitride layer and the second metal nitride layer comprises tantalum nitride.

5. The RRAM structure according to claim 3, wherein the first metal layer comprises at least one of tungsten and iridium.

6. The RRAM structure according to any one of claims 1-5, wherein the upper surface of the passivation layer is self-aligned with the bottom surface of the first metal interconnect.

7. The RRAM structure according to any one of claims 1-5, wherein the layer of the resistive conversion material comprises hafnium oxide.

8. The RRAM structure according to any one of claims 1-5, wherein the passivation layer comprises at least one of silicon carbide, silicon dioxide, and silicon carbonate.

9. The RRAM structure according to any one of claims 1-5, wherein the passivation layer comprises a conformal dielectric pad.

10. The RRAM structure of claim 1, wherein the passivation layer is electrically connected to the top electrode.

11. The RRAM structure according to any one of claims 1-5, wherein the total width of the top electrode, the bottom electrode, and the resistive conversion layer is less than the width of the first metal interconnect, thereby enabling the RRAM structure to be scaled to a size smaller than the first metal interconnect.

12. A method for forming a resistive random access memory (RRAM) structure, the method comprising: A bottom electrode is formed on the upper surface of the first metal connection wire; A layer of resistance-converting material is formed on at least a portion of the upper surface of the bottom electrode, the resistance-converting material exhibiting a measurable resistance change under the influence of at least one of an electric field and heat; A top electrode is formed on the upper surface of the resistive conversion material layer; A dielectric spacer is formed on at least the sidewall of the bottom electrode; as well as A passivation layer is formed on the upper surface of the dielectric spacer, and the passivation layer covers at least a portion of the sidewall of the top electrode. The passivation layer is self-aligned with a second metal connection line, and the second metal connection line is electrically connected to the top electrode. The dielectric spacer is formed on the sidewalls of at least the bottom electrode and the resistivity conversion material layer, and the passivation layer comprises a conductive material.

13. The method of claim 12, wherein the passivation layer comprises a conformal dielectric pad, the method further comprising: A dielectric layer is formed surrounding the RRAM structure; A trench is formed that at least partially penetrates the dielectric layer, thereby exposing at least a portion of the top electrode and the dielectric spacer of the RRAM structure; A conformal dielectric pad is deposited in the trench to fill the over-etched area of ​​the trench; as well as An isotropic etchback is performed on the conformal dielectric pad to remove a portion of the conformal dielectric pad on the sidewall of the trench, the conformal dielectric pad remaining in the over-etched region of the trench, and at least a portion of the upper surface of the top electrode being exposed in the trench through the recessed conformal dielectric pad.

14. The method according to claim 13, wherein, The second metal interconnect is formed by depositing metal in the trench and on the respective upper surfaces of the conformal dielectric pad and the top electrode of the RRAM structure.

15. The method of claim 12, wherein the first metal connection wire and the second metal connection wire are formed using a copper inlay process.

16. The method according to any one of claims 12 to 15, wherein forming at least one of the top electrode and the bottom electrode comprises forming a multilayer electrode.

17. The method of claim 16, wherein the multilayer electrode comprises a first metal nitride layer and at least one of a second metal nitride layer and a first metal layer formed on an upper surface of the first metal nitride layer.

18. The method according to any one of claims 12 to 15, wherein, The total width of the top electrode, the bottom electrode, and the resistivity conversion material layer is less than the width of the second metal connection line.

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