Imaging device and imaging method

Abstract

One embodiment of the present application may relate to an imaging device, comprising a comparator, a pixel and a control circuit, wherein the comparator comprises a switch, a first transistor and a first capacitor, wherein when the switch is turned on, the first capacitor is charged, and wherein, after the switch is turned off, the comparator uses the power charged in the first capacitor to compare the pixel signal input from the pixel with the ramp signal input from the control circuit, and outputs an output signal.

Description

Technical Field

[0001] The embodiments described below relate to imaging apparatus / methods, for example, for still images and / or movies. Background Art

[0002] Imaging devices and imaging methods for still images and / or movies are generally widely used. Imaging devices are exemplified by digital cameras, cellular phones, terminal equipment, and automobiles (car-mounted cameras), but are not limited thereto. Summary of the invention

[0003] The present disclosure including the aspects shown below may be directed to, for example, imaging devices / methods for still images and / or movies. It should be understood that the following disclosure does not limit or restrict the pending application / invention.

[0004] A first aspect is an imaging device, comprising a comparator, a pixel and a control circuit, wherein the comparator comprises a switch, a first transistor and a first capacitor, wherein when the switch is turned on, the first capacitor is charged, and wherein after the switch is turned off, the comparator uses the power charged in the first capacitor to compare the pixel signal input from the pixel with the ramp signal input from the control circuit and outputs an output signal.

[0005] A second aspect is the imaging device according to the above aspect, wherein the ramp signal includes a first ramp signal and a second ramp signal.

[0006] A third aspect is the imaging device according to the above aspect, wherein the ramp signal includes a predetermined voltage difference between the first ramp signal and the second ramp signal.

[0007] A fourth aspect is the imaging device according to the above aspect, wherein when the first ramp signal reaches the same level as the pixel signal, the comparator inverts the output signal.

[0008] A fifth aspect is the imaging device according to the above aspect, wherein when a voltage having the same voltage level as the predetermined voltage difference is applied to a gate terminal of the first transistor, the first transistor causes a bias current to flow to drive the comparator.

[0009] A sixth aspect is the imaging device according to the above aspect, wherein the capacitance of the first capacitor is large enough to drive the comparator.

[0010] A seventh aspect is the imaging device according to the above aspect, wherein when the second ramp signal reaches the same level as the pixel signal, the comparator completes its comparison operation.

[0011] An eighth aspect is the imaging device according to the above aspect, wherein when the switch is turned off, the comparator is disconnected from a common power supply of the imaging device.

[0012] A ninth aspect is the imaging device according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-up signals.

[0013] A tenth aspect is the imaging device according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-down signals.

[0014] The eleventh aspect is an imaging method for an imaging device including a comparator, a pixel and a control circuit, the imaging method comprising: when the switch of the comparator is turned on, charging the first capacitor of the comparator; after the switch is turned off, using the power charged in the first capacitor to compare the pixel signal input from the pixel with the ramp signal input from the control circuit; and outputting an output signal.

[0015] A twelfth aspect is the imaging method according to the above aspect, wherein the ramp signal includes a first ramp signal and a second ramp signal.

[0016] A thirteenth aspect is the imaging method according to the above aspect, wherein the ramp signal includes a predetermined voltage difference between the first ramp signal and the second ramp signal.

[0017] A fourteenth aspect is the imaging method according to the above aspect, wherein when the first ramp signal reaches the same level as the pixel signal, the comparator inverts the output signal.

[0018] A fifteenth aspect is the imaging method according to the above aspect, wherein when a voltage having the same voltage level as the predetermined voltage difference is applied to a gate terminal of the first transistor, the first transistor causes a bias current to flow to drive the comparator.

[0019] A sixteenth aspect is the imaging method according to the above aspect, wherein the capacitance of the first capacitor is large enough to drive the comparator.

[0020] A seventeenth aspect is the imaging method according to the above aspect, wherein when the second ramp signal reaches the same level as the pixel signal, the comparator completes its comparison operation.

[0021] An eighteenth aspect is the imaging method according to the above aspect, wherein when the switch is turned off, the comparator is disconnected from the common power supply of the imaging device.

[0022] A nineteenth aspect is an imaging method according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-up signals.

[0023] The twentieth aspect is the imaging method according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-down signals.

[0024] The above disclosure does not limit or restrict the present application / invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of an imaging device described in one embodiment.

[0026] Figure 2 is a circuit diagram of an embodiment.

[0027] Figure 3 is a timing diagram of an embodiment.

[0028] Figure 4 is a circuit diagram of an embodiment.

[0029] Figure 5 is a timing diagram of an embodiment. DETAILED DESCRIPTION

[0030] The following disclosure includes examples only. The scope of the present invention and application should not be considered to be limited by the embodiments shown below.

[0031] Figure 1 Schematic diagram of an imaging device of an embodiment is shown. The imaging device 100 includes a camera module 110, a pixel 120, an analog to digital (AD) converter 130, and a timing generator (T / G) 140. The imaging device 100 may include a logic circuit 150 that replaces the T / G 140. The imaging device 100 may also include a set of lenses, a battery, a memory, and a screen or panel, etc. The imaging device 100 may also include a processor, a hard disk, an optical drive, a transceiver, a speaker, a microphone, etc.

[0032] The camera module 110 includes a pixel 120, an AD converter 130, and a T / G 140. As described above, the T / G 140 may be replaced with a logic circuit 150 outside the camera module 110. The camera module 110 may be Figure 2 The image sensor circuit shown in .

[0033] Pixel 120 may be a complementary metal oxide semiconductor (CMOS) image sensor, a charge coupled device (CCD) image sensor or other device. Pixel 120 may be composed of a plurality of pixels. Pixel 120 may also include a color filter. Pixel 120 receives light through a lens not shown in the figure and outputs an analog signal corresponding to the intensity of the received light.

[0034] The AD converter 130 is input with an analog signal from the pixel 120 and outputs a digital signal indicating the intensity of light received by the pixel 120. A processor not shown in the figure may receive the digital signal from the AD converter 130 and generate image data. The processor may store the image data in a memory, for example. The image data may be a still image or part of a movie.

[0035] The T / G 140 (or the logic circuit 150) outputs a pulse signal indicating an operation timing, based on which the constituent elements of the imaging device 100 operate. For example, when a timing signal is input from the T / G 140 (or the logic circuit 150), the AD converter 130 may compare the voltage of the analog signal output from the pixel 120 with the voltage of the analog signal output from the pixel 120. Figure 1 The reference voltage is not shown.

[0036] Hereinafter, details of the AD converter 130 are explained with reference to the drawings.

[0037] The imaging device may include an AD converter, for example, a single slope analog to digital converter (SS ADC). Generally, it is desirable to reduce the power consumption of the SS ADC without causing side effects.

[0038] For example, the power consumption of an AD converter (except for the SSADC) can be reduced by only reducing the bias current of the comparator included in the AD converter. One example of a bias circuit that reduces power consumption is implemented using a dynamic bias circuit. On the other hand, less bias current may reduce the performance of the comparator (e.g., analog-to-digital conversion performance): reduced speed, increased noise, and / or reduced AD accuracy.

[0039] As mentioned above, it is generally desirable to reduce the power consumption of the ADC. It should be noted that applying the dynamic bias circuit of the comparator that can reduce the power consumption of the AD converter to the SS ADC is not the best choice.

[0040] Because generally, a comparator with a dynamic bias circuit can compare input signals corresponding to input digital signals, while in the SS ADC, these digital signals cannot be generated during the AD conversion operation.

[0041] Typically, dynamically biasing comparators can cause large "banding noise". This is because the dynamic bias circuit causes large changes in the comparator's supply current. This can negatively affect image quality.

[0042] Hereinafter, a first embodiment will be explained. Figure 2 An image sensor circuit is shown that includes two input pixel signal lines (Vpixel1 and Vpixel2) and two single slope ADCs. Figure 2 The image sensor circuits shown in FIG. 1 show simplified structures to make it easier to explain their operation. In actual image sensors, more ADCs need to be placed, and these ADCs are usually column-type to accommodate the number of pixel signal outputs. Figure 2 The image sensor circuit shown in Figure 1 The camera module shown in .

[0043] Input pixel signal lines Vpixel1 and Vpixel2 are included in Figure 1 In the pixel 120 shown in . Each of the input pixel signal lines Vpixel1 and Vpixel2 corresponds to one pixel. Figure 2 I1 and I2 shown in the figure are comparators. Comparator I1 receives the pixel signal from Vpixel1 through the input pixel signal line Vpixel1. Figure 2 The comparator I2 receives the signal from the pixel not shown in the figure through the input pixel signal line Vpixel1. Figure 2 The signal of the pixel not shown in the figure.

[0044] Figure 2 VRAMP1 and VRAMP2 shown in FIG. 1 represent ramp reference voltages provided through lines. Comparator I1 receives ramp reference voltage VRAMP1 from terminal 3. Comparator I1 receives ramp reference voltage VRAMP2 from terminal 2. Comparator 2 has the same structure as comparator I1. The ramp reference voltages VRAMP1 and VRAMP2 can be provided from Figure 2 The control circuit (eg, Figure 1 The logic circuit 150 shown in FIG. 1 outputs the output.

[0045] Figure 2The VDD_common shown in is a common power supply shared with all or part of the comparators. The comparator I1 receives the common power supply VDD_common through the terminal 1 and performs its operation. The comparator I2 has the same structure as the comparator I1. The common power supply VDD_common can be supplied from a power supply circuit not shown in the drawings.

[0046] The comparator I1 receives the ramp reference voltage VRAMP1 / VRAMP2 and the input pixel voltage (hereinafter referred to as Vpixel1 for ease of understanding) and performs a comparison operation. Figure 2 The terminal Vout1 shown in FIG. 1 outputs a signal indicating the comparison result. The comparator I2 outputs a signal indicating the comparison result. Figure 2 The terminal Vout2 shown in FIG. 1 outputs a signal indicating the comparison result thereof.

[0047] The comparator I1 includes transistors M1, M2, M3, M4, M6, M7, M8, M9 and M10. The comparator I1 includes capacitors Cp, C G and Cs. The comparator I1 includes a switch SW1. The comparator I1 includes terminals 1 to 5. Terminal 1 is connected to a common power supply VDD_common. Terminal 2 receives a ramp reference voltage VRAMP2. Terminal 3 receives a ramp reference voltage VRAMP1. Terminal 4 is connected to an input pixel signal line Vpixel1. An output signal from the comparator I1 is output from a terminal 5 and provided to a counter circuit I3.

[0048] The comparator I2 has a substantially similar structure to the comparator I1. There are minor differences between them. The terminal 4 of the comparator I2 is connected to the input pixel signal line Vpixel2, and the output signal of the comparator I2 is provided to the counter circuit I4 through the terminal 5.

[0049] The counter circuit I3 receives the output signal from the terminal Vout1. The counter circuit I3 receives the clock signal (CLK). The counter circuit I3 counts the clocks included in the clock signal within a predetermined period of time while the counter circuit detects the output signal from the terminal Vout1. The clock signal (CLK) may be generated by a control circuit (e.g., Figure 1 Logic circuit 150) output.

[0050] The counter circuit 14 receives the output signal from the terminal Vout2. The counter circuit 14 receives the clock signal (CLK). The counter circuit 14 counts the clock included in the clock signal within a predetermined period of time, while the counter circuit detects the output signal from the terminal Vout1. The clock signal (CLK) may be generated by a control circuit (e.g., Figure 1 Logic circuit 150) is provided.

[0051] refer to Figure 3 The timing diagram shown in Figure 2 The operation of the image sensor circuit shown in FIG. Figure 3 In the embodiment, it is assumed that the first pixel signal level corresponding to the input pixel signal line Vpixel1 (hereinafter referred to as Vpixel1 for ease of understanding) is lower than the second pixel signal level corresponding to the input pixel signal line Vpixel2 (hereinafter referred to as Vpixel2 for ease of understanding). In actual use, the first pixel signal level Vpixel1 may be higher than the second pixel signal level Vpixel2 or the same as the second pixel signal level Vpixel2. Figure 3 The horizontal axis is the time axis.

[0052] exist Figure 3 In the embodiment, the ramp reference voltage VRAMP2 is higher than the ramp reference voltage VRAMP1 and accurately tracks the ramp reference voltage VRAMP1 with a predetermined offset level (Vth). The ramp reference voltage VRAMP1 is initially at a predetermined initial level (Vinit). At a predetermined timing, the ramp reference voltage VRAMP1 starts to ramp up from Vinit at a constant rate. For example, when a user operates an imaging device to take a photo or shoot a movie, the ramp reference voltage starts to ramp up. When the ramp reference voltage VRAMP1 starts to ramp up, the ramp reference voltage VRAMP2 simultaneously starts to ramp up from a predetermined level (Vinit+Vth) higher than VRAMP 1 at the same rate as VRAMP 1. Both the ramp reference voltages VRAMP1 and VRAMP2 pause ramping up at the same timing and keep them at a predetermined level.

[0053] The offset level Vth is a predetermined voltage and can be designed to Figure 2 The transistor M5 shown in 2 causes the target bias current to flow through the voltage used. The transistor M5 has a source terminal connected to ground. When a voltage is applied to the gate terminal of the transistor M5, the transistor M5 acts as a current source for the comparator.

[0054] Figure 2 The transistor M5 shown in can be a MOS transistor.For example, the drain current (Id) of the transistor M5 is determined as follows.

[0055] Id=k*W / L*(Vgs–Vt) 2 (1)

[0056] In formula (1), k is a constant, W is a channel width, L is a channel length, Vgs is a voltage difference between a gate terminal and a source terminal, and Vt is a threshold voltage.

[0057] If it is assumed that "k", "W", "L", and "Vt" are all known, and the target drain current Id can be determined or predetermined, then "Vgs" can be automatically calculated using formula (1). When the source terminal is grounded and Vth is applied to the gate terminal, Vth is equal to Vgs. Therefore, a predetermined offset level Vth is applied to the gate terminal of transistor M5.

[0058] Here, the target drain current Id may be determined in consideration of, for example, power consumption, random noise, voltage gain, transient response, etc. of the comparators I1 and I2 .

[0059] exist Figure 2 In the embodiment, each pixel signal (for ease of understanding, Vpixel1 or Vpixel2) is fed to the negative input terminal (terminal 4) of the comparator I1 (or I2), and the comparator I1 (or I2) compares the pixel signal Vpixel1 (or Vpixel2) with the ramp reference voltage Vramp1. Another ramp reference voltage Vramp2 is used to apply a voltage to the gate terminal of the transistor M5. The reference voltage Vramp2 can be provided by a sample / hold circuit not shown in the drawings. The transistor M5 acts as a bias current source for the comparator I1 (or I2).

[0060] In the following, the basic operation of the comparator I1 / I2 is explained. The comparators I1 and I2 in this embodiment can be differential amplifiers. The comparators I1 and I2 have the same structure, including transistors M1 to M5. The transistors M1 and M2 can be NMOS differential input transistors driven by the current source transistor M5. The transistors M3 and M4 are used as load transistors for the input transistors M1 and M2. The transistors M3 and M4 can be understood as current mirror circuits.

[0061] In this embodiment, it is assumed that the sizes of transistors M1 and M2 are the same, and the sizes of transistors M3 and M4 are the same. When the gate terminal voltage of transistor M1 is higher than the gate terminal voltage of transistor M2, the drain current (IdM1) of transistor M1 is greater than the drain current (IdM2) of transistor M2. The drain current (IdM1) of transistor M1 is equal to the drain current (IdM3) of transistor M3. Since transistors M3 and M4 act as a current mirror circuit, the drain current of transistor M3 is mirrored to the drain current of transistor M4 (IdM3=IdM4).

[0062] The output current of the comparator I1 (or I2) is generated by the difference (IdM4-IdM2) between the drain current of the transistor M2 and the drain current of the transistor M4. Since the drain current from the transistor M2 is smaller than the drain current of the transistor M1, the drain current difference (IdM1-IdM2) between the transistors M1 and M2 exceeds the output current of the comparator I1 (or I2) at the terminal 5. The output terminal impedance can be designed to have a high value, and therefore, the output voltage can be increased accordingly.

[0063] exist Figure 2 In the embodiment of the present invention, each signal from a pixel (input pixel voltage Vpixel1 / Vpixel2) is fed to the negative input terminal (terminal 4) of comparator I1 (or I2). Comparator I1 (or I2) compares the pixel signal with a ramp reference voltage (Vramp1). The other ramp reference voltage (Vramp2) is used to provide a voltage to the gate terminal of transistor M5 (through transistor M7) through a sample / hold circuit. Transistor M5 acts as a bias current source for comparator I1 (or I2).

[0064] As described above, the predetermined offset level Vth can be designed as a voltage level of the bias current source transistor M5 to make the target bias current flow to the comparator I1 (or I2). When the ramp reference signal Vramp1 reaches the same level as the input pixel signal (Vpixel1 / Vpixel2), the comparator I1 (or I2) can have a voltage gain having a level sufficient to compare the input signal. The timing of this situation is Figure 3 The "T5" shown in the figure.

[0065] like Figure 2 As shown in FIG. 1 , the output from the comparator I1 (or I2) is supplied to the counter circuit I3 (or I4) through the terminal Vout1 (or Vout2). The counter circuit I3 (or I4) counts the number of pulses supplied from the terminal CLK while the output voltage level from the output of the comparator I1 (or I2) is maintained at a low level. This situation corresponds to Figure 3 In a similar manner, when the ramp reference voltage VRAMP1 is lower than the input pixel voltage Vpixel2, the counter circuit I4 counts the number of pulses applied through the terminal CLK. Therefore, the output value from the counter circuit I3 may be different from the output value of the counter circuit I4. For example, Figure 1 The logic circuit 150 shown in FIG. 1 can receive the output value from the counter circuit I3 (or I4 ) and generate an image using the output digital value.

[0066] exist Figure 3In the embodiment of the present invention, at the timing T1, when the pulse ΦPW becomes a high level, the switch SW1 is turned on. The common power supply VDD_common is provided to the local power supply line Vdd1 (or Vdd2) of the comparator I1 (or I2) through the switch SW1. The capacitor Cp as a storage capacitor is charged so as to have the same voltage as the common power supply VDD_common. Before "T1", the switch SW1 remains off, and the capacitor Cp having one ground terminal is not charged. The pulse ΦPW and other pulse signals can be provided from, for example, the logic circuit 150 or the T / G 140.

[0067] At the timing T1, the pulse ΦPW becomes a high level, and the switch SW1 is turned on accordingly. Then, from the timing T1 to T2, the capacitor Cp is charged. At the timing T2, the pulse ΦPW becomes a low level, the switch SW1 is turned off, and the local power line Vdd1 (or Vdd2) of the comparator I1 (or I2) is disconnected from the common power supply VDD_common. After T3, the comparator I1 (or I2) uses the power stored in the capacitor Cp to perform its operation. Therefore, for example, when the comparator I1 (or I2) performs a comparison function, the local power line of each comparator can be isolated from each other, and thus, the negative effects caused by the power line-related crosstalk between the comparators (I1, I2) can be reduced. Since the crosstalk of the power line is less and the power line is more stable, this can promote the improvement of the quality of the image obtained by the imaging device 100. In addition, the comparator I1 (or I2) consumes power only when the comparison operation is required, and thus, the power consumption of the imaging device 100 can be reduced. It should be noted that the imaging device 100 may include millions or more pixels and comparators. The power consumption of the entire circuit can be significantly reduced, which is very beneficial for devices that obtain high-resolution images.

[0068] At timing T3, the pulse Φ1 provided from the logic circuit 150 or the T / G 140 changes to a high level, and the transistors M8 and M10 in the comparator I1 (or I2) are turned on. G One terminal of the capacitor C is connected to the terminal 4 through the transistor M8, and the input pixel voltage Vpixel1 (or Vpixel2) is applied to the terminal 4. G The other terminal of is connected to the ground terminal of the comparator I1 (or I2) through the transistor M10.

[0069] exist Figure 3 , when the pulse Φ1 becomes high level, the pulse Φ applied to the gate terminal of the transistor M6 becomes high level at the same time. The transistor M6 having the grounded source terminal is turned on, and then the capacitor Cs connected to the drain terminal and the source terminal of the transistor M6 is discharged. The source terminal of the transistor M5 is connected to the capacitor Cs, and therefore, the voltage level of the source terminal of the transistor M5 becomes the ground level.

[0070] At timing T4, pulse Φ1 changes to a low level, and pulse Φ2 provided by logic circuit 150 or T / G 140 changes to a high level. Transistors M8 and M10 are turned off due to pulse Φ1 applied to their gate terminals. When transistor M8 is turned off, capacitor C G One terminal of is disconnected from terminal 4. When transistor M10 is turned off, capacitor C G The other terminal of is disconnected from the ground terminal of the comparator I1 (or I2).

[0071] At timing T4, the transistor M7 is turned on by the pulse Φ2 applied to the gate terminal of the transistor M7. G One terminal of is connected to terminal 2 through transistor M7. At timing T4, transistor M9 is turned on by pulse Φ2 applied to the gate terminal of transistor M9. Capacitor C G The other terminal of is connected to the gate terminal of transistor M5 through transistor M9. Transistor M5 acts as a current source in comparator I1. Since the ramp reference voltage Vramp2 is applied to terminal 2 and capacitor C G The charge in the capacitor C is stored. G The voltage difference between the two terminals of is kept constant, so it can be understood that the gate voltage of transistor M5 ( Figure 2 The “VGATE” shown in FIG. 1 can be calculated by the following formula “Vinit+Vth−Vpixel1”. In the case of comparator I2, the formula is “Vinit+Vth−Vpixel2”.

[0072] exist Figure 3 At the timing T5 shown in , the ramp reference voltage Vramp1 reaches the input pixel voltage Vpixel1. Since the voltage increase in the ramp reference voltage Vramp1 applied to the comparator I1 is obtained by "Vpixel1-Vinit", and the voltage difference between the ramp reference voltages Vramp1 and Vramp2 is Vth, the voltage applied to the gate terminal of the transistor M5 in the comparator I1 can be obtained according to the formula shown below.

[0073] {(Vinit+Vth–Vpixel1)+(Vpixel1–Vinit)}=Vth

[0074] This means that transistor M5 can pass a bias current large enough to drive comparator I1, and the output of comparator I1 goes high, and responds to changes in its input voltage with a certain amount of delay. These responses are Figure 3 In the figure, they are shown as “Vout1” and “ibias1”.

[0075] exist Figure 3 As shown in FIG. 1 , at T6, the ramp reference voltage Vramp1 reaches the input pixel voltage Vpixel2. Since the voltage increase in the ramp reference voltage Vramp1 of the comparator I2 is (Vpixel2–Vinit), where the voltage difference between the ramp reference voltages Vramp1 and Vramp2 is Vth, it can be understood that the voltage (VGATE) applied to the gate terminal of the transistor M5 included in the comparator I2 is obtained by the formula shown below. This is similar to the comparator I1.

[0076] {(Vinit+Vth–Vpixel2)+(Vpixel2–Vinit)}=Vth

[0077] This means that transistor M5 can pass a bias current large enough to drive comparator I2, and the output of comparator I2 goes high, and responds to changes in its input voltage with a certain amount of delay. These responses are Figure 3 In the figure, it is shown as “Vout2” and “ibias2”.

[0078] As described above, since the bias current of each comparator I1 / I2 flows only when the level of the ramp reference voltage Vramp1 is close to its input pixel signal level (Vpixel1 or Vpixel2), the power consumption of the comparators I1 and I2 is reduced compared to the comparators driven by a constant current source in some conventional SS ADCs. In addition, the timing at which the bias current flows in the comparators I1 / I2 can be automatically controlled by the input signal level and the ramp reference level (Vramp1 / Vramp2).

[0079] Figure 2 The capacitance of capacitor Cp shown in FIG. Figure 3 The comparator I1 / I2 is operated after T2 shown in FIG. At timing T2, the switch SW1 is opened and the comparator I1 / I2 is disconnected from the common power supply VDD_common. When implementing the comparison operation with the comparator I1 / I2, it may be helpful to have the following information: how the capacitance of the capacitor Cp can be estimated, and how the comparator (I1 / I2) disclosed above can correctly operate its local power supply line (Vdd1 / Vdd2) after being disconnected from the common power supply line (VDD_common).

[0080] Before estimating the capacitance of capacitor Cp (referred to as "Cp" here for ease of understanding), it can be understood that the total charge flowing into capacitor Cs during the comparison process of comparator I1 / I2 is less than Vth*Cs. For ease of understanding, in this formula, "Cs" represents the capacitance of capacitor Cs. For the correct operation of comparator I1 / I2, the minimum power supply voltage applied to capacitor Cs can be estimated based on various aspects such as voltage gain, input-output time delay, input offset voltage and output dynamic range of comparator I1 / I2. In order to achieve these specifications required to achieve ADC specifications, the drain-source voltage of each transistor in comparator I1 / I2 needs to be maintained at a voltage higher than the so-called saturation voltage (Vds_min) calculated according to the formula shown below.

[0081] Vds_min=Vgs–Vt

[0082] Therefore, by adding the saturation voltage Vds_min of each transistor M4, M2, and M5, the minimum power supply voltage (Vdd_min) can be estimated as shown below. In this embodiment, it is assumed that the transistors are of the same size.

[0083] Vdd_min=3*Vds_min

[0084] The capacitance of capacitor Cp needs to be greater than "Cs*Vth / (VDD_common-Vdd_min)". Based on this calculation, the minimum capacitance of capacitor Cp can be estimated. This minimum capacitance can reduce the power consumption of imaging device 100. In addition, when comparator I1 / I2 is placed in the chip, by using such calculation results, the silicon area shared by capacitor Cp can be minimized. Minimizing the silicon area can help reduce the cost of imaging device 100.

[0085] Hereinafter, a second embodiment is explained. Figure 4 Comparators I1 and I2 are shown. Figure 3 The reference numerals correspond to Figure 2 The comparator I1 / I2 includes transistors M1 to M10, wherein M1, M2, M5, M6, M7, M8, M9, M10 are PMOS transistors, and M3 and M4 are NMOS transistors, and also includes terminals 1 to 5, a capacitor C G , Cp and Cs and switch SW1. It should be noted that transistors M1 to M10 and Figure 2 I3 and I4 are counter circuits. CLK is provided from, for example, Figure 1 The clock signal of the T / G 140 or the logic circuit 150 shown in FIG. Figure 5 This is the timing diagram of the comparator I1 / I2 when it is operating. Figure 4 and Figure 5In FIG. 1 , it is assumed that the pixel signal level Vpixel1 is higher than the pixel signal level Vpixel2, the ramp reference voltage VRAMP2 is lower than the ramp reference voltage VRAMP1, and the ramp reference voltage VRAMP2 accurately tracks the ramp reference voltage VRAMP1 at a predetermined offset level (Vth). The ramp reference voltage VRAMP1 ramps down from a predetermined initial level (Vinit) at a constant rate. The operation of transistors M1 to M4 is similar to Figure 2 .

[0086] exist Figure 4 In the embodiment, each pixel signal / voltage (for ease of understanding, Vpixel1 and Vpixel2) is provided to the negative input terminal (terminal 4) of the comparator I1 (or I2), which compares the pixel signal Vpixel1 (or Vpixel2) with a ramp reference voltage (VRAMP1). Another ramp reference voltage (VRAMP2) can provide a voltage to the gate terminal of the transistor M5 through a sample / hold circuit, which acts as a bias current source for the comparator I1 (or I2).

[0087] As described above, "Vth" can be designed as a voltage level of the bias current source transistor (M5) to allow the bias current to flow to the comparator I1 (or I2). Therefore, the comparator I1 (or I2) can have a voltage gain that is large enough to compare the input signal when the ramp reference voltage Vramp1 reaches the same voltage as the input pixel signal Vpixel1 (or Vpixel2).

[0088] As described above, the counter circuit I3 (or I4) inputs the signal output from the comparator I1 (or I2). The counter circuit I3 (or I4) counts the number of pulses supplied through the CLK terminal while the output signal from the comparator I1 (or I2) remains at a low level.

[0089] exist Figure 5 In the embodiment, at the timing T1, the pulse ΦPW becomes a high level, and the switch SW1 is turned on accordingly. The common power supply VDD_common is provided to the local power supply line of each comparator (Vdd1, Vdd2) through the switch SW1, and the storage capacitor Cp is charged to have the same level as VDD_common. From the timing T1 to T2, the capacitor Cp is charged.

[0090] At timing T2, pulse φPW becomes low level and switch SW1 is turned off. The local power supply line (Vdd1 / Vdd2, at Figure 4The common power supply line (VDD_common) is disconnected from the common power supply line (VDD_common). At timing T3, the pulse Φ1, which has been at a high level and applied to the gate terminals of transistors M8 and M10, becomes a low level. Therefore, the transistors M8 and M10 in the comparator I1 (or I2) are turned on. The capacitor C G One terminal of is connected to terminal 4 through transistor M10. Terminal 4 receives input pixel signal Vpixel1 (or Vpixel2), and capacitor C G The other terminal of is connected to Vdd1 derived from the common power supply VDD_common through the transistor M8. After the timing T3, the comparator I1 (or I2) uses the power stored in the capacitor Cp to perform its operation. Therefore, for example, when the comparator I1 (or I2) performs the comparison function, the local power supply lines of each comparator can be isolated from each other, and therefore, the negative effects caused by the power supply line related crosstalk between the comparators (I1, I2) can be reduced.

[0091] When the pulse Φ1 which has been at a high level and applied to the gate terminals of the transistors M8 and M10 changes to a low level and the pulse Φres applied to the gate terminal of the transistor M6 changes to a low level, the transistors M8, M10 and M6 are turned on, the capacitor Cs connected to the transistor M6 is discharged, and the voltage applied to the source terminal of the transistor M5 reaches the same level as Vdd1 / Vdd2, that is, the same level as the common power supply VDD_common.

[0092] At timing T4, pulse Φ1 becomes high level, and pulse Φ2 becomes low level. Transistors M8 and M10 receiving pulse Φ1 at the gate node are turned off, and transistors M7 and M9 receiving pulse Φ2 at the gate node are turned on. Therefore, capacitor C G The two terminals of are disconnected from terminal 4 (through transistor M10) and the common power supply Vdd (through transistor M8) and connected to terminal 2 (through transistor M9) and the gate terminal of transistor M5 (through transistor M7). Transistor M5 is used as a current source for comparator I1 (or I2). The ramp reference voltage VRAMP2 is applied to terminal 2, so the capacitor C G The charge on the capacitor C is stored. G The voltage difference between the two terminals still exists, and the voltage on the gate terminal of the transistor M5 is calculated by “Vinit−Vth+Vdd−Vpixelx (x=1 or 2)”.

[0093] At timing T5, the ramp reference voltage VRAMP1 reaches the same voltage as the input pixel signal Vpixel1. The voltage of the ramp reference voltage VRAMP1 applied to the comparator I1 is reduced to (Vinit-Vpixel1), and the voltage difference between the ramp reference voltages VRAMP1 and VRAMP2 is Vth, so the gate terminal of the transistor M5 in the comparator I1 reaches the voltage shown below.

[0094] (Vinit–Vth+Vdd1–Vpixel1)–(Vinit–Vpixel1)=Vdd1–Vth

[0095] This formula indicates that transistor M5 can allow a bias current large enough to drive comparator I1 to flow, and the output signal of comparator I1 becomes a low level and responds to its input voltage change with a certain amount of delay time. Figure 5 In FIG. 1 , the responses are shown as “Vout1” and “ibias1”.

[0096] At timing T6, the ramp reference voltage VRAMP1 reaches the same voltage as the input pixel signal Vpixel2. The voltage of the ramp reference voltage VRAMP1 applied to the comparator I2 is reduced to (Vinit-Vpixel2), and the voltage difference between the ramp reference voltages VRAMP1 and VRAMP2 is Vth. The voltage applied to the gate terminal of the transistor M5 in the comparator I2 is calculated by the formula shown below.

[0097] (Vinit–Vth+Vdd2–Vpixel2)–(Vinit–Vpixel2)=Vdd2–Vth

[0098] This means that if transistor M5 can pass a bias current large enough to drive comparator I2, the output of comparator I2 goes low and responds to changes in its input voltage with a certain amount of delay. These responses are Figure 5 In the figure, it is shown as “Vout2” and “ibias2”.

[0099] It will be appreciated that imaging devices typically have a large number of pixels arranged along a plurality of columns and rows. Figure 3 and / or Figure 5 The timing diagrams included in can be applied to these pixels, and for example, the pixels on each column or row can be based on Figure 3 or Figure 5 The logic circuit 150 or the T / G 140 may output a signal and / or a pulse to control the comparators I1 / I2.

[0100] The above-described embodiments may have various advantages. First, for example, the bias current of each of the above-described comparators in the SS ADC depends on the voltage difference between the input signal and the ramp reference voltage applied to the comparator. The bias current of the comparator starts to flow only when the ramp reference voltage level is close to the input signal level. Therefore, the dynamic bias circuit is fully suitable for the SS ADC, and in addition, the power consumption of the SS ADC is reduced.

[0101] Next, for example, a local power supply line of each of the above-mentioned comparators in the SS ADC is connected to a common power supply (VDD_common) through a switch (SW1). Such separate local power supply lines have storage capacitors (Cp), respectively.

[0102] As described in the above embodiment, just before starting AD conversion, these switches ( SW1 ) are closed and at the same time, the local power supply line of each comparator corresponding to pixels arranged on one column is disconnected from the common (sensor) power supply line (VDD_common).

[0103] The supply current for each column comparator is provided by a storage capacitor (Cp) rather than by a common (sensor) power supply line (VDD_common). Therefore, negative effects, such as fluctuations generated in each local power supply line (Vdd1 / Vdd2), are not propagated to other local power supply lines, so that, for example, "banding noise" can be eliminated.

[0104] In addition to the above embodiments, the present application may have other aspects. For example, a first aspect is an imaging device, the imaging device comprising a comparator, a pixel and a control circuit, wherein the comparator comprises a switch, a first transistor and a first capacitor, wherein when the switch is turned on, the first capacitor is charged, and wherein after the switch is turned off, the comparator uses the power charged in the first capacitor to compare the pixel signal input from the pixel with the ramp signal input from the control circuit, and outputs an output signal.

[0105] A second aspect is the imaging device according to the above aspect, wherein the ramp signal includes a first ramp signal and a second ramp signal.

[0106] A third aspect is the imaging device according to the above aspect, wherein the ramp signal includes a predetermined voltage difference between the first ramp signal and the second ramp signal.

[0107] A fourth aspect is the imaging device according to the above aspect, wherein when the first ramp signal reaches the same level as the pixel signal, the comparator inverts the output signal.

[0108] A fifth aspect is the imaging device according to the above aspect, wherein when a voltage having the same voltage level as the predetermined voltage difference is applied to a gate terminal of the first transistor, the first transistor causes a bias current to flow to drive the comparator.

[0109] A sixth aspect is the imaging device according to the above aspect, wherein the capacitance of the first capacitor is large enough to drive the comparator.

[0110] A seventh aspect is the imaging device according to the above aspect, wherein when the second ramp signal reaches the same level as the pixel signal, the comparator completes its comparison operation.

[0111] An eighth aspect is the imaging device according to the above aspect, wherein when the switch is turned off, the comparator is disconnected from a common power supply of the imaging device.

[0112] A ninth aspect is the imaging device according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-up signals.

[0113] A tenth aspect is the imaging device according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-down signals.

[0114] The eleventh aspect is an imaging method for an imaging device including a comparator, a pixel and a control circuit, the imaging method comprising: when the switch of the comparator is turned on, charging the first capacitor of the comparator; after the switch is turned off, using the power charged in the first capacitor to compare the pixel signal input from the pixel with the ramp signal input from the control circuit; and outputting an output signal.

[0115] A twelfth aspect is the imaging method according to the above aspect, wherein the ramp signal includes a first ramp signal and a second ramp signal.

[0116] A thirteenth aspect is the imaging method according to the above aspect, wherein the ramp signal includes a predetermined voltage difference between the first ramp signal and the second ramp signal.

[0117] A fourteenth aspect is the imaging method according to the above aspect, wherein when the first ramp signal reaches the same level as the pixel signal, the comparator inverts the output signal.

[0118] A fifteenth aspect is the imaging method according to the above aspect, wherein when a voltage having the same voltage level as the predetermined voltage difference is applied to a gate terminal of the first transistor, the first transistor causes a bias current to flow to drive the comparator.

[0119] A sixteenth aspect is the imaging method according to the above aspect, wherein the capacitance of the first capacitor is large enough to drive the comparator.

[0120] A seventeenth aspect is the imaging method according to the above aspect, wherein when the second ramp signal reaches the same level as the pixel signal, the comparator completes its comparison operation.

[0121] An eighteenth aspect is the imaging method according to the above aspect, wherein when the switch is turned off, the comparator is disconnected from the common power supply of the imaging device.

[0122] A nineteenth aspect is an imaging method according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-up signals.

[0123] The twentieth aspect is the imaging method according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-down signals.

[0124] The embodiments disclosed above are examples, and it should be understood that the scope of the invention and the present application are not limited or restricted by such disclosures.

Claims

1. An imaging device, characterized in that: It includes a comparator, a pixel and a control circuit, wherein: The comparator comprises a switch, a first transistor and a first capacitor, wherein: When the switch is turned on, the first capacitor is charged, and wherein, After the switch is turned off, the comparator compares the pixel signal input from the pixel and the ramp signal input from the control circuit using the power charged in the first capacitor, and outputs an output signal.

2. The imaging device according to claim 1, characterized in that The ramp signal includes a first ramp signal and a second ramp signal.

3. The imaging device according to claim 2, characterized in that The ramp signal includes a predetermined voltage difference between the first ramp signal and the second ramp signal.

4. The imaging device according to claim 2, characterized in that: When the first ramp signal reaches the same level as the pixel signal, the comparator inverts the output signal.

5. The imaging device according to claim 1, characterized in that When a voltage having the same voltage level as a predetermined voltage difference is applied to a gate terminal of the first transistor, the first transistor causes a bias current to flow to drive the comparator.

6. The imaging device according to claim 1, characterized in that The capacitance of the first capacitor is large enough to drive the comparator.

7. The imaging device according to claim 2, characterized in that: When the second ramp signal reaches the same level as the pixel signal, the comparator completes its comparison operation.

8. The imaging device according to claim 1, characterized in that When the switch is open, the comparator is disconnected from the common power supply of the imaging device.

9. The imaging device according to claim 2, characterized in that: The first ramp signal and the second ramp signal are ramp-up signals.

10. The imaging device according to claim 2, characterized in that: The first ramp signal and the second ramp signal are ramp-down signals.

11. An imaging method for an imaging device comprising a comparator, a pixel and a control circuit, characterized in that: The imaging method comprises: When the switch of the comparator is turned on, charging the first capacitor of the comparator; After the switch is turned off, comparing a pixel signal input from the pixel with a ramp signal input from the control circuit using power charged in the first capacitor; Outputs the output signal.

12. The imaging method according to claim 11, characterized in that: The ramp signal includes a first ramp signal and a second ramp signal.

13. The imaging method according to claim 12, characterized in that: The ramp signal includes a predetermined voltage difference between the first ramp signal and the second ramp signal.

14. The imaging method according to claim 12, characterized in that: When the first ramp signal reaches the same level as the pixel signal, the comparator inverts the output signal.

15. The imaging method according to claim 11, characterized in that: When a voltage having the same voltage level as a predetermined voltage difference is applied to a gate terminal of a first transistor of the comparator, the first transistor causes a bias current to flow to drive the comparator.

16. The imaging method according to claim 11, characterized in that: The capacitance of the first capacitor is large enough to drive the comparator.

17. The imaging method according to claim 12, characterized in that: When the second ramp signal reaches the same level as the pixel signal, the comparator completes its comparison operation.

18. The imaging method according to claim 11, characterized in that: When the switch is open, the comparator is disconnected from the common power supply of the imaging device.

19. The imaging method according to claim 12, characterized in that: The first ramp signal and the second ramp signal are ramp-up signals.

20. The imaging method according to claim 12, characterized in that: The first ramp signal and the second ramp signal are ramp-down signals.

Images