Memory trace in analog computing systems

Abstract

Systems, apparatuses, and methods related to memory tracking in a simulation computing system are described. Static tracepoints can be inserted into a particular function as part of operating a simulation computing system. By executing the function containing the static tracepoints as part of a memory access request, the simulation computing system can receive information corresponding to both a virtual address and a physical address in a real computing system in which data corresponding to the memory access request is stored.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more specifically to apparatus, systems, and methods for memory tracking in analog computing systems. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), and Thyristor Random Access Memory (TRAM), among others. Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, and resistive variable memory, such as Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), and Magnetoresistive Random Access Memory (MRAM), such as Spin Torque Transfer Random Access Memory (STT RAM), among others.

[0003] A memory device may be coupled to a host computer (e.g., a host computing device) to store data, commands, and / or instructions for use by the host computer or electronic system during operation. For example, data, commands, and / or instructions may be transferred between the host computer and the memory device during operation of the computing or other electronic system. Summary of the Invention

[0004] According to one aspect of this application, a method for memory tracing in an analog computing system is provided. The method includes: generating data representing a function corresponding to a memory access operation, the function including one or more bits corresponding to a static tracking point; executing instructions containing the function as part of performing a memory access operation via an analog computing system to cause a physical computing system to perform the memory access operation; and determining a physical address corresponding to the memory access operation and a virtual address corresponding to the memory access operation in response to the execution of the instructions and the execution of the memory access operation.

[0005] According to another aspect of this application, a method for memory tracing in an analog computing system is provided. The method includes: receiving, via a host processing unit, an instruction instructing a memory access operation, wherein the instruction includes addressing information corresponding to an analog client computing system and a plurality of static tracing points; executing the instruction to perform the memory access operation; and transmitting data corresponding to the memory access operation, virtual address information corresponding to the memory access operation, and physical address information corresponding to the memory access operation to the analog client computing system.

[0006] According to another aspect of this application, an apparatus for memory tracing in a simulated computing system is provided. The apparatus includes: a first plurality of processing units configured to execute a virtualized operating system environment; and a first memory resource coupled to the plurality of processing units, wherein at least one of the first plurality of processing units will: determine whether a virtual address of the virtualized operating system environment is associated with a physical address of the first memory resource; in response to determining that the virtual address of the virtualized operating system environment is associated with the physical address of the first memory resource, generate a memory access request including instructions containing a physical address and one or more static trace points; execute the instructions to cause a second plurality of processing units coupled to a second memory resource to perform a memory access corresponding to the memory access request; and receive data corresponding to the memory access, virtual address information corresponding to a storage location in the second memory resource where the data is written, and physical address information corresponding to a storage location in the second memory resource where the data is written.

[0007] According to another aspect of this application, a system for memory tracing in an analog computing system is provided. The system includes: an analog processing unit associated with an analog client computing system; and a physical processing unit associated with a physical host computing system, the physical processing unit being communicatively coupled to the analog processing unit, wherein the analog processing unit will: generate instructions instructing a memory access operation, the instructions including addressing information corresponding to the analog client computing system and a plurality of static tracing points; perform an address translation operation within the analog client computing system to determine a client physical address location associated with the memory access operation; and transmit the instructions and information associated with the client physical address location to the physical processing unit, and wherein the physical processing unit will: in response to receiving the instructions, perform a memory access operation to retrieve data from memory resources of the physical host computing system; and transmit the data to the analog client computing system. Attached Figure Description

[0008] Figure 1A This is a functional block diagram of a computing system comprising a device having a memory system, according to several embodiments of the present disclosure.

[0009] Figure 1B This is another functional block diagram of a computing system comprising a device having a memory system, according to several embodiments of the present disclosure.

[0010] Figure 2 This is a functional block diagram of a computing system comprising devices according to several embodiments of the present disclosure, the computing system including an analog computing system and a real computing system.

[0011] Figure 3 This is a flowchart illustrating a translation mechanism for inserting static tracking points associated with memory tracking in an analog computing system, according to several embodiments of the present disclosure.

[0012] Figure 4 This is a flowchart illustrating an example method for simulating memory tracing in a computing system, according to several embodiments of the present disclosure.

[0013] Figure 5 This is a flowchart illustrating another example method for simulating memory tracing in a computing system, according to several embodiments of the present disclosure. Detailed Implementation

[0014] Systems, apparatus, and methods related to memory tracing in analog computing systems are described. Static trace points can be inserted into specific functions as part of operating the analog computing system. By executing a function containing static trace points as part of a memory access request, the analog computing system can receive information corresponding to both virtual and physical addresses in a real computing system, whereby data corresponding to the memory access request is stored.

[0015] The main memory (or "system memory") of a computing system is a fast, critical, shared memory resource that stores operating system software, software applications, and other information for the computing system's central processing unit (CPU) to perform tasks and / or operations with fast and direct access when needed. Main memory is typically provided in a computing system as an inherently volatile random access memory (RAM) device. The main memory of a computing system typically contains a contiguous range of addresses (e.g., the physical address space) that can be accessed independently by, for example, the CPU. However, the CPU typically treats the contiguous range of addresses associated with main memory as a range of virtual addresses corresponding to a specific physical address range in main memory.

[0016] To analyze the behavior of memory accesses in a computing system (e.g., memory accesses involving the computing system's main memory), memory tracing techniques can be employed within the computing system. Memory traces typically contain the execution of specific instructions, in addition to those executed during the execution of memory access operations, and can be used to enhance the understanding of the computing system's behavior. For example, memory tracing techniques can be used for debugging, taint checking, data flow tracing, workload analysis, software performance analysis, and / or computing system security analysis, among others. Furthermore, information gathered from memory traces can be used as input for microarchitecture simulation and / or modeling, providing insights into potential new computing architectures.

[0017] Memory tracing can be facilitated by inserting tracepoints into functions, commands, and / or instructions executed by the memory system. As used herein, the term "tracepoint" generally refers to a location in the computing application or memory system where data can be evaluated during the runtime of the computing system. When a tracepoint is reached during the execution of a function, command, and / or instruction, the value corresponding to any set of data can be targeted and collected at that point. Generally, a "static tracepoint" refers to a tracepoint inserted into a function or command at a specific point in time during the operation of the computing system.

[0018] However, memory tracing is a time-consuming and computationally intensive process. Several approaches to memory tracing include dynamic binary instrumentation (DBI) of code, system emulation, and / or hardware parsing tools, each with its drawbacks. Approaches involving DBI may only provide memory tracing data specific to a particular application (e.g., DBI-based approaches may not provide complete system access and / or emulation and therefore may not provide complete system memory tracing) and / or may only be able to return the virtual addresses associated with memory accesses to the simulated computing system. Approaches involving system emulation may not support certain operating system distributions and therefore may not provide complete system memory tracing. Hardware parsing tools may require physical access to memory pins and expensive resources such as interpolation and / or protocol analyzers to adequately perform memory tracing operations.

[0019] To address these and other drawbacks that exist in some ways, the embodiments described herein can allow full system memory tracing, wherein both the virtual and physical addresses associated with memory access (as well as other information) can be determined and provided to the analog computing system. Furthermore, the embodiments described herein can allow full system memory tracing for any operating system distribution executed by the analog computing system.

[0020] In some embodiments, a simulation computing system can be used to simulate a complete computing system (e.g., from the application layer down to the hardware). This simulation computing system can, for example, provide a fast simulator and virtualizer for hardware virtualization (e.g., QEMU). The simulation computing system can be a managed virtual machine monitor that can simulate the processor of a real computing system through dynamic binary translation and can provide a collection of different hardware and device models for the simulation computing system, thereby enabling the simulation computing system to run multiple guest operating systems. The simulation computing system can also be used with kernel-based virtual machines (KVM) to run virtual machines at near-native speeds (by leveraging hardware extensions such as Intel VT-x). The simulation computing system can also perform simulations for user-level processes, allowing applications compiled for one architecture to run on another.

[0021] The simulated computing system may be referred to herein as a “client system” or a variant thereof, while the computing system performing the simulation may be referred to as a “physical system” and / or a “real system” or a variant thereof. Specialized instructions may be generated by the client system and transmitted to the physical system as part of memory access operations. Specialized instructions may correspond to trace points (e.g., static trace points) that can be used to retrieve virtual and physical addresses of the physical system other than data involving memory access.

[0022] Memory tracing can be improved compared to the methods described above by providing a complete system simulation with the ability to execute specialized instructions to retrieve both the virtual and physical addresses associated with memory accesses. This, in turn, can improve the performance of the computing system by allowing for improved debugging, taint checking, data flow tracing, workload analysis, software performance analysis, and / or computing system security analysis, among other things.

[0023] In the following detailed description of this disclosure, reference is made to the accompanying drawings, which form a part of this disclosure, and the drawings illustrate by way of illustration one or more embodiments of this disclosure. These embodiments are described in sufficient detail to enable those skilled in the art to practice embodiments of this disclosure, and it should be understood that other embodiments may be utilized and process, electrical, and structural changes may be made without departing from the scope of this disclosure.

[0024] As used herein, designators such as “N”, “M”, etc., specifically relative to reference numerals in the drawings, indicate that a number of such specific features may be included. It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” may include both singular and plural designations. Additionally, “a number,” “at least one,” and “one or more” (e.g., a number of memory banks) may refer to one or more memory banks, while “more” is intended to mean more than one such thing.

[0025] Furthermore, the words “may” and “can” are used throughout this application in a permissive sense (i.e., possible, able) rather than in a mandatory sense (i.e., must). The term “comprising” and its derivatives mean “including but not limited to”. Depending on the context, the term “coupled / coupling” means physically connected, directly or indirectly, or used for accessing and moving (transmitting) commands and / or data. Depending on the context, the terms “data” and “data value” are used interchangeably herein and may have the same meaning.

[0026] The diagrams in this document follow a numbering convention, where the first one or more digits correspond to the diagram number, and the remaining digits identify the elements or components within the diagram. Similar elements or components between different diagrams can be identified by using similar numbers. For example, 107 can be referenced. Figure 1A Component "107" in the text, and similar components can be found in Figure 2 Reference numeral is 207. A single element number may typically refer to a group or number of similar elements or components herein. For example, multiple reference elements 116-1 to 116-N may generally be referred to as 116. As will be understood, elements shown in the various embodiments herein may be added, interchanged, and / or removed to provide several additional embodiments of this disclosure. Furthermore, the scale and / or relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of this disclosure and should not be considered limiting in any way.

[0027] Figure 1A This is a functional block diagram of a computing system 100 comprising a device having a memory system 104, according to several embodiments of the present disclosure. As used herein, "device" may refer to, but is not limited to, any of a variety of structures or combinations thereof, such as, for example, a circuit or circuit system, one or more dies, one or more modules, one or more devices, or one or more systems. Figure 1AIn the embodiments described herein, memory devices 116-1 to 116-N may include one or more memory modules (e.g., single in-line memory modules, dual in-line memory modules, etc.). Memory devices 116-1 to 116-N may include volatile memory and / or non-volatile memory. In several embodiments, memory devices 116-1 to 116-N may include multi-chip devices. Multi-chip devices may include several different memory types and / or memory modules. For example, a memory system may contain non-volatile or volatile memory on any type of module.

[0028] In some embodiments, memory system 104 may be a compute high-speed link (CXL) compliant memory system (e.g., the memory system may include a PCIe / CXL interface). CXL is a high-speed central processing unit (CPU) to device and CPU to memory interconnect designed to accelerate the performance of next-generation data centers. CXL technology maintains memory coherence between the CPU memory space and the memory on the attached device, allowing resource sharing to achieve higher performance, reduced software stack complexity, and lower overall system cost.

[0029] CXL is designed as an industry-open standard interface for high-speed communications, as accelerators are increasingly used to supplement CPUs to support emerging applications such as artificial intelligence and machine learning. Built on the Peripheral Component Interconnect High Speed ​​(PCIe) infrastructure, CXL technology leverages PCIe physical and electrical interfaces to provide advanced protocols in areas such as input / output (I / O) protocols, memory protocols (e.g., initially allowing hosts to share memory with accelerators), and coherence interfaces.

[0030] Memory devices 116-1 to 116-N may provide main memory for computing system 100 or may be used as additional memory or storage devices throughout computing system 100. Memory devices 116-1 to 116-N may comprise one or more arrays of memory cells, such as volatile and / or non-volatile memory cells. For example, the array may be a flash array with a NAND architecture. Embodiments are not limited to a particular type of memory device. For example, the memory device may comprise RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, etc.

[0031] In embodiments where memory devices 116-1 to 116-N include persistent or non-volatile memory, memory devices 116-1 to 116-N may be flash memory devices, such as NAND or NOR flash memory devices. However, embodiments are not limited thereto, and memory devices 116-1 to 116-N may include other non-volatile memory devices, such as non-volatile random access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM), "emerging" memory devices, such as ferroelectric RAM devices including ferroelectric capacitors that can exhibit hysteresis characteristics, 3D crosspoint (3D XP) memory devices, etc., or combinations thereof.

[0032] As an example, a ferroelectric RAM device may include a ferroelectric capacitor and may perform bit storage based on the voltage or amount of charge applied thereto. In such an example, relatively small and relatively large voltages allow the ferroelectric RAM device to exhibit properties similar to ordinary dielectric materials (e.g., dielectric materials with a relatively high dielectric constant), but at various voltages between such relatively small and large voltages, the ferroelectric RAM device may exhibit polarization reversal that produces nonlinear dielectric behavior.

[0033] As another example, a 3D XP array of non-volatile memory can perform bit storage based on changes in volume resistance by combining with a stackable cross-mesh data access array. Furthermore, compared to many flash-based memories, 3D XP non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without pre-erasing them.

[0034] like Figure 1A As shown, memory system 104 includes controller 106. In some embodiments, controller 106 may be a media controller, such as a non-volatile memory high-speed (NVMe) controller. For example, controller 106 may be configured to perform operations such as copying, writing, reading, error correction, etc., for memory devices 116-1 to 116-N. Additionally, controller 106 may include dedicated circuitry and / or instructions to perform the various operations described herein. That is, in some embodiments, controller 106 may include circuitry and / or instructions that can be executed to control the movement of data and / or addresses associated with data between memory devices 116-1 to 116-N and host 102.

[0035] like Figure 1AAs described, host 102 can be coupled to memory system 104 via interface 103. Interface 103 can be any type of communication path, bus, or similar that allows information to be transferred between host 102 and memory system 104. Non-limiting examples of the interface can include a Peripheral Component Interconnect (PCI) interface, a Peripheral Component Interconnect High Speed ​​(PCIe) interface, a Serial Advanced Technology Attachment (SATA) interface, and / or a Miniature Serial Advanced Technology Attachment (mSATA) interface, etc. However, in at least one embodiment, interface 103 is a PCIe 5.0 interface conforming to the Compute High Speed ​​Link (CXL) protocol standard. Therefore, in some embodiments, interface 103 can support a transfer rate of at least 32 gigabits per second.

[0036] In some embodiments, interface 103 may be configured to selectively transmit signaling according to multiple protocols. For example, signaling may be selectively transmitted via interface 103 according to a caching protocol in which data is transferred between the host and memory system 104 and a memory protocol in which data is transferred between the host and memory devices 116-1 to 116-N. In some embodiments, a caching protocol may be invoked to efficiently cache data associated with host memory 105 according to a request and response manner. In contrast, a memory protocol may be invoked to provide access to memory devices 116-1 to 116-N via read / write commands by the host, wherein the host processor (e.g., CPU 107) acts as the master device and the memory devices 116-1 to 116-N act as slave devices.

[0037] In several embodiments, memory devices 116-1 to 116-N may reside on memory system 104; however, as Figure 1B As illustrated herein, the embodiments are not so limited, and in some embodiments, memory devices 116-1 to 116-N may be external to memory system 104. As used herein, the term "resides on" means something is physically located on a particular component. For example, "resides on memory system 104" for memory devices 116-1 to 116-N means that memory devices 116-1 to 116-N are physically within memory system 104. The term "resides on" may be used interchangeably herein with other terms such as "deployed on" or "located on".

[0038] Host 102 may include host memory 105 and central processing unit (CPU) 107. Host 102 may be a host system, such as a personal laptop computer, desktop computer, digital camera, smartphone, memory card reader and / or Internet of Things enabled device, as well as various other types of host, and may include memory access means, such as a processor (or processing device). Those skilled in the art will understand that "processor" may mean one or more processors, such as a parallel processing system, several coprocessors, etc.

[0039] Host 102 may include a system motherboard and / or backplane, and may include several processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry). System 100 may include separate integrated circuits, or host 102, memory system 104, controller 106, and / or memory devices 116-1 to 116-N may be on the same integrated circuit. For example, system 100 may be a server system and / or a high-performance computing (HPC) system and / or a portion thereof. Although in Figure 1A The examples shown illustrate systems with a von Neumann architecture, but embodiments of this disclosure can be implemented in a non-von Neumann architecture that may not include one or more components typically associated with a von Neumann architecture (e.g., CPU, ALU, etc.).

[0040] Figure 1A Embodiments may include additional circuitry not described to avoid obscuring the embodiments of this disclosure. For example, controller 106 may include address circuitry to latch address signals provided on I / O connections via I / O circuitry. Address signals can be received and decoded by row decoders and column decoders to access memory devices 116-1 to 116-N. Those skilled in the art will understand that the number of address input connections may depend on the density and architecture of memory devices 116-1 to 116-N.

[0041] Figure 1B This is another functional block diagram, according to several embodiments of the present disclosure, in the form of a computing system 100 including a device having a memory system 104. (The last sentence appears to be incomplete and possibly contains errors.) Figure 1A Compared to the embodiments shown, in Figure 1B In the embodiments described herein, memory devices 116-1 to 116-N are external to memory system 104.

[0042] Figure 2 This is a functional block diagram of a computing system 200 comprising devices, according to several embodiments of the present disclosure, the computing system including an analog computing system 220 and a real computing system 221. Figure 2As shown, the computing system 200 includes an analog computing system 220 and a real computing system 221. The analog computing system 220 and the real computing system 221 can communicate via a translation component 229.

[0043] As used herein, a “simulated computing system” or “client computing system” generally refers to a computing system that provides virtual hosting of one or more virtual computers on a single computing system. A simulated computing system can virtualize one or more complete computing systems, including peripheral devices associated with the virtualized computing system. In some embodiments, a simulated computing system can support multiple computing architectures and multiple instruction sets. A simulated computing system can provide a complete simulation of a real computing system from the application layer to the hardware level. In some embodiments, a simulated computing system may be equipped with processing (e.g., compute) resources and memory resources and may have its own virtual address space.

[0044] As used herein, "real computing system" generally refers to a "host" computing system that includes physical processing (e.g., computing) resources and memory resources. In some embodiments, a simulated computing system may be equipped with these physical resources. A real computing system may run a host operating system (e.g., Linux, Windows, etc.) on which applications associated with the simulated computing system can run.

[0045] Translation component 229 may include hardware and / or executable instructions that can translate signals and / or commands between analog computing system 220 and real computing system 221. In some embodiments, translation component 229 may include a code generator (e.g., a QEMU microcode generator) that can incorporate computational code compilers into other tasks performed by analog computing system 220 at runtime.

[0046] In some embodiments, translation component 229 may execute load / store instructions (e.g., load / store instructions associated with a simulated computing system and / or load / store instructions associated with a real computing system). As used herein, the term “load / store instruction” generally refers to instructions, commands, and / or signaling that instruct the execution of operations to read (“load”) data and / or write (“store”) data.

[0047] Additionally, the acceleration circuitry system can perform translation operations to, for example, translate semantics used by analog computing system 220 into semantics used by real computing system 221. As used herein, "semantics" generally refers to the format of an instruction, command, or signal that refers to the meaning of a reference instruction, command, or signal. For example, an instruction that can be understood by analog computing system 220 to perform an arbitrary operation "0" may not be understood by real computing system 221, and vice versa. By translating the semantics associated with analog computing system 220 into semantics that can be understood by real computing system 221, the real computing system can understand the instruction corresponding to the execution of an arbitrary operation "0".

[0048] like Figure 2 As shown, the analog computing system 220 may include an analog processor (e.g., an analog CPU 228) and an analog main memory 203. The analog computing system 220 may further include a memory management unit (MMU) 222, a translation back buffer (TLB) 224, and / or an analog address translation block 226. In some embodiments, the MMU 222 may be a software MMU that associates virtual addresses of the analog computing system 220 with physical addresses in the TLB 224 and / or the analog main memory 203.

[0049] In addition, such as Figure 2 As shown, the real computing system 221 may include a real processor (e.g., a real CPU 207) and a real main memory 205. The real computing system 221 may further include a memory management unit (MMU) 223, a translation back buffer (TLB) 225, and / or a real address translation block 227. In some embodiments, the MMU 222 may associate virtual addresses of the real computing system 221 with physical addresses in the TLB 225 and / or the real main memory 205.

[0050] In some embodiments, the computing system 200 may operate as follows: First, the emulated CPU 228 may execute a load / store instruction instructing a memory access request relating to the real computing system 221. The load / store instruction may contain a virtual address of the emulated computing system 220. Second, the emulated computing system 220 may perform operations to search the TLB 224 (e.g., using the emulated address translation block 226) to locate the physical address associated with the virtual address of the emulated computing system 220. If the virtual address is not found in the TLB 224 (e.g., if a "miss" occurs when locating the virtual address in the TLB 224), then operations to locate and / or retrieve the physical address associated with the virtual address of the emulated computing system 220 may be performed. This may be combined with the following... Figure 3If a virtual address is not found in TLB 224, then one or more trace points can be inserted into a function (e.g., a load / store function).

[0051] Load / store functions (including trace points) can be passed to the acceleration circuitry system and translated into a set of semantics that can be understood by the real computing system 221. The translated load / store instructions can then be passed to the real computing system 221. The real computing system 221 (e.g., the real CPU 207 of the real computing system 221) can execute instructions to retrieve a virtual address associated with the real computing system 221 corresponding to data involving a memory access request. Next, the real computing system 221 can perform an operation to search the TLB 225 (e.g., using the real address translation block 227) to locate the physical address associated with the virtual address of the real computing system 220. If the virtual address is not found in the TLB 225 (e.g., if a "miss" occurs when locating the virtual address in the TLB 225), then operations to locate and / or retrieve the physical address associated with the virtual address of the real computing system 221 can be performed.

[0052] Once the physical address corresponding to the data involved in the memory access request is located, the data can be retrieved (e.g., from the real main memory 205) and returned to the analog computing system 220. As described in more detail herein, due to the insertion of the trace point discussed above, both the virtual address in the real computing system 221 and the physical address in the real computing system 221 corresponding to the data can be returned to the analog computing system 220.

[0053] In a non-limiting example, the device (e.g., computing system 200) may include a first number of processing units (e.g., emulated CPU 228), which may be referred to as a "first processing unit" for simplicity. The first processing unit may execute a virtualized operating system environment (e.g., emulated computing system 220). In at least one embodiment, the virtualized operating system environment may be a Quick Emulation (QEMU) computing environment. A first memory resource (e.g., emulated main memory 203) may be coupled to the first memory resource. Continuing this example, the first processing unit may determine whether a virtual address of the virtualized operating system environment is associated with a physical address of the first memory resource.

[0054] In response to determining that a virtual address of the virtualized operating system environment is associated with a physical address of a first memory resource (e.g., an address in emulated main memory 203), the first memory resource may generate a memory access request including instructions containing a physical address and one or more static trace points. In some embodiments, the instructions may include virtual address information and / or physical address information associated with the first processing unit and the first memory resource. The first processing unit may subsequently execute instructions to cause a second number of processing units (e.g., a real CPU 207) coupled to a second memory resource (e.g., real main memory 205) to perform a memory access corresponding to the memory access request; for simplicity, the second number of processing units may be referred to as the "second processing unit".

[0055] In some embodiments, the first processing unit and the second processing unit are communicatively coupled to each other via a Fast Simulation Application Programming Interface (FSAPI), and instructions and / or commands can be transmitted between the first processing unit and the second processing unit via the Fast Simulation API and / or via an application translation layer associated with the computing system 200.

[0056] After the memory access is executed, the first processing unit may receive data corresponding to the memory access, virtual address information corresponding to the storage location in the second memory resource where data is written, and physical address information corresponding to the storage location in the second memory resource where data is written. However, the embodiments are not limited to this, and in some embodiments, the first processing unit may receive information corresponding to the type of data access operation (e.g., load / store operation, etc.), the data access size, the timestamp corresponding to the data access, information corresponding to the translation back buffer 224 with addresses contained therein (e.g., "TLB hit"), information corresponding to the translation back buffer 224 with inaccurate addresses contained therein (e.g., "TLB miss"), etc.

[0057] The first processing unit may, in response to determining that the virtual address of the virtualized operating system environment is not associated with the physical address of the first memory resource, perform an operation to locate the physical address within the first memory resource invoked by the memory access request. The first processing unit may subsequently update the physical address in the translation back buffer 224 coupled to the first memory resource.

[0058] In another non-limiting example, the system (e.g., computing system 200) may include an analog processing unit 228 associated with an analog client computing system 220. The system may further include a physical processing unit (e.g., a real CPU 207) associated with a physical host computing system (e.g., a real computing system 221) communicatively coupled to the analog processing unit 228. The analog processing unit 228 may generate instructions instructing memory access operations, the instructions containing addressing information corresponding to the analog client computing system 220 and a plurality of static trace points.

[0059] The analog processing unit 228 can perform address translation operations within the analog client computing system to determine the client physical address location associated with the memory access operation and transmit the instructions and information associated with the client physical address location to the physical processing unit. In some embodiments, the analog processing unit 228 can transmit the instructions and information associated with the client physical address location to the physical processing unit via an application programming interface.

[0060] In response to receiving an instruction, the physical processing unit may perform a memory access operation to retrieve data from the memory resources of the physical host computing system (e.g., main memory 205) and transfer the data to the analog client computing system. In some embodiments, the analog processing unit 228 may determine the physical address and virtual address associated with the physical host computing system corresponding to the data retrieved during the execution of the memory access operation.

[0061] Continuing this example, before the execution of the address translation operation within the simulated client computing system 220, the simulation processing unit 228 may perform a lookup operation in the translation backup buffer 224 of the simulated client computing system 220 to determine the client virtual address associated with the memory access operation. In some embodiments, the simulation processing unit 228 may perform a translation operation to translate the load / store command associated with the instruction before transmitting the instructions and information associated with the client physical address location to the physical processing unit.

[0062] In some embodiments, the physical processing unit may perform address translation operations within the physical host computing system to determine the physical host computing system virtual address location associated with a memory access operation. In some embodiments, the physical processing unit may perform address translation operations within the physical host computing system to determine the physical host computing system physical address location associated with a memory access operation.

[0063] Figure 3This is a flowchart 330 illustrating a translation mechanism for inserting static trace points associated with memory tracing in a simulated computing environment, according to several embodiments of this disclosure. At operation 331, a client virtual address can be retrieved. In the embodiments shown, in response to a client CPU (e.g., as described herein), Figure 2 The simulated CPU described herein generates instructions to retrieve the client virtual address. The client virtual address can be stored in conjunction with the client computing system (e.g., in the example described herein). Figure 2 The translation backup buffer associated with the simulation computing system 220 described herein (e.g., in this document) Figure 2 In TLB 224 as described in the document.

[0064] At operation 332, a virtual TLB index and tag corresponding to the client's virtual address can be determined. The virtual TLB index can correspond to a location in the TLB where the client's virtual address is expected to be stored, while the tag can associate each entry in the TLB with an address space associated with the client computing system.

[0065] At operation 333, the tag and the virtual TLB index can be compared to determine whether a match has occurred between the tag and the virtual TLB index. That is, in some embodiments, a determination can be made regarding whether the client virtual address resides in the space within the virtual TLB index corresponding to the tag. If a match occurs between the tag and the virtual TLB index, then at operation 334, the value corresponding to the real computing system (e.g., in this document) can be extracted. Figure 2 The data associated with the virtual address of the real computing system 221 described herein.

[0066] In response to retrieving virtual addresses at the real computing system (e.g., in this paper), the real computing system (e.g., in this paper) Figure 2 The actual CPU 207 described herein can trigger the execution of an address translation operation to determine the physical address where the requested data is stored (e.g., in this document). Figure 2 (The physical address in the actual main memory 205 as described herein). Data can then be retrieved from the memory of the actual computing system and transferred to the client computing system. In some embodiments, data can be transferred to the client computing system via an application programming interface.

[0067] If it is determined that the tag and the virtual TLB index do not match, then at operation 335, the virtual TLB can be updated so that the tag corresponds to the correct virtual address in the TLB, or vice versa. Once the virtual TLB index and / or tag has been updated to reflect the correct location of the client virtual address in the TLB, then at operation 336, the client computing system can execute instructions to invoke an auxiliary function. As used herein, the term "auxiliary function" generally refers to a function invoked during the execution of the translated target code phase. Auxiliary functions can be mixed in during the translation from target code to TCG code. Furthermore, auxiliary functions can assist in target code translation. Additionally, auxiliary functions can provide high-level functionality and library access in the running host (e.g., client computing system and / or real computing system).

[0068] In some embodiments, as described herein, one or more trace points (e.g., static trace points) may be inserted into the helper function to provide memory tracing. For example, one or more trace points may be inserted into the helper function prior to the reception of the requested data at operation 333. Thus, the virtual and physical addresses associated with the memory access request can be determined and returned to the client computing system along with the requested data.

[0069] Figure 4 This is a flowchart illustrating an example method 440 for simulating memory tracing in a computing environment, according to several embodiments of the present disclosure. Method 440 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 440 is performed by... Figure 1A Or the controller 106 described in 1B may be used. However, the embodiments are not limited, and in some embodiments, method 440 is performed by... Figure 2 The computing system 200 described herein is executed. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the described embodiments should be understood as examples only, and the described processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0070] At block 442, method 440 may include generating data representing a function corresponding to a memory access operation, the function including one or more bits corresponding to a static tracking point. In some embodiments, the function may include a fast simulator load / store command.

[0071] At block 444, method 440 may include instructions for performing included functions as part of performing memory access operations. In some embodiments, method 440 may include simulating a computing system (e.g., as described herein). Figure 2 The analog computing system 220 described herein executes instructions to cause the physical computing system to perform memory access operations.

[0072] At block 446, method 440 may include determining a physical address corresponding to a memory access operation and a virtual address corresponding to a memory access operation in response to the execution of an instruction and the execution of a memory access operation. In some embodiments, method 440 may include determining the physical address corresponding to a memory access operation based at least in part on information stored in a translation back buffer associated with the analog computing system.

[0073] In some embodiments, method 440 may include a simulation computing system and a physical computing system coupled to execution instructions (e.g., as described herein). Figure 2 The translation component of the real computing system 221 described herein (e.g., in this paper) Figure 2 The translation component 229 described herein receives the executed instructions. Method 440 may further include using the translation component to perform operations to translate load / store commands associated with the analog computing system into load / store commands associated with the physical computing system and / or to transmit the executed instructions and the load / store commands associated with the physical computing system to the physical computing system.

[0074] Figure 5 This is a flowchart illustrating another example of a method 550 for simulating memory tracing in a computing environment, according to several embodiments of the present disclosure. Method 440 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 440 is performed via… Figure 1A Or the controller 106 described in 1B may be used. However, the embodiments are not limited, and in some embodiments, method 440 is performed by... Figure 2 The computing system 200 described herein is executed. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the described embodiments should be understood as examples only, and the described processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0075] At block 552, method 550 may include receiving instructions via a host processing unit instructing a memory access operation, wherein the instructions contain instructions corresponding to an analog client computing system (e.g., as described herein). Figure 2 The simulation computing system 220 described herein and the addressing information of multiple static tracking points.

[0076] At block 554, method 550 may include execution instructions to perform a memory access operation. In some embodiments, method 540 may include receiving instructions and transferring data via an application programming interface, as described above.

[0077] At block 556, method 550 may include transmitting data corresponding to a memory access operation, virtual address information corresponding to the memory access operation, and physical address information corresponding to the memory access operation to a simulated client computing system. In some embodiments, the virtual address information corresponding to the memory access operation and / or the physical address information corresponding to the memory access operation may be determined at least in part based on information corresponding to at least one of a plurality of static trace points. In some embodiments, the virtual address information corresponding to the memory access operation and / or the physical address information corresponding to the memory access operation may correspond to data residing in a host processing unit (e.g., as described herein). Figure 2 The CPU 207 described herein is deployed on the computing system's memory resources (e.g., in this document). Figure 2 The address location in the actual main memory (205) described in the document.

[0078] Method 540 may further include using a translation component coupled to the host processing unit and the analog client computing system (e.g., as described herein) before receiving instructions instructing memory access operations. Figure 2 The translation component 229 described herein translates virtual load / store instructions into host load / store instructions.

[0079] In some embodiments, method 540 may include determining, at least in part, the physical address of data relating to a memory access operation based on information stored in a translation back buffer associated with the analog client computing system, the physical address being associated with the analog client computing system and corresponding to the memory access operation.

[0080] While specific embodiments have been described and illustrated herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of this disclosure. It should be understood that the above description is illustrative rather than restrictive. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the above description. The scope of one or more embodiments of this disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of this disclosure should be determined by reference to the appended claims and the full scope of equivalents to which such claims are given.

[0081] In the foregoing detailed embodiments, some features are grouped together in a single embodiment for the purpose of simplifying this disclosure. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than are expressly stated in each claim. In fact, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is, in itself, a separate embodiment.

Claims

1. A method for memory tracing in an analog computing system, comprising: Generate data representing a function corresponding to a memory access operation, the function including one or more bits corresponding to a static tracking point; The analog computing system (220) executes instructions containing the aforementioned functions as part of the memory access operation, so that the physical computing system (221) performs the memory access operation. as well as In response to the execution of the instruction and the execution of the memory access operation, the physical address corresponding to the memory access operation and the virtual address corresponding to the memory access operation are determined.

2. The method of claim 1, further comprising determining the physical address corresponding to the memory access operation based at least in part on information stored in a translation backup buffer (224) associated with the analog computing system (220).

3. The method according to any one of claims 1 to 2, further comprising: The executed instructions are received by a translation component (229) coupled to the simulation computing system (220) and the physical computing system (221) that execute the instructions; The translation component is used to perform operations to translate load / store commands associated with the simulation computing system into load / store commands associated with the physical computing system; as well as The executed instructions and the load / store commands associated with the physical computing system are transmitted to the physical computing system.

4. The method according to any one of claims 1 to 2, further comprising determining, in response to the execution of the instruction and the execution of the memory access operation, the type of the operation performed to access the data, the access size of the data, the timestamp corresponding to the access of the data, information corresponding to a translation back buffer (224) having an exact address contained therein, or information corresponding to the translation back buffer having an inaccurate address contained therein, or any combination thereof.

5. A method for memory tracing in an analog computing system, comprising: The host processing unit (107, 207) receives instructions indicating memory access operations, wherein the instructions contain addressing information corresponding to the analog client computing system (220) and a plurality of static tracking points; Execute the instructions to perform the memory access operation; as well as The data corresponding to the memory access operation, the virtual address information corresponding to the memory access operation, and the physical address information corresponding to the memory access operation are transmitted to the simulated client computing system.

6. The method of claim 5, wherein the virtual address information corresponding to the memory access operation and the physical address information corresponding to the memory access operation are determined at least in part based on information corresponding to at least one of the plurality of static trace points.

7. The method of claim 5, further comprising translating the virtual load / store instruction into a host load / store instruction using a translation component (229) coupled to the host processing unit and the emulated client computing system before receiving the instruction instructing the memory access operation.

8. The method according to any one of claims 5 to 7, wherein the virtual address information corresponding to the memory access operation and the physical address information corresponding to the memory access operation correspond to address locations in memory resources (105, 205) residing on the computing system (102, 221) on which the host processing unit is deployed.

9. A device for memory tracking in an analog computing system, comprising: A first plurality of processing units (228) configured to execute a virtualized operating system environment (220); as well as A first memory resource (203) is coupled to the plurality of processing units, wherein at least one of the first plurality of processing units will: Determine whether the virtual address of the virtualized operating system environment is associated with the physical address of the first memory resource; In response to determining that the virtual address of the virtualized operating system environment is associated with the physical address of the first memory resource, a memory access request is generated including instructions containing the physical address and one or more static trace points. The instructions are executed such that a second plurality of processing units (207) coupled to the second memory resource (205) perform a memory access corresponding to the memory access request; as well as The system receives data corresponding to access in the memory, virtual address information corresponding to a storage location in a second memory resource where the data is written, and physical address information corresponding to the storage location in the second memory resource where the data is written.

10. The apparatus of claim 9, wherein the first plurality of processing units will: In response to determining that the virtual address of the virtualized operating system environment is not associated with the physical address of the first memory resource: Perform operations to locate the physical address within the first memory resource invoked via the memory access request; and Update the physical address in the translation backup buffer coupled to the first memory resource.

11. The apparatus according to any one of claims 9 to 10, wherein the first plurality of processing units are configured to: A virtualized operating system environment that performs the simulation; and Receive information corresponding to the access size of the data.

12. A system for memory tracking in an analog computing system, comprising: A simulation processing unit (228) is associated with a simulation client computing system (220); as well as A physical processing unit (207), associated with a physical host computing system (221), is communicatively coupled to the simulation processing unit, wherein the simulation processing unit will: Generate instructions that indicate memory access operations, the instructions containing addressing information corresponding to the simulated client computing system and multiple static tracking points; Perform an address translation operation within the simulated client computing system to determine the client physical address location associated with the memory access operation; and The instructions and information associated with the customer's physical address location are transmitted to the physical processing unit, wherein the physical processing unit will: In response to receiving the instruction, the memory access operation is performed to retrieve data from the memory resources of the physical host computing system; as well as The data is transmitted to the simulated client computing system.

13. The system of claim 12, wherein prior to the execution of the address translation operation within the simulated client computing system, the simulation processing unit performs a lookup operation in the translation backup buffer (224) of the simulated client computing system to determine the client virtual address associated with the memory access operation.

14. The system of claim 12, wherein the analog processing unit performs a translation operation to translate the load / store command associated with the instruction before transmitting the instruction and information associated with the client's physical address location to the physical processing unit.

15. The system according to any one of claims 12 to 14, wherein the simulation processing unit transmits the instructions and information associated with the client's physical address location to the physical processing unit via an application programming interface.

16. The system according to any one of claims 12 to 14, wherein the physical processing unit performs an address translation operation within the physical host computing system to determine the physical host computing system virtual address location associated with the memory access operation.

17. The system according to any one of claims 12 to 14, wherein the instructions comprise the type of operation performed to access the data, the size of the data access, a timestamp corresponding to the data access, information corresponding to a translation back buffer having an exact address contained therein, or information corresponding to a translation back buffer having an inaccurate address contained therein, or any combination thereof.

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