Performing refresh operations on memory cells

Abstract

The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. Embodiments include a memory having a group of memory cells and one or more additional memory cells whose data states indicate whether to refresh the group of memory cells; and circuitry configured to: apply a first voltage pulse to the group of memory cells to sense data states of the memory cells of the group; apply a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense data states of the one or more additional memory cells while the first voltage pulse is applied to the group of memory cells; and determine whether to perform a refresh operation on the group of memory cells based on the sensed data states of the one or more additional memory cells.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more specifically, to performing refresh operations on memory cells. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuit systems and / or external removable devices in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and may include random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory provides persistent data by retaining stored data when no power is supplied and may include NAND flash memory, NOR flash memory, read-only memory (ROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and programmable conductive memory, etc.

[0003] Memory devices can be used as volatile and non-volatile memory for a wide range of electronic applications requiring high memory density, high reliability, and low power consumption. Non-volatile memory can be used in, for example, personal computers, Memory Sticks, solid-state drives (SSDs), digital cameras, cellular phones, portable music players and movie players such as MP3 players, and other electronic devices.

[0004] A variable resistance memory device may include a variable resistance memory cell that can store data based on the resistance state of a memory element (e.g., a memory element with variable resistance). Thus, the variable resistance memory cell can be programmed to store data corresponding to a target data state by changing the resistance level of the memory element. The cell can be programmed to a target data state (e.g., corresponding to a specific resistance state) by applying an electric field or energy source, such as a positive or negative electrical pulse (e.g., a positive or negative voltage or current pulse), to the variable resistance memory cell (e.g., to the memory element of the cell) for a specific duration. The state of the cell can be determined by sensing the current through the variable resistance memory cell in response to an applied interrogation voltage. The sensed current, varying based on the resistance level of the cell, indicates the state of the cell.

[0005] Various memory arrays can be organized into a crosspoint architecture, wherein memory cells (e.g., variable-resistance cells) are positioned at the intersection of a first and a second signal line for accessing the cell (e.g., at the intersection of a word line and a bit line). Some variable-resistance memory cells may include a selection element (e.g., a diode, transistor, or other switching device) connected in series with a storage element (e.g., a phase-change material, a metal oxide material, and / or some other material programmable to different resistance levels). Some variable-resistance memory cells (which may be referred to as auto-select memory cells) may include a single material that can be used as both the selection element and the storage element for the memory cell. Summary of the Invention

[0006] On one hand, this application provides an apparatus for performing a refresh operation on memory cells, comprising: a memory having a group of memory cells and a data state indication of whether to refresh one or more additional memory cells of the group of memory cells; and a circuit system configured to: apply a first voltage pulse to the group of memory cells to sense the data state of the memory cells in the group; while applying the first voltage pulse to the group of memory cells, apply a second voltage pulse having a larger magnitude than the first voltage pulse to the one or more additional memory cells to sense the data state of the one or more additional memory cells; and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.

[0007] On the other hand, this application provides a method for performing a refresh operation on memory cells, comprising: sensing a corresponding data state of memory cells in a group of memory cells by applying a first voltage pulse to the group of memory cells; simultaneously applying the first voltage pulse to the group of memory cells and applying a second voltage pulse having a larger magnitude than the first voltage pulse to one or more additional memory cells to sense the data state of the one or more additional memory cells; and performing a refresh operation on the group of memory cells in response to the sensing data state of the one or more additional memory cells being different from a specific data state previously programmed to the one or more additional memory cells.

[0008] In another aspect, this application provides an apparatus for performing a refresh operation on memory cells, comprising: a memory having a group of memory cells and a data state indicator for whether to refresh one or more additional memory cells of the group of memory cells; and a circuit system configured to: receive a command for sensing a corresponding data state of the memory cells of the group; upon receiving the command, apply a first voltage pulse to the group of memory cells to sense the corresponding data state of the memory cells of the group; upon receiving the command, apply a second voltage pulse having an amount greater than the first voltage pulse to sense the data state of the one or more additional memory cells; and perform a refresh operation on the group of memory cells in response to a difference between the sensed data state of the one or more additional memory cells and a predetermined data state.

[0009] In another aspect, this application provides a method for performing a refresh operation on memory cells, comprising: receiving a command for sensing a corresponding data state of a group of memory cells; sensing the corresponding data state of the memory cells in the group by applying a first voltage pulse to the group of memory cells after receiving the command; sensing the data state of the one or more additional memory cells by applying a second voltage pulse having an amount greater than that of the first voltage pulse to one or more additional memory cells previously programmed to a first data state and in a specific polarity after receiving the command, wherein the data state of the one or more additional memory cells indicates whether to refresh the group of memory cells; and performing a refresh operation on those memory cells in the group having a first data state and in the specific polarity in response to the sensed data state of the one or more additional memory cells being in a second data state. Attached Figure Description

[0010] Figure 1 This is a three-dimensional view of an example of a memory array according to an embodiment of the present disclosure.

[0011] Figure 2A This describes the distribution of threshold voltages associated with various states of memory cells according to embodiments of the present disclosure.

[0012] Figure 2B The embodiments corresponding to this disclosure Figure 2A An example of a current-to-voltage curve for memory states.

[0013] Figure 2C The embodiments corresponding to this disclosure Figure 2A Another example of a current-to-voltage curve for a memory state.

[0014] Figure 3This is a block diagram illustration of an example device according to embodiments of the present disclosure.

[0015] Figure 4 This section describes conceptual examples of read interference that a memory cell may experience over time according to embodiments of the present disclosure.

[0016] Figure 5 This section describes a conceptual example of increasing the magnitude of a voltage pulse used to sense the data status of a backup memory cell, according to embodiments of the present disclosure.

[0017] Figure 6 This describes an instance memory cell whose data status indicator, according to an embodiment of the present disclosure, is refreshed to indicate whether other memory cells are refreshed. Detailed Implementation

[0018] This disclosure includes apparatus, methods, and systems for performing refresh operations on memory cells. Embodiments include: a memory having a group of memory cells and data state indicators for whether to refresh one or more additional memory cells of the group of memory cells; and a circuit system configured to: apply a first voltage pulse to the group of memory cells to sense the data state of the memory cells in the group; simultaneously applying the first voltage pulse to the group of memory cells and applying a second voltage pulse having a larger magnitude than the first voltage pulse to the one or more additional memory cells to sense the data state of the one or more additional memory cells; and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.

[0019] During the sensing of a variable-resistance memory cell, such as a selectable memory cell, a voltage can be applied to the memory cell, and the data state of the cell can be determined based on the amount of current flowing through the cell in response to the applied voltage. However, during this sensing operation, other (e.g., unselected) memory cells coupled to the same signal line as the sensed memory cell may be adversely affected by the voltage applied to the sensed selected memory cell. This adverse effect on unselected memory cells can be referred to as read interference. Memory cells significantly affected by read interference may be sensed as being in a data state different from the state to which the cell is actually programmed, because, for example, the read interference may have caused a decrease in the threshold voltage of the memory cell. This erroneous data sensing due to read interference can degrade memory performance and / or lifetime, and may be more severe in memories with increased memory cell density. Therefore, it may be beneficial to refresh the cell before read interference causes erroneous sensing of those affected cells.

[0020] In some previous methods, a programming / read cycle counter could be used to determine when a memory cell might need to be refreshed to avoid read interference. However, such methods may not always provide an accurate indication of when a memory cell needs to be refreshed. Furthermore, such methods may increase the cost and / or complexity of the memory.

[0021] However, embodiments of this disclosure can, for example, determine whether to refresh a memory cell before it is significantly affected by read interference without utilizing a programming / read cycle counter. For example, embodiments of this disclosure can use a sensing voltage pulse having a magnitude different (e.g., higher) from the magnitude associated with sensing other memory cells (e.g., non-standby memory cells) to operate an additional memory cell (e.g., a standby memory cell), which will deterministically fail the standby memory cell before the non-standby memory cell fails (e.g., causing the standby memory cell to be sensed as being in a data state different from the state to which it was programmed). Thus, standby memory cell failure can be a deterministic indicator for refreshing non-standby memory cells (e.g., to refresh non-standby memory cells before they fail). As used herein, a memory cell whose data state indicates whether to refresh (some) other memory cells may be referred to as a standby memory cell.

[0022] As used herein, “a,” “an,” or “a plurality of” can refer to one or more of something, and “a plurality of” can refer to two or more such things. For example, a memory device can refer to one or more memory devices, and a plurality of memory devices can refer to two or more memory devices. Additionally, as used herein, particularly with respect to the reference numerals in the accompanying drawings, the identifiers “N” and “M” indicate that several specific features thus specified may be included in several embodiments of this disclosure.

[0023] The figures in this document follow a numbering convention, where the first few digits correspond to the figure number and the remaining digits identify the elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits.

[0024] Figure 1 This is a three-dimensional view of an example of a memory array 100 (e.g., a cross-point memory array) according to embodiments of the present disclosure. The memory array 100 may include: a plurality of first signal lines (e.g., first access lines), which may be referred to as word lines 110-0 to 110-N; and a plurality of second signal lines (e.g., second access lines), which may be referred to as bit lines 120-0 to 120-M, that intersect each other (e.g., intersect in different planes). For example, each of the word lines 110-0 to 110-N may intersect with the bit lines 120-0 to 120-M. Memory cells 125 may be located between bit lines and word lines (e.g., at each bit line / word line intersection).

[0025] For example, memory cell 125 may be a variable-resistance memory cell. Memory cell 125 may contain a material programmable to different data states. In some instances, each of memory cells 125 may contain a single material between a top electrode (e.g., a top plate) and a bottom electrode (e.g., a bottom plate), which can serve as both a selection element (e.g., a switching material) and a storage element, such that each memory cell 125 can function as both a selector device and a memory element. This memory cell may be referred to herein as a selectable memory cell. For example, each memory cell may contain a chalcogenide material, which may be formed from various doped or undoped materials, may or may not be a phase-change material, and / or may or may not undergo a phase change during reading and / or writing to the memory cell. Chalcogenide materials may be materials or alloys containing at least one of the elements S, Se, and Te. Chalcogenide materials may include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), and platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-A s, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, T e-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-B i-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. Examples of chalcogenide materials may also include SAG-based glass non-phase change materials, such as SeAsGe. As used herein, hyphenated chemical composition symbols indicate the elements contained in a particular compound or alloy and are intended to represent all stoichiometry involving the indicated element. For example, Ge-Te may include GexTey, where x and y can be any positive integers.

[0026] In various embodiments, the threshold voltage of memory cell 125 may shunt back in response to an applied voltage difference exceeding its threshold voltage. Such a memory cell may be referred to as a shunt memory cell. For example, memory cell 125 may change (e.g., shunt back) from a non-conductive (e.g., high impedance) state to a conductive (e.g., low impedance) state in response to an applied voltage difference exceeding a threshold voltage. For example, a memory cell shunt back may refer to a memory cell transitioning from a high impedance state to a lower impedance state in response to an applied voltage difference exceeding the memory cell's threshold voltage. For example, the threshold voltage of a memory cell shunt back may be referred to as a shunt event.

[0027] The architecture of memory array 100 can be referred to as a cross-point architecture, in which memory cells such as Figure 1 The crossover architecture, as described, is formed at the topological intersection between the word line and the bit line. Compared to other memory architectures, this crossover architecture can provide relatively high-density data storage at a lower manufacturing cost. For example, compared to other architectures, the crossover architecture can have memory cells with a reduced area and therefore a higher memory cell density.

[0028] However, the embodiments disclosed herein are not limited to Figure 1 The example memory array architecture described herein. For example, embodiments of this disclosure may include a three-dimensional memory array having a plurality of vertically oriented (e.g., vertical) access lines and a plurality of horizontally oriented (e.g., horizontal) access lines. The vertical access lines may be bit lines arranged in a columnar architecture, while the horizontal access lines may be word lines arranged in a plurality of conductive planes or layers separated from each other (e.g., insulated) by a dielectric material. The chalcogenide material of the respective memory cell of this memory array may be positioned at the intersection of the respective vertical bit line and horizontal word line.

[0029] Furthermore, in some architectures (not shown), multiple first access lines may be formed on a parallel plane or layer parallel to the substrate. The multiple first access lines may be configured to include multiple vias to allow multiple second access lines formed orthogonally to the plane of the first access lines, such that each of the multiple second access lines penetrates a vertically aligned set of vias (e.g., the second access lines are positioned vertically relative to the plane of the first access lines and the horizontal substrate). Memory cells containing storage elements (e.g., self-selecting memory cells containing chalcogenide material) may be formed at the intersection of the first and second access lines (e.g., the space between the first and second access lines in the vertically aligned set of vias). Memory cells (e.g., self-selecting memory cells containing chalcogenide material) can be operated (e.g., read and / or programmed) by selecting a corresponding access line and applying a voltage or current pulse.

[0030] Figure 2AExplanation of embodiments according to this disclosure and, for example Figure 1 The threshold distribution associated with various states of the memory cells of memory cell 125 as described herein. For example, as... Figure 2A As shown, memory cells can be programmed to one of two possible data states (e.g., state 0 or state 1). That is, Figure 2A This describes the distribution of threshold voltages associated with the two possible data states to which a memory cell can be programmed.

[0031] exist Figure 2A In this context, the voltage VCELL can correspond to the voltage difference applied to (e.g., across) a memory cell, such as the difference between the bit line voltage (VBL) and the word line voltage (VWL) (e.g., VCELL = VBL – VWL). Threshold voltage distributions (e.g., ranges) 201-1, 201-2, 202-1, and 202-2 can represent the statistical variation of the threshold voltage of a memory cell programmed into a particular state. Figure 2A The distribution described in the text corresponds to the combination Figure 2B and 2C Further description of the current versus voltage curve, Figure 2B and 2C This demonstrates the asymmetry of sudden recursion associated with the assigned data state.

[0032] In some instances, the threshold voltage of a memory cell 125 in a specific state can be asymmetric for different polarities, such as... Figure 2A , 2B As shown in 2C. For example, the threshold voltage of a memory cell 125 programmed to a reset state (e.g., state 0) or a set state (e.g., state 1) may have a different value in one polarity than it has in the opposite polarity. For example, in Figure 2A In the example described, a first data state (e.g., state 0) is associated with a first asymmetric threshold voltage distribution (e.g., threshold voltage distributions 202-1 and 202-2) whose magnitude for positive polarity is greater than that for negative polarity, and a second data state (e.g., state 1) is associated with a second asymmetric threshold voltage distribution (e.g., threshold voltage distributions 201-1 and 201-2) whose magnitude for negative polarity is greater than that for positive polarity. In this example, the applied voltage magnitude sufficient to cause memory cell 125 to shunt for one applied voltage polarity may be different from (e.g., higher or lower than) the applied voltage magnitude for the other applied voltage polarity.

[0033] Figure 2AThe description uses boundary voltages VDM1 and VDM2 to determine the state of a memory cell (e.g., to distinguish states as part of a read operation). In this example, VDM1 is a positive voltage used to distinguish cells in state 1 (e.g., threshold voltage distribution 201-2) from cells in state 0 (e.g., threshold voltage distribution 202-2). Similarly, VDM2 is a negative voltage used to distinguish cells in state 0 (e.g., threshold voltage distribution 202-1) from cells in state 1 (e.g., threshold voltage distribution 201-1). Figure 2A-2C In the example, memory cell 125 in positive state 0 will not abruptly return in response to the application of VDM1; memory cell 125 in positive state 1 will abruptly return in response to the application of VDM1; memory cell 125 in negative state 0 will abruptly return in response to the application of VDM2; and memory cell 125 in negative state 1 will not abruptly return in response to the application of VDM2.

[0034] Examples are not limited to Figure 2A Examples are shown in the document. For example, the designation of state 0 and state 1 can be interchanged (e.g., distributions 201-1 and 201-2 can be designated as state 0, while distributions 202-1 and 202-2 can be designated as state 1).

[0035] Figure 2B and 2C The embodiments corresponding to this disclosure Figure 2A An example of the current-to-voltage curve for the memory state. Therefore, in this example, Figure 2B and 2C The curves in the diagram correspond to cells where state 0 is specified as a higher threshold voltage state of a specific polarity (positive polarity in this example), and state 1 is specified as a higher threshold voltage state of the opposite polarity (negative polarity in this example). As mentioned above, the state designations are interchangeable such that state 1 can correspond to a higher threshold voltage state in the positive polarity direction, while state 0 can correspond to a higher threshold voltage state in the negative polarity direction.

[0036] Figure 2B and 2C This describes a memory cell cascade as described herein. VCELL can represent the applied voltage across a memory cell. For example, VCELL can be the voltage applied to the top electrode corresponding to the cell minus the voltage applied to the bottom electrode corresponding to the cell (e.g., via the respective word line and bit line). Figure 2BAs shown, in response to the application of a positive polarity voltage (VCELL), a memory cell programmed to state 0 (e.g., threshold voltage distribution 202-2) remains in a non-conductive state until VCELL reaches voltage Vtst02, at which point the cell transitions to a conductive (e.g., lower resistance) state. This transition can be referred to as a ripple event, which occurs when the voltage applied across the cell (in a specific polarity) exceeds the cell's threshold voltage. Therefore, voltage Vtst02 can be referred to as the ripple voltage. Figure 2B In this context, voltage Vtst01 corresponds to the rapid return voltage of a cell programmed to state 0 (e.g., threshold voltage distribution 202-1). That is, as... Figure 2B As shown, when VCELL crosses Vtst01 in the negative polarity direction, the memory cell transitions (e.g., switches) to a conductive state.

[0037] Similarly, such as Figure 2C As shown, in response to the application of a negative polarity voltage (VCELL), a memory cell programmed to state 1 (e.g., threshold voltage distribution 201-1) remains in a non-conductive state until VCELL reaches voltage Vtst11, at which point the cell abruptly returns to a conductive (e.g., lower resistance) state. Figure 2C In this context, voltage Vtst12 corresponds to the rapid return voltage of a cell programmed to state 1 (e.g., threshold voltage distribution 201-2). That is, as... Figure 2C As shown in the figure, when VCELL exceeds Vtst12 in the positive polarity direction, the memory cell abruptly returns from a high-impedance non-conductive state to a lower-impedance conductive state.

[0038] In various examples, a ripple event can cause a memory cell to switch states. For instance, if a VCELL exceeding Vtst02 is applied to a state 0 cell, the resulting ripple event can lower the cell's threshold voltage to below VDM1, causing the cell to be read as state 1 (e.g., threshold voltage distribution 201-2). Similarly, if a VCELL exceeding Vtst11 is applied to a state 1 cell, the resulting ripple event can lower the cell's threshold voltage to below VDM2, causing the cell to be read as state 0 (e.g., threshold voltage distribution 201-2). Thus, in several embodiments, a ripple event can be used to write a cell to the opposite state (e.g., from state 0 to state 1 and vice versa).

[0039] As the selected memory cell 125 is repeatedly sensed, the magnitudes of the surge voltages (e.g., Vtst01, Vtst02, Vtst11, and Vtst12) of adjacent cells (e.g., unselected memory cells coupled to the same access line as the selected cell) may decrease due to read interference. This decrease may cause the affected memory cell to be sensed as being in a data state different from the state to which the cell is actually programmed. (As will be used herein, e.g., in conjunction with...) Figure 4 This further describes a conceptual example of this read interference. Therefore, those affected memory cells need to be refreshed before their data state is erroneously sensed. A VCELL that would cause a retrace event in the memory cell can be used to refresh the data state of the affected memory cell. For example, an affected memory cell that is actually programmed to a reset state (but whose threshold voltage has decreased sufficiently to be sensed as a set state) can be refreshed by applying a VCELL greater than Vtst11. Similarly, a memory cell that is actually programmed to a set state (but whose threshold voltage has decreased sufficiently to be sensed as a reset state) can be refreshed by applying a VCELL greater than Vtst02.

[0040] Figure 3 This is a block diagram illustration of an example device, such as an electronic memory system 300, according to an embodiment of the present disclosure. The memory system 300 may include, for example, a memory device 302 and a controller 304, such as a memory controller (e.g., a host controller). The controller 304 may include, for example, a processor. For example, the controller 304 may be coupled to a host and may receive command signals (or commands), address signals (or addresses), and data signals (or data) from the host and may output data to the host.

[0041] Memory device 302 includes a memory array 306 of memory cells. For example, memory array 306 may include one or more of the memory arrays of memory cells disclosed herein, such as a crosspoint array. Memory device 302 may include an address circuitry 308 to latch address signals provided via I / O connection 310 through I / O circuitry 312. The address signals may be received and decoded by row decoder 314 and column decoder 316 to access memory array 306. For example, row decoder 314 and / or column decoder 316 may include drivers.

[0042] Memory device 302 can sense (e.g., read) data in memory array 306 by sensing voltage and / or current changes in the memory array column using a sensing / buffering circuitry system, which in some instances may be a read / latch circuitry system 320. Latch circuitry system 320 can read and latch data from memory array 306. Sensing circuitry system 305 may include several sensing amplifiers coupled to memory cells of memory array 306, which can operate in conjunction with read / latch circuitry system 320 to sense (e.g., read) memory states from target memory cells, as will be further described herein. I / O circuitry system 312 may be included for bidirectional data communication with controller 304 via I / O connection 310. Write circuitry system 322 may be included for writing data to memory array 306.

[0043] The control circuitry 324 can decode signals provided from the controller 304 via the control connection 326. These signals may include chip signals, write enable signals, and address latch signals used to control operations on the memory array 306 (including data read and data write operations).

[0044] For example, control circuitry 324 may be included in controller 304. Controller 304 may include other circuitry, firmware, software, etc., individually or in combination. Controller 304 may be an external controller (e.g., in a separate die from memory array 306, either wholly or partially) or an internal controller (e.g., included in the same die as memory array 306). For example, an internal controller may be a state machine or a memory sequencer.

[0045] In some instances, controller 304 may be configured to operate the memory cells of memory array 306 using voltage pulses of different magnitudes. For example, controller 304 may operate the backup memory cells by applying voltage pulses with a larger magnitude (when sensing the data state of backup memory cells of array 306) than those applied to non-backup memory cells, which may cause the backup memory cells to fail before the non-backup memory cells. Therefore, the failure of a backup memory cell can be used as an indication of whether to refresh the non-backup memory cells. That is, a determination to perform a refresh operation on the non-backup memory cells can be made based on the sensed data state of the backup memory cells (e.g., based on whether the sensed data state of the backup memory cells is incorrect). For example, if the sensed data state of a backup memory cell differs from a predetermined data state (e.g., the data state to which the backup memory cell is actually programmed), then controller 304 may perform a refresh operation on the non-backup memory cells, which may readjust the threshold voltage of the non-backup memory cells before the sensing of the non-backup memory cells fails. The voltage pulses used to sense the backup and non-backup memory cells may have the same polarity, although embodiments are not limited to this. In addition, for example, the controller may prevent refresh operations from being performed on non-standby memory cells in response to the fact that the sensed data state of one or more standby memory cells is no different from a specific data state (e.g., a predetermined data state).

[0046] In some instances, spare memory cells may be coupled to additional capacitors, such as boost capacitors. Figure 3 (Not shown in the image), the additional capacitor can be used to amplify (e.g., amplify) the magnitude of the voltage pulse used to sense the backup memory cell. For example, a boost capacitor can reduce the magnitude from the combined... Figure 5 The value of VDM 542 described herein is increased to the point of combination. Figure 5 The value of VDM,SPARE 544 is described in the document.

[0047] Figure 4 This section illustrates conceptual examples of read interference that a memory cell may experience over time according to embodiments of the present disclosure. While embodiments are not limited thereto, Figure 4 The threshold voltage distribution 432 described herein can be, for example, the previously combined Figure 2A The threshold voltage distribution described is 202-2 (e.g., state 0).

[0048] Read interference to memory cells can cause the threshold voltage distribution 432 of the cells to deviate undesirably. For example, the threshold voltage distribution 432 of the cells may deviate undesirably (e.g., in the direction indicated by arrow 434) to the threshold voltage distribution 438, which may produce... Figure 4The tail portion is as described in the diagram. The tail portion may extend beyond the threshold voltage (e.g., previously combined). Figure 2A The values ​​of VDM1 and / or VDM2 described herein may lead to incorrect determination of the data state (e.g., logic state) of the cell. For example, in an instance where threshold voltage distribution 432 represents a reset state (e.g., state 0), a memory cell having threshold voltage distribution 432 may have its distribution shifted to, for example, a value that could lead to incorrect determination of the data state (e.g., logic state) of the cell. Figure 4 The distribution 438 described herein is incorrectly identified as a set state (e.g., state 1). Therefore, it is necessary to perform a refresh operation to reverse the offset of the threshold voltage distribution 438 (e.g., in the direction indicated by arrow 436) back to the threshold voltage distribution 432.

[0049] Figure 5 This section describes conceptual examples of increasing the magnitude of voltage pulses used to sense the data status of backup memory cells according to embodiments of the present disclosure. For example, Figure 5 This describes an example of a boundary voltage VDM,SPARE (e.g., for sensing the data state of an additional (e.g., spare) memory cell according to embodiments of the present disclosure. Figure 5 The voltage 544 described in the document). Boundary voltage VDM (e.g., Figure 5 The voltage 542 described herein can be, for example, the previously combined Figure 2A The described boundary voltages VDM1 and / or VDM2. For example, Figure 5 The VDM 542 described herein can be used to distinguish between cells in one state and cells in different states. Although the embodiments are not limited thereto, threshold voltage distributions 546 and 548 may respectively correspond to the combination... Figure 2A The threshold voltage distributions described are 201-2 (e.g., state 1) and 202-2 (e.g., state 0).

[0050] Although the VDM 542 is used to sense non-standby memory cells (e.g., Figure 6 The memory cells 652-1, ..., 652-M described herein, but spare memory cells (e.g., Figure 6The memory cells 654-1 and / or 654-N described herein can be sensed using VDM,SPARE 544. Since VDM,SPARE 544 has a larger magnitude than VDM 542, using VDM,SPARE 544 to sense the spare memory cell will cause the spare memory cell to fail at an earlier point in time than using VDM 542 to sense the non-spare memory cell. Therefore, the failure of the spare memory cell sensed using VDM,SPARE 544 can serve as an indicator for whether to refresh the non-spare memory cell. For example, refreshing the non-spare memory cell in response to an erroneous sensed data state of the spare memory cell can readjust the threshold voltage distribution (e.g., distribution 548) of the non-spare memory cell before its failure.

[0051] Refresh operations can be selectively performed on those memory cells initially programmed to a specific data state. For example, threshold voltage distribution 548 may shift toward threshold voltage distribution 546 (e.g., due to read interference), which would cause a portion of those memory cells previously programmed to the data state corresponding to threshold voltage distribution 548 (e.g., state 0) to be incorrectly sensed as being in the data state corresponding to threshold voltage distribution 546 (e.g., state 1). In contrast, a shift in threshold voltage distribution 546 (e.g., toward 0V) may not affect sensing those memory cells programmed to the data state corresponding to threshold voltage distribution 546. Therefore, when needed, refresh operations can be selectively performed only on those memory cells previously programmed to the data state corresponding to threshold voltage distribution 548, and not on those memory cells previously programmed to the data state corresponding to threshold voltage distribution 546. In other words, since memory cells programmed to the data state corresponding to threshold voltage distribution 546 will experience a ripple event in response to the application of VDM 542, refresh operations can be performed on those memory cells that do not experience a ripple event in response to the application of VDM 542.

[0052] In some instances, refresh programming to a memory cell corresponding to the data state of threshold voltage distribution 548 can be performed by applying a voltage pulse (to a memory cell) having a magnitude greater than that of VDM 542 or VDM,SPARE 544 and a polarity opposite to that of VDM 542 or VDM,SPARE 544. For example, when the polarities of VDM 542 and VDM,SPARE 544 are positive, a negative voltage pulse having a magnitude greater than the threshold voltage of the memory cell with threshold voltage distribution 548 can be applied to refresh the cell.

[0053] Figure 6This describes instances of memory cells 654-1, ..., 654-N (collectively referred to as memory cells 654), whose data status indicators, according to embodiments of this disclosure, indicate whether other memory cells 652-1, ..., 652-M (e.g., collectively referred to as memory cells 652), are being refreshed. Memory cells 652 and / or 654 may be, for example, previously combined... Figure 1 The memory unit 125 described.

[0054] Each group of memory cells 656-1, ..., 656-N (e.g., collectively referred to as 656) having memory cells 652-1, ..., 652-M (e.g., collectively referred to as memory cells 652), may be referred to as a partition. Each partition may be associated with additional (e.g., spare) memory cells whose data state indicates whether the memory cells of the corresponding partition are refreshed. For example, partition 656-1 may be associated with additional memory cell 654-1 (whose data state indicates whether memory cell 652 of partition 656-1 is refreshed), and partition 656-N may be associated with additional memory cells 654-N (whose data state indicates whether memory cell 652 of partition 656-N is refreshed). Although a single additional memory cell is described as being associated with Figure 6 Each partition in the memory is associated with a specific number of additional memory cells, but the embodiments are not limited to a particular number that may be associated with each partition. For example, each partition (e.g., partitions 656-1, ..., 656-N) may be associated with more than one (e.g., three) additional memory cells. Furthermore, partition 656 may be associated with a different number of additional memory cells. For example, the number of additional memory cells associated with one partition may differ from the number of additional memory cells associated with different partitions. While the embodiments are not limited thereto, the number of spare memory cells may be less than 1% of the number of non-spare memory cells associated with the number of spare memory cells. For example, the ratio of non-spare memory cells to spare memory cells may be greater than 100:1.

[0055] The memory cells 652 of each partition 656 may be distributed (e.g., located separately on) different memory blocks. Furthermore, spare memory cells may be located in different blocks than those blocks where non-spare memory cells are located. Memory cells in different blocks can be accessed simultaneously. In other words, the non-spare memory cells 652 and their associated spare memory cells 652 of each partition 656 can be accessed simultaneously.

[0056] As described in this article, the controller (e.g., in conjunction with...) Figure 3The controller 304 described herein can apply voltage pulses of different magnitudes to memory cells 652 and 654 respectively. For example, controller 304 can apply a first voltage pulse to memory cell 652 (to sense the data state of memory cell 652), and simultaneously apply a second voltage pulse with a larger magnitude than the first voltage pulse to memory cell 654 to sense the data state of memory cell 654. The controller can apply the voltage pulses to memory cells 652 and 654, for example, after receiving a command (e.g., from a host) to sense the data state of memory cell 652.

[0057] In a non-limiting instance, memory (e.g., combined with) Figure 3 The illustrated memory array 306 may have a group of memory cells (e.g., non-standby memory cells 652) and one or more additional memory cells (e.g., standby memory cells 654) indicating whether the memory cell group is refreshed. A controller (e.g., in conjunction with...) Figure 3 The described controller 304 can receive a command to sense the corresponding data state of the memory cells in the group. Upon receiving the command, the controller can apply a first voltage pulse to the group of memory cells to sense the corresponding data state of the memory cells in the group and apply a second voltage pulse having an amount greater than the first voltage pulse to sense the data state of one or more additional memory cells. The controller can perform a refresh operation on the group of memory cells in response to a difference between the sensed data state of one or more additional memory cells and a predetermined data state.

[0058] Continuing with a non-limiting example, a refresh operation can be performed by applying a third voltage pulse to memory cells 652 whose data state is sensed to be in a predetermined data state. The third voltage pulse may have a magnitude greater than that of the second voltage pulse and a polarity opposite to that of the first or second voltage pulse.

[0059] In another non-limiting instance, the controller (e.g., combined with...) Figure 3The described controller 304 can receive a command to sense the corresponding data state of a group of memory cells. Upon receiving the command, the controller can sense the corresponding data state of the memory cells in the group by applying a first voltage pulse to the group of memory cells and sense the data state of one or more additional memory cells previously programmed to a first data state (e.g., a reset state) and in a specific polarity by applying a second voltage pulse having a magnitude greater than that of the first voltage pulse to one or more additional (e.g., spare) memory cells. As described herein, the data state of one or more additional memory cells can indicate whether to refresh the group of memory cells. In response to the sensed data state of one or more additional memory cells being in a second data state (e.g., a set state), the controller can perform a refresh operation on those memory cells in the group that have the first data state and are in a specific polarity.

[0060] In an example, the decision to perform a refresh operation can be determined based on the number of spare memory cells whose sensed data state differs from a predetermined data state (e.g., a reset state). For example, a refresh operation can be performed on non-spare memory cells in response to the number of spare memory cells whose sensed data state differs from a predetermined data state reaching or exceeding a threshold number. Although embodiments are not limited thereto, the threshold number can be 20-30% of the total number of spare memory cells. For example, if the spare memory cells associated with a partition of non-spare memory cells comprise 100 spare memory cells, then the non-spare memory cells can be refreshed when it is determined that at least 20-30 of the 100 spare memory cells have failed.

[0061] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of several embodiments of this disclosure. It should be understood that the above description is illustrative and not restrictive. After reviewing the above description, combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of several embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of several embodiments of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

[0062] In the foregoing detailed embodiments, some features are grouped in a single embodiment for the purpose of simplifying this disclosure. This disclosure method should not be construed as reflecting an intention that the disclosed embodiments of this disclosure must use more features than are expressly stated in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the appended claims are thus incorporated into the detailed embodiments, wherein each claim is considered an independent, separate embodiment.

Claims

1. An apparatus for performing a refresh operation on a memory cell, comprising: Memory (306), the memory having a group of memory cells (656-1, ..., 656-N) and a data status indicator indicating whether to refresh one or more additional memory cells (654-1, ..., 654-N) of the group of memory cells; and Circuit system (304), configured to: A first voltage pulse (542) is applied to the group of memory cells to sense the data state of the memory cells in the group; While applying the first voltage pulse to the group of memory cells, a second voltage pulse (544) having a larger value than the first voltage pulse is applied to the one or more additional memory cells to sense the data status of the one or more additional memory cells. Whether to perform a refresh operation on the group of memory cells is determined based on the sensed data state of the one or more additional memory cells; and The refresh operation is performed on the group of memory cells by applying a third voltage pulse to those memory cells whose sensed data state corresponds to a predetermined data state, wherein the third voltage pulse has a magnitude greater than the second voltage pulse and a polarity opposite to the first voltage pulse or the second voltage pulse.

2. The device of claim 1, wherein the circuitry is configured to determine whether to perform the refresh operation on the group of memory cells based on the number of the one or more additional memory cells whose sensed data state differs from the predetermined data state.

3. The device of claim 2, wherein the predetermined data state is associated with an asymmetric threshold voltage distribution whose magnitude for the positive polarity is greater than that for the negative polarity.

4. The device of claim 2, wherein the memory cells of the memory cell group are programmable to include one of two data states, namely a first data state and a second data state, corresponding to the predetermined data state, and wherein the second data state is associated with an asymmetric threshold voltage distribution whose magnitude for negative polarity is greater than that for positive polarity.

5. The device according to any one of claims 1 to 4, wherein: The memory cells of the group are distributed across multiple slabs of the memory; and The one or more additional memory units are located in additional blocks of the memory.

6. The device according to any one of claims 1 to 4, wherein the first voltage pulse and the second voltage pulse have the same polarity.

7. A method for performing a refresh operation on a memory cell, comprising: The corresponding data status of the memory cells in the group of memory cells is sensed by applying a first voltage pulse (542) to the group of memory cells (656-1, ..., 656-N); While applying the first voltage pulse to the group of memory cells, the data status of the one or more additional memory cells is sensed by applying a second voltage pulse (544) having a larger value than the first voltage pulse to one or more additional memory cells (654-1, ..., 654-N). and A refresh operation is performed on the group of memory cells in response to the sensing data state of the one or more additional memory cells being different from a specific data state previously programmed to the one or more additional memory cells. The refresh operation performed on the group of memory cells includes applying a third voltage pulse to those memory cells of the group whose data state is sensed to be in the specific data state. and The third voltage pulse has a magnitude greater than that of the second voltage pulse and a polarity opposite to that of the first voltage pulse or the second voltage pulse.

8. The method of claim 7, wherein performing the refresh operation on the group of memory cells comprises refreshing only those memory cells of the group that do not experience a shunt event in response to the application of the first voltage pulse.

9. The method according to any one of claims 7 to 8, further comprising preventing the refresh operation from being performed on the group of memory cells in response to the fact that the sensed data state of the one or more additional memory cells is no different from the specific data state.

10. An apparatus for performing a refresh operation on a memory cell, comprising: Memory (306), the memory having a group of memory cells (656-1, ..., 656-N) and a data status indicator indicating whether to refresh one or more additional memory cells (654-1, ..., 654-N) of the group of memory cells; and Circuit system (304), configured to: Receive a command for sensing the corresponding data status of the memory cells in the group; Upon receiving the command, a first voltage pulse (542) is applied to the group of memory cells to sense the corresponding data state of the memory cells in the group; Upon receiving the command, a second voltage pulse (544) with a magnitude greater than that of the first voltage pulse is applied to sense the data status of the one or more additional memory cells; A refresh operation is performed on the group of memory cells in response to a difference between the sensed data state and a predetermined data state of the one or more additional memory cells; and The refresh operation is performed on the group of memory cells by applying a third voltage pulse to those memory cells whose sensed data state corresponds to the predetermined data state, wherein the third voltage pulse has a magnitude greater than the second voltage pulse and a polarity opposite to the first voltage pulse or the second voltage pulse.

11. The device of claim 10, wherein the memory cells of the group are programmable to a first data state or a second data state corresponding to the predetermined state, and wherein the first data state is associated with a threshold voltage distribution whose magnitude is greater than that of the second data state.

12. The device of claim 10, wherein the memory cells of the group and the one or more additional memory cells are selectable memory cells, wherein a single material is used as both a selection element and a storage element in the selectable memory cell.

13. The device according to any one of claims 10 to 12, wherein: The memory cell group is one of a plurality of memory cell groups in the memory; and Each of the plurality of memory cell groups is associated with its data state indicator to refresh one or more additional memory cells in that memory cell group.

14. The device of claim 13, wherein the circuitry is configured to perform a refresh operation on each of the plurality of memory cell groups in response to the number of the one or more additional memory cells associated with that corresponding group that differs from the predetermined data state reaching or exceeding a threshold number.

15. The device according to any one of claims 10 to 12, wherein the one or more additional memory cells are coupled to a boost capacitor configured to increase the magnitude of the first voltage pulse applied to the group of memory cells to the magnitude of the second voltage pulse applied to the one or more additional memory cells.

16. A method for performing a refresh operation on a memory cell, comprising: Receive a command for sensing the corresponding data status of the memory cell (656-1, ..., 656-N) group of the memory (306); The corresponding data state of the memory cells in the group is sensed by applying a first voltage pulse (542) to the group of memory cells after receiving the command; The data state of one or more additional memory cells (654-1, ..., 654-N) is sensed by applying a second voltage pulse (544) with a magnitude greater than that of the first voltage pulse to one or more additional memory cells (654-1, ..., 654-N) previously programmed to a first data state and in a specific polarity after receiving the command, wherein the data state of the additional memory cells indicates whether the group of memory cells is refreshed. and In response to the sensed data state of the additional one or more memory cells being in a second data state, a refresh operation is performed on those memory cells in the group that have a first data state and are in the specific polarity; Performing the refresh operation on those memory cells in the group that have the first data state and are in the specific polarity further includes applying a voltage pulse having a magnitude greater than that of the second voltage pulse and a polarity opposite to that of the specific polarity to those memory cells in the group that have the first data state.

Images