Methods for manufacturing semiconductor devices

Abstract

A method for manufacturing a semiconductor device includes: preparing a substrate (12) made of a compound semiconductor comprising a first element and a second element bonded to the first element and having an electronegativity 1.5 or more less than that of the first element; allowing current to flow in the substrate (12); and cleaving the substrate (12) at locations including current regions for allowing current to flow and along cleavage planes of the substrate (12). Another method for manufacturing a semiconductor device includes: stacking a first substrate (52) and a second substrate (54) both made of compound semiconductors; and bonding the first substrate (52) and the second substrate (54) by allowing current to flow between the first substrate (52) and the second substrate (54).

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing semiconductor devices. Background Technology

[0002] Various techniques for separating and bonding substrates made of compound semiconductors have been proposed for manufacturing semiconductor devices. For example, JP 2019-126838 A discloses a technique for dicing a gallium oxide-containing substrate in a method for manufacturing a semiconductor device. In this manufacturing method, firstly, a laser beam is applied along a predetermined dicing line on the substrate to form a modified region along the predetermined dicing line. The modified region is more brittle than other regions of the substrate. Then, the substrate is diced along the predetermined dicing line using a cutting blade. In this manufacturing method, because the substrate is diced at the modified region formed along the predetermined dicing line, it is possible to diced the substrate at a higher speed than conventional dicing. Summary of the Invention

[0003] In the manufacturing method of JP 2019-126838 A, a laser beam is applied along a predetermined dicing line on the substrate, such that the width of the modified region is wider than the width of the dicing blade. Therefore, when the substrate is cut by the dicing blade, the modified region remains on the dicing surface. Because the modified region has been damaged by the laser beam, the dicing surface is uneven, which may affect the performance of the semiconductor device. This disclosure provides a technique for suppressing damage to a substrate made of compound semiconductor by effectively performing substrate dicing. This disclosure also provides a technique for suppressing damage to a substrate made of compound semiconductor by effectively performing substrate bonding.

[0004] According to a first aspect of this disclosure, a method for manufacturing a semiconductor device includes: preparing a substrate made of a compound semiconductor, the compound semiconductor comprising a first element and a second element, the second element being bonded to the first element and having an electronegativity 1.5 or more less than that of the first element; allowing a current to flow in the substrate; and cleaving the substrate at locations including current regions through which the current flows and along cleavage planes.

[0005] Electronegativity is a value that represents the ability of atoms in a molecule to attract electrons. In this disclosure, electronegativity refers to Pauling's electronegativity.

[0006] In this manufacturing method, a substrate made of a compound semiconductor comprising a first element and a second element bonded to the first element is prepared. It is known that when the electronegativity difference between the first and second elements is 1.5 or greater, the bonding between the first and second elements exhibits ionic bonding properties. In compound semiconductors exhibiting ionic bonding properties, charges generated when current flows move within the compound semiconductor, thus potentially disrupting the internal polarity of the crystal. Furthermore, thermal stress may be generated due to the current flow, making the crystal structure prone to deformation. As described above, the crystal structure of a compound semiconductor exhibiting ionic bonding properties can be altered by allowing current to flow through it. In this manufacturing method, by utilizing this property, current is flowed through the substrate made of a compound semiconductor with ionic bonding properties to cleave the substrate along its cleavage planes. According to this manufacturing method, the substrate can be effectively cleaved while suppressing damage to the cleaved surfaces.

[0007] According to a second aspect of this disclosure, a method of manufacturing a semiconductor device includes: stacking a first substrate and a second substrate; and bonding the first substrate and the second substrate by allowing current to flow between the first substrate and the second substrate. Both the first substrate and the second substrate are made of a compound semiconductor. The compound semiconductor comprises a first element and a second element, the second element being bonded to the first element and having an electronegativity 1.5 or more lower than that of the first element.

[0008] In this manufacturing method, firstly, a first substrate and a second substrate are stacked. Both the first and second substrates are made of compound semiconductors. The compound semiconductor comprises a first element and a second element bonded to the first element and having an electronegativity 1.5 or more less than that of the first element. As described above, the crystal structure of the compound semiconductor exhibits ionic bonding characteristics that can be disturbed by the flow of current. Therefore, by allowing current to flow between the first and second substrates, the crystal structure at the interface between the first and second substrates is disturbed, and the vicinity of the interface melts. Subsequently, when the current flow stops, the disordered crystal structure rearranges during the solidification of the molten semiconductor material. As a result, the first and second substrates can be effectively bonded to each other. Attached Figure Description

[0009] The features and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawings, the same parts are indicated by the same reference numerals, and in the drawings:

[0010] Figure 1 This is a plan view of the semiconductor substrate in the manufacturing method according to the first embodiment;

[0011] Figure 2 It is a cross-sectional view showing the process of introducing dopants into a semiconductor substrate;

[0012] Figure 3 It is a cross-sectional view showing the process of allowing current to flow through a semiconductor substrate;

[0013] Figure 4 It is a cross-sectional view showing the state in which the semiconductor substrate is divided;

[0014] Figure 5 This is a cross-sectional view showing the process of arranging electrodes on a semiconductor substrate in the manufacturing method according to the second embodiment;

[0015] Figure 6 It is a cross-sectional view showing the state in which the semiconductor substrate is divided;

[0016] Figure 7 It is a cross-sectional view showing the process of dividing the semiconductor substrate along the plane direction of the semiconductor substrate in the manufacturing method according to a variant example;

[0017] Figure 8 This is a cross-sectional view showing the process of implanting ions into the surface of a semiconductor substrate in the manufacturing method according to the third embodiment;

[0018] Figure 9 It is a cross-sectional view showing the process of stacking semiconductor substrates; and

[0019] Figure 10 It is a cross-sectional view showing the process of allowing current to flow through a semiconductor substrate. Detailed Implementation

[0020] The embodiments disclosed herein will be described in conjunction with the technical elements listed below. The following technical elements may also be useful even when used independently.

[0021] In one embodiment of this disclosure, a method for manufacturing a semiconductor device includes the following steps: preparing a substrate made of a compound semiconductor, the compound semiconductor comprising a first element and a second element, the second element being bonded to the first element and having an electronegativity 1.5 or more less than that of the first element; allowing a current to flow in the substrate; and slicing the substrate at locations including current regions through which the current flows and along a cleavage plane of the substrate.

[0022] Electronegativity is a value that represents the ability of atoms in a molecule to attract electrons. In this disclosure, electronegativity refers to Pauling's electronegativity.

[0023] In this manufacturing method, a substrate is prepared from a compound semiconductor comprising a first element and a second element bonded to the first element and having an electronegativity 1.5 or greater less than that of the first element. It is known that when the electronegativity difference between the first and second elements is 1.5 or greater, the bond between the first and second elements exhibits ionic bonding characteristics. In compound semiconductors exhibiting ionic bonding characteristics, charges generated by the flow of current move within the compound semiconductor, making the internal polarity of the crystal easily disturbed. Furthermore, thermal stress may be generated due to the flow of current, and the crystal structure may be easily deformed. That is, the crystal structure of a compound semiconductor exhibiting ionic bonding characteristics may change due to the flow of current. In the manufacturing method of this embodiment, by utilizing this property, current is flowed through the substrate, thereby cleaving the substrate along its cleavage plane. Therefore, the substrate can be effectively cleaved while suppressing damage to the cleaved surfaces.

[0024] In one embodiment of this disclosure, in the step of making current flow in the substrate during the manufacturing method, for example, a probe may be brought into contact with the substrate, and current may flow between the substrate and the probe.

[0025] In this configuration, the current region flowing through the substrate can be controlled by adjusting the position of the probe in contact with the substrate. This allows the substrate to be easily segmented along its cleavage planes.

[0026] In one embodiment of this disclosure, the manufacturing method may further include the step of forming an electrode on the surface of the current region of the substrate. In the step of allowing current to flow in the substrate, the current may be allowed to flow through the electrode in the substrate.

[0027] In this configuration, the current region flowing through the substrate can be controlled by adjusting the position of the formed electrodes. This allows the substrate to be easily segmented along its cleavage planes.

[0028] In one embodiment of this disclosure, during the step of forming an electrode in the manufacturing method, the electrode may be formed along a cleavage plane on the surface of the current region.

[0029] In this configuration, electrodes are formed on the surface of the substrate along cleavage planes. Therefore, current can flow easily along the cleavage planes, and thus stress can be easily applied locally along them.

[0030] In one embodiment of this disclosure, the manufacturing method may further include the step of introducing a dopant or a heterogeneous material different from the compound semiconductor into the current region to increase the resistance of the current region so that it is higher than the resistance of the peripheral region on the periphery of the current region.

[0031] In such a configuration, by introducing dopants or dissimilar materials into the current region where current flows, the resistance in the current region increases to a level higher than that in the surrounding region. Therefore, when current flows, the temperature in the current region may rise more than that in the surrounding region, thus enabling the application of large thermal stress to the current region.

[0032] In one embodiment of this disclosure, the manufacturing method may further include the step of introducing a dopant or a heterogeneous material different from the compound semiconductor into the current region to increase the thermal resistance of the current region so that it is higher than the thermal resistance of the peripheral region on the periphery of the current region.

[0033] In this configuration, by introducing dopants or dissimilar materials into the current region where current flows, the thermal resistance in the current region increases to a level higher than that in the surrounding regions. Therefore, when current flows, heat tends to remain more readily in the current region, and thus the temperature in the current region may rise more significantly than in the surrounding regions. This allows for the application of substantial thermal stress to the current region.

[0034] In one embodiment of this disclosure, in the manufacturing method, the compound semiconductor may be an oxide semiconductor, and the first element may be oxygen. Furthermore, the compound semiconductor may be made of β-Ga₂O₃. The cleavage plane may be the (100) crystal plane and / or the (001) crystal plane of β-Ga₂O₃.

[0035] In compound semiconductors made of β-Ga2O3, cleavage may occur along the (100) or (001) crystal planes. Therefore, if the substrate is cleaved along the (100) or (001) crystal planes of β-Ga2O3, the substrate can be easily cleaved.

[0036] In one embodiment of this disclosure, a method for manufacturing a semiconductor device includes the steps of: stacking a first substrate and a second substrate; and bonding the first substrate and the second substrate by allowing current to flow between the first substrate and the second substrate. Both the first substrate and the second substrate are made of a compound semiconductor. The compound semiconductor comprises a first element and a second element, the second element being bonded to the first element and having an electronegativity 1.5 or less than that of the first element.

[0037] In this manufacturing method, a first substrate and a second substrate are stacked one on top of the other. Both the first and second substrates are made of a compound semiconductor comprising a first element and a second element bonded to the first element, the second element having an electronegativity 1.5 or more less than that of the first element. Due to the flow of current, the crystal structure of the compound semiconductor exhibiting ionic bonding characteristics may be disturbed. Therefore, by allowing current to flow between the first and second substrates, the crystal structure at the interface between the first and second substrates is disturbed, and the vicinity of the interface is melted. Thus, when the current flow stops, the disordered crystal structure rearranges during the solidification of the molten semiconductor material. As a result, the first and second substrates can be effectively bonded.

[0038] In one embodiment of this disclosure, the manufacturing method may further include introducing a dopant or a dissimilar material different from the compound semiconductor onto the surface of the first substrate prior to the step of stacking the first and second substrates. In the step of stacking the first and second substrates, the second substrate may be stacked on the surface of the first substrate.

[0039] In this configuration, the surface resistivity of the first substrate is increased by introducing dopants or dissimilar materials. A second substrate is then stacked on the surface of the first substrate, which has increased resistance. Therefore, when current flows between the first and second substrates, the temperature at the interface between them tends to rise. Consequently, the semiconductor material readily melts at the interface between the first and second substrates, and the first and second substrates can be effectively bonded / joined to each other.

[0040] In one embodiment of this disclosure, the manufacturing method may further include, prior to the step of bonding the first substrate and the second substrate, annealing at least one of the first substrate and the second substrate to increase the resistance of at least one of the surface layer portions of the first substrate and the surface layer portions of the second substrate.

[0041] In this configuration, the resistance of the interface between the first and second substrates increases as they come into contact with each other, with the increased resistance surface layer portion located at the interface between the first and second substrates. Therefore, when current flows between the first and second substrates, the temperature at the interface between them, i.e., the temperature at the contact surface, tends to rise. As a result, the semiconductor material readily melts at the interface, and the first and second substrates are effectively bonded together.

[0042] In one embodiment of this disclosure, the manufacturing method may further include, prior to the step of bonding the first substrate and the second substrate, annealing at least one of the first substrate and the second substrate to increase the thermal resistance of at least one of the surface layer portions of the first substrate and the surface layer portions of the second substrate.

[0043] In this configuration, the thermal resistance at the interface between the first and second substrates increases as the first and second substrates come into contact with each other, resulting in a surface layer portion with increased thermal resistance located at the interface between the first and second substrates. Therefore, when current flows between the first and second substrates, heat may be retained at the interface, i.e., at the contact surface between the first and second substrates, and the temperature at the interface may easily rise. As a result, the semiconductor material readily melts at the interface, and the first and second substrates are effectively bonded together.

[0044] In one embodiment of this disclosure, in the manufacturing method, the compound semiconductor can be an oxide semiconductor, and the first element can be oxygen. Furthermore, the compound semiconductor can be made of β-Ga₂O₃.

[0045] Exemplary embodiments of this disclosure will now be further described with reference to the first to third embodiments.

[0046] (First Embodiment)

[0047] The method for manufacturing a semiconductor device 10 according to the first embodiment will be described with reference to the accompanying drawings. In the manufacturing method of the first embodiment, the semiconductor device 10 is manufactured by using a semiconductor substrate 12 in a wafer state, such as... Figure 1 As shown. The manufacturing method of the first embodiment is characterized by a process of dividing a semiconductor substrate 12 made of a specific material, which will be described later. This manufacturing method can be used for various semiconductor devices and their semi-finished products using the specific material. In the following text, the process of dividing the semiconductor substrate 12 will be mainly described, and descriptions of other manufacturing processes will be omitted.

[0048] Figure 1The semiconductor substrate 12 shown is made of a compound semiconductor. Specifically, the semiconductor substrate 12 is made of β-Ga₂O₃. However, the material of the semiconductor substrate 12 is not limited to β-Ga₂O₃. As the material of the semiconductor substrate 12, a compound semiconductor containing a first element and a second element bonded to each other, wherein the electronegativity difference between the first element and the second element is 1.5 or greater, can be used. Generally, a simple requirement is that the semiconductor substrate 12 is made of a material with ionic bonding properties. In the case of β-Ga₂O₃, O corresponds to the first element and has an electronegativity of 3.44, and Ga corresponds to the second element and has an electronegativity of 1.81. The compound semiconductor constituting the semiconductor substrate 12 may also contain elements different from the first element and the second element. Examples of compound semiconductors constituting the semiconductor substrate 12 other than β-Ga₂O₃ may include gallium oxide semiconductors such as (Ga,Rh)₂O₃, (Ga,Ir)₂O₃, (Ga,Bi)₂O₃, and ZnGa₂O₄, and other oxide semiconductors.

[0049] exist Figure 1 In this context, the planes including the X and Z directions correspond to the (100) crystal plane of β-Ga₂O₃, and the planes including the Y and Z directions correspond to the (001) crystal plane of β-Ga₂O₃. Furthermore, the planes including the X and Y directions, i.e., the planes along surface 12a, correspond to the (010) crystal plane of β-Ga₂O₃. In other words, in Figure 1 In the diagram, the Y direction corresponds to the

[100] crystal orientation, the X direction corresponds to the

[001] crystal orientation, and the Z direction corresponds to the

[010] crystal orientation.

[0050] like Figure 1 As shown, the semiconductor substrate 12 has a plurality of element regions 30 and predetermined partitioned regions 32 surrounding each element region 30, wherein a semiconductor device 10 is formed in each element region 30. The predetermined partitioned regions 32 correspond to regions that will be cut later. The element regions 30 are arranged in a grid pattern along the X and Y directions.

[0051] In the manufacturing method of the first embodiment, firstly, a dopant is introduced into the semiconductor substrate 12 by ion implantation. In this case, as... Figure 2 As shown, dopants are selectively introduced along a predetermined segmentation region 32. There are no particular restrictions on the dopants to be introduced, but for example, Fe or V can be used. The result is as follows: Figure 2 As shown, a dopant is introduced into the interior of the semiconductor substrate 12, thus forming a high-resistivity region 34. Due to the introduction of the dopant, the high-resistivity region 34 has a higher resistance than the surrounding region, i.e., the element region 30. Figure 2 The internal structure of the semiconductor substrate 12 is omitted in the subsequent cross-sectional views.

[0052] Next, as Figure 3 As shown, probe 16 contacts the front surface 12a and the rear surface 12b of the semiconductor substrate 12, respectively. Here, each probe 16 contacts the semiconductor substrate 12 within a predetermined segmented region 32. In this process, as... Figure 3 As shown, the probe 16 can contact each of the front surface 12a and the rear surface 12b of the semiconductor substrate 12 at only one location or at multiple locations within the predetermined segmentation region 32. Furthermore, the probe 16 can contact the front surface 12a and the rear surface 12b at locations outside the predetermined segmentation region 32.

[0053] Next, current is flowed through the semiconductor substrate 12 via each probe 16 that contacts the semiconductor substrate 12. Since dopants have been introduced into the high-resistivity region 34 within the predetermined segmentation region 32, the high-resistivity region 34 has a higher resistance than the surrounding region. Therefore, when current flows through the substrate 12, the temperature of the high-resistivity region 34 rises to a higher temperature than the surrounding region. Thus, large thermal stress is applied to the high-resistivity region 34 when current flows through the substrate 12. Because the semiconductor substrate 12 is made of a compound semiconductor exhibiting ionic bonding characteristics, the internal polarity of the crystal may be disturbed when current flows through the semiconductor substrate 12. Furthermore, because the predetermined segmentation region 32 is arranged along the (100) and (001) planes of β-Ga2O3, cleavage may easily occur. For these reasons, during this process, when the current exceeds, for example, approximately 800 W / cm², the temperature rises to a higher temperature than the surrounding region. 2 When electrical power is applied to the semiconductor substrate 12, the semiconductor substrate 12 can be divided along the predetermined division region 32, such as Figure 4 As shown. As a result, the semiconductor substrate 12 is divided into a plurality of semiconductor devices 10.

[0054] (Second Embodiment)

[0055] In the manufacturing method of the second embodiment, the technique for flowing current in the semiconductor substrate 12 differs from that of the first embodiment. In the manufacturing method of the second embodiment, until... Figure 2 The process shown is the same as in the first embodiment. In the second embodiment, in Figure 2 Following the process shown, an electrode 18 is formed on the surface 12a of the semiconductor substrate 12, as follows: Figure 5As shown. In this case, electrode 18 is formed on the surface 12a of semiconductor substrate 12 along a predetermined segmentation region 32. Electrode 18 can be, for example, an electrode that contacts the Schottky electrode with semiconductor substrate 12. Electrode 18 can be formed to cover the entire surface of the predetermined segmentation region 32 on the surface 12a of semiconductor substrate 12, or it can be formed intermittently on the surface of the surface 12a of semiconductor substrate 12 that segments the predetermined segmentation region 32.

[0056] Next, current is allowed to flow through the semiconductor substrate 12 via electrodes 18 disposed on surface 12a of the semiconductor substrate 12. For example, current can be allowed to flow between the electrodes 18 and the rear surface 12b of the semiconductor substrate 12. Then, by exceeding approximately 800 W / cm 2 Electrical power is applied to the semiconductor substrate 12, which can be segmented along a predetermined segmentation region 32 as in the first embodiment. Figure 6 As shown, the semiconductor substrate 12 is divided into multiple semiconductor devices 10.

[0057] As described above, in the manufacturing methods of the first and second embodiments, the semiconductor substrate 12 can be easily segmented by applying a current through it. Therefore, for example, compared to cutting techniques using conventional cutting blades for segmenting semiconductor substrates, the semiconductor substrate 12 can be segmented in a shorter time. Furthermore, in the above embodiments, the semiconductor substrate 12 can be segmented at low cost without the need for cutting blades or cutting strips used to protect the surface of the semiconductor substrate during cutting.

[0058] Furthermore, in the first and second embodiments described above, since the semiconductor substrate 12 is divided by utilizing the cleavage of the compound semiconductor caused by the current flowing through it, damage is unlikely to remain on the dicing surface. Therefore, the dicing surface is substantially uniform, and the semiconductor device 10 can be manufactured in high yield.

[0059] In the first and second embodiments described above, the entire semiconductor substrate 12 is made of β-Ga2O3. Alternatively, only a predetermined segmentation region 32 in the semiconductor substrate 12 may be made of β-Ga2O3. That is, regions other than the predetermined segmentation region 32 (e.g., element region 30, etc.) may contain elements other than O and Ga.

[0060] Furthermore, in the above embodiments, current flows between the front surface 12a and the rear surface 12b of the semiconductor substrate 12. As another example, two or more probes or two or more electrodes 18 can be arranged at any location on the front surface 12a of the semiconductor substrate 12, and current can flow only near the front surface 12a of the semiconductor substrate, that is, only in the surface layer portion adjacent to the front surface 12a. Alternatively, current can flow only near the rear surface 12b of the semiconductor substrate 12 in a similar manner.

[0061] In the first and second embodiments described above, the high-resistivity region 34 is formed by ion implantation of a dopant. The formation of the high-resistivity region 34 is not limited to ion implantation of a dopant. The high-resistivity region 34 can be formed by introducing a dopant through epitaxial growth. As another example, the resistance of the predetermined segmented region 32 can be increased by introducing a dissimilar material different from the material constituting the semiconductor substrate 12 into the predetermined segmented region 32. For example, instead of... Figure 2 The process shown involves etching trenches from surface 12a along a predetermined segmentation region 32, and the interior of the trenches can be filled with a dissimilar material (e.g., SiO2). In this configuration, a high-resistivity region 34 extending from surface 12a of the semiconductor substrate 12 to a predetermined depth (i.e., the depth of the trench) can be formed.

[0062] Furthermore, in the first and second embodiments, a high-resistivity region 34 is formed by introducing a dopant. As another example, a high thermal resistance region with a higher thermal resistance than the surrounding region can be formed by introducing a dopant. A high thermal resistance region can be formed by introducing the aforementioned dissimilar material. In a high thermal resistance region, heat tends to be retained more easily than in the surrounding region when current flows through it, and the temperature may rise more significantly. Therefore, it is also possible to apply large thermal stress by forming such a high thermal resistance region. However, the aforementioned high-resistivity region 34 and high thermal resistance region may not be formed. That is, in the art disclosed herein, the process of introducing a dopant or dissimilar material is not always necessary. Even in such a configuration, the semiconductor substrate 12 can be cleaved along the cleavage plane by allowing current to flow through it.

[0063] In the first and second embodiments, the process of dividing the semiconductor substrate 12 into semiconductor devices 10 has been primarily described. Alternatively, the techniques described in the first and second embodiments can be applied, for example, to the step of thinning the semiconductor substrate 12. For example, as Figure 7As shown, a high-resistivity region 40 is formed by selectively ion-implanting dopant from the surface 12a of a semiconductor substrate 12 to a desired depth. Then, a probe 16 contacts the front surface 12a and the rear surface 12b of the semiconductor substrate 12, and current flows through the probe 16 in the semiconductor substrate 12, enabling the semiconductor substrate 12 to be cleaved along the high-resistivity region 40. By setting this surface along the high-resistivity region 40 as the (100) or (001) plane of β-Ga2O3, i.e., by setting the surface to be cleaved as the (100) or (001) plane of β-Ga2O3, the semiconductor substrate 12 can be cleaved more easily. This allows the semiconductor substrate 12 to be fabricated to be thinner.

[0064] The formation of the high-resistivity region 40 is not limited to the mode of ion implantation of dopant. For example, when the semiconductor substrate 12 is fabricated by epitaxial growth in the step of preparing the semiconductor substrate 12, a semiconductor material containing dopant can be epitaxially grown at the depth where the high-resistivity region 40 is to be formed. Furthermore, the semiconductor substrate 12 having the high-resistivity region 40 can be fabricated using different materials.

[0065] In the first and second embodiments described above, by applying more than approximately 800 W / cm to the semiconductor substrate 12 2 The semiconductor substrate 12 is divided along a predetermined division region 32 to increase the electrical power applied to it. During this process, as the electrical power applied to the semiconductor substrate 12 increases, a groove is formed along the predetermined division region 32 from the surface 12a of the semiconductor substrate 12 in the thickness direction. That is, the technique disclosed herein is also useful as a technique for forming trenches on the surface 12a of the semiconductor substrate 12.

[0066] (Third Embodiment)

[0067] The manufacturing method of the third embodiment will now be described. The manufacturing method of the third embodiment is characterized by bonding two semiconductor substrates 52 and 54, each of which is made of a specific material described later. The manufacturing method of the third embodiment is applicable to various semiconductor devices and their semi-finished products made of the specific material. In the following description, the process of bonding semiconductor substrates 52 and 54 will be primarily described, and descriptions of other manufacturing processes will be omitted. Semiconductor substrate 52 and semiconductor substrate 54 are examples of a "first substrate" and a "second substrate," respectively.

[0068] Semiconductor substrates 52 and 54 are made of compound semiconductors similar to those in the first and second embodiments. That is, semiconductor substrates 52 and 54 are made of β-Ga₂O₃. However, the materials of semiconductor substrates 52 and 54 are not limited to β-Ga₂O₃. Compound semiconductors containing a first element and a second element bonded to each other, wherein the electronegativity difference between the first element and the second element is 1.5 or greater, can be used as materials for semiconductor substrates 52 and 54. Generally, it is simply required that semiconductor substrate 12 be made of a material with ionic bonding properties. In β-Ga₂O₃, O corresponds to the first element and has an electronegativity of 3.44, and Ga corresponds to the second element and has an electronegativity of 1.81. The compound semiconductor constituting semiconductor substrate 12 may also contain elements different from the first and second elements. Examples of compound semiconductors constituting semiconductor substrate 12 may include gallium oxide semiconductors such as (Ga,Rh)₂O₃, (Ga,Ir)₂O₃, (Ga,Bi)₂O₃, and ZnGa₂O₄, as well as other oxide semiconductors.

[0069] First, such as Figure 8 As shown, a dopant is introduced into the surface 52a of the semiconductor substrate 52 by ion implantation. In this case, the dopant is introduced onto the entire surface 52a of the semiconductor substrate 52. As a result, a high-resistivity region 56 is formed in the area facing the surface 52a of the semiconductor substrate 52, i.e., in the surface portion of the surface 52a of the semiconductor substrate 52, where the ions are implanted. There are no particular limitations on the dopant to be introduced, but for example, Fe or V can be used. Next, as... Figure 9 As shown, semiconductor substrate 54 is stacked on surface 52a of semiconductor substrate 52.

[0070] Next, the stacked semiconductor substrates 52 and 54 are annealed in an oxygen-containing environment. An oxygen-containing environment refers to an environment containing oxygen as an element. For example, semiconductor substrates 52 and 54 are annealed in an environment such as oxygen (O2). As a result, the interface 55 between semiconductor substrates 52 and 54 has a high resistance. That is, during this process, the resistance in the region near the interface 55 of semiconductor substrates 52 and 54, which contains the high-resistance region 56, is further increased.

[0071] Subsequently, current is allowed to flow between semiconductor substrate 52 and semiconductor substrate 54. Specifically, as... Figure 9As shown, probe 59 contacts the front surface 54a of semiconductor substrate 54 and the rear surface 52b of semiconductor substrate 52, respectively. Current is then flowed through probe 59 in semiconductor substrates 52 and 54. A high-resistance region 56 has been formed in surface 52a of semiconductor substrate 52. Furthermore, the resistance near the interface 55 between semiconductor substrates 52 and 54 has increased due to annealing. Therefore, when current flows through the stack of semiconductor substrates 52 and 54, the temperature near interface 55 rises to a higher temperature than the surrounding region. As a result, a molten layer 60 is formed near interface 55 in which semiconductor material is melted, and the crystal structure in the molten layer 60 is disturbed. Subsequently, when the current flow stops, the disordered crystal structure rearranges again during the solidification process of the molten layer 60, and semiconductor substrates 52 and 54 are able to bond to each other. As described above, in the manufacturing method of the third embodiment, semiconductor substrates 52 and 54 can be easily bonded by flowing current through the stacked semiconductor substrates 52 and 54.

[0072] In the third embodiment, the entire semiconductor substrates 52 and 54 are made of β-Ga2O3. As another example, only the region near the front surface 52a of the semiconductor substrate 52 and the region near the rear surface 54b of the semiconductor substrate 54, i.e. only the region facing the coupling surface, can be made of β-Ga2O3.

[0073] In the third embodiment, the high-resistivity region 56 is formed by ion implantation of a dopant. As another example, the high-resistivity region 56 can be formed by epitaxially growing a dopant-containing semiconductor material on the surface 52a of the semiconductor substrate 52. As yet another example, the high-resistivity region 56 can be formed by forming a dissimilar material (e.g., SiO2, etc.) different from the material constituting the semiconductor substrate 52 on the surface 52a.

[0074] In the third embodiment, the high-resistance region 56 is formed in a surface layer portion adjacent to the front surface 52a of the semiconductor substrate 52. As another example, the high-resistance region may be formed in a surface layer portion adjacent to the rear surface 54a of the semiconductor substrate 54. Furthermore, the high-resistance region 56 may be formed in both the surface layer portion adjacent to the front surface 52a of the semiconductor substrate 52 and the surface layer portion adjacent to the rear surface 54a of the semiconductor substrate 54.

[0075] In the third embodiment, the high-resistivity region 56 is formed by ion implantation. As an alternative to or addition to the high-resistivity region 56, a high thermal resistance region with a higher thermal resistance than the surrounding region can be formed by ion implantation. The high thermal resistance region can be formed using a dopant or a dissimilar material as described above. In the high thermal resistance region, heat tends to be retained more easily than in the surrounding region when current flows, and the temperature may rise more than in the surrounding region. Therefore, forming a high thermal resistance region can induce large thermal stress. The high thermal resistance region can be formed in a surface layer portion near the front surface 52a of the semiconductor substrate 52, in a surface layer portion near the rear surface 54a of the semiconductor substrate 54, or in these surface layer portions of both the semiconductor substrate 52 and the semiconductor substrate 54. Similarly, as an alternative to or addition to the process of increasing the resistance of the interface 55 by annealing, the thermal resistance of the interface 55 between the semiconductor substrate 52 and the semiconductor substrate 54 can be increased by annealing. The aforementioned high-resistivity region 56 and high thermal resistance region may not be formed. That is, in the technology disclosed herein, it is not always necessary to provide a step of introducing dopants or dissimilar materials. Furthermore, it is not always necessary to have an annealing step. Even with this configuration, it is possible to bond the semiconductor substrates 52 and 54 by allowing current to flow between the semiconductor substrates 52 and 54.

[0076] While only selected exemplary embodiments and examples have been described to illustrate this disclosure, it will be apparent to those skilled in the art that various modifications and alterations can be made without departing from the scope of this disclosure as defined in the appended claims. Furthermore, the foregoing description of exemplary embodiments and examples provided according to this disclosure is for illustrative purposes only and is not intended to limit the disclosure as defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: preparing a substrate (12) made of a compound semiconductor containing a first element and a second element bonded to the first element and having an electronegativity smaller than that of the first element by 1.5 or more; causing a current to flow in the substrate (12) between a front surface (12a) and a back surface (12b); and splitting the substrate (12) at a position of a current region including the current flow and along a cleavage plane of the substrate (12).

2. The method according to claim 1, wherein a probe (16) is brought into contact with the substrate (12) to cause the current to flow between the substrate (12) and the probe (16) when the current is caused to flow.

3. The method according to claim 1, further comprising: forming an electrode (18) on the front surface of the current region, wherein the current is caused to flow in the substrate (12) through the electrode (18) when the current is caused to flow.

4. The method according to claim 3, wherein the electrode (18) is formed on the front surface of the current region along the cleavage plane when the electrode (18) is formed.

5. The method according to claim 1, further comprising: increasing the electrical resistance of the current region higher than that of a peripheral region on a periphery of the current region by introducing a dopant or a dissimilar material different from the compound semiconductor into the current region.

6. The method according to claim 1, further comprising: increasing the thermal resistance of the current region higher than that of a peripheral region on a periphery of the current region by introducing a dopant or a dissimilar material different from the compound semiconductor into the current region.

7. The method according to any one of claims 1 to 6, wherein the compound semiconductor is an oxide semiconductor; and the first element is oxygen.

8. The method according to claim 7, wherein the compound semiconductor consists of β-Ga2O3, and the cleavage plane is a (100) crystal plane and / or a (001) crystal plane of β-Ga2O3.

9. A method for manufacturing a semiconductor device, comprising: stacking a first substrate (52) and a second substrate (54); and bonding the first substrate (52) and second substrate (54) by causing a current to flow between the first substrate (52) and the second substrate (54), wherein the first substrate (52) and second substrate (54) are each made of a compound semiconductor, and the compound semiconductor contains a first element and a second element bonded to the first element and having an electronegativity smaller than that of the first element by 1.5 or more.

10. The method according to claim 9, further comprising: introducing a dopant or a dissimilar material different from the semiconductor compound into a surface (52a) of the first substrate (52) before stacking the first substrate (52) and the second substrate (54). wherein the second substrate (54) is laminated on a surface (52a) of the first substrate (52) when laminating the first substrate (52) and the second substrate (54).

11. The method according to claim 9, further comprising: increasing the electrical resistance of at least one of a surface layer portion of the first substrate (52) and a surface layer portion of the second substrate (54) by annealing at least one of the first substrate (52) and the second substrate (54) before bonding the first substrate (52) and the second substrate (54).

12. The method according to claim 9, wherein increasing the thermal resistance of at least one of a surface layer portion of the first substrate (52) and a surface layer portion of the second substrate (54) by annealing at least one of the first substrate (52) and the second substrate (54) before bonding the first substrate (52) and the second substrate (54).

13. The method according to any one of claims 9 to 12, wherein the compound semiconductor is an oxide semiconductor, and the first element is oxygen.

14. The method according to claim 13, wherein the compound semiconductor is made of β-Ga2O3.

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