Edge fin trimming process

Abstract

This disclosure relates to edge fin trimming processes. Semiconductor structures and methods are provided. In one embodiment, a method of this disclosure includes forming a plurality of semiconductor fins on a substrate, removing an outer semiconductor fin from the plurality of semiconductor fins after forming the plurality of semiconductor fins, and forming a gate structure on the plurality of semiconductor fins. The plurality of semiconductor fins has more than three semiconductor fins, and the removal causes a portion of the substrate directly below the outer semiconductor fin to be recessed.

Description

Technical Field

[0001] This disclosure generally relates to edge FIN trimming processes. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded several generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has typically increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization process generally provides benefits by increasing production efficiency and reducing associated costs. However, this miniaturization also increases the complexity of handling and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology has evolved to smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCE). Multi-gate devices generally refer to devices having a gate structure or a portion thereof disposed on more than one side of the channel region. FinFETs are an example of multi-gate devices and have become a popular and promising candidate for high-performance and low-leakage applications. FinFETs have a rise channel enclosed by gates located on more than one side (e.g., the gates enclose the top and sidewalls of a semiconductor material "fin" extending from the substrate).

[0004] In some existing technologies, the formation of a FinFET involves forming multiple semiconductor fins that extend parallel to each other. These multiple semiconductor fins can appear in groups. Each group can include a central portion and an edge portion. Because the semiconductor fins in the edge portions are in a more loosely stacked region, they may be wider than the semiconductor fins in the central portions. Therefore, while fin formation processes are generally sufficient to achieve their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a plurality of semiconductor fins on a substrate, the plurality of semiconductor fins having more than three semiconductor fins; after forming the plurality of semiconductor fins, removing an outer semiconductor fin from the plurality of semiconductor fins; and forming a gate structure on the plurality of semiconductor fins, wherein the removal causes a portion of the substrate directly below the outer semiconductor fin to be recessed.

[0006] According to another embodiment of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming a first plurality of semiconductor fins and a second plurality of semiconductor fins on a substrate, each of the first plurality of semiconductor fins and the second plurality of semiconductor fins comprising more than three semiconductor fins; after forming the first plurality of semiconductor fins and the second plurality of semiconductor fins, removing a first outer semiconductor fin from the first plurality of semiconductor fins and a second outer semiconductor fin from the second plurality of semiconductor fins; and forming a first gate structure fin on the first plurality of semiconductor fins and forming a second gate structure on the second plurality of semiconductor fins, wherein the removal forms a first groove located directly below the first outer semiconductor fin and a second groove located directly below the second outer semiconductor fin.

[0007] According to another embodiment of this disclosure, a method for forming a semiconductor structure is provided, comprising: providing a workpiece including a semiconductor layer on a substrate, the composition of the semiconductor layer being different from the composition of the substrate; forming a plurality of semiconductor fins from the semiconductor layer and the substrate, the plurality of semiconductor fins including more than three semiconductor fins; after forming the plurality of semiconductor fins, removing an outer semiconductor fin from the plurality of semiconductor fins; after removing the outer semiconductor fin, forming a semiconductor liner on the plurality of semiconductor fins; and forming a gate structure on the plurality of semiconductor fins, wherein the removal forms a recess located directly below the outer semiconductor fin. Attached Figure Description

[0008] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figure 1 A flowchart of a method for forming a semiconductor structure having a plurality of semiconductor fins according to one or more aspects of the present disclosure is shown.

[0010] Figures 2-14 The disclosure illustrates the basis for one or more aspects thereof. Figure 1 A partial cross-sectional view or top view of the workpiece during the manufacturing process of the method.

[0011] Figure 15 A flowchart of a method for forming a semiconductor structure having a plurality of semiconductor fins according to one or more aspects of the present disclosure is shown.

[0012] Figures 16-27 The disclosure illustrates the basis for one or more aspects thereof. Figure 15A partial cross-sectional view or top view of the workpiece during the manufacturing process of the method.

[0013] Figure 28 A flowchart of a method for forming a semiconductor structure having a plurality of semiconductor fins according to one or more aspects of the present disclosure is shown.

[0014] Figures 29-41 The disclosure illustrates the basis for one or more aspects thereof. Figure 28 A partial cross-sectional view or top view of the workpiece during the manufacturing process of the method. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Spatially related terms (e.g., “below,” “under,” “down,” “above,” “up,” etc.) are used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein will be interpreted accordingly.

[0017] Furthermore, when using terms such as "about," "approximately," etc., to describe numbers or ranges of numbers, the term is intended to cover a reasonable range of numbers that takes into account variations inherent during manufacturing, as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing features having numerical characteristics, the number or range of numbers covers a reasonable range including the described number, such as within + / - 10% of the described number. For example, a material layer having a thickness of "about 5 nm" can cover a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%. Further, reference numerals and / or letters may be repeated in various examples of this disclosure. Such repetition is for the purposes of simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, exemplary embodiments are described herein with reference to various schematic and / or idealized partial cross-sectional or top views. Therefore, variations in the illustrated shapes due to manufacturing tolerances are expected. Unless expressly specified herein, the shapes in the figures are not intended to illustrate actual shapes and should not limit the scope of this disclosure. Moreover, unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain.

[0019] IC devices can include a variety of transistors for different functions, such as logic functions, memory functions, input / output functions, or electrostatic discharge (ESD) functions. To meet the on-current, leakage, or resistance requirements of different functions, these transistors can have different active region arrangements. Some designs require multi-fin transistors with three or more semiconductor fins to increase on-current while maintaining gate control. To form such multi-fin transistors, fins can be formed in groups parallel to each other. It has been observed that when the number of fins in a group is three or more, the etch loading effect may cause the middle fin to be thinner than the edge fins. This is because the middle fin is located in a more densely packed region, while the edge fins are located in a more isolated or loosely packed region. The same effect was not observed in dual-fin devices because both fins in a dual-fin device are subjected to the same etch loading conditions. Since fins of different widths may exhibit different on-current and different gate control, fin width non-uniformity can lead to variations in device performance and process control.

[0020] This disclosure provides a method for reducing or eliminating fin width non-uniformity in a multi-fin device after fin formation. In one embodiment, after forming the semiconductor fins, the outer fins with larger widths are selectively removed. In another embodiment, the outer fins are selectively trimmed, while the remaining fins are protected by a mask. The semiconductor fins may include silicon, silicon-germanium, or germanium. The method of this disclosure can make the fins in a group uniform in width and improve device performance by 0.5% or more.

[0021] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 , Figure 15 and Figure 28 This is a flowchart illustrating methods 100, 300, and 400 for forming a semiconductor device according to embodiments of the present disclosure. Methods 100, 300, and 400 are merely examples and are not intended to limit the present disclosure to what is explicitly described in methods 100, 300, and 400. Additional steps may be provided before, during, and after methods 100, 300, or 400, and some described steps may be replaced, eliminated, or moved for additional embodiments of the methods. For simplicity, not all steps are described in detail herein. Methods 100, 300, and 400 are combined below. Figure 2-14 , Figure 16-27 and Figure 29-41 These figures are partial cross-sectional or top views of workpiece 200 at different manufacturing stages according to methods 100, 300, and 400. Since workpiece 200 will be manufactured into a semiconductor device or semiconductor structure at the end of the manufacturing process, workpiece 200 may also be referred to as semiconductor device 200 or semiconductor structure 200, depending on the context. Furthermore, throughout this application, unless otherwise stated, the same reference numerals denote the same features. Additionally, although the semiconductor device shown in the figures may have three fins, this disclosure is not limited to this and can be applied to semiconductor devices having three or more fins in a single transistor.

[0022] refer to Figure 1 and Figure 2 Method 100 includes a frame 102 in which a workpiece 200 is provided. For example... Figure 2As shown, workpiece 200 includes a substrate 202, a pad oxide layer 204, a pad nitride layer 206, an oxide mask layer 208, and a nitride mask layer 210. The substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also include an insulating layer (e.g., a silicon oxide layer) to have a silicon-on-insulator (SOI) structure. Figure 2 As shown, the workpiece 200 further includes a pad oxide layer 204 disposed on the substrate 202, a pad nitride layer 206 disposed on the pad oxide layer 204, an oxide mask layer 208 disposed on the pad nitride layer 206, and a nitride mask layer 210 disposed on the oxide mask layer 208. In some embodiments, the pad nitride layer 206 is thicker than the pad oxide layer 204, and the nitride mask layer 210 is thicker than the oxide mask layer 208. In some cases, the pad oxide layer 204 may comprise silicon oxide and may have approximately and The thickness between; the liner nitride layer 206 may include silicon nitride and may have approximately Peace Treaty The thickness between; the oxide mask layer 208 may include silicon oxide and may have approximately Peace Treaty The thickness between; and the nitride mask layer 210 may include silicon nitride and may have approximately Peace Treaty The thickness between layers. The pad oxide layer 204, pad nitride layer 206, oxide mask layer 208 and nitride mask layer 210 can be deposited using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD) or low-pressure CVD (LPCVD).

[0023] refer to Figure 1 and Figure 2Method 100 includes a block 104 in which a patterned nitride mask layer 210 is disposed. At block 104, the nitride mask layer 210 can be patterned using photolithography and etching processes. In an example process, a photoresist layer (not explicitly shown) is deposited over the nitride mask layer 210. The photoresist layer is exposed to patterned radiation reflected or transmitted through the photomask, developed in a developer solution, and baked in a baking process to form the patterned photoresist layer. When the nitride mask layer 210 is etched in a dry etching process, the patterned photoresist layer can then be used as an etching mask to form… Figure 2 The patterned nitride mask layer 210 is shown. An example dry etching process can be a reactive ion etching (RIE) process using the following: nitrogen, fluorine-containing gases (e.g., CF4, NF3, SF6, CH2F2, CHF3 and / or C2F6), hydrocarbons (e.g., methane), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof.

[0024] refer to Figure 1 and Figure 3 Method 100 includes block 106, in which a patterned nitride mask layer 210 is used as an etching mask to pattern an oxide mask layer 208, a pad nitride layer 206, and a pad oxide layer 204. In some embodiments, the etching process at block 106 may be a reactive ion etching (RIE) process using oxygen, hydrogen, fluorine-containing gases (e.g., CF4, NF3, SF6, CH2F2, CHF3, and / or C2F6), hydrocarbons (e.g., methane), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. At the end of the operation at block 106, a patterned oxide mask layer 2080 is formed. The patterned oxide mask layer 2080 includes a pad oxide layer 204, a pad nitride layer 206, and an oxide mask layer 208. In some cases, the patterns in the patterned oxide mask layer 2080 may have uneven widths. To prevent uneven pattern widths from leading to uneven fin widths, additional photolithography and etching processes can be selectively performed to trim wider patterns.

[0025] refer to Figure 1 and Figure 4Method 100 includes block 108, in which a substrate 202 is patterned to form multiple sets of fins 212. In block 108, a patterned oxide mask layer 2080 is used as an etching mask to anisotropically etch the substrate 202. In some embodiments, the anisotropic etching can be performed using a RIE process utilizing: hydrogen, fluorine-containing gases (e.g., CF4, NF3, SF6, CH2F2, CHF3 and / or C2F6), hydrocarbons (e.g., methane), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. Figure 4 As shown, anisotropic etching can form multiple sets of fins, such as a first set of fins 212-1 and a second set of fins 212-2. The first set of fins 212-1 is spaced apart from the second set of fins 212-2 by an opening 214. The first set of fins 212-1 includes fins 212 and edge fins 212E interlaced by grooves 213. Edge fins 212E may also be referred to as outer fins 212E. Similarly, the second set of fins 212-2 includes fins 212 and edge fins 212E interlaced by grooves 213. In the depicted embodiment, fins adjacent to the opening 214 (in the first set of fins 212-1 and the second set of fins 212-2) are not considered edge fins, especially when the width of the opening 214 is less than about 55 nm. Due to its small width, the opening 214 does not cause a significant loading effect that requires correction. Figure 4 As shown, a portion of the pad oxide layer 204 and a portion of the pad nitride layer 206 can be retained on the fin 212 or edge fin 212E. In the depicted embodiment, the oxide mask layer 208 can be substantially removed during etching of the substrate 202. Figure 4 In the illustrated embodiment, fin 212 and edge fin 212E may have tapered sidewalls and may have similar heights. The heights of fin 212 and edge fin 212E may be between approximately 50 nm and approximately 150 nm, excluding the thickness of the pad oxide layer 204 and the pad nitride layer 206. Additionally, due to the etch loading effect, the width of each edge fin 212E may be greater than the width of each fin 212. For example, each edge fin 212E may have a bottom fin width WW, and each fin 212 may have a bottom fin width WB. The bottom fin width WW of each edge fin 212E may be greater than the bottom fin width WB of each fin 212. In some cases, the bottom fin width WW may be between approximately 12 nm and approximately 25 nm, and the bottom fin width WB may be between approximately 10 nm and approximately 20 nm.

[0026] refer to Figure 1 and Figure 5Method 100 includes frame 110, wherein a mask layer 2200 is deposited over a workpiece 200. In the depicted embodiment, the mask layer 2200 is multilayered and includes a base layer 216, an intermediate layer 218, and a photoresist layer 220. A curing process, such as an annealing process, can be performed after the base layer 216 is deposited. During formation, the base layer 216 is a carbon-containing layer and may include silicon carbide (SiC), silicon carbide oxide (SiOC), or spin-coated carbon (SOC). The intermediate layer 218 is a silicon-containing layer comprising silicon, nitrogen, and hydrogen. In one embodiment, the intermediate layer 218 is a bottom antireflective coating (BARC) layer and includes a polysilazane resin. The base layer 216 can be considered a carbon hard mask layer, and the intermediate layer 218 can be considered a silicon hard mask layer. The base layer 216, the intermediate layer 218, and the photoresist layer 220 can be deposited using flowable CVD (FCVD) or spin coating. After depositing the underlayer 216, intermediate layer 218, and photoresist layer 220, a curing process, such as annealing or baking, can be performed. Mask layer 2200 can also be referred to as a three-layer mask. Figure 5 As shown, the bottom layer 216 fills the groove 213 and opening 214 between the fin 212 and the edge fin 212E.

[0027] refer to Figure 1 , Figure 6 and Figure 7 Method 100 includes a frame 112 in which a patterned mask layer 2200 is used to expose the outer fins 212E. In an example process, a photoresist layer 220 is first patterned using a photolithography process to form a patterned photoresist layer 220 including an opening 222 located directly above the edge fins 212E. In some embodiments, the patterned photoresist layer 220 can be treated with hydrogen bromide (HBr) plasma to improve line edge roughness (LER) and line width roughness (LWR). Subsequently, the pattern of the patterned photoresist layer 220 is transferred to an intermediate layer 218 using an etching process utilizing a gas containing fluorine and carbon. In one embodiment, the intermediate layer 218 is etched in a dry etching process using difluoromethane (CH2F2). The pattern of the intermediate layer 218 is then transferred to a carbon-rich bottom layer 216, such as... Figure 7 As shown. In one embodiment, the bottom layer 216 is etched in a dry etching process that includes the use of oxygen (O2) and sulfur dioxide (SO2). Figure 7 In some embodiments shown, to ensure protection of the fins 212 except for the edge fins 212E, the bottom layer 216 is not etched through its entire thickness. For example... Figure 7 As shown, a portion of the bottom layer 216 above the edge fin 212E is etched or pulled back to expose a portion or top of the edge fin 212E. After the bottom layer 216 is patterned, a patterned mask layer 2200 is formed.

[0028] refer to Figure 1and Figure 8 Method 100 includes block 114, in which external fins 212E are removed. At block 114, external fins 212E in the first group of fins 212-1 and the second group of fins 212-2 are removed. Figure 7 When (as shown), a patterned mask layer 2200 is applied as an etching mask. In some embodiments, the outer fin 212E is removed by a dry etching process including: oxygen, hydrogen, fluorine-containing gases (e.g., CF4, NF3, SF6, CH2F2, CHF3 and / or C2F6), hydrocarbons (e.g., methane), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. In one embodiment, the dry etching process at block 114 may include the use of sulfur hexafluoride (SF6), difluoromethane (CH2F2), fluoromethane (CH3F), and oxygen (O2). In this embodiment, the flow rate ratio of sulfur hexafluoride (SF6) to difluoromethane (CH2F2) is between about 3 and about 4, the flow rate of fluoromethane (CH3F) is between 10 standard cubic centimeters per minute (SCCM) and about 30 SCCM, and the flow rate ratio of difluoromethane (CH2F2) to oxygen (O2) is between about 1 and about 2. To prevent short circuits or leaks due to the presence of residual edge fins 212E, dry etching is performed at block 114 until an edge groove 212R is formed beneath the removed edge fins 212E. The edge groove 212R extends vertically into the substrate 202. According to this disclosure, the dry etching process at block 114 is selected such that it selectively etches the edge fins 212E relative to the underlying layer 216, which serves as a carbon hard mask. Figure 8 As shown, selective etching of the edge fin 212E essentially does not etch the underlying layer 216, and some residual underlying features 2160 can remain on the substrate 202 adjacent to the edge groove 212R.

[0029] refer to Figure 1 and Figure 9 Method 100 includes block 116, in which the underlying layer 216 is selectively removed. In some embodiments, a dry etching process implementing oxygen (O2) and sulfur dioxide (SO2) can be used to selectively remove the remaining underlying layer 216 and underlying features 2160. Because the dry etching process at block 116 is selective for the underlying layer 216, the substrate 202 and fins 212 are substantially unetched at block 116. Figure 9 In some embodiments shown, one or more etching processes may also be used to remove the pad oxide layer 204 and pad nitride layer 206 above the fin 212. In some alternative embodiments, the pad oxide layer 204 and pad nitride layer 206 may be removed after the isolation features (described below) are formed.

[0030] refer to Figure 1 , Figure 10 , Figure 11 , Figure 12 and Figure 14 Method 100 includes block 118, in which further processing is performed. This further processing may include fin roughing processes (such as...). Figure 10 As shown), an isolation feature 226 is formed between fins 212 (as shown). Figure 11 As shown), a dielectric fin 228 is formed on the isolation feature 226 (as shown). Figure 11 As shown), forming a dummy gate stack 230 (as shown). Figure 12 (as shown), forming source / drain characteristics (not explicitly shown), removing dummy gate stack 230 (as shown) Figure 13 As shown), and forming a gate structure (as shown). Figure 14 (As shown).

[0031] First refer to Figure 10 The diagram shows a schematic top view of workpiece 200. The removal of edge fins 212E at box 114 is along the longitudinal direction of edge fin 212E and can be referred to as a fine fin cutting process. In contrast to a fine fin cutting process, a coarse fin cutting process refers to the process of removing regions extending along the length direction of fin 212. An example coarse fin cutting process includes depositing a mask layer similar to mask layer 2200, patterning the mask layer to form a patterned mask layer with openings spanning and across several fins 212. Figure 10 In some of the examples shown, the notch or opening 224 may also extend over a portion of the edge groove 212R. A patterned mask layer is then applied as an etching mask to etch the fin 212. As a result, the notch 224 may extend along the X direction across several fins 212 extending longitudinally along the Y direction. It should be noted that if the opening in the patterned mask layer includes optical aids that help prevent the edges from rounding at the intersection of the fine fin cutting process and the coarse fin cutting process, the fine fin cutting process and the coarse fin cutting process at box 114 can theoretically be performed simultaneously. When the fine fin cutting process and the coarse fin cutting process are performed simultaneously, both can be performed at box 114 of method 100.

[0032] refer to Figure 11 Isolation features 226 are formed on substrate 202 to isolate fins 212 from each other. Isolation features 226 are also formed in edge grooves 212R and openings 214 (e.g., ...). Figure 4(Shown) Above and within. In the depicted embodiment, isolation feature 226 surrounds the bottom portion of fin 212. Isolation feature 226 may be referred to as shallow trench isolation (STI) feature 226. In the example process, a dielectric layer is first deposited on substrate 202 to fill trenches. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by CVD processes, subatmospheric CVD (SACVD) processes, FCVD processes, spin coating processes, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by dry etching processes, wet etching processes, and / or combinations thereof to form isolation feature 226.

[0033] Still referencing Figure 11 Dielectric fins 228 can be formed over isolation feature 226. In an example process, a first dielectric layer and a second dielectric layer can be sequentially and conformally deposited over workpiece 200, including over fin 212 and isolation feature 226. The composition of the first dielectric layer can be similar to that of isolation feature 226. The second dielectric layer can include a dielectric material different from that of isolation feature 226. In some embodiments, the second dielectric layer can include silicon nitride, silicon carbonitride, silicon carbonitride oxycarbonate, aluminum oxide, zinc oxide, titanium oxide, zirconium oxide, hafnium oxide, or other suitable metal oxides. After depositing the first and second dielectric layers, the first dielectric layer is selectively etched back until the second dielectric layer rises above isolation feature 226 to form dielectric fins 228. That is, dielectric fins 228 and the second dielectric layer share the same composition.

[0034] refer to Figure 12A dummy gate stack 230 is deposited on workpiece 200, including on fin 212, isolation feature 226, and dielectric fin 228. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 230 serves as a placeholder for various processes and is removed and replaced by a functional gate structure. Although not explicitly shown, the dummy gate stack 230 may include a dummy gate dielectric layer and a dummy gate electrode on top of the dummy gate dielectric layer. In some cases, the dummy gate dielectric layer may include silicon oxide. The dummy electrode layer may include polysilicon. Although not explicitly shown in the figures, one or more gate spacers may be deposited on the sidewalls of the dummy gate stack 230, and the source / drain regions of fin 212 may be recessed. Epitaxial features may then be formed on the recessed source / drain regions. Epitaxial features may include silicon (Si) doped with an n-type dopant (e.g., phosphorus (P) or arsenic (As)) or silicon germanium (SiGe) doped with a p-type dopant (e.g., boron (B) or boron difluoride (BF2)). After forming the epitaxial features, a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer may be sequentially deposited on the workpiece 200.

[0035] refer to Figure 13 After forming the ILD layer, the dummy gate stack 230 can be removed to expose the fin 212. (See reference...) Figure 14A first gate structure 240 is formed on fin 212 (excluding the removed edge fin 212E) in the first group of fins 212-1, and a second gate structure 242 is formed on fin 212 (excluding the removed edge fin 212E) in the second group of fins 212-2. The first gate structure 240 and the second gate structure 242 are spaced apart integrally or partially by dielectric fins 228. Each of the first gate structure 240 and the second gate structure 242 may include a gate dielectric layer 236 and a gate electrode layer 238. The gate dielectric layer 236 may include an interface layer and a high-k dielectric layer. The interface layer may include silicon oxide, hafnium silicate, or silicon oxynitride. The high-k dielectric layer may include hafnium oxide. Alternatively, the high-k dielectric layer may comprise other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. Figure 14 In some embodiments shown, the first gate structure 240 is configured to control a transistor comprising three fins 212 of a first set of fins 212-1, and the second gate structure 242 is configured to control another transistor comprising three fins 212 of a second set of fins 212-2. In the depicted embodiments, each of the first gate structure 240 and the second gate structure 242 extends over an edge recess 212R, which is now filled with an isolation feature 226.

[0036] Still referencing Figure 14 Since the wider edge fins 212E have been removed at box 114 in method 100, the size, profile angle, and shape of the fins 212 in the first group of fins 212-1 and the second group of fins 212-2 are essentially the same. For example... Figure 14As shown, each fin 212 may include a bottom width WB, a top width WT, and a profile angle θ. In some cases, the bottom width WB may be between about 10 nm and about 20 nm, the top width WT may be between about 8 nm and about 19 nm, and the profile angle θ may be between about 83° and about 90°. The edge groove 212R is now filled with the isolation feature 226. Each edge groove 212R has a width WR and a depth DR. In some cases, the width WR may be between about 15 nm and about 30 nm, and the depth DR may be between about 5 nm and about 50 nm. As measured from the lowest point of the edge groove 212R to the highest point of the fin 212, the absolute fin height H may be between about 100 nm and about 200 nm.

[0037] In some other embodiments, the multiple sets of semiconductor fins may include a silicon-germanium layer or a germanium layer. In those embodiments, method 300 may be used.

[0038] refer to Figure 15 and Figure 16 Method 300 includes a frame 302 in which a workpiece 200 is provided. For example... Figure 16 As shown, workpiece 200 includes a substrate 202, a semiconductor layer 203 over the substrate 202, a pad oxide layer 204 over the semiconductor layer 203, a pad nitride layer 206 over the pad oxide layer 204, an oxide mask layer 208 over the pad nitride layer 206, and a nitride mask layer 210 over the oxide mask layer 208. The substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include a III-V semiconductor material. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also include an insulating layer (e.g., a silicon oxide layer) to have a silicon-on-insulator (SOI) structure. The composition of the semiconductor layer 203 differs from that of the substrate 202. In some embodiments, the semiconductor layer 203 may comprise germanium (Ge) or silicon germanium (SiGe). Figure 16 The pad oxide layer 204, pad nitride layer 206, oxide mask layer 208, and nitride mask layer 210 shown herein are in relation to their respective substrates. Figure 2 The counterparts shown are similar. Detailed descriptions of them are omitted for brevity. Oxide mask layer 208 and nitride mask layer 210 are thicker than pad oxide layer 204 and pad nitride layer 206 because they serve as mask layers. Pad oxide layer 204 and pad nitride layer 206 are thinner because they serve as etch stop layers for removing oxide mask layer 208.

[0039] refer to Figure 15 and Figure 16 Method 300 includes box 304, in which a nitride mask layer 210 is patterned. The operation of box 304 is similar to that of box 104. Therefore, for the sake of brevity, a detailed description of the operation of box 304 is omitted.

[0040] refer to Figure 15 and Figure 17 Method 300 includes block 306, in which a patterned nitride mask layer 210 is used as an etch mask to pattern an oxide mask layer 208, a pad nitride layer 206, and a pad oxide layer 204. The operation of block 306 is similar to that of block 106. Therefore, a detailed description of the operation of block 306 is omitted for brevity. At the end of the operation of block 306, a patterned oxide mask layer 2080 is formed.

[0041] refer to Figure 15 and Figure 18 Method 300 includes block 308, in which a semiconductor layer 203 and a substrate 202 are patterned to form multiple sets of heterogeneous fins. At block 308, a patterned oxide mask layer 2080 is used as an etching mask to anisotropically etch the substrate 202 and the semiconductor layer 203. In some embodiments, the anisotropic etching can be performed using a RIE process utilizing oxygen, hydrogen, fluorine-containing gases (e.g., CF4, NF3, SF6, CH2F2, CHF3 and / or C2F6), hydrocarbons (e.g., methane), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. Figure 18As shown, anisotropic etching can form multiple sets of heterogeneous fins, such as a first set of heterogeneous fins 2120-1 and a second set of heterogeneous fins 2120-2. The first set of heterogeneous fins 2120-1 and the second set of heterogeneous fins 2120-2 are spaced apart by an opening 214. The first set of heterogeneous fins 2120-1 includes heterogeneous fins 2120 and edge heterogeneous fins 2120E that are interlaced by trenches 213. The edge heterogeneous fins 2120E can also be referred to as outer heterogeneous fins 2120E. Similarly, the second set of heterogeneous fins 2120-2 includes heterogeneous fins 2120 and edge heterogeneous fins 2120E that are interlaced by trenches 213. Compared to fins 212 formed only by the substrate 202, heterogeneous fins 2120 and edge heterogeneous fins 2120E are formed not only by the substrate 202 but also by the semiconductor layer 203. As a result, each of them includes a lower portion formed by substrate 202 and a top portion formed by semiconductor layer 203. In the depicted embodiment, the heterostructure fins (in the first set of heterostructure fins 2120-1 and the second set of heterostructure fins 2120-2) adjacent to the opening 214 are not considered edge fins, especially when the width of the opening 214 is less than about 55 nm. Figure 18 As shown, a portion of the pad oxide layer 204 and a portion of the pad nitride layer 206 can be retained on the heterostructure fin 2120 or the edge heterostructure fin 2120E. In the depicted embodiment, the oxide mask layer 208 can be substantially removed during etching of the substrate 202 and the semiconductor layer 203. Figure 18 In the illustrated embodiment, heterostructure fin 2120 and edge heterostructure fin 2120E may have tapered sidewalls and may have similar heights. The heights of heterostructure fin 2120 and edge heterostructure fin 2120E may be between approximately 50 nm and approximately 150 nm, excluding the thickness of the pad oxide layer 204 and the pad nitride layer 206. Additionally, due to the etch loading effect, the width of each edge heterostructure fin 2120E may be greater than the width of each heterostructure fin 2120. For example, each edge heterostructure fin 2120E may have a bottom fin width WW, and each heterostructure fin 2120 may have a bottom fin width WB. The bottom fin width WW of each edge heterostructure fin 2120E may be greater than the bottom fin width WB of each heterostructure fin 2120. In some cases, the bottom fin width WW may be between approximately 12 nm and approximately 25 nm, and the bottom fin width WB may be between approximately 10 nm and approximately 20 nm.

[0042] refer to Figure 15 and Figure 19 Method 300 includes a frame 310, wherein a mask layer 2200 is deposited on a workpiece 200. In the depicted embodiment, the mask layer 2200 is multilayered and includes a bottom layer 216, an intermediate layer 218, and a photoresist layer 220. Figure 19 The bottom layer 216, the intermediate layer 218, and the photoresist layer 220 shown are in relation to them. Figure 5 The corresponding counterparts shown are similar. Detailed descriptions of them have been omitted for brevity.

[0043] refer to Figure 15 , Figure 20 and Figure 21 Method 300 includes box 312, in which a patterned mask layer is used to expose the outer fins of each set of fins. The operation at box 312 is similar to the operation at box 112. Therefore, for the sake of brevity, a detailed description of the operation at box 312 is omitted.

[0044] refer to Figure 15 and Figure 22 Method 300 includes block 314, in which the outer fin 2120E is removed. The operation at block 314 is similar to that at block 114. Therefore, for brevity, a detailed description of the operation at block 314 is omitted. Note that because the semiconductor layer 203 is etched faster than the substrate 202, the edge heterostructure fin 2120E is etched faster than the edge fin 212E. Figure 22 As shown, the removal of the edge heterogeneous fin 2120E leaves an edge groove 212R.

[0045] refer to Figure 15 and Figure 23 Method 300 includes box 316, in which the underlying layer is selectively removed. The operation at box 316 is similar to the operation at box 116. Therefore, for the sake of brevity, a detailed description of the operation at box 314 is omitted.

[0046] refer to Figure 15 and Figure 23 Method 300 includes block 318, wherein a silicon liner 244 is deposited on workpiece 200. In some embodiments, the silicon liner 244 may be epitaxially deposited using CVD deposition techniques, such as vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. In some other embodiments, the silicon liner 244 may be deposited using CVD.

[0047] refer to Figure 1 , Figure 24 , Figure 25 , Figure 26 and Figure 27 Method 300 includes block 320, in which further processing is performed. This further processing may include fin roughing processes (such as...). Figure 24 As shown), an isolation feature 226 is formed between the heterogeneous fins 2120 (as shown). Figure 25 As shown), a dielectric fin 228 is formed on the isolation feature 226 (as shown). Figure 25 As shown), forming a dummy gate stack 230 (as shown). Figure 26(as shown), forming source / drain features (not explicitly shown), and replacing the dummy gate stack with gate structures 238 and 240 (as shown). Figure 27 (As shown). The operation at box 320 is similar to the operation at box 118. Therefore, for the sake of brevity, a detailed description of the operation at box 320 is omitted. Figure 27 In some embodiments shown, the first gate structure 240 is configured to control a transistor comprising three heterostructure fins 2120 in a first set of heterostructure fins 2120-1, and the second gate structure 242 is configured to control another transistor comprising three heterostructure fins 2120 in a second set of heterostructure fins 2120-2. In the depicted embodiment, each of the first gate structure 240 and the second gate structure 242 extends over an edge recess 212R, which is now filled with an isolation feature 226.

[0048] Still referencing Figure 27 Since the wider edge heterogeneous fin 2120E has been removed at box 314 of method 300, the size, profile angle, and shape of the heterogeneous fins 212 in the first group of heterogeneous fins 2120-1 and the second group of heterogeneous fins 2120-2 are basically the same. For example... Figure 27 As shown, each heterogeneous fin 212 may include a bottom width WB, a top width WT, and a profile angle θ. In some cases, the bottom width WB may be between about 10 nm and about 20 nm, the top width WT may be between about 8 nm and about 19 nm, and the profile angle θ may be between about 83° and about 90°. The edge groove 212R is now filled with the isolation feature 226. Each edge groove 212R has a width WR and a depth DR. In some cases, the width WR may be between about 15 nm and about 30 nm, and the depth DR may be between about 5 nm and about 50 nm. As measured from the lowest point of the edge groove 212R to the highest point of the heterogeneous fin 2120, the absolute fin height H may be between about 100 nm and about 200 nm.

[0049] In other embodiments, the external fins are not removed but only trimmed. In those embodiments, method 400 can be used.

[0050] refer to Figure 28 and Figure 29 Method 400 includes a box 402 in which a workpiece 200 is provided. The operation of box 402 is similar to that of box 102. Therefore, for the sake of brevity, a detailed description of the operation at box 402 is omitted.

[0051] refer to Figure 28 and Figure 29Method 400 includes box 404, in which a nitride mask layer 210 is patterned. The operation of box 404 is similar to that of box 402. Therefore, for the sake of brevity, a detailed description of the operation of box 402 is omitted.

[0052] refer to Figure 28 and Figure 30 Method 400 includes block 406, in which a patterned nitride mask layer 210 is used as an etch mask to pattern an oxide mask layer 208, a pad nitride layer 206, and a pad oxide layer 204. The operation of block 406 is similar to that of block 106. Therefore, a detailed description of the operation of block 406 is omitted for brevity. At the end of the operation of block 406, a patterned oxide mask layer 2080 is formed.

[0053] refer to Figure 28 and Figure 31 Method 400 includes a frame 408 in which a substrate 202 is patterned to form sets of fins 212. The operation of frame 408 is similar to that of frame 108. Therefore, a detailed description of the operation of frame 408 is omitted for brevity. Note that because method 400 trims edge fins rather than removes them, the number of fins in the first set of fins 212-1 and the second set of fins 212-2 remains the same throughout the operation of method 400. When method 100 or method 300 is used, at least one additional fin 212 or heterogeneous fin 2120 is formed such that after removing edge fins 212E or edge heterogeneous fins 2120E, the number of fins or heterogeneous fins meets the desired number. In the depicted embodiment, three fins 212 are required in each set of fins, and no more and no less than three fins 212 are formed at frame 408, as shown below. Figure 31 As shown.

[0054] refer to Figure 28 and Figure 32 Method 400 includes frame 410, in which a mask layer 2200 is deposited on workpiece 200. The operation of frame 410 is similar to that of frame 110. Therefore, a detailed description of the operation of frame 410 is omitted for brevity.

[0055] refer to Figure 28 , Figure 33 , Figure 34 and Figure 35 Method 400 includes frame 412, in which a patterned mask layer 2200 is used to expose the outer fins 212E of each fin group. The operation of frame 412 is similar to that of frame 112. The difference between frame 412 and frame 112 is that, in frame 412, the underlying layer 216 above and around the edge fins 212E is further etched to expose the sidewalls of the edge fins 212E. Full exposure of the sidewalls of the edge fins 212E allows for trimming of the edge fins 212E in frame 414.

[0056] refer to Figure 28 and Figure 36 Method 400 includes block 414, in which the outer fins 212E are trimmed. At block 414, a patterned mask layer 2200 is used as a trimming mask when trimming the outer fins 212E in the first set of fins 212-1 and the second set of fins 212-2. In some embodiments, the outer fins 212E are trimmed using an isotropic wet etching process or an isotropic dry etching process. Example isotropic wet etching processes include using ethylenediamine pyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), ammonia (NH3), ammonium fluoride (NH4F), or a suitable wet etchant. Example isotropic dry etching processes include using fluorine-containing gases (e.g., CF4, NF3, SF6, CH2F2, CH3F, CHF3, and / or C2F6), argon (Ar), helium (He), sulfur dioxide (SO2), ammonia (NH3), or methane (CH4). Figure 36 As shown, the trimming at box 414 involves slightly etching the edge fin 212E from all directions to form a thinner trimmed fin 212T. The etching parameters at box 414 are selected so that the size of the trimmed fin 212T is similar to that of the fin 212. In the depicted embodiment, due to the use of an isotropic etching process, the top surface of the trimmed fin 212T can be more rounded than that of the fin 212, such as... Figure 36 As shown.

[0057] refer to Figure 28 and Figure 36 Method 400 includes box 416, in which the underlying layer 216 is selectively removed. The operation of box 416 is similar to that of box 116. Therefore, for the sake of brevity, a detailed description of the operation at box 416 is omitted.

[0058] refer to Figure 1 , Figure 37 , Figure 38 , Figure 39 , Figure 40 and Figure 41 Method 400 includes box 418, in which further processing is performed. The operation of box 418 is similar to that of box 118. Figure 41 In some embodiments shown, the first gate structure 240 is configured to control a transistor comprising two fins 212 in a first set of fins 212-1 and a trimmed fin 212T, and the second gate structure 242 is configured to control another transistor comprising two fins 212 in a second set of fins 212-2 and a trimmed fin 212T. Since no edge recess 212R is formed, neither the first gate structure 240 nor the second gate structure 242 is in contact with... Figure 27 or Figure 41 The edge groove 212R shown extends over any edge groove similar to the one shown.

[0059] Now for reference Figure 41 Since the wider edge fin 212E has been trimmed in frame 414 to form the trimmed fin 212T, the size, outline angle, and shape of the fins 212 and trimmed fin 212T in the first set of fins 212-1 and the second set of fins 212-2 are basically the same. For example... Figure 41 As shown, each of fin 212 and trimmed fin 212T may include a bottom width WB, a top width WT, and a profile angle θ. In some cases, the bottom width WB may be between about 10 nm and about 20 nm, the top width WT may be between about 8 nm and about 19 nm, and the profile angle θ may be between about 83° and about 90°. The edge groove 212R is now filled with isolation feature 226. Each edge groove 212R has a width WR and a depth DR. In some cases, the width WR may be between about 15 nm and about 30 nm, and the depth DR may be between about 5 nm and about 55 nm.

[0060] The embodiments of this disclosure offer advantages. For example, the methods of this disclosure remove or trim wider external fins so that the transistor fins have a consistent size and profile. Fin removal or trimming is performed after fin formation.

[0061] In one exemplary aspect, this disclosure relates to a method. The method includes forming a plurality of semiconductor fins on a substrate, the plurality of semiconductor fins having more than three semiconductor fins; after forming the plurality of semiconductor fins, removing an outer semiconductor fin from the plurality of semiconductor fins; and forming a gate structure on the plurality of semiconductor fins. The removal causes a portion of the substrate directly beneath the outer semiconductor fin to be recessed.

[0062] In some embodiments, the outer semiconductor fin is not disposed between two of the plurality of semiconductor fins. In some embodiments, the width of the outer semiconductor fin is greater than the width of any of the remaining semiconductor fins in the plurality of semiconductor fins. In some embodiments, forming the plurality of semiconductor fins includes depositing a pad oxide layer on a substrate, depositing a pad nitride layer on the pad oxide layer, depositing an oxide layer on the pad nitride layer, forming a first patterned hard mask on the oxide layer, etching the pad oxide layer, pad nitride layer, and oxide layer using the first patterned hard mask as an etch mask to form a second patterned hard mask from the oxide layer, pad nitride layer, and pad oxide layer, and etching the pad using the second patterned hard mask as an etch mask. In some cases, removing the outer semiconductor fin includes depositing an underlayer on the plurality of semiconductor fins, depositing an intermediate layer on the underlayer, and depositing a photoresist layer on the intermediate layer. In some embodiments, removing the outer semiconductor fin further includes curing a photoresist layer, etching the photoresist layer directly above the outer semiconductor fin, etching the intermediate layer directly above the outer semiconductor fin using difluoromethane, etching the bottom layer directly above the outer semiconductor fin using oxygen and sulfur dioxide, and etching the outer semiconductor fin using a fluorine-containing gas. In some embodiments, the method further includes, after removing the outer semiconductor fin, forming a fin-cutting groove across a plurality of semiconductor fins to divide each of the plurality of semiconductor fins into a first portion and a second portion. In some cases, the plurality of semiconductor fins extend longitudinally along a first direction, and the fin-cutting groove extends along a second direction perpendicular to the first direction.

[0063] In another exemplary aspect, this disclosure relates to a method. The method includes forming a first plurality of semiconductor fins and a second plurality of semiconductor fins on a substrate, each of the first plurality of semiconductor fins and the second plurality of semiconductor fins including more than three semiconductor fins; after forming the first plurality of semiconductor fins and the second plurality of semiconductor fins, removing a first outer semiconductor fin from the first plurality of semiconductor fins and a second outer semiconductor fin from the second plurality of semiconductor fins; and forming a first gate structure fin on the first plurality of semiconductor fins and forming a second gate structure on the second plurality of semiconductor fins. This removal forms a first recess located directly beneath the first outer semiconductor fin and a second recess located directly beneath the second outer semiconductor fin.

[0064] In some embodiments, the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by an opening. In some embodiments, the method may further include forming isolation features between the first plurality of semiconductor fins, between the second plurality of semiconductor fins, over the first recess, over the second recess, and over the opening before forming the first gate structure and the second gate structure. In some embodiments, the method may further include forming a dielectric fin over the isolation feature in the opening. In some cases, after forming the first gate structure and the second gate structure, the first gate structure and the second gate structure are spaced apart by dielectric fins. In some cases, after removing the first and second external semiconductor fins, each of the first plurality of semiconductor fins and the second plurality of semiconductor fins includes a bottom width and a top width. The bottom width is between about 10 nm and about 20 nm, and the top width is between about 8 nm and about 19 nm. In some embodiments, the sidewalls of each of the first plurality of semiconductor fins and the second plurality of semiconductor fins form a profile angle with a horizontal surface, wherein the profile angle is between about 83° and about 90°. In some embodiments, each of the first recess and the second recess includes a width between about 0 nm and about 30 nm and a depth between about 0 nm and about 50 nm.

[0065] In another exemplary aspect, this disclosure relates to a method. The method includes providing a workpiece including a semiconductor layer over a substrate, the composition of the semiconductor layer being different from that of the substrate; forming a plurality of semiconductor fins from the semiconductor layer and the substrate, the plurality of semiconductor fins including more than three semiconductor fins; after forming the plurality of semiconductor fins, removing an outer semiconductor fin from the plurality of semiconductor fins; after removing the outer semiconductor fin, forming a semiconductor liner over the plurality of semiconductor fins; and forming a gate structure over the plurality of semiconductor fins. The removal forms a recess located directly beneath the outer semiconductor fin.

[0066] In some embodiments, the substrate comprises silicon, the semiconductor layer comprises germanium or silicon-germanium, and the semiconductor liner comprises silicon. In some embodiments, the method may further include forming fin-cutting trenches across a plurality of semiconductor fins prior to forming the semiconductor liner to divide each of the plurality of semiconductor fins into a first portion and a second portion. In some embodiments, removing the outer semiconductor fins comprises using sulfur hexafluoride, difluoromethane, fluoromethane, and oxygen.

[0067] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0068] Example 1 is a method of forming a semiconductor structure, comprising: forming a plurality of semiconductor fins on a substrate, the plurality of semiconductor fins having more than three semiconductor fins; after forming the plurality of semiconductor fins, removing an outer semiconductor fin from the plurality of semiconductor fins; and forming a gate structure on the plurality of semiconductor fins, wherein the removal causes a portion of the substrate directly below the outer semiconductor fin to be recessed.

[0069] Example 2 is the method described in Example 1, wherein the external semiconductor fin is not disposed between two of the plurality of semiconductor fins.

[0070] Example 3 is the method of Example 1, wherein the width of the outer semiconductor fin is greater than the width of any of the remaining semiconductor fins among the plurality of semiconductor fins.

[0071] Example 4 is the method of Example 1, wherein forming the plurality of semiconductor fins includes: depositing a pad oxide layer on the substrate; depositing a pad nitride layer on the pad oxide layer; depositing an oxide layer on the pad nitride layer; forming a first patterned hard mask on the oxide layer; using the first patterned hard mask as an etch mask to etch the pad oxide layer, the pad nitride layer and the oxide layer to form a second patterned hard mask from the oxide layer, the pad nitride layer and the pad oxide layer; and using the second patterned hard mask as an etch mask to etch the substrate.

[0072] Example 5 is the method of Example 1, wherein removing the external semiconductor fins includes: depositing an underlayer over the plurality of semiconductor fins; depositing an intermediate layer over the underlayer; and depositing a photoresist layer over the intermediate layer.

[0073] Example 6 is the method described in Example 5, wherein removing the external semiconductor fin further includes: curing the photoresist layer; etching the photoresist layer directly above the external semiconductor fin; etching the intermediate layer directly above the external semiconductor fin using difluoromethane; etching the bottom layer directly above the external semiconductor fin using oxygen and sulfur dioxide; and etching the external semiconductor fin using a fluorine-containing gas.

[0074] Example 7 is the method of Example 1, further comprising: after removing the external semiconductor fins, forming fin cutting grooves across the plurality of semiconductor fins to divide each of the plurality of semiconductor fins into a first portion and a second portion.

[0075] Example 8 is the method of Example 7, wherein the plurality of semiconductor fins extend longitudinally along a first direction, and wherein the fin cutting grooves extend along a second direction perpendicular to the first direction.

[0076] Example 9 is a method of forming a semiconductor structure, comprising: forming a first plurality of semiconductor fins and a second plurality of semiconductor fins on a substrate, each of the first plurality of semiconductor fins and the second plurality of semiconductor fins comprising more than three semiconductor fins; after forming the first plurality of semiconductor fins and the second plurality of semiconductor fins, removing a first outer semiconductor fin of the first plurality of semiconductor fins and a second outer semiconductor fin of the second plurality of semiconductor fins; and forming a first gate structure fin on the first plurality of semiconductor fins and forming a second gate structure on the second plurality of semiconductor fins, wherein the removal forms a first groove located directly below the first outer semiconductor fin and a second groove located directly below the second outer semiconductor fin.

[0077] Example 10 is the method described in Example 9, wherein the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by an opening.

[0078] Example 11 is the method of Example 10, further comprising: forming isolation features between the first plurality of semiconductor fins, between the second plurality of semiconductor fins, over the first recess, over the second recess, and over the opening before forming the first gate structure and the second gate structure.

[0079] Example 12 is the method of Example 11, further comprising: forming a dielectric fin over the isolation feature in the opening.

[0080] Example 13 is the method of Example 12, wherein, after the first gate structure and the second gate structure are formed, the first gate structure and the second gate structure are spaced apart by the dielectric fin.

[0081] Example 14 is the method of Example 9, wherein, after removing the first external semiconductor fin and the second external semiconductor fin, each of the first plurality of semiconductor fins and the second plurality of semiconductor fins includes a bottom width and a top width, wherein the bottom width is between about 10 nm and about 20 nm, and wherein the top width is between about 8 nm and about 19 nm.

[0082] Example 15 is the method of Example 9, wherein the sidewalls of each of the first plurality of semiconductor fins and the second plurality of semiconductor fins form a profile angle with a horizontal surface, wherein the profile angle is between about 83° and about 90°.

[0083] Example 16 is the method of Example 9, wherein each of the first groove and the second groove includes a width between about 0 nm and about 30 nm and a depth between about 0 nm and about 50 nm.

[0084] Example 17 is a method of forming a semiconductor structure, comprising: providing a workpiece including a semiconductor layer on a substrate, the composition of the semiconductor layer being different from the composition of the substrate; forming a plurality of semiconductor fins from the semiconductor layer and the substrate, the plurality of semiconductor fins including more than three semiconductor fins; after forming the plurality of semiconductor fins, removing an outer semiconductor fin from the plurality of semiconductor fins; after removing the outer semiconductor fin, forming a semiconductor liner on the plurality of semiconductor fins; and forming a gate structure on the plurality of semiconductor fins, wherein the removal forms a recess located directly below the outer semiconductor fin.

[0085] Example 18 is the method of Example 17, wherein the substrate comprises silicon, wherein the semiconductor layer comprises germanium or silicon-germanium, and wherein the semiconductor liner comprises silicon.

[0086] Example 19 is the method of Example 17, further comprising: forming fin-cutting trenches across the plurality of semiconductor fins prior to forming the semiconductor liner to divide each of the plurality of semiconductor fins into a first portion and a second portion.

[0087] Example 20 is the method described in Example 17, wherein removing the external semiconductor fin includes using sulfur hexafluoride, difluoromethane, fluoromethane, and oxygen.

Claims

1. A method for forming a semiconductor structure, comprising: Multiple semiconductor fins are formed on a substrate, wherein the multiple semiconductor fins have more than three semiconductor fins; After forming the plurality of semiconductor fins, the outer semiconductor fins are removed from the plurality of semiconductor fins; as well as A gate structure is formed on the plurality of semiconductor fins. The removal process causes a portion of the substrate directly beneath the outer semiconductor fin to be recessed. The width of the outer semiconductor fin is greater than the width of any of the remaining semiconductor fins among the plurality of semiconductor fins.

2. The method of claim 1, wherein, The external semiconductor fin is not positioned between two of the plurality of semiconductor fins.

3. The method of claim 1, wherein, Forming the plurality of semiconductor fins includes: A pad oxide layer is deposited on the substrate; A liner nitride layer is deposited on the liner oxide layer; An oxide layer is deposited on the nitride liner layer; A first patterned hard mask is formed on the oxide layer; Using the first patterned hard mask as an etching mask, the pad oxide layer, the pad nitride layer, and the oxide layer are etched to form a second patterned hard mask from the oxide layer, the pad nitride layer, and the pad oxide layer; and The substrate is etched using the second patterned hard mask as an etching mask.

4. The method according to claim 1, wherein, Removing the external semiconductor fins includes: A substrate is deposited on the plurality of semiconductor fins; An intermediate layer is deposited on top of the underlying layer; and A photoresist layer is deposited on top of the intermediate layer.

5. The method according to claim 4, wherein, Removing the external semiconductor fins also includes: Curing the photoresist layer; Etch the photoresist layer directly above the outer semiconductor fin; The intermediate layer directly above the outer semiconductor fin is etched using difluoromethane; The underlying layer directly above the external semiconductor fins was etched using oxygen and sulfur dioxide; and The external semiconductor fins are etched using a fluorine-containing gas.

6. The method according to claim 1, further comprising: After the outer semiconductor fins are removed, fin cutting grooves are formed across the plurality of semiconductor fins to divide each of the plurality of semiconductor fins into a first portion and a second portion.

7. The method according to claim 6, in, The plurality of semiconductor fins extend longitudinally along a first direction. The fin cutting groove extends along a second direction perpendicular to the first direction.

8. A method for forming a semiconductor structure, comprising: A first plurality of semiconductor fins and a second plurality of semiconductor fins are formed on a substrate, each of the first plurality of semiconductor fins and the second plurality of semiconductor fins comprising more than three semiconductor fins; After forming the first plurality of semiconductor fins and the second plurality of semiconductor fins, the first outer semiconductor fin in the first plurality of semiconductor fins and the second outer semiconductor fin in the second plurality of semiconductor fins are removed. as well as A first gate structure fin is formed on the first plurality of semiconductor fins, and a second gate structure is formed on the second plurality of semiconductor fins. Specifically, the removal process involves forming a first groove directly below the first external semiconductor fin and a second groove directly below the second external semiconductor fin. Wherein, the width of the first outer semiconductor fin is greater than the width of any of the remaining semiconductor fins of the first plurality of semiconductor fins, and the width of the second outer semiconductor fin is greater than the width of any of the remaining semiconductor fins of the second plurality of semiconductor fins.

9. The method according to claim 8, wherein, The first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by openings.

10. The method of claim 9, further comprising: Before forming the first gate structure and the second gate structure, isolation features are formed between the first plurality of semiconductor fins, between the second plurality of semiconductor fins, on the first groove, on the second groove, and on the opening.

11. The method of claim 10, further comprising: Dielectric fins are formed over the isolation feature in the opening.

12. The method according to claim 11, wherein, After the first gate structure and the second gate structure are formed, the first gate structure and the second gate structure are separated by the dielectric fin.

13. The method according to claim 8, in, After removing the first and second external semiconductor fins, each of the first and second plurality of semiconductor fins includes a bottom width and a top width. The bottom width is between 10 nm and 20 nm. The top width is between 8 nm and 19 nm.

14. The method according to claim 8, in, The sidewalls of each of the first plurality of semiconductor fins and the second plurality of semiconductor fins form a profile angle with the horizontal surface. The contour angle is between 83° and 90°.

15. The method according to claim 8, wherein, Each of the first and second grooves includes a width between 0 nm and 30 nm and a depth between 0 nm and 50 nm.

16. A method for forming a semiconductor structure, comprising: A workpiece is provided, the workpiece comprising a semiconductor layer located on a substrate, the composition of the semiconductor layer being different from the composition of the substrate; A plurality of semiconductor fins are formed from the semiconductor layer and the substrate, the plurality of semiconductor fins including more than three semiconductor fins; After forming the plurality of semiconductor fins, the outer semiconductor fins are removed from the plurality of semiconductor fins; After removing the external semiconductor fins, a semiconductor liner is formed over the plurality of semiconductor fins; as well as A gate structure is formed on the plurality of semiconductor fins. The removal process involves forming a groove located directly below the external semiconductor fin. The width of the outer semiconductor fin is greater than the width of any of the remaining semiconductor fins among the plurality of semiconductor fins.

17. The method according to claim 16, in, The substrate comprises silicon. The semiconductor layer includes germanium or silicon germanium. The semiconductor liner includes silicon.

18. The method of claim 16, further comprising: Prior to forming the semiconductor liner, fin-cutting grooves are formed across the plurality of semiconductor fins to divide each of the plurality of semiconductor fins into a first portion and a second portion.

19. The method of claim 16, wherein, Removing the external semiconductor fins includes using sulfur hexafluoride, difluoromethane, fluoromethane, and oxygen.

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