Method for manufacturing a semiconductor device

Abstract

In a method of fabricating a semiconductor device, a fin structure is formed including a stack of a first semiconductor layer and a second semiconductor layer disposed above a bottom fin structure and a hardmask layer above the stack. A sacrificial cladding layer is formed above exposed hardmask layer and at least sidewalls of the stack. An etching operation is performed to remove lateral portions of the sacrificial cladding layer, leaving the sacrificial cladding layer on the exposed hardmask layer and sidewalls of the stack. A first dielectric layer and a second dielectric layer are formed, the second dielectric layer having a material different from a material of the first dielectric layer. The second dielectric layer is recessed, and a third dielectric layer is formed on the recessed second dielectric layer, the third dielectric layer having a material different from a material of the second dielectric layer. A protective layer is formed above the sacrificial cladding layer during the etching operation.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and particularly to a method for manufacturing a semiconductor device. Background Technology

[0002] As the semiconductor industry progresses to nanometer technology nodes in pursuit of greater device density, higher efficiency, and lower cost, manufacturing and design challenges have led to the development of three-dimensional designs, such as multi-gate field-effect transistors (FETs). FETs include fin FETs (FinFETs) and gate-all-around (GAA) FETs. In a fin FET, the gate electrode is adjacent to three sides of a channel region with a gate dielectric layer disposed therebetween. Because the gate structure surrounds the fins on the three surfaces, the transistor essentially has three gates to control the current flowing through the fins or channel region. Unfortunately, the fourth side (the bottom of the channel) is far from the gate electrode and therefore not controlled by the adjacent gates. In contrast, in fully wound gate field-effect transistors (FFETs), the gate electrode surrounds all sides of the channel region, allowing for more complete depletion of the channel region. This results in a steeper sub-threshold current swing (SS) and a smaller drain-induced barrier lowering (DIBL), thus mitigating the short-channel effect. As transistor dimensions continue to shrink to the next 10-15 nm technology node, further improvements to fully wound gate field-effect transistors are needed. Summary of the Invention

[0003] In some embodiments, a method of manufacturing a semiconductor device is provided, the method comprising forming a fin structure including a stacked layer of a first semiconductor layer and a second semiconductor layer disposed above a bottom fin structure and a hard mask (mask) layer disposed above the stacked layer; forming an isolation insulating layer such that the isolation insulating layer exposes the hard mask layer and the stacked layer; forming a sacrificial cladding layer above the hard mask layer and the stacked layer; performing an etching operation to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on the sidewalls of the hard mask layer and the stacked layer; forming a first dielectric layer above the stacked layer and the sacrificial cladding layer; forming a second dielectric layer above the first dielectric layer, the second dielectric layer being made of a material different from that of the first dielectric layer; recessing the second dielectric layer; and forming a third dielectric layer on the recessed second dielectric layer, the third dielectric layer being made of a material different from that of the second dielectric layer, thereby forming a wall fin structure, wherein a protective layer is formed above the sacrificial cladding layer during the etching operation.

[0004] In some embodiments, a method of manufacturing a semiconductor device is provided, the method comprising forming a plurality of fin structures, each fin structure including a stacked layer of a first semiconductor layer and a second semiconductor layer disposed above a bottom fin structure and a hard mask layer disposed above the stacked layer; forming an isolation insulating layer such that the isolation insulating layer exposes the hard mask layer and the stacked layer; forming a sacrificial cladding layer above the hard mask layer and the stacked layer; performing an etching operation to remove a lateral portion of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on the sidewalls of the hard mask layer and the stacked layer, wherein a protective layer is formed above the sacrificial cladding layer during the etching operation; forming a first dielectric layer, the first dielectric layer not completely filling the space between the fin structures; and forming a second fin structure above the first dielectric layer. A second dielectric layer is formed to completely fill the space between the fin structures, the material of the second dielectric layer being different from that of the first dielectric layer; the second dielectric layer is recessed; a third dielectric layer is formed on the recessed second dielectric layer, the material of the third dielectric layer being different from that of the second dielectric layer, thereby forming a wall fin structure; a hard masking layer is removed; a sacrificial gate structure is formed above the fin structure; a sidewall spacer is formed on the sidewall of the sacrificial gate structure and a portion of the sidewall of the wall fin structure; a source / drain structure is formed above the fin structure adjacent to the sidewall spacer; a fourth dielectric layer is formed above the source / drain structure; the sacrificial gate structure is removed; the sacrificial cladding layer is removed; the first semiconductor layer is removed; and a metal gate structure is formed around the second semiconductor layer.

[0005] In other embodiments, a method of manufacturing a semiconductor device is provided, the method comprising forming a plurality of fin structures, each fin structure having a semiconductor fin, a hard mask layer on the semiconductor fin, and an upper portion of the semiconductor fin protruding from an insulating layer; forming a sacrificial cladding layer over the hard mask layer and the semiconductor fin; partially etching a lateral portion of the sacrificial cladding layer; forming a protective layer over the sacrificial cladding layer; removing the remaining portion of the lateral portion of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on the sidewalls of the hard mask layer and the semiconductor fin; forming a first dielectric layer to partially fill the space between the semiconductor fins; forming a second dielectric layer over the first dielectric layer to completely fill the space, the second dielectric layer being made of a material different from that of the first dielectric layer; recessing the second dielectric layer; and forming a third dielectric layer on the recessed second dielectric layer, the third dielectric layer being made of a material different from that of the second dielectric layer, thereby forming a wall fin structure between the fin structures. Attached Figure Description

[0006] The embodiments of the present invention can be better understood from the following detailed description and accompanying drawings. It should be noted that, according to industry standard practice, the various features shown in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity.

[0007] Figure 1A , 1BTables 2A, 2B, 3, 4, 5, 6, 7A, 7B, 7C, 7D, 7E, 8, and 9 show cross-sectional schematic diagrams of various stages of manufacturing a semiconductor fully wound gate field-effect transistor apparatus according to an embodiment of the present invention.

[0008] Figure 10A , 10B The figures 10C and 10D show cross-sectional schematic diagrams of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0009] Figure 11A , 11B Figures 11C and 11D show cross-sectional schematic diagrams of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0010] Figure 12A , 12B 12C shows a cross-sectional schematic diagram of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0011] Figure 13A , 13B 13C shows a cross-sectional schematic diagram of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0012] Figure 14A , 14B Figures 14C and 14D show cross-sectional schematic diagrams of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0013] Figure 15A , 15B Figures 15C and 15D show cross-sectional schematic diagrams of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0014] Figure 16A , 16B Figures 16C and 16D show cross-sectional schematic diagrams of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0015] Figure 17A , 17B Figures 17C and 17D show cross-sectional schematic diagrams of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0016] Figure 18A , 18BFigures 18C and 18D show cross-sectional schematic diagrams of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0017] Figure 19A , 19B Figure 19C shows a cross-sectional schematic diagram of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0018] Figure 20A , 20B Figure 20C shows a cross-sectional schematic diagram of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0019] Figure 21A , 21B Figures 21C and 21C show a cross-sectional schematic diagram of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0020] Figure 22A , 22B Figures 22C and 22D show cross-sectional schematic diagrams of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0021] Figure 23A , 23B Figures 23C, 23D, and 23E show cross-sectional schematic diagrams of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0022] Figure 24A , 24B Figures 24C and 24D show cross-sectional schematic diagrams of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention.

[0023] Explanation of reference numerals in the attached figures:

[0024] 10: Semiconductor substrate

[0025] 15,66: Hard mask layer

[0026] 15A: First hard mask layer

[0027] 15B: Second hard mask layer

[0028] 18: Lining layer

[0029] 20: First semiconductor layer

[0030] 22,22A: First bottom semiconductor layer

[0031] 22B: Second bottom semiconductor layer

[0032] 23: Bottom fin structure

[0033] 24: Top semiconductor layer

[0034] 25: Second semiconductor layer

[0035] 26: Covering the semiconductor layer

[0036] 29: Fin Structure

[0037] 30: Insulating material layer

[0038] 32: Chemical Oxidation Layer

[0039] 35: Sacrificial Encapsulation Layer

[0040] 36: Protective layer

[0041] 40: First dielectric layer

[0042] 45: Second dielectric layer

[0043] 50: Third dielectric layer

[0044] 62: Sacrificial gate dielectric layer

[0045] 64: Sacrificial gate electrode layer

[0046] 65: Sidewall gap wall

[0047] 69: Source / Drain Space

[0048] 70: Internal spacer wall

[0049] 71A, 71B: Holes

[0050] 82: First epitaxial layer

[0051] 84: Second epitaxial layer

[0052] 86: Third epitaxial layer

[0053] 84N, 84P: Epitaxial layers

[0054] 90: Fifth dielectric layer

[0055] 102: Gate dielectric layer

[0056] 104: Gate electrode layer

[0057] A, B: Width Detailed Implementation

[0058] It is important to understand that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the description of the disclosure. Of course, these are merely examples and are not intended to limit the invention. For example, the dimensions of the components are not limited to the range or values ​​of one embodiment of this disclosure, but may depend on the processing conditions and / or required nature of the components. Furthermore, embodiments in the following description where the first component is formed above or on the second component include those where the first and second components are formed in direct contact, and embodiments may also include those where additional components may be formed between the first and second components, such that the first and second components are not in direct contact. For simplicity and clarity, different components may be drawn at arbitrary different scales.

[0059] Furthermore, to facilitate the description of the relationship between one element or component and another element(s) in the accompanying drawings, spatially related terms such as "below," "under," "lower," "above," "upper," and similar terms may be used. In addition to the orientations shown in the drawings, spatially related terms also cover different orientations of the device during use or operation. The device may also be otherwise positioned (e.g., rotated 90 degrees or located in other orientations), and the descriptions using the spatially related terms will be interpreted accordingly. Furthermore, the term "made of" may mean "comprising" or "consisting of." In embodiments of the invention, unless otherwise stated, "A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean an element from A, an element from B, and an element from C.

[0060] One of the factors determining the device performance of a field-effect transistor (FET) (such as a FinFET and a gate-all-around (GAA) FET) is the shape of its epitaxial source / drain structure. Specifically, when the source / drain regions of a FinFET or GAA are recessed, and an epitaxial source / drain layer is formed within the recess, etching generally defines the shape of the epitaxial source / drain structure. Furthermore, when two adjacent fin structures are close to each other, the epitaxial layers undesirably merge together. In embodiments of the invention, a wall fin structure is used to physically and electrically isolate adjacent source / drain epitaxial layers and to define the shape of the source / drain epitaxial layers. Optimized source / drain shapes can improve the Ion / Ioff current ratio of FinFETs and GAAs and improve device performance.

[0061] In this embodiment of the invention, source / drain represents the source and / or drain. It should be noted that in this embodiment of the invention, the source and drain can be used interchangeably, and the source and drain have substantially the same structure.

[0062] Figures 1-24D illustrate the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention. It should be understood that additional operations may be provided before, during, and after the processes shown in Figures 1-24D, and for other embodiments of the method, some of the operations described below may be substituted or eliminated. The order of these operations / processes may be interchanged.

[0063] like Figure 1A As shown, a first semiconductor layer 20 and a second semiconductor layer 25 are alternately formed over a semiconductor substrate 10. In some embodiments, the semiconductor substrate 10 is a crystalline silicon substrate. In other embodiments, the semiconductor substrate 10 comprises other elemental semiconductors (e.g., germanium), compound semiconductors (including group IV-IV compound semiconductors (e.g., SiC and SiGe), group III-V compound semiconductors (e.g., GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP)) or combinations thereof. In one embodiment, the semiconductor substrate 10 is a silicon layer of a silicon-on-insulator (SOI) substrate.

[0064] The first semiconductor layer 20 and the second semiconductor layer 25 are made of materials with different lattice constants, and may contain one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. In some embodiments, the first semiconductor layer 20 and the second semiconductor layer 25 are made of Si, a Si compound, SiGe, Ge, or a Ge compound. In one embodiment, the first semiconductor layer 20 is Si. 1-x Ge x Where x is equal to or greater than about 0.2 and equal to or less than about 0.6, and the second semiconductor layer 25 is Si 1-y Ge y , where y is less than x and equal to or less than about 0.1. In embodiments of the invention, "M compound" or "M-based compound" means that the majority of the compound is M.

[0065] The thickness of the first semiconductor layer 20 may be equal to or less than the thickness of the second semiconductor layer 25. In some embodiments, the thickness of the first semiconductor layer 20 is in the range of about 4 nm to about 30 nm, and in other embodiments, the thickness of the first semiconductor layer 20 is in the range of about 5 nm to about 20 nm. In some embodiments, the thickness of the second semiconductor layer 25 is in the range of about 4 nm to about 30 nm, and in other embodiments, the thickness of the second semiconductor layer 25 is in the range of about 5 nm to about 20 nm. The thicknesses of the first semiconductor layers 20 may be the same or different from each other, and the thicknesses of the second semiconductor layers 25 may be the same or different from each other. Although Figure 1A The diagram shows three first semiconductor layers 20 and three second semiconductor layers 25, but the number is not limited to three. In some embodiments, the number of first semiconductor layers 20 and second semiconductor layers 25 may be 1, 2 or more than 3.

[0066] Furthermore, in some embodiments, the top semiconductor layer 24 is epitaxially formed over the stacked structure of the first semiconductor layer 20 and the second semiconductor layer 25. In some embodiments, the top semiconductor layer 24 is Si. 1-z Ge z Where z is equal to or greater than about 0.2 and equal to or less than about 0.7. In some embodiments, z = x. The thickness of the top semiconductor layer 24 is greater than each of the first semiconductor layer 20 and the second semiconductor layer 25. In some embodiments, the thickness of the top semiconductor layer 24 is in the range of about 10 nm to about 100 nm, and in other embodiments, the thickness of the top semiconductor layer 24 is in the range of about 20 nm to about 50 nm. Furthermore, in some embodiments, a cap semiconductor layer 26 made of a material different from that of the top semiconductor layer 24 is epitaxially formed on the top semiconductor layer 24. In some embodiments, the cap semiconductor layer 26 is made of Si and has a thickness in the range of about 0.5 nm to about 10 nm. The cap semiconductor layer 26 is used to control the outward diffusion of Ge from the top semiconductor layer 24 and to maintain the surface quality of the top semiconductor layer 24 during subsequent chemical mechanical polishing (CMP).

[0067] Furthermore, a hard mask layer 15 comprising one or more layers of insulating material or amorphous semiconductor material (e.g., amorphous silicon) is formed over the cover semiconductor layer 26. In some embodiments, the hard mask layer 15 comprises a first hard mask layer 15A and a second hard mask layer 15B. In some embodiments, the first hard mask layer 15A is silicon oxide having a thickness ranging from about 1 nm to about 20 nm, and the second hard mask layer 15B is silicon nitride having a thickness ranging from about 10 nm to about 100 nm.

[0068] In formation Figure 1AFollowing the stacked layers shown, fin structures are formed using one or more lithography and etching operations, such as... Figure 2A As shown. The fin structure can be patterned using any suitable method. For example, the fin can be patterned using one or more photolithography processes (including dual or multiple patterning processes). Generally, dual or multiple patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches, for example, patterns with smaller pitches than those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the hard mask layer 15. The stacked semiconductor layers are patterned into the fin structure 29 by using the patterned hard mask layer as an etch mask, as shown. Figure 2A As shown. In some embodiments, the top semiconductor layer 24 and the cover semiconductor layer 26 are part of a hard mask layer and an etch stop layer for subsequent chemical mechanical polishing processes.

[0069] exist Figure 2A In the middle, fin structures 29 extend along the Y direction and are arranged along the X direction. The number of fin structures is not limited to... Figure 2A Two can be displayed, and the number can be as small as one, three, or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structure 29 to improve pattern fidelity during patterning operations. Figure 2A As shown, alternating stacks of the first and second semiconductor layers are disposed on the bottom fin structure 23.

[0070] In some embodiments, the width of the upper portion of the fin structure 29 extending along the Y direction is in the range of about 5 nm to about 40 nm, and in other embodiments, the width of the upper portion of the fin structure 29 extending along the Y direction is in the range of about 10 nm to about 30 nm.

[0071] In some embodiments, a first bottom semiconductor layer 22A is epitaxially formed on the semiconductor substrate 10 prior to the formation of an alternating stack of the first and second semiconductor layers. The first bottom semiconductor layer 22A is made of a material different from that of the semiconductor substrate 10. In some embodiments, when the semiconductor substrate 10 is a silicon substrate, the first bottom semiconductor layer 22A comprises SiGe, wherein the germanium content is from about 10% atomic percentage to about 60% atomic percentage (SiGe). 0.9 Ge 0.1 -Si 0.4 Ge 0.6In some embodiments, the thickness of the first bottom semiconductor layer 22A is in the range of about 4 nm to about 30 nm, and in other embodiments, the thickness of the first bottom semiconductor layer 22A is in the range of about 5 nm to about 25 nm.

[0072] Furthermore, a second bottom semiconductor layer 22B is epitaxially formed over the first bottom semiconductor layer 22A. The second bottom semiconductor layer 22B is made of a material different from that of the first bottom semiconductor layer 22A. In some embodiments, when the first bottom semiconductor layer 22A is made of SiGe, the second bottom semiconductor layer 22B comprises Si or SiGe, wherein the germanium content of the second bottom semiconductor layer 22B is less than that of the first bottom semiconductor layer 22A, and is greater than 0% atomic percentage to about 10% atomic percentage. In some embodiments, the thickness of the second bottom semiconductor layer 22B is in the range of about 40 nm to about 200 nm, and in other embodiments, the thickness of the second bottom semiconductor layer 22B is in the range of about 50 nm to about 150 nm.

[0073] Next, as Figure 1B As shown, a first semiconductor layer 20 and a second semiconductor layer 25 are alternately formed above the second bottom semiconductor layer 22B. Similar to... Figure 2A , forming fin structures 29, such as Figure 2B As shown.

[0074] In formation Figure 2A Following the fin structure 29 shown, one or more padding layers 18 are formed above the fin structure 29, and an insulating material layer 30 containing one or more layers of insulating material is formed above the substrate to completely embed the fin structure 29 with the padding layers 18 in the insulating material layer 30.

[0075] The insulating materials used for the pad layer 18 and the insulating material layer 30 may be the same or different from each other, and may include one or more of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiOC, SiCN, fluorine-doped silicate glass (FSG), or low dielectric constant dielectric materials. In some embodiments, the pad layer 18 is made of silicon oxide or silicon nitride, and the insulating material layer 30 is made of silicon oxide. The insulating material is formed by low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), and / or atomic layer deposition (ALD). After the insulating material layer 30 is formed, an annealing operation may be performed. Next, a planarization operation is performed (e.g., chemical mechanical polishing (CMP) and / or etch-back method) to expose the upper surface of the hard mask layer 15 (second hard mask layer 15B) from the insulating material layer 30, such as... Figure 3 As shown.

[0076] Next, as Figure 4 As shown, the insulating material layer 30 is recessed to form an isolation insulating layer, exposing the upper part of the fin structure 29. In this operation, the isolation insulating layer separates the fin structures 29 from each other, hence the isolation insulating layer is also referred to as shallow trench isolation (STI).

[0077] In some embodiments, the insulating material layer 30 is recessed until the upper portion of the bottom fin structure 23 is exposed. The first semiconductor layer 20 is a sacrificial layer to be subsequently removed, and the second semiconductor layer 25 is to be subsequently formed as a semiconductor line or semiconductor wafer (nanobody or nanostructure) as a channel layer for a fully wrapped gate field-effect transistor. In some embodiments, during or after the recess etching of the insulating material layer 30, the pad layer 18, the hard mask layer 15, and the cap semiconductor layer 26 are removed, thereby exposing the top semiconductor layer 24, such as... Figure 4 As shown. In some embodiments, after forming an insulating layer by recess etching, a wet cleaning operation is performed to form a chemical oxide layer 32 on the sides of the top semiconductor layer 24 and in the exposed portions of the fin structure of the first and second semiconductor layers (see Figure 1). Figure 11D ).

[0078] After the insulating layer is formed, the sacrificial cladding layer 35 is formed above the exposed portion of the fin structure 29, such as... Figure 5As shown. The sacrificial cladding layer 35 comprises one or more insulating or semiconductor materials. In some embodiments, the sacrificial cladding layer 35 comprises an amorphous or polycrystalline semiconductor material (e.g., Si, SiC, SiGe, or Ge). In some embodiments, the sacrificial cladding layer 35 is amorphous SiGe with a Ge concentration ranging from about 20% atomic percentage to about 40% atomic percentage. In some embodiments, the Ge concentration of the sacrificial cladding layer 35 is the same as or similar to the Ge concentration of the first semiconductor layer 20 (within ±5%). In some embodiments, the thickness of the sacrificial cladding layer 35 ranges from about 5 nm to about 50 nm. If the thickness of the sacrificial cladding layer 35 is less than this range, the space for forming the metal gate is too small, and it may be impossible to properly form some layers of the metal gate structure. If the thickness of the sacrificial cladding layer 35 is greater than this range, it may be insufficient to electrically isolate adjacent fin structures. In some embodiments, a thin semiconductor layer is formed over the exposed portion of the fin structure 29 prior to the formation of the sacrificial cladding layer 35. In some embodiments, the thin semiconductor layer is undoped silicon. In some embodiments, the undoped silicon is crystalline silicon. In some embodiments, the thickness of the thin semiconductor layer is in the range of about 2 nm to about 3 nm. In some embodiments, the sacrificial cladding layer 35 is formed compliantly by chemical vapor deposition or atomic layer deposition. In some embodiments, the deposition temperature of the sacrificial cladding layer 35 is less than or similar to the deposition temperature of the first semiconductor layer 20. In some embodiments, the deposition temperature of the sacrificial cladding layer 35 is in the range of about 500 °C to about 650 °C. The source gas comprises a mixture of SiH4, GeH4, and HCl, with H2 or N2 as the carrier gas. The sacrificial cladding layer 35 controls stress in the isolation region.

[0079] Next, as Figure 6 As shown, one or more etch-back operations are performed to remove the horizontal portion of the sacrificial cladding layer 35, thereby exposing the upper surface of the top semiconductor layer 24 and the upper surface of the insulating material layer 30. In some embodiments, a wet cleaning process is performed after the deposition-etch operation to remove residues.

[0080] Figures 7A-7D This shows details of the etch-back operation that removes the horizontal portion of the sacrificial overlay 35.

[0081] In some embodiments, such as Figure 7A As shown, a breakthrough plasma etching was performed using a mixed gas of CF4 and Ar. The breakthrough etching removed the shoulder of the sacrificial cladding layer 35. Next, a primary plasma etching was performed, as shown... Figure 7BAs shown. In some embodiments, a mixture of Cl2 and N2 gas is used. In some embodiments, the bias voltage of the primary plasma etching is greater than the bias voltage of the penetration etching. By using a primary plasma etching bias voltage greater than the penetration etching bias voltage, the horizontal portion of the sacrificial cladding layer 35 is removed more effectively. In some embodiments, the plasma generated by radio frequency is in the range of about 0.5 MHz to 2 MHz. In some embodiments, the primary etching stops when the thickness of the horizontal portion of the sacrificial cladding layer 35 is reduced to about 1 nm to about 2 nm.

[0082] Following the primary etching, an atomic layer processing step is performed to form a protective layer 36 over the sacrificial overlay layer 35, such as... Figure 7C As shown. In some embodiments, the protective layer 36 comprises an oxide (e.g., SiGe oxide) of the sacrificial cladding layer 35. In some embodiments, the surface of the sacrificial cladding layer 35 is directly oxidized with an oxygen-containing gas using an atomic layer process. In some embodiments, the oxygen-containing gas is one or more of SO2, NO2, N2O, CO2, O2, or ozone. In some embodiments, SO2 is used. In some embodiments, one or more carrier gases (e.g., H2, N2, or Ar) are used together with the oxygen-containing gas. In some embodiments, the oxidation of the sacrificial cladding layer 35 is performed using plasma. In some embodiments, the substrate temperature during plasma oxidation is in the range of about 25°C to about 100°C, and in other embodiments, the substrate temperature during plasma oxidation is in the range of about 40°C to about 80°C. In some embodiments, the thickness of the protective layer 36 is in the range of about 1 nm to about 5 nm. When the protective layer 36 is too thin, it cannot protect the sidewalls of the sacrificial cladding layer 35 during subsequent defooting etching operations. Conversely, when the protective layer 36 is too thick, it requires an unnecessarily long oxidation process, which may weaken the characteristics of the sacrificial cladding layer 35 and / or the first / second semiconductor layer. In other embodiments, the protective layer 36 comprises a nitride or oxide oxynitride (e.g., SiGe nitride or SiGe oxide) of the sacrificial cladding layer 35.

[0083] Next, as Figure 7D As shown, lead removal etching is performed to completely remove the horizontal portion of the sacrificial cover layer 35 formed on the insulating material layer 30. In some embodiments, lead removal etching uses a mixture of Cl2 and N2 or a mixture of CF4 and Ar. In some embodiments, lead removal etching includes a high bias mode (bias voltage in the range of about 250 W to about 350 W) and a low bias mode (bias voltage in the range of about 50 W to about 150 W). Since the bottom of the sidewalls of the sacrificial cover layer 35 is not covered by the protective layer 36, the bottom of the sidewalls of the sacrificial cover layer 35 is etched further than the middle portion of the sidewalls of the sacrificial cover layer 35. Therefore, as Figure 7EAs shown, width A is the distance between the outer surfaces of the sidewalls of the sacrificial cladding layer 35, measured at the interface between the uppermost second semiconductor layer 25 and the top semiconductor layer 24, and width B is the distance between the outer surfaces of the sidewalls of the sacrificial cladding layer 35, measured at the interface between the sidewalls of the sacrificial cladding layer 35 and the upper surface of the insulating material layer 30. Width A is similar to width B. In other words, after the etch-back operation, the sidewalls of the sacrificial cladding layer 35 do not have tails or feet (tail shapes). In some embodiments, the BA value in a dense pattern is in the range of about 0 nm to about 0.1 nm, where the space between adjacent fin structures is about 40 nm or less. In other embodiments, the BA value in a dense pattern is in the range of about 0.2 nm to about 0.8 nm. When the space between adjacent fin structures is about 100 nm or more, the BA value in a loose pattern is in the range of about 0.5 nm to about 1.0 nm. When the protective layer 36 is not formed, the BA value in a loose pattern is 5 nm or more. In some embodiments, the protective layer 36 on the sidewalls of the sacrificial overlay 35 is completely removed, for example, by wet etching using diluted hydrofluoric acid, after or during an etch-back operation. In other embodiments, in dense patterns, width A is approximately 0.1 nm to approximately 0.5 nm greater than width B.

[0084] Subsequently, a first dielectric layer 40 is formed above the fin structure, and a second dielectric layer 45 is formed above the first dielectric layer 40, such that the fin structure is completely embedded in the second dielectric layer 45, as follows. Figure 8 As shown. The first dielectric layer 40 comprises one or more layers of insulating material (e.g., silicon oxide, silicon oxynitride, silicon nitride, SiOC, SiCN, or SiOCN), which is formed by low-pressure chemical vapor deposition (LPCVD), plasma-assisted chemical vapor deposition, atomic layer deposition (ALD), or any other suitable film formation method. In some embodiments, SiCN or SiOCN is used as the first dielectric layer 40. In some embodiments, as Figure 8 As shown, a first dielectric layer 40 is compliantly formed over the fin structures, thereby creating spaces between adjacent fin structures. In some embodiments, the thickness of the first dielectric layer 40 is in the range of about 2.5 nm to about 20 nm, and in other embodiments, the thickness of the first dielectric layer 40 is in the range of about 5 nm to about 10 nm.

[0085] The material of the second dielectric layer 45 is different from the material of the first dielectric layer 40. In some embodiments, the second dielectric layer 45 comprises one or more layers of insulating material (e.g., silicon oxide, silicon oxynitride, silicon nitride, SiOC, SiCN, or SiOCN), which is formed by low-pressure chemical vapor deposition (LPCVD), plasma-assisted chemical vapor deposition, atomic layer deposition (ALD), or any other suitable film formation method. In some embodiments, the second dielectric layer 45 is made of silicon nitride or silicon oxide. In some embodiments, the second dielectric layer 45 comprises a first layer and a second layer. The first layer is silicon oxide formed, for example, by a flowable chemical vapor deposition process followed by a thermal annealing process at 400°C to 800°C in an inert gas environment. The second layer may also be a second layer formed by a plasma-assisted chemical vapor deposition process. In some embodiments, the thickness of the second dielectric layer 45 is in the range of about 60 nm to about 500 nm. Figure 8 As shown, in some embodiments, the second dielectric layer 45 completely fills the space between adjacent fin structures. In other embodiments, a gap is formed at the bottom of the space. In some embodiments, one or more additional dielectric layers are formed between the first dielectric layer 40 and the second dielectric layer 45.

[0086] After the second dielectric layer 45 is formed, a planarization process (e.g., etch-back or chemical mechanical polishing (CMP)) is performed to planarize the second dielectric layer 45 and expose the upper surface of the top semiconductor layer 24. In some embodiments, the top semiconductor layer 24 is lightly etched from about 5 nm to about 10 nm. Furthermore, one or more additional etch-back operations are performed to recess the second dielectric layer 45, such as... Figure 9 As shown, the second dielectric layer 45 is recessed to approximately the same height (±5 nm) as the interface between the top semiconductor layer 24 and the uppermost second semiconductor layer 25. In some embodiments, the first dielectric layer 40 is then further trimmed (etched) to expose a portion of the sacrificial cladding layer 35.

[0087] Next, as Figure 10A-10D As shown, the third dielectric layer 50 is formed on the recessed second dielectric layer 45. Figure 10A This is a schematic cross-sectional view along the X direction. Figure 10B For along the corresponding Figure 10A A schematic cross-sectional view of line Y1-Y1 along the Y direction. Figure 10C For along the corresponding Figure 10A A schematic cross-sectional view of line Y2-Y2 in the Y direction, and Figure 10D This is an isometric view.

[0088] The material of the third dielectric layer 50 is different from the materials of the first dielectric layer 40 and the second dielectric layer 45. In some embodiments, the third dielectric layer 50 comprises a material having a lower etch rate for polysilicon or amorphous SiGe etching than the second dielectric layer 45. In some embodiments, the third dielectric layer 50 comprises a high-k dielectric material. In some embodiments, the third dielectric layer 50 comprises a material having a larger dielectric constant (k) than the second dielectric layer 45 and / or the first dielectric layer 40.

[0089] In some embodiments, the third dielectric layer 50 comprises one or more layers of undoped hafnium oxide (e.g., HfO x , 0 < x ≤ 2), hafnium oxide doped with one or more other elements (e.g., HfSiO, HfSiON, HfTaO, HfTiO, or HfZrO), zirconia, alumina, titanium oxide, and hafnium oxide-alumina (HfO2-Al2O3) alloy. In certain embodiments, hafnium oxide (HfO x ) is used as the third dielectric layer 50. The third dielectric layer 50 can be formed by low-pressure chemical vapor deposition (LPCVD), plasma-assisted chemical vapor deposition, or atomic layer deposition (ALD), or any other suitable film-forming method. As Figure 10A shown, the third dielectric layer 50 completely fills the space between adjacent fin structures. After forming the third dielectric layer 50 to completely cover the fin structures, a planarization operation (e.g., a back-etch process or a chemical mechanical polishing process) is performed to planarize the upper surface of the third dielectric layer 50 to expose the upper surface of the top semiconductor layer 24, as Figure 10A-10D shown. In some embodiments, depending on the device and / or process requirements, the thickness of the third dielectric layer 50 remaining on the top semiconductor layer 24 ranges from about 5 nm to about 100 nm, and the width of the third dielectric layer 50 remaining on the top semiconductor layer 24 ranges from about 10 nm to about 80 nm. Thus, a wall fin structure is formed by the first dielectric layer 40, the second dielectric layer 45, and the third dielectric layer 50 between adjacent fin structures. In some embodiments, after forming the wall fin structure, an annealing process is performed at a temperature of about 800 °C to about 1000 °C, and the time of the annealing process is about 10 seconds to about 60 seconds.

[0090] Next, as Figure 11A-11D shown, the top semiconductor layer 24 is removed by one or more dry etching operations or wet etching operations. In Figure 11A-11C to Figures 23A-23C , the drawing "B" is a schematic cross-sectional view in the Y direction along the line Y1-Y1 corresponding to the drawing "A", and the drawing "C" is a schematic cross-sectional view in the Y direction along the line Y2-Y2 corresponding to the drawing "A". Figure 11D is a top view (plan view). As Figure 11AAs shown, a groove with sidewalls formed by the sacrificial overlay layer 35 is formed. After removing the top semiconductor layer 24, a sacrificial gate dielectric layer 62 is formed on the uppermost second semiconductor layer 25, the sidewalls of the first dielectric layer 40, and the third dielectric layer 50, as shown in Figures 11A-11C. The sacrificial gate dielectric layer 62 comprises one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide is formed using chemical vapor deposition. The thickness of the sacrificial gate dielectric layer 62 is in the range of about 1 nm to about 5 nm.

[0091] Furthermore, such as Figures 12A-12C As shown, a sacrificial (dummy) gate electrode layer 64 is formed, and a hard mask layer 66 is formed on the sacrificial gate electrode layer 64. The sacrificial gate electrode layer 64 is deposited in a blanket manner on the sacrificial gate dielectric layer 62 and over the third dielectric layer 50, such that the third dielectric layer 50 is completely buried in the sacrificial gate electrode layer 64. The sacrificial gate electrode layer 64 comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer 64 is in the range of about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer 64 is planarized. The sacrificial gate dielectric layer 62 and the sacrificial gate electrode layer 64 are deposited using chemical vapor deposition (including low-pressure chemical vapor deposition and plasma-assisted chemical vapor deposition), physical vapor deposition (PVD), atomic layer deposition, or other suitable processes. Subsequently, a hard mask layer 66 is formed over the sacrificial gate electrode layer 64. The hard mask layer 66 comprises one or more layers of silicon nitride or silicon oxide.

[0092] Next, the hard mask layer 66 and the sacrificial gate electrode layer 64 are patterned to form the sacrificial gate electrode, such as... Figures 13A-13C As shown. In some embodiments, the width of the sacrificial gate electrode layer 64 is in the range of about 5 nm to about 30 nm, and in other embodiments, the width of the sacrificial gate electrode layer 64 is in the range of about 10 nm to about 20 nm. In some embodiments, two or more sacrificial gate electrodes are arranged along the Y direction. In some embodiments, one or more dummy sacrificial gate electrodes are formed on both sides of the sacrificial gate electrode to improve pattern fidelity.

[0093] Furthermore, the sidewall spacer 65 is formed above the sacrificial gate electrode layer 64, such as Figures 14A-14CAs shown. One or more insulating layers are deposited in a compliant manner to have substantially equal thicknesses on the vertical surface (e.g., sidewalls), horizontal surface, and top and sidewalls of the first dielectric layer 40 of the sacrificial gate electrode, respectively. Then, a sidewall spacer 65 is formed by using anisotropic etching. In some embodiments, the sidewall spacer 65 has a thickness ranging from about 3 nm to about 20 nm. The sidewall spacer 65 comprises one or more of silicon nitride, SiON, SiCN, SiOC, SiOCN, or any other suitable dielectric material. In some embodiments, because the height of the third dielectric layer 50 is much smaller than the height of the sacrificial gate electrode layer 64 with a hard mask layer, the thickness of the sidewall spacer 65 on the sidewalls of the first dielectric layer 40 (on the third dielectric layer 50) is less than the thickness of the sidewall spacer 65 on the sacrificial gate electrode layer 64, or no sidewall spacer is formed on the sidewalls of the first dielectric layer 40 (on the third dielectric layer 50), as shown. Figure 14D As shown.

[0094] Next, by using one or more etching operations, the stacked structure of the first semiconductor layer 20 and the second semiconductor layer 25 is etched downwards into the source / drain region, thereby forming the source / drain space 69, as shown below. Figures 15A-15D As shown. Figure 15D This is a top (planar) view, where some layers / components are omitted for simplicity. In some embodiments, the bottom fin structure 23 is also partially etched. In some embodiments, the sacrificial cladding layer 35 is partially or completely removed during etching. In some embodiments, the sacrificial cladding layer 35 is also removed during etching to form the source / drain space 69 when no or very thin sidewall spacers are formed on the sidewalls of the first dielectric layer 40 on the third dielectric layer 50.

[0095] Furthermore, it forms internal spacer walls, such as Figure 16A-16D and Figures 17A-17C As shown, the first semiconductor layer 20 is laterally etched in the Y direction within the source / drain space 69 to form a hole 71A, as shown. Figure 16B As shown. In some embodiments, the lateral etching amount of the first semiconductor layer 20 is in the range of about 0.5 nm to about 10 nm, and in other embodiments, the lateral etching amount of the first semiconductor layer 20 is in the range of about 1 nm to about 5 nm.

[0096] When the first semiconductor layer 20 is SiGe and the second semiconductor layer 25 is Si, the first semiconductor layer 20 can be selectively etched by isotropic etching (e.g., wet etching). In some embodiments, the wet etchant comprises a mixed solution of H2O2, CH3COOH, and HF, followed by cleaning with H2O. In some embodiments, the etching with the mixed solution and the water cleaning are repeated 10 to 20 times. In some embodiments, the etching time using the mixed solution is from about 1 minute to about 2 minutes. In some embodiments, the temperature using the mixed solution is from about 60°C to about 90°C. Figure 16D As shown, the source / drain space 69 is extended to have a hole 71B along the Y direction.

[0097] Next, a fourth dielectric layer is compliantly formed on the etched lateral ends of the first semiconductor layer 20 in the source / drain space 69 and on the end surfaces of the second semiconductor layer 25. The fourth dielectric layer comprises one or more of silicon nitride, silicon oxide, SiON, SiCN, SiOC, SiOCN, or any other suitable dielectric material. In some embodiments, the fourth dielectric layer is made of a material different from the sidewall spacer 65. The fourth dielectric layer can be formed by atomic layer deposition or any other suitable method.

[0098] After the fourth dielectric layer is formed, an etching operation is performed to partially remove the fourth dielectric layer, thereby forming the internal spacer wall 70, as shown below. Figure 17B As shown. In some embodiments, the end surface of the internal spacer wall 70 is more recessed than the end surface of the second semiconductor layer 25. In some embodiments, the amount of recess is in the range of about 0.2 nm to about 3 nm, and in other embodiments, the amount of recess is in the range of about 0.5 nm to about 2 nm. In other embodiments, the amount of recess is less than 0.5 nm and may be equal to 0 (i.e., the end surface of the internal spacer wall 70 is flush with the end surface of the second semiconductor layer 25). In some embodiments, an additional dielectric layer having a smaller thickness than the fourth dielectric layer is formed before the fourth dielectric layer is formed, so the internal spacer wall 70 has a two-layer structure.

[0099] like Figure 17D As shown, a fourth dielectric layer 70A, made of the same material as the internal spacer wall 70, is also formed on the remaining sacrificial cladding layer 35. In some embodiments, the fourth dielectric layer 70A contacts the third dielectric layer 50 and separates the adjacent sacrificial cladding layer 35. Furthermore, the bottom of the sacrificial cladding layer 35 is sufficiently removed by the aforementioned lead removal etching, and the surface of the sacrificial cladding layer 35 is not exposed to the source / drain space 69.

[0100] After that, as Figures 18A-18D As shown, the source / drain epitaxial layer is formed in the source / drain space 69. Figure 18DTo omit some components / elements, a top view (plan view) is provided. The source / drain epitaxial layer comprises one or more layers of SiP, SiAs, SiCP, SiPAs, and / or SiC for an n-type field-effect transistor and SiGe, GeSn, and / or SiGeSn for a p-type field-effect transistor. In some embodiments, the semiconductor device comprises a p-type field-effect transistor and an n-type field-effect transistor having source / drain epitaxial layers that are different from each other. In some embodiments, the n-type field-effect transistor comprises an epitaxial layer 84N, which comprises SiP, SiAs, SiCP, SiPAs, and / or SiC, and the p-type field-effect transistor comprises an epitaxial layer 84P, which comprises SiGe, GeSn, and / or SiGeSn. In some embodiments, for the p-type field-effect transistor, the source / drain epitaxial layer is boron (B) doped. In some embodiments, the source / drain epitaxial layer comprises multiple layers. In some embodiments, the source / drain epitaxial layer is not in contact with... Figure 18D The fourth dielectric layer 70A shown has a gap, and in other embodiments, the source / drain epitaxial layer contacts the fourth dielectric layer 70A with a small gap. In some embodiments, no gap is formed between the source / drain epitaxial layer and the fourth dielectric layer 70A.

[0101] In some embodiments, the source / drain epitaxial layer of the n-type field-effect transistor includes a first epitaxial layer 82, a second epitaxial layer 84, and a third epitaxial layer 86. In some embodiments, the first epitaxial layer 82 is made of SiP, SiAs, or SiAs:P, or a combination thereof. In some embodiments, the P concentration of the first epitaxial layer 82 is approximately 0.5 × 10⁻⁶. 19 atoms / cm 3 Approximately 5×10 20 atoms / cm 3 Within the range, and in other embodiments, the P concentration of the first epitaxial layer 82 is approximately 0.8 × 10⁻⁶. 19 atoms / cm 3 Approximately 2×10 20 atoms / cm 3 Within the range of [specific parameters]. In some embodiments, the second epitaxial layer 84 is made of SiP. In some embodiments, the P concentration of the second epitaxial layer 84 is greater than the P concentration of the first epitaxial layer 82, and the P concentration of the second epitaxial layer 84 is within the range of approximately 1 × 10⁻⁶. 21 atoms / cm 3 Approximately 5×10 21 atoms / cm 3 Within the range. In other embodiments, the P concentration of the second epitaxial layer 84 is approximately 12 × 10⁻⁶. 21 atoms / cm 3 Approximately 4×10 21 atoms / cm 3Within the range of [specific parameters]. In some embodiments, the third epitaxial layer 86 is made of SiGeP. In some embodiments, the P concentration of the third epitaxial layer 86 is equal to or less than the P concentration of the second epitaxial layer 84, and greater than the P concentration of the first epitaxial layer 82, and the P concentration of the third epitaxial layer 86 is approximately 0.5 × 10⁻⁶. 21 atoms / cm 3 Approximately 4×10 21 atoms / cm 3 Within the range. In other embodiments, the P concentration of the third epitaxial layer 86 is approximately 1 × 10⁻⁶. 21 atoms / cm 3 Approximately 3×10 21 atoms / cm 3 In some embodiments, the Ge concentration of the third epitaxial layer 86 is in the range of about 0.5% atomic percentage to about 10% atomic percentage, and in other embodiments, the Ge concentration of the third epitaxial layer 86 is in the range of about 1% atomic percentage to about 5% atomic percentage.

[0102] In some embodiments, the source / drain epitaxial layer of the p-type field-effect transistor comprises a first epitaxial layer 82, a second epitaxial layer 84, and a third epitaxial layer 86. The first epitaxial layer 82 is made of boron-doped SiGe. In some embodiments, the Ge content of the first epitaxial layer 82 is in the range of about 15% atomic percentage to about 30% atomic percentage. In some embodiments, the boron concentration of the first epitaxial layer 82 is about 1 × 10⁻⁶. 19 atoms / cm 3 To approximately 1×10 21 atoms / cm 3 Within the range. In other embodiments, the B concentration of the first epitaxial layer 82 is approximately 5 × 10⁻⁶. 19 atoms / cm 3 Approximately 5×10 20 atoms / cm 3 In some embodiments, the second epitaxial layer 84 is made of boron-doped SiGe. In some embodiments, the Ge content of the second epitaxial layer 84 is in the range of about 20% atomic percentage to about 35% atomic percentage. In some embodiments, the boron concentration of the second epitaxial layer 84 is equal to or greater than the boron concentration of the first epitaxial layer 82, and the boron concentration of the second epitaxial layer 84 is in the range of about 0.5 × 10⁻⁶. 20 atoms / cm 3 To approximately 1×10 21 atoms / cm 3 Within the range. In other embodiments, the B concentration of the second epitaxial layer 84 is approximately 1 × 10⁻⁶. 20 atoms / cm 3 Approximately 5×1020 atoms / cm 3 In some embodiments, the third epitaxial layer 86 is made of B-doped SiGe. In some embodiments, the Ge content of the third epitaxial layer 86 is in the range of about 25% atomic percentage to about 60% atomic percentage. In some embodiments, the average Ge content of the third epitaxial layer 86 is greater than the Ge content of the second epitaxial layer 84. In some embodiments, the B concentration of the third epitaxial layer 86 is about 5 × 10⁻⁶. 19 atoms / cm 3 Approximately 5×10 21 atoms / cm 3 Within the range. In other embodiments, the B concentration of the third epitaxial layer 86 is approximately 1 × 10⁻⁶. 20 atoms / cm 3 Approximately 3×10 21 atoms / cm 3 Within this range. The source / drain epitaxial layers are formed using epitaxial growth methods such as chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy (MBE).

[0103] like Figure 18A and Figure 18D As shown, the wall structure that separates adjacent epitaxial layers along the X direction includes a second dielectric layer 45, a third dielectric layer, a first dielectric layer 40, and a fourth dielectric layer 70A (internal spacer wall) as sidewalls.

[0104] After the source / drain epitaxial layers are formed, the fifth dielectric layer 90 is formed on top of the source / drain epitaxial layers, such as... Figures 19A-19C As shown. The fifth dielectric layer 90 comprises one or more of silicon nitride, silicon oxide, SiON, SiOC, SiCN, SiOCN, or any other suitable dielectric material. Next, a planarization operation (e.g., chemical mechanical polishing) is performed to expose the upper surface of the sacrificial gate electrode layer 64, as shown. Figure 19B and Figure 19C As shown.

[0105] Next, the sacrificial gate electrode layer 64 and the sacrificial gate dielectric layer 62 are removed, as follows: Figures 20A-20C As shown. The fifth dielectric layer 90 protects the source / drain epitaxial layers during the removal of the sacrificial gate structure. The sacrificial gate structure can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 64 is polysilicon, a wet etchant (e.g., a tetramethyl ammonium hydroxide (TMAH) solution) can be used to selectively remove the sacrificial gate electrode layer 64. Subsequently, the sacrificial gate dielectric layer 62 is removed using plasma dry etching and / or wet etching.

[0106] After the sacrificial gate structure is removed, the sacrificial cladding layer 35 is removed by one or more dry and / or wet etching operations, such as Figures 21A-21C As shown.

[0107] Next, the first semiconductor layer 20 is removed, thereby forming the wires, sheets, or semiconductor nanobody (channel region) of the second semiconductor layer 25, such as... Figures 22A-22D As shown. Figure 22D This is a top view (plan view). The first semiconductor layer 20 can be removed or etched using an etchant that can selectively etch the first semiconductor layer 20 relative to the second semiconductor layer 25. For example... Figure 22B As shown, due to the formation of the internal spacer wall 70, the etching of the first semiconductor layer 20 stops at the internal spacer wall 70. In some embodiments, such as Figure 22D As shown, the sacrificial cover layer 35 is completely removed.

[0108] In some embodiments, the semiconductor device includes a p-type field-effect transistor and an n-type field-effect transistor having source / drain epitaxial layers that are different from each other. In some embodiments, the n-type field-effect transistor includes an epitaxial layer 84N, which includes SiP, SiAs, SiCP, SiPAs, and / or SiC, and the p-type field-effect transistor includes an epitaxial layer 84P, which includes SiGe, GeSn, and / or SiGeSn. As described above, the first semiconductor layer 20 and the sacrificial cladding layer 35 can be formed using SiGe. In this case, if any portion of the sacrificial cladding layer 35 made of SiGe is exposed to the source / drain space, when the first semiconductor layer 20 and the sacrificial cladding layer 35 are removed, part or all of the epitaxial layer 84P may be removed. However, as described above, since no portion of the sacrificial cladding layer 35 made of SiGe is exposed to the source / drain space, such epitaxial layer loss can be avoided.

[0109] After releasing the semiconductor lines or wafers (channel regions) of the second semiconductor layer 25, a gate dielectric layer 102 is formed around each channel region, and a gate electrode layer 104 is formed on the gate dielectric layer 102, as shown in Figures 23A-23D. Figure 23D This is a top (planar) view with some components / layers omitted or transparent. In some embodiments, the structure and / or material of the gate electrode of an n-type fully wound gate field-effect transistor differs from the structure and / or material of the gate electrode of a p-type fully wound gate field-effect transistor. Figure 23E This shows the structure when no sidewall spacers are formed on the first dielectric layer 40, wherein the first dielectric layer 40 is on the third dielectric layer 50.

[0110] In some embodiments, the gate dielectric layer 102 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-dielectric-constant dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-dielectric-constant dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-dielectric-constant dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 102 comprises an interface layer (not shown) formed between the channel layer and the dielectric material. The gate dielectric layer 102 may be formed by chemical vapor deposition, atomic layer deposition, or any suitable method. In one embodiment, the gate dielectric layer 102 may be formed using a highly compliant deposition process (e.g., atomic layer deposition) to ensure that the gate dielectric layer 102 has a uniform thickness around each channel layer. In one embodiment, the thickness of the gate dielectric layer 102 is in the range of about 1 nm to about 6 nm.

[0111] A gate electrode layer 104 is formed on the gate dielectric layer 102 to surround each channel layer. The gate electrode layer 104 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0112] The gate electrode layer 104 may be formed by chemical vapor deposition, atomic layer deposition, electroplating, or other suitable methods. Next, the gate dielectric layer 102 and the gate electrode layer 104 are planarized using, for example, chemical mechanical polishing, until the top surfaces of the fifth dielectric layer 90 and the third dielectric layer 50 are exposed. In some embodiments, after the planarization operation, the gate electrode layer 104 is recessed, and a cap insulating layer (not shown) is formed over the recessed gate electrode layer 104. The cap insulating layer comprises one or more layers of a silicon nitride-based material, such as silicon nitride. The cap insulating layer may be formed by depositing an insulating material followed by a planarization operation.

[0113] In some embodiments of the present invention, one or more work function adjustment layers (not shown) are disposed between the gate dielectric layer 102 and the gate electrode layer 104. The work function adjustment layers are made of conductive materials, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or multiple layers of two or more of these materials. For n-type field-effect transistors, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer. For p-type field-effect transistors, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer. The work function adjustment layers can be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. Furthermore, the work function adjustment layers can be individually formed using different metal layers for n-type and p-type channel field-effect transistors.

[0114] Figures 24A-24D Various views are shown of one of the stages of manufacturing a semiconductor fully wound gate field-effect transistor device according to an embodiment of the present invention. Figures 24A-24D Corresponding to Figures 23A-23C and Figure 23E Except for the first bottom semiconductor layer 22 formed in Figures 24A-24D middle.

[0115] It should be understood that field-effect transistors are further processed using complementary metal oxide semiconductor (CMOS) technology to form various components, such as contacts / vias, interconnect metal layers, dielectric layers, protective layers, etc.

[0116] As described above, the sacrificial cladding layer 35 (e.g., amorphous SiGe) surrounds the semiconductor nanowire or sheet and is replaced by a work function metal. In some embodiments, when the sacrificial cladding layer 35 is removed, residue (SiGe residue) remains. To avoid SiGe residue, the SiGe-cladding profile is fabricated as vertically as possible due to the U-shaped overall etching profile. In some embodiments, when etching the sacrificial cladding layer 35, a bottom-through process for the SiGe cladding layer is used to address the faceting issues of the crystalline SiGe cladding method. However, after the SiGe through-process, the base profile of the amorphous SiGe cladding layer may result in overall etching leaving SiGe residue, which can lead to epitaxial damage during final wafer formation.

[0117] In some embodiments, the process of this invention forms a protective layer 36 using atomic layer processing to have a vertical profile at the bottom of the SiGe coating, and a necking feature (a side effect of good iso-dense loading) and a smaller upper shoulder loss than the facets near the coated SiGe. These methods avoid epitaxial damage during wafer formation (epitaxylenic layer formation) and improve the iso-dense loading effect.

[0118] It should be understood that this document does not need to discuss all the advantages, nor does it require that all embodiments or examples have specific advantages, and other embodiments or examples may provide different advantages.

[0119] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, wherein a fin structure is formed. The fin structure includes a stacked layer of a first semiconductor layer and a second semiconductor layer disposed above a bottom fin structure, and a hard mask layer disposed above the stacked layer. An isolation insulating layer is formed such that the isolation insulating layer exposes the hard mask layer and the stacked layer. A sacrificial cladding layer is formed over at least the sidewalls of the hard mask layer and the stacked layer. An etching operation is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on the exposed sidewalls of the hard mask layer and the stacked layer. A first dielectric layer is formed, and a second dielectric layer is formed over the first dielectric layer, the material of the second dielectric layer being different from the material of the first dielectric layer. The second dielectric layer is recessed, and a third dielectric layer is formed on the recessed second dielectric layer, the material of the third dielectric layer being different from the material of the second dielectric layer, thereby forming a wall fin structure. During the etching operation, a protective layer is formed over the sacrificial cladding layer. In one or more of the above or following embodiments, the protective layer is an oxide of the material of the sacrificial cladding layer. In one or more of the above or following embodiments, the oxide is formed by treating the surface of the sacrificial cladding layer with one or more of SO2 or O2. In one or more of the above or following embodiments, the treatment includes plasma treatment. In one or more of the above or following embodiments, the protective layer is formed after some portions of the sacrificial cladding layer are removed. In one or more of the above or following embodiments, the protective layer is formed before the lateral portions of the sacrificial cladding layer disposed on the insulating layer are completely removed. In one or more of the above or following embodiments, the first semiconductor layer is made of SiGe, the second semiconductor layer is made of Si, and the sacrificial cladding layer is made of SiGe. In one or more of the above or following embodiments, the sacrificial cladding layer is amorphous or polycrystalline. In one or more of the above or following embodiments, the hard mask layer is made of SiGe. In one or more of the above or following embodiments, the first dielectric layer comprises at least one of SiOC, SiCN, or SiOCN, the second dielectric layer comprises at least one of silicon nitride, silicon oxide, or SiON, and the third dielectric layer comprises at least one of hafnium oxide, zirconium oxide, aluminum oxide, or titanium oxide.

[0120] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, wherein fin structures are formed. Each fin structure includes a stacked layer of a first semiconductor layer and a second semiconductor layer disposed above a bottom fin structure, and a hard mask layer disposed above the stacked layer. An isolation insulating layer is formed such that the isolation insulating layer exposes the hard mask layer and the stacked layer. A sacrificial cladding layer is formed over at least the sidewalls of the exposed hard mask layer and the stacked layer. An etching operation is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on the sidewalls of the exposed hard mask layer and the stacked layer. During the etching operation, a protective layer is formed over the sacrificial cladding layer. A first dielectric layer is formed such that the first dielectric layer does not completely fill the space between the fin structures. A second dielectric layer is formed over the first dielectric layer to completely fill the space between the fin structures, the material of the second dielectric layer being different from the material of the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer, the material of the third dielectric layer being different from the material of the second dielectric layer, thereby forming a wall fin structure. The hard mask layer is removed. A sacrificial gate structure is formed. Sidewall spacers are formed on the sidewalls of the sacrificial gate structure and a portion of the sidewalls of the wall fin structure. A source / drain structure is formed. A fourth dielectric layer is formed. The sacrificial gate structure is removed. The sacrificial cladding layer is removed. The first semiconductor layer is removed. A metal gate structure is formed around the second semiconductor layer. In one or more of the above or following embodiments, the etching operation includes: a through-etch operation; a main etching operation following the through-etch operation; an atomic layer treatment for forming a protective layer following the main etching operation; and a lead removal etching operation following the atomic layer treatment. In one or more of the above or following embodiments, the atomic layer treatment includes plasma treatment using oxygen-containing gas. In one or more of the above or following embodiments, the atomic layer treatment is performed at a temperature ranging from 25°C to 100°C. In one or more of the above or following embodiments, the main etching operation is stopped before the lateral portion of the sacrificial cladding layer disposed on the isolation insulating layer is completely removed, and the lead removal etching operation completely removes the lateral portion of the sacrificial cladding layer disposed on the isolation insulating layer. In one or more of the above or below embodiments, after the lead removal etching operation, the difference between a first width, measured at the interface between the hard mask layer and the stacked layer on the outer surfaces of the sacrificial cladding layer on the sidewalls of the hard mask layer and the stacked layer, and a second width, measured at the interface between the hard mask layer and the isolation insulating layer, on the outer surfaces of the sacrificial cladding layer on the sidewalls of the hard mask layer and the stacked layer, is in the range of 0.5 nm to 1.0 nm, wherein the second width is greater than the first width. In one or more of the above or below embodiments, the sacrificial cladding layer is made of amorphous SiGe, and the step of forming the sacrificial cladding layer includes compliantly forming a layer for the sacrificial cladding layer above the hard mask layer and the stacked layer and on the isolation insulating layer; and removing a portion of this layer on top of the hard mask layer and on the isolation insulating layer.In one or more of the above or below embodiments, the step of forming the source / drain structure includes recessing the source / drain region of the fin structure; laterally recessing the end of the first semiconductor layer; forming an insulating internal spacer wall on the recessed end of the first semiconductor layer; and forming one or more semiconductor epitaxial layers. During the recessing process, at least a portion of the sacrificial cladding layer is removed.

[0121] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, wherein fin structures are formed. Each fin structure has a semiconductor fin, a hard mask layer located on the semiconductor fin, and an upper portion of the semiconductor fin protruding from an insulating layer. A sacrificial cladding layer is formed over at least the sidewalls of the hard mask layer and over the upper portion of each semiconductor fin. A lateral portion of the sacrificial cladding layer is partially etched. A protective layer is formed over the sacrificial cladding layer. The remaining portion of the lateral portion of the sacrificial cladding layer is removed, thereby leaving the sacrificial cladding layer on the sidewalls of the hard mask layer and the semiconductor fin. A first dielectric layer is formed to partially fill the space between the semiconductor fins. A second dielectric layer is formed over the first dielectric layer to completely fill the space, the material of the second dielectric layer being different from the material of the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer, the material of the third dielectric layer being different from the material of the second dielectric layer, thereby forming a wall fin structure between the fin structures. In one or more of the above or following embodiments, the sacrificial cladding layer is made of amorphous or polycrystalline SiGe, and the protective layer is an oxide of SiGe. In one or more of the above or below embodiments, the thickness of the protective layer is in the range of 1 nm to 5 nm.

[0122] The foregoing outlines the features of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various perspectives. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive concept and scope of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive concept and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: A fin structure is formed, the fin structure comprising a stacked layer of a first semiconductor layer and a second semiconductor layer disposed above a bottom fin structure, and a hard masking layer located above the stacked layer; An insulating layer is formed, which exposes the hard mask layer and the stacked layers. A sacrificial overlay is formed over the hard mask layer and the stacked layer; An etching operation is performed to remove a lateral portion of the sacrificial cover layer, thereby leaving the sacrificial cover layer on the sidewalls of the hard mask layer and the stacked layer; A first dielectric layer is formed above the stacked layer and the sacrificial cover layer; A second dielectric layer is formed above the first dielectric layer, and the material of the second dielectric layer is different from that of the first dielectric layer; The second dielectric layer is recessed; and A third dielectric layer is formed on the recessed second dielectric layer. The material of the third dielectric layer is different from that of the second dielectric layer, thereby forming a wall fin structure. During the etching operation, a protective layer is formed above the sacrificial cover layer. The protective layer is an oxide of the material of the sacrificial cover layer.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the oxide is formed by treating the surface of the sacrificial coating with one or more of SO2 or O2.

3. The method of manufacturing a semiconductor device as claimed in claim 2, wherein the process includes a plasma treatment.

4. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the protective layer is formed after a portion of the sacrificial cladding layer is removed.

5. The method of manufacturing a semiconductor device as claimed in claim 4, wherein the protective layer is formed before the lateral portion of the sacrificial cladding layer disposed on the insulating layer is completely removed.

6. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the first semiconductor layer is made of SiGe, the second semiconductor layer is made of Si, and the sacrificial cladding layer is made of SiGe.

7. The method of manufacturing a semiconductor device as claimed in claim 6, wherein the sacrificial cladding layer is amorphous or polycrystalline.

8. The method of manufacturing a semiconductor device as claimed in claim 6, wherein the hard mask layer is made of SiGe.

9. A method for manufacturing a semiconductor device, comprising: Multiple fin structures are formed, each of which includes a stacked layer of a first semiconductor layer and a second semiconductor layer disposed above a bottom fin structure, and a hard masking layer located above the stacked layer; An insulating layer is formed, which exposes the hard mask layer and the stacked layers. A sacrificial overlay is formed over the hard mask layer and the stacked layer; An etching operation is performed to remove a lateral portion of the sacrificial cover layer, thereby leaving the sacrificial cover layer on the sidewalls of the hard mask layer and the stacked layer, wherein a protective layer is formed over the sacrificial cover layer during the etching operation; A first dielectric layer is formed, which does not completely fill a space between the plurality of fin structures; A second dielectric layer is formed above the first dielectric layer to completely fill the space between the plurality of fin structures. The material of the second dielectric layer is different from that of the first dielectric layer. The second dielectric layer is recessed; A third dielectric layer is formed on the recessed second dielectric layer. The material of the third dielectric layer is different from that of the second dielectric layer, thereby forming a wall fin structure. Remove the hard mask layer; A sacrificial gate structure is formed above the multiple fin structures; A sidewall gap wall is formed on the sidewall of the sacrificial gate structure and a portion of the sidewall of the wall fin structure; A source / drain structure is formed above the multiple fin structures adjacent to the sidewall gap wall; A fourth dielectric layer is formed above the source / drain structure; Remove the sacrificial gate structure; Remove the sacrificial covering layer; Remove the first semiconductor layer; as well as A metal gate structure is formed around the second semiconductor layer.

10. The method of manufacturing a semiconductor device as claimed in claim 9, wherein the etching operation comprises: One-through etching operation; A major etching operation following this penetrating etching operation; An atomic layer treatment for forming the protective layer following the main etching operation; as well as A lead removal etching operation following the treatment of this atomic layer.

11. The method of manufacturing a semiconductor device as claimed in claim 10, wherein the atomic layer processing includes a plasma process using an oxygen-containing gas.

12. The method of manufacturing a semiconductor device as claimed in claim 11, wherein the atomic layer treatment is performed in a temperature range of 25 °C to 100 °C.

13. The method of manufacturing a semiconductor device as claimed in claim 10, wherein: The main etching operation is stopped before the lateral portion of the sacrificial cover layer disposed on the insulating layer is completely removed, and The lead removal etching operation completely removes the lateral portion of the sacrificial cover layer disposed on the insulating layer.

14. The method of manufacturing a semiconductor device as claimed in claim 13, wherein after the lead removal etching operation, the difference between a first width, measured at an interface between the hard mask layer and the stacked layer, between the outer surfaces of the sacrificial cladding layer on the sidewalls of the hard mask layer and the stacked layer, and a second width, measured at an interface between the hard mask layer and the insulating layer, between the outer surfaces of the sacrificial cladding layer on the sidewalls of the hard mask layer and the stacked layer, is in the range of 0.5 nm to 1.0 nm, wherein the second width is greater than the first width.

15. The method of manufacturing a semiconductor device as claimed in claim 10, wherein: The sacrificial cladding layer is made of amorphous SiGe, and the steps for forming the sacrificial cladding layer include: A layer for the sacrificial cover layer is compliantly formed above the hard mask layer and the stacked layer and on the insulating layer; and Remove a portion of the layer on top of the hard shielding layer and on the insulating layer.

16. The method of manufacturing a semiconductor device as claimed in claim 9, wherein: The steps for forming this source / drain structure include: The source / drain region of the multiple fin structures is recessed; One end of the first semiconductor layer is laterally recessed; and An insulating internal spacer wall is formed at the recessed end of the first semiconductor layer; and One or more semiconductor epitaxial layers are formed, and at least a portion of the sacrificial cladding layer is removed during the recess.

17. A method for manufacturing a semiconductor device, comprising: Multiple fin structures are formed, each of which has a semiconductor fin, a hard masking layer on the semiconductor fin, and an upper part of the semiconductor fin protruding from an insulating layer. A sacrificial cladding layer is formed above the hard masking layer and the semiconductor fin; Partial etching of a lateral portion of the sacrificial coating; A protective layer is formed above the sacrificial coating layer; Remove a remaining portion of the lateral portion of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on the sidewalls of the hard mask layer and the semiconductor fin; A first dielectric layer is formed to partially fill a space between the plurality of semiconductor fins; A second dielectric layer is formed above the first dielectric layer to completely fill the space. The material of the second dielectric layer is different from that of the first dielectric layer. The second dielectric layer is recessed; and A third dielectric layer is formed on the recessed second dielectric layer. The material of the third dielectric layer is different from that of the second dielectric layer, thereby forming a wall fin structure between the plurality of fin structures.

18. The method of manufacturing a semiconductor device as claimed in claim 17, wherein: The sacrificial cladding layer is made of amorphous or polycrystalline SiGe, and The protective layer is an oxide of SiGe.

19. The method of manufacturing a semiconductor device as claimed in claim 17, wherein the thickness of the protective layer is in the range of 1 nm to 5 nm.

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