A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

Embodiments of the present disclosure provide a preparation method of a semiconductor structure and the semiconductor structure. The method comprises: providing an initial structure, the initial structure comprising a substrate, a plurality of active regions on the substrate, and a plurality of bit lines and a plurality of isolation fences formed above the substrate, the plurality of bit lines extending along a first direction, the plurality of isolation fences extending along a second direction intersecting the first direction, the plurality of bit lines and the plurality of isolation fences intersecting each other to define a plurality of openings, and part of the active regions being exposed from the openings; forming a compound layer, the compound layer covering at least the part of the active regions exposed from the openings; forming a first conductive layer, the first conductive layer covering at least part of the compound layer; and performing a heat treatment process, so that an alloying reaction occurs at an interface between the compound layer and the substrate to form an ohmic contact; wherein the compound layer comprises a transition metal chalcogenide, and the first conductive layer comprises a metal of the fifth main group.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] With technological advancements, semiconductor devices are continuously evolving towards miniaturization and higher integration. Dynamic Random Access Memory (DRAM), as an important semiconductor device, can be used to store data or programs for data processing in electronic devices. However, while the size and linewidth of DRAM continue to decrease, many problems in its manufacturing process still need to be addressed. Summary of the Invention

[0003] This disclosure provides a method for fabricating a semiconductor structure, including:

[0004] An initial structure is provided, the initial structure including a substrate, a plurality of active regions located on the substrate, and a plurality of bit lines and a plurality of isolation barriers formed above the substrate, the plurality of bit lines extending along a first direction, the plurality of isolation barriers extending along a second direction intersecting the first direction, the plurality of bit lines and the plurality of isolation barriers intersecting each other to define a plurality of openings, and a portion of the active regions being exposed from the openings;

[0005] A compound layer is formed, the compound layer at least covering the portion of the active region exposed from the opening;

[0006] A first conductive layer is formed, wherein the first conductive layer at least partially covers the compound layer;

[0007] A heat treatment process is performed to cause an alloying reaction at the interface between the compound layer and the substrate to form an ohmic contact; wherein,

[0008] The compound layer comprises a transition metal chalcogenide compound, and the first conductive layer comprises a Group V metal.

[0009] In the above scheme, the material forming the compound layer includes molybdenum sulfide; the material forming the first conductive layer includes metallic bismuth.

[0010] In the above scheme, a compound layer is formed, the compound layer at least covering a portion of the active region exposed from the opening, including:

[0011] An initial compound layer is formed on the substrate, the initial compound layer filling the opening and covering the top of the plurality of bit lines and the plurality of isolation fences;

[0012] After removing a portion of the initial compound layer, the remaining initial compound layer becomes a plurality of compound layers separated by the bit line and the isolation fence, the upper surface of the compound layer being lower than the upper surface of the bit line and the isolation fence;

[0013] After forming the compound layer, the method further includes:

[0014] A first conductive film is deposited, which covers the upper surface of the compound layer and the top and sidewalls of the bit lines and the isolation fence that are not covered by the compound layer.

[0015] In the above scheme, after depositing the first conductive thin film, the method further includes:

[0016] An etch-back process is performed on the first conductive film to remove the first conductive film located on the top and sidewalls of the bit line and the isolation fence, leaving the first conductive film located on the upper surface of the compound layer to form the first conductive layer.

[0017] In the above scheme, a compound layer is formed, which at least covers a portion of the active region exposed from the opening, forming a first conductive layer, which at least covers a portion of the compound layer, including:

[0018] A compound film is formed on the substrate, the compound film covering the bottom of the opening and the top and sidewalls of the plurality of bit lines and the plurality of isolation fences;

[0019] An initial first conductive layer is formed on the compound film, and the initial first conductive layer covers the compound film;

[0020] A back etching process is performed on a portion of the initial first conductive layer and the compound film, such that the remaining compound film and the remaining initial first conductive layer become a plurality of compound layers and first conductive layers separated by the bit line and the isolation barrier, wherein the upper surface of the first conductive layer is flush with the upper surface of the compound layer and the upper surface of the first conductive layer is lower than the upper surface of the bit line and the isolation barrier.

[0021] In the above schemes, in any of the above methods, after the heat treatment process, the method further includes: forming a second conductive layer, the second conductive layer covering the compound layer, the first conductive layer, and the top and sidewalls of the plurality of bit lines and the plurality of isolation fences.

[0022] In the above scheme, the step of forming the second conductive layer includes:

[0023] A metal barrier layer is formed, which covers the compound layer, the first conductive layer, and the top and sidewalls of the plurality of bit lines and the plurality of isolation fences;

[0024] A metal conductive layer is formed, which covers the metal barrier layer, and the metal conductive layer and the metal barrier layer together constitute a second conductive layer.

[0025] In the above scheme, after forming the second conductive layer, the method further includes:

[0026] A groove is formed extending along a third direction and a fourth direction. The groove penetrates the second conductive layer and a portion of the first conductive layer. The groove, together with the bit line and the isolation fence, divides the second conductive layer, the first conductive layer, and the compound layer into multiple discrete stacked structures. The stacked structures serve as node contact plugs. The third direction intersects the fourth direction, and the third direction and the fourth direction are not perpendicular to the first direction or the second direction.

[0027] In the above scheme, the heat treatment process includes:

[0028] Rapid thermal annealing, alternating thermal annealing, or cyclic thermal annealing processes in an oxygen-free environment.

[0029] In the above scheme, providing the initial structure includes:

[0030] Provide substrate;

[0031] Multiple active regions are formed on the substrate;

[0032] Multiple word lines extending along a second direction are formed within the substrate;

[0033] Multiple bit line layers extending along a first direction are formed on the substrate;

[0034] A protective layer is formed, which covers the top and sidewalls of the bit line layer and the active region between adjacent bit line layers;

[0035] A filler layer is formed, which covers the protective layer;

[0036] The filler layer is etched along a second direction to form a plurality of gaps extending along the second direction within the filler layer;

[0037] The gaps are filled with insulating material to form multiple isolation fences extending along the second direction;

[0038] Remove the filler layer.

[0039] In the above scheme, after removing the filler layer, the method further includes:

[0040] The protective layer retained on the top and sidewalls of the bit line and the isolation fence are thickened, and an opening is formed between adjacent bit lines and the isolation fence;

[0041] Remove the protective layer located at the bottom of the opening, so that a portion of the active region is exposed from the opening.

[0042] This disclosure also provides a semiconductor structure, including:

[0043] Substrate and multiple active regions located on the substrate;

[0044] Multiple bit lines extending in a first direction and multiple isolation barriers extending in a second direction are formed above the substrate. The multiple bit lines and the multiple isolation barriers intersect each other to form multiple openings, and a portion of the active region is exposed from the openings.

[0045] A compound layer located within the opening and at least partially covering the active region, and a first conductive layer located above the compound layer and at least partially covering the compound layer, wherein an ohmic contact is formed at the interface between the compound layer and the substrate by an alloying reaction, the compound layer comprising a transition metal chalcogenide compound, and the first conductive layer comprising a Group V metal.

[0046] In the above scheme, the material of the compound layer includes molybdenum sulfide, and the material of the first conductive layer includes metallic bismuth.

[0047] In the above scheme, along the direction perpendicular to the substrate plane, the projection of the compound layer overlaps with the projection of the first conductive layer.

[0048] In the above scheme, the first conductive layer also covers part of the top and part of the sidewalls of the bit line and the isolation fence.

[0049] In the above scheme, the compound layer has a basin-shaped structure, the basin-shaped structure includes a bottom and a sidewall located above the bottom, the first conductive layer covers the bottom, and the sidewall of the first conductive layer is covered by the sidewall.

[0050] In the above schemes, in any of the above structures, the semiconductor structure further includes:

[0051] A second conductive layer, wherein the second conductive layer at least covers the upper surface of the first conductive layer.

[0052] In the above scheme, the semiconductor structure further includes:

[0053] Grooves extending along a third direction and a fourth direction penetrate the second conductive layer and a portion of the first conductive layer, and together with the bit line and the isolation fence, divide the second conductive layer, the first conductive layer and the compound layer into multiple discrete stacked structures, which constitute node contact plugs, wherein the third direction intersects the fourth direction, and the third direction and the fourth direction are not perpendicular to the first direction or the second direction.

[0054] The semiconductor structure fabrication method and semiconductor structure provided in this disclosure include the following steps: providing an initial structure, the initial structure including a substrate, a plurality of active regions located on the substrate, and a plurality of bit lines and a plurality of isolation barriers formed above the substrate, the plurality of bit lines extending along a first direction, the plurality of isolation barriers extending along a second direction intersecting the first direction, the plurality of bit lines and the plurality of isolation barriers intersecting each other to define a plurality of openings, and a portion of the active regions being exposed from the openings; forming a compound layer, the compound layer at least covering a portion of the active regions exposed from the openings; forming a first conductive layer, the first conductive layer at least covering a portion of the compound layer; and performing a heat treatment process to cause an alloying reaction at the interface between the compound layer and the substrate to form an ohmic contact; wherein the compound layer includes a transition metal chalcogenide compound, and the first conductive layer includes a Group V metal. Thus, multiple openings exposing portions of the active region are first formed. Then, a compound layer, comprising a transition metal chalcogenide, is filled into these openings. This compound layer covers at least a portion of the active region exposed by the openings. Next, a first conductive layer, comprising a Group V metal, is formed on the compound layer. Following this, a heat treatment process is performed. By incorporating a heat treatment process, an alloying reaction occurs at the interface between the substrate and the compound layer, forming an ohmic contact between them, thereby effectively reducing the contact resistance. Furthermore, the heat treatment process can simultaneously form an ohmic contact between the compound layer and the first conductive layer, further reducing the contact resistance between them. Therefore, the semiconductor structure fabrication method provided in this disclosure, by changing the layer structure and improving the process method, can fabricate a conductive structure with low contact resistance between the semiconductor structure and the substrate within the openings, effectively reducing the operating current and energy consumption of the final semiconductor structure.

[0055] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0056] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0058] Figures 2 to 4 A process flow diagram of the preparation process of the initial structure provided in the embodiments of this disclosure;

[0059] Figures 5 to 9 A process flow diagram of the semiconductor structure fabrication process provided in one embodiment of this disclosure;

[0060] Figure 10 This is a partially enlarged schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0061] Figures 11 to 12 A process flow diagram of the semiconductor structure fabrication process provided in another embodiment of this disclosure;

[0062] Figure 13 This is a partially enlarged schematic diagram of another semiconductor structure provided in the embodiments of this disclosure;

[0063] Figures 14 to 17 A process flow diagram of the semiconductor structure provided in yet another embodiment of this disclosure during fabrication;

[0064] Figure 18 A partially enlarged schematic diagram of yet another semiconductor structure provided in the embodiments of this disclosure;

[0065] Figure 19 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0066] Figure 20A The semiconductor structure provided in the embodiments of this disclosure is along Figure 19 Detailed sectional view along the A1-A2 direction;

[0067] Figure 20B The semiconductor structure provided in the embodiments of this disclosure is along Figure 19 Detailed sectional view along the B1-B2 direction. Detailed Implementation

[0068] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0069] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0070] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0071] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0072] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0073] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0074] Semiconductor devices, such as Dynamic Random Access Memory (DRAM), can be used as data storage or program storage for electronic devices during operation, enabling data processing. In some architectures with large data processing volumes, multiple DRAM structures need to be configured simultaneously to perform data processing operations. In such cases, a significant power consumption is often required to maintain normal operation.

[0075] However, as the size of semiconductor devices shrinks, the resistance of some semiconductor devices increases, further increasing the power consumption of semiconductor devices.

[0076] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0077] This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the method includes the following steps:

[0078] Step S101: Provide an initial structure, the initial structure including a substrate, a plurality of active regions located on the substrate, and a plurality of bit lines and a plurality of isolation barriers formed above the substrate, the plurality of bit lines extending along a first direction, the plurality of isolation barriers extending along a second direction intersecting the first direction, the plurality of bit lines and the plurality of isolation barriers intersecting each other to define a plurality of openings, and a portion of the active regions being exposed from the openings;

[0079] Step S102: Form a compound layer that at least covers the portion of the active region exposed from the opening;

[0080] Step S103: Form a first conductive layer, wherein the first conductive layer at least partially covers the compound layer;

[0081] Step S104: Perform a heat treatment process to cause an alloying reaction at the interface between the compound layer and the substrate to form an ohmic contact; wherein the compound layer comprises a transition metal chalcogenide compound, and the first conductive layer comprises a Group V metal.

[0082] In this embodiment, multiple openings exposing a portion of the active region are first formed. Then, a compound layer is filled into the openings. The compound layer is made of a transition metal chalcogenide compound, and it covers at least a portion of the active region exposed by the openings. Next, a first conductive layer is formed on the compound layer. The first conductive layer is made of a Group V metal. Following this, a heat treatment process is performed. By incorporating a heat treatment process, an alloying reaction occurs at the interface between the substrate and the compound layer, forming an ohmic contact between them, thereby effectively reducing the contact resistance. Furthermore, the heat treatment process can simultaneously form an ohmic contact between the compound layer and the first conductive layer, further reducing the contact resistance between them. Therefore, the semiconductor structure fabrication method provided in this embodiment, by changing the layer structure and improving the process, can fabricate a conductive structure with low contact resistance between the semiconductor structure and the substrate within the openings, effectively reducing the operating current and energy consumption of the final semiconductor structure.

[0083] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, the schematic diagrams may be partially enlarged off-scale for ease of explanation, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0084] Figures 2 to 4 A process flow diagram of the preparation process of the initial structure provided in the embodiments of this disclosure; Figures 5 to 9A process flow diagram of the semiconductor structure fabrication process provided in one embodiment of this disclosure; Figure 10 This is a partially enlarged schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figures 11 to 12 A process flow diagram of the semiconductor structure fabrication process provided in another embodiment of this disclosure; Figure 13 This is a partially enlarged schematic diagram of another semiconductor structure provided in the embodiments of this disclosure; Figures 14 to 17 A process flow diagram of the semiconductor structure provided in yet another embodiment of this disclosure during fabrication; Figure 18 A partially enlarged schematic diagram of yet another semiconductor structure provided in the embodiments of this disclosure;

[0085] Figure 19 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 20A The semiconductor structure provided in the embodiments of this disclosure is along Figure 19 Detailed sectional view along the A1-A2 direction; Figure 20B The semiconductor structure provided in the embodiments of this disclosure is along Figure 19 Detailed sectional view along the B1-B2 direction.

[0086] The method for preparing the semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0087] First, execute step S101: as follows Figure 4 As shown, an initial structure IS is provided, the initial structure IS including a substrate 1, a plurality of active regions 101 located on the substrate, and a plurality of bit lines BL and a plurality of isolation barriers 102 formed above the substrate 1. The plurality of bit lines BL extend along a first direction, and the plurality of isolation barriers 102 extend along a second direction intersecting the first direction. The plurality of bit lines BL and the plurality of isolation barriers 102 intersect each other to define a plurality of openings H, and a portion of the active regions 101 are exposed from the openings H.

[0088] In some embodiments, such as Figures 2 to 3 As shown, the provision of the initial structure IS includes:

[0089] Substrate 1 is provided;

[0090] A plurality of active regions 101 are formed on the substrate 1;

[0091] Multiple word lines WL extending along the second direction are formed within the substrate 1;

[0092] Multiple bit line layers L1 extending along a first direction are formed on the substrate 1;

[0093] A protective layer L2 is formed, which covers the top and sidewalls of the bit line layer L1 and the active region 101 between adjacent bit line layers L1;

[0094] A filling layer L3 is formed, which covers the protective layer L2;

[0095] The filling layer L3 is etched along the second direction to form a plurality of gaps T1 extending along the second direction within the filling layer L3;

[0096] The gap T1 is filled with insulating material to form multiple isolation fences 102 extending along the second direction;

[0097] Remove the filler layer L3.

[0098] Here, the substrate can be a semiconductor substrate. In some specific embodiments, the substrate may include a silicon substrate.

[0099] In actual manufacturing processes, conventional methods, such as patterning the substrate, can be used to form the active region, which will not be elaborated upon here. In some embodiments, the active region is made of the same material as the substrate.

[0100] In some embodiments, the protective layer, the filling layer, and the insulating material include, but are not limited to, oxides, nitrides, and nitrogen oxides.

[0101] In some specific embodiments, the protective layer may include, but is not limited to, silicon nitride; the filling layer may include, but is not limited to, silicon oxide; and the insulating material may include, but is not limited to, silicon nitride.

[0102] In some embodiments, the bit line layer L1 and the protective layer L2 together constitute the bit line BL.

[0103] In some embodiments, such as Figure 3 and Figure 4 As shown, after removing the filler layer L3, the method further includes:

[0104] The protective layer L2 retained on the top and sidewalls of the bit line BL and the isolation fence 102 are thickened, and an opening H is formed between adjacent bit lines BL and isolation fence 102;

[0105] Remove the protective layer L2 located at the bottom of the opening H, so that a portion of the active region 101 is exposed from the opening H.

[0106] Next, proceed to step S102, as follows: Figure 5 and Figure 6As shown, a compound layer 11 is formed, which at least covers the portion of the active region 101 exposed from the opening H.

[0107] Continue to refer to Figure 5 and Figure 6 In some embodiments, the formation of compound layer 11, which at least covers a portion of the active region 101 exposed from the opening H, includes:

[0108] An initial compound layer 11a is formed on the substrate 1, the initial compound layer 11a filling the opening H and covering the top of the plurality of bit lines BL and the plurality of isolation barriers 102;

[0109] After removing a portion of the initial compound layer 11a, the remaining initial compound layer 11a becomes a plurality of compound layers 11 separated by the bit line BL and the isolation barrier 102, with the upper surface of the compound layer 11 being lower than the upper surface of the bit line BL and the isolation barrier 102.

[0110] Next, continue with step S103, as follows: Figure 7 As shown, a first conductive layer 12 is formed, which at least partially covers the compound layer 11.

[0111] In some embodiments, such as Figure 7 As shown, after forming the compound layer 11, the method further includes:

[0112] A first conductive film 12a is deposited, which covers the upper surface of the compound layer 11 and the top and sidewalls of the bit line BL and the isolation fence 102 that are not covered by the compound layer 11.

[0113] In some embodiments, such as Figure 7 As shown, after the first conductive film 12a is formed, the first conductive film 12a can be directly used as the first conductive layer 12 of the semiconductor structure, and then subsequent processes can be performed.

[0114] Finally, step S104 is performed to conduct a heat treatment process, so that an alloying reaction occurs at the interface between the compound layer 11 and the substrate 1 to form an ohmic contact; wherein, the compound layer 11 includes a transition metal chalcogenide compound, and the first conductive layer 12 includes a Group V metal.

[0115] Compared with the traditional method of forming a conductive structure by directly contacting a polycrystalline silicon layer with a substrate, the present invention uses a transition metal chalcogenide compound as the material for direct contact with the substrate, which creates favorable conditions for the subsequent formation of an ohmic contact between the substrate and the compound layer.

[0116] In some embodiments, the transition metal chalcogenides include, but are not limited to, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), molybdenum distelluride (MoTe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), tungsten distelluride (WTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), zirconium disulfide (ZrS2), and zirconium diselenide (ZrSe2); the material of the first conductive layer includes a conductive metal.

[0117] In some specific embodiments, the material forming the compound layer 11 includes molybdenum sulfide; the material forming the first conductive layer 12 includes metallic bismuth.

[0118] In some embodiments, the heat treatment process includes: rapid thermal annealing in an oxygen-free environment, alternating thermal annealing, or cyclic thermal annealing.

[0119] In actual processes, rapid thermal annealing in an oxygen-free environment can be performed in an atmosphere containing inert gases such as N2, He, and Ar, or in a reducing gas such as H2, or in a mixture of these gases.

[0120] In some embodiments, the equipment for performing the heat treatment process may include, but is not limited to, furnace tubes, etc., and the temperature range of the heat treatment process is between 200°C and 650°C, such as 220°C, 250°C, 300°C, 400°C, 460°C, 520°C, etc.

[0121] During the heat treatment process, atoms in the compound layer and atoms in the substrate can diffuse into each other near the interface between them. That is, atoms of the material constituting the substrate diffuse into the compound layer, and similarly, atoms of the material constituting the compound layer diffuse into the substrate. This interdiffusion causes an alloying reaction at the interface between the substrate and the compound layer, thereby forming an ohmic contact between them and effectively reducing the contact resistance between them.

[0122] In some embodiments, the active region can be obtained by performing a patterning process on the substrate, where the substrate and the active region can be made of the same material. Therefore, when an ohmic contact is formed between the substrate and the compound layer, an ohmic contact is obtained between the active region and the compound layer. Thus, the fabrication method of this disclosure can also reduce the contact resistance between the active region and the compound layer, effectively reducing the operating current of the final semiconductor structure and lowering energy consumption.

[0123] Furthermore, the aforementioned heat treatment process can simultaneously form an ohmic contact between the compound layer and the first conductive layer, further reducing the contact resistance between them. Therefore, the semiconductor structure fabrication method provided in this disclosure can form a conductive structure with low contact resistance with the substrate, effectively reducing the operating current of the final semiconductor structure and lowering energy consumption.

[0124] In some embodiments, such as Figures 8 to 10 As shown, after the heat treatment process, the method further includes: forming a second conductive layer 13, the second conductive layer 13 covering the compound layer 11, the first conductive layer 12, and the top and sidewalls of the plurality of bit lines BL and the plurality of isolation fences 102.

[0125] In some embodiments, the step of forming the second conductive layer 13 includes:

[0126] A metal barrier layer 13a is formed, which covers the compound layer 11, the first conductive layer 12, and the top and sidewalls of the multiple bit lines BL and the multiple isolation fences 102;

[0127] A metal conductive layer 13b is formed, which covers the metal barrier layer 13a. The metal conductive layer 13b and the metal barrier layer 13a together constitute the second conductive layer 13.

[0128] In some embodiments, the material of the metal barrier layer includes, but is not limited to, titanium nitride; the material of the metal conductive layer includes, but is not limited to, tungsten.

[0129] In another embodiment of this disclosure, such as Figure 4 , Figure 7 , Figures 11 to 13 As shown, forming the semiconductor structure includes:

[0130] First, provide the initial structure IS;

[0131] Next, compound layer 11 is formed;

[0132] Then, the first conductive layer 12 is formed;

[0133] Finally, a heat treatment process is performed to cause an alloying reaction at the interface between the compound layer 11 and the substrate 1 to form an ohmic contact; wherein the compound layer 11 comprises a transition metal chalcogenide compound, and the first conductive layer 12 comprises a Group V metal.

[0134] In this embodiment, the method of providing the initial structure IS and forming the compound layer 11 is the same as in the previous embodiment, and will not be described again here.

[0135] In this embodiment, such as Figure 7 and Figure 11 As shown, the formation of the first conductive layer 12 includes:

[0136] A first conductive film 12a is deposited, which covers the upper surface of the compound layer 11 and the top and sidewalls of the bit line BL and the isolation fence 102 that are not covered by the compound layer 11.

[0137] After depositing the first conductive thin film 12a, the method further includes:

[0138] An etch-back process is performed on the first conductive film 12a to remove the first conductive film 12a located on the top and sidewalls of the bit line BL and the isolation barrier 102, leaving the first conductive film 12a located on the upper surface of the compound layer 11 to form the first conductive layer 12.

[0139] Finally, a heat treatment process is performed to form an ohmic contact at the interface between the compound layer and the substrate, i.e., to form an ohmic contact between the compound layer and the substrate. At the same time, the heat treatment process can also form an ohmic contact between the compound layer and the first conductive layer.

[0140] In this embodiment, such as Figure 12 and Figure 13 As shown, after the heat treatment process, the method further includes: forming a second conductive layer 13, which covers the compound layer 11, the first conductive layer 12, and the top and sidewalls of the plurality of bit lines BL and the plurality of isolation fences 102.

[0141] In this embodiment, the material composition and forming process of each layer structure can be the same as or different from the previous embodiment, and can be flexibly adjusted according to the actual situation.

[0142] In yet another embodiment of this disclosure, such as Figure 4 and Figures 14 to 18 As shown, forming the semiconductor structure includes:

[0143] First, provide the initial structure IS;

[0144] Next, compound layer 11 is formed;

[0145] Then, the first conductive layer 12 is formed;

[0146] Finally, a heat treatment process is performed to cause an alloying reaction at the interface between the compound layer 11 and the substrate 1 to form an ohmic contact; wherein the compound layer 11 comprises a transition metal chalcogenide compound, and the first conductive layer 12 comprises a Group V metal.

[0147] In this embodiment, the method for providing the initial structure IS is the same as that in the above embodiments, and will not be described in detail here.

[0148] like Figure 4 and Figures 14 to 16 As shown, a compound layer 11 is formed, which at least covers a portion of the active region 101 exposed from the opening H, and a first conductive layer 12 is formed, which at least covers a portion of the compound layer 11, comprising:

[0149] A compound film 11b is formed on the substrate, the compound film 11b covering the bottom of the opening H and the top and sidewalls of the plurality of bit lines BL and the plurality of isolation fences 102;

[0150] An initial first conductive layer 12b is formed on the compound film 11b, and the initial first conductive layer 12b covers the compound film 11b.

[0151] A partial etch-back process is performed on the initial first conductive layer 12b and the compound film 11b, such that the remaining compound film 11b and the remaining initial first conductive layer 12b become a plurality of compound layers 11 and first conductive layers 12 separated by the bit line and the isolation barrier. The upper surfaces of the first conductive layers 12 are flush with the upper surfaces of the compound layers 11, and the upper surfaces of the first conductive layers 12 are lower than the upper surfaces of the bit line BL and the isolation barrier 102.

[0152] Finally, a heat treatment process is performed to form an ohmic contact at the interface between the compound layer and the substrate, i.e., to form an ohmic contact between the compound layer and the substrate. At the same time, the heat treatment process can also form an ohmic contact between the compound layer and the first conductive layer.

[0153] In this embodiment, such as Figure 17 and Figure 18 As shown, after the heat treatment process, the method further includes: forming a second conductive layer 13, which covers the compound layer 11, the first conductive layer 12, and the top and sidewalls of the plurality of bit lines BL and the plurality of isolation fences 102.

[0154] In this embodiment, the material composition and forming process of each layer structure can be the same as or different from the previous embodiment, and can be flexibly adjusted according to the actual situation.

[0155] In this embodiment of the present disclosure, after forming the semiconductor structure in the above embodiments, a plurality of groove structures may be formed on the semiconductor structure, the groove structures dividing the second conductive layer, the first conductive layer and the compound layer into a plurality of stacked structures.

[0156] by Figure 9 Taking the example of the semiconductor structure forming a groove structure shown, in some embodiments, such as Figure 19 , Figure 20A and Figure 20B As shown, after forming the second conductive layer 13, the method further includes:

[0157] A groove T2 is formed extending along a third direction and a fourth direction. The groove T2 penetrates the second conductive layer 13 and part of the first conductive layer 12. The groove T2, together with the bit line BL and the isolation fence 102, divides the second conductive layer 13, the first conductive layer 12 and the compound layer 11 into multiple discrete stacked structures ST. The stacked structures ST serve as node contact plugs. The third direction intersects the fourth direction, and the third direction is not perpendicular to the first direction or the second direction.

[0158] Understandably, when the semiconductor structure is a dynamic random access memory (DRAM), the node contact plug can be used to form an electrical connection between the subsequently formed capacitor structure and the active region. The node contact plug formed using the method of this disclosure effectively reduces the contact resistance between the node contact plug and the active region. Furthermore, there are no Schottky barriers or metal-induced gap states between the semiconductor and metal materials contained in the node contact plug itself, avoiding situations with high contact resistance. Therefore, this disclosure embodiment can significantly reduce the power consumption of the semiconductor structure.

[0159] It should be noted that, in the appendix Figure 20A and attached Figure 20B The diagram only schematically illustrates the relationships between the grooves, stacked structures, bit lines, and word lines. For descriptions of other structures, please refer to the remaining figures.

[0160] Alternatively, similar methods can be used to form grooves and node contact plugs in the semiconductor structure mentioned in any of the other embodiments, which will not be elaborated here.

[0161] This disclosure also provides a semiconductor structure, such as... Figure 4 and Figure 10 As shown, it includes:

[0162] Substrate 1 and a plurality of active regions 101 located on said substrate 1;

[0163] Multiple bit lines BL extending in a first direction and multiple isolation barriers 102 extending in a second direction are formed above the substrate 1. The multiple bit lines BL and the multiple isolation barriers 102 intersect each other to form multiple openings H, and a portion of the active region 102 is exposed from the openings H.

[0164] A compound layer 11 located within the opening H and at least partially covering the active region 101, and a first conductive layer 12 located above the compound layer 11 and at least partially covering the compound layer, wherein an ohmic contact is formed at the interface between the compound layer 11 and the substrate 1 by an alloying reaction, the compound layer 11 comprising a transition metal chalcogenide compound, and the first conductive layer 12 comprising a Group V metal.

[0165] In actual manufacturing processes, conventional methods, such as patterning the substrate, can be used to form the active region, which will not be elaborated upon here. In some embodiments, the active region is made of the same material as the substrate.

[0166] Compared with the traditional method of using a polycrystalline silicon layer to directly contact the substrate to form a conductive structure, the present invention uses a transition metal chalcogenide compound as the material layer for direct contact with the substrate, which creates favorable conditions for forming an ohmic contact between the substrate and the compound layer.

[0167] In some embodiments, the transition metal chalcogenides include, but are not limited to, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), molybdenum distelluride (MoTe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), tungsten distelluride (WTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), zirconium disulfide (ZrS2), and zirconium diselenide (ZrSe2); the material of the first conductive layer includes a conductive metal.

[0168] In some specific embodiments, the compound layer 11 is made of molybdenum sulfide, and the first conductive layer 12 is made of metallic bismuth.

[0169] In this embodiment of the disclosure, an ohmic contact can be formed by performing a heat treatment process on the semiconductor structure to induce an alloying reaction at the interface between the compound layer and the substrate.

[0170] In this embodiment, an ohmic contact is formed between the substrate and the compound layer, thereby effectively reducing the contact resistance between them. Furthermore, the aforementioned heat treatment process can simultaneously form an ohmic contact between the compound layer and the first conductive layer, further reducing the contact resistance between them. Therefore, the semiconductor structure fabrication method provided in this embodiment, by changing the layer structure configuration and combining it with improved process methods, can fabricate a conductive structure with low contact resistance with the substrate within the opening, effectively reducing the operating current of the final semiconductor structure and lowering energy consumption.

[0171] In some embodiments, the heat treatment process includes: rapid thermal annealing in an oxygen-free environment, alternating thermal annealing, or cyclic thermal annealing.

[0172] In actual processes, rapid thermal annealing in an oxygen-free environment can be performed in an atmosphere containing inert gases such as N2, He, and Ar, or in a reducing gas such as H2, or in a mixture of these gases.

[0173] In some embodiments, the equipment for performing the heat treatment process may include, but is not limited to, furnace tubes, etc., and the temperature range of the heat treatment process is between 200°C and 650°C, such as 220°C, 250°C, 300°C, 400°C, 460°C, 520°C, etc.

[0174] In the structure of one embodiment of this disclosure, as Figure 12 and Figure 13 As shown, along a direction perpendicular to the plane of the substrate 1, the projection of the compound layer 11 overlaps with the projection of the first conductive layer 12.

[0175] In another embodiment of the structure of this disclosure, as Figure 9 and Figure 10 As shown, the first conductive layer 12 also covers part of the top and part of the sidewalls of the bit line BL and the isolation fence 102.

[0176] In yet another embodiment of the structure of this disclosure, as Figure 17 and Figure 18 As shown, the compound layer 11 has a basin-shaped structure, the basin-shaped structure includes a bottom and a sidewall located above the bottom, the first conductive layer 12 covers the bottom, and the sidewall of the first conductive layer 12 is covered by the sidewall.

[0177] In the structure of any of the above embodiments, combined with Figure 10 , Figure 13 and Figure 18 It can be seen that the semiconductor structure also includes:

[0178] The second conductive layer 13 covers at least the upper surface of the first conductive layer 12.

[0179] In some embodiments, the second conductive layer 13 includes a metal barrier layer 13a and a metal conductive layer 13b, wherein the metal conductive layer 13b and the metal barrier layer 13a together constitute the second conductive layer 13.

[0180] In some specific embodiments, the material of the metal barrier layer includes, but is not limited to, titanium nitride; the material of the metal conductive layer includes, but is not limited to, tungsten.

[0181] In some embodiments, the semiconductor structure may further include a plurality of groove structures that divide the second conductive layer, the first conductive layer, and the compound layer into a plurality of stacked structures.

[0182] by Figure 9 Taking the semiconductor structure shown as an example, the specific structure formed after setting multiple grooves T2 can be found in the reference. Figure 19 , Figure 20A and Figure 20B As shown, the semiconductor structure further includes:

[0183] A groove T2 extending along a third direction and a fourth direction penetrates the second conductive layer 13 and a portion of the first conductive layer 12, and together with the bit line BL and the isolation fence 102, divides the second conductive layer 13, the first conductive layer 12 and the compound layer 11 into a plurality of discrete stacked structures ST, which constitute node contact plugs, wherein the third direction intersects the fourth direction, and the third direction is not perpendicular to the first direction or the second direction.

[0184] Understandably, when the semiconductor structure is a dynamic random access memory (DRAM), the node contact plug can be used to form an electrical connection between the subsequently formed capacitor structure and the active region. In this embodiment, the contact resistance between the node contact plug and the active region is effectively reduced; furthermore, there are no Schottky barriers or metal-induced gap states between the semiconductor and metal materials contained in the node contact plug itself, avoiding situations with high contact resistance. Therefore, this embodiment can significantly reduce the power consumption of the semiconductor structure.

[0185] It should be noted that a similar method of setting a groove structure can also be used to set a groove in the semiconductor structure mentioned in any other embodiment to form a node contact plug structure, which will not be elaborated here.

[0186] In summary, in this embodiment, multiple openings exposing portions of the active region are first formed. Then, a compound layer is filled into the openings. The compound layer is made of a transition metal chalcogenide compound, and it covers at least a portion of the active region exposed by the openings. Next, a first conductive layer is formed on the compound layer. The first conductive layer is made of a Group V metal. Following this, a heat treatment process is performed. By incorporating a heat treatment process, an alloying reaction occurs at the interface between the substrate and the compound layer, forming an ohmic contact between the substrate and the compound layer, thereby effectively reducing the contact resistance between them.

[0187] Furthermore, an ohmic contact can be formed simultaneously between the compound layer and the first conductive layer through a heat treatment process, further reducing the contact resistance between them. Therefore, the semiconductor structure fabrication method provided in this disclosure, by changing the structure of each layer and combining it with improvements in the process method, can fabricate a conductive structure with low contact resistance with the substrate in the opening, which can effectively reduce the operating current of the final semiconductor structure and reduce energy consumption.

[0188] Furthermore, it is understood that when the semiconductor structure is a dynamic random access memory (DRAM), the node contact plug can be used to form an electrical connection between the subsequently formed capacitor structure and the active region. The node contact plug formed using the method of this disclosure effectively reduces the contact resistance between the node contact plug and the active region. In addition, there are no Schottky barriers or metal-induced gap states between the semiconductor and metal materials contained in the node contact plug itself, avoiding situations with high contact resistance. Therefore, the embodiments of this disclosure can significantly reduce the power consumption of the semiconductor structure.

[0189] It should be noted that the semiconductor device fabrication method provided in this disclosure can be applied to DRAM structures or other semiconductor devices, and is not limited thereto. The embodiments of the semiconductor device fabrication method provided in this disclosure and the embodiments of the semiconductor devices belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0190] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: providing an initial structure, the initial structure including a substrate, a plurality of active regions located on the substrate, and a plurality of bit lines and a plurality of isolation barriers formed above the substrate, the plurality of bit lines extending along a first direction, the plurality of isolation barriers extending along a second direction intersecting the first direction, the plurality of bit lines and the plurality of isolation barriers intersecting each other to define a plurality of openings, and a portion of the active regions being exposed from the openings; A compound layer is formed, the compound layer at least covering the portion of the active region exposed from the opening; A first conductive layer is formed, wherein the first conductive layer at least partially covers the compound layer; A heat treatment process is performed to cause an alloying reaction at the interface between the compound layer and the substrate to form an ohmic contact; wherein, The compound layer comprises a transition metal chalcogenide compound, and the first conductive layer comprises a Group V metal. The provision of the initial structure includes: Provide substrate; Multiple active regions are formed on the substrate; Multiple word lines extending along a second direction are formed within the substrate; Multiple bit line layers extending along a first direction are formed on the substrate; A protective layer is formed, which covers the top and sidewalls of the bit line layer and the active region between adjacent bit line layers; A filler layer is formed, which covers the protective layer; The filler layer is etched along a second direction to form a plurality of gaps extending along the second direction within the filler layer; The gaps are filled with insulating material to form multiple isolation fences extending along the second direction; Remove the filler layer.

2. The method according to claim 1, characterized in that, The material forming the compound layer includes molybdenum sulfide; the material forming the first conductive layer includes metallic bismuth.

3. The method according to claim 1, characterized in that, Forming a compound layer that at least covers a portion of the active region exposed from the opening, including: An initial compound layer is formed on the substrate, the initial compound layer filling the opening and covering the top of the plurality of bit lines and the plurality of isolation fences; After removing a portion of the initial compound layer, the remaining initial compound layer becomes a plurality of compound layers separated by the bit line and the isolation fence, the upper surface of the compound layer being lower than the upper surface of the bit line and the isolation fence; After forming the compound layer, the method further includes: A first conductive film is deposited, which covers the upper surface of the compound layer and the top and sidewalls of the bit lines and the isolation fence that are not covered by the compound layer.

4. The method according to claim 3, characterized in that, After depositing the first conductive thin film, the method further includes: An etch-back process is performed on the first conductive film to remove the first conductive film located on the top and sidewalls of the bit line and the isolation fence, leaving the first conductive film located on the upper surface of the compound layer to form the first conductive layer.

5. The method according to claim 1, characterized in that, A compound layer is formed, the compound layer at least covering a portion of the active region exposed from the opening, and a first conductive layer is formed, the first conductive layer at least covering a portion of the compound layer, including: A compound film is formed on the substrate, the compound film covering the bottom of the opening and the top and sidewalls of the plurality of bit lines and the plurality of isolation fences; An initial first conductive layer is formed on the compound film, and the initial first conductive layer covers the compound film; A back etching process is performed on a portion of the initial first conductive layer and the compound film, such that the remaining compound film and the remaining initial first conductive layer become a plurality of compound layers and first conductive layers separated by the bit line and the isolation barrier, wherein the upper surface of the first conductive layer is flush with the upper surface of the compound layer and the upper surface of the first conductive layer is lower than the upper surface of the bit line and the isolation barrier.

6. The method according to any one of claims 1-5, characterized in that, After the heat treatment process, the method further includes forming a second conductive layer that covers the compound layer, the first conductive layer, and the top and sidewalls of the plurality of bit lines and the plurality of isolation fences.

7. The method according to claim 6, characterized in that, The step of forming the second conductive layer includes: A metal barrier layer is formed, which covers the compound layer, the first conductive layer, and the top and sidewalls of the plurality of bit lines and the plurality of isolation fences; A metal conductive layer is formed, which covers the metal barrier layer, and the metal conductive layer and the metal barrier layer together constitute a second conductive layer.

8. The method according to claim 6, characterized in that, After forming the second conductive layer, the method further includes: A groove is formed extending along a third direction and a fourth direction. The groove penetrates the second conductive layer and a portion of the first conductive layer. The groove, together with the bit line and the isolation fence, divides the second conductive layer, the first conductive layer, and the compound layer into multiple discrete stacked structures. The stacked structures serve as node contact plugs. The third direction intersects the fourth direction, and the third direction and the fourth direction are not perpendicular to the first direction or the second direction.

9. The method according to claim 1, characterized in that, The heat treatment process includes: Rapid thermal annealing, alternating thermal annealing, or cyclic thermal annealing processes in an oxygen-free environment.

10. The method according to claim 1, characterized in that, After removing the filler layer, the method further includes: The protective layer retained on the top and sidewalls of the bit line and the isolation fence are thickened, and an opening is formed between adjacent bit lines and the isolation fence; Remove the protective layer located at the bottom of the opening, so that a portion of the active region is exposed from the opening.

11. A semiconductor structure, characterized in that, include: Substrate and multiple active regions located on the substrate; Multiple bit lines extending in a first direction and multiple isolation barriers extending in a second direction are formed above the substrate. The multiple bit lines and multiple isolation barriers intersect each other to form multiple openings, and a portion of the active region is exposed from the openings. A compound layer located within the opening and at least partially covering the active region, and a first conductive layer located above the compound layer and at least partially covering the compound layer, wherein an ohmic contact is formed at the interface between the compound layer and the substrate by an alloying reaction, the compound layer comprising a transition metal chalcogenide compound, and the first conductive layer comprising a Group V metal; The compound layer has a basin-shaped structure, which includes a bottom and a sidewall located above the bottom. The first conductive layer covers the bottom, and the sidewall of the first conductive layer is covered by the sidewall.

12. The structure according to claim 11, characterized in that, The compound layer is made of molybdenum sulfide, and the first conductive layer is made of metallic bismuth.

13. The structure according to claim 11, characterized in that, Along a direction perpendicular to the plane of the substrate, the projection of the compound layer overlaps with the projection of the first conductive layer.

14. The structure according to claim 11, characterized in that, The first conductive layer also covers a portion of the top and a portion of the sidewalls of the bit line and the isolation fence.

15. The structure according to any one of claims 11-14, characterized in that, The semiconductor structure also includes: A second conductive layer, wherein the second conductive layer at least covers the upper surface of the first conductive layer.

16. The structure according to claim 15, characterized in that, The semiconductor structure also includes: Grooves extending along a third direction and a fourth direction penetrate the second conductive layer and a portion of the first conductive layer, and together with the bit line and the isolation fence, divide the second conductive layer, the first conductive layer and the compound layer into multiple discrete stacked structures, which constitute node contact plugs, wherein the third direction intersects the fourth direction, and the third direction and the fourth direction are not perpendicular to the first direction or the second direction.

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