Method for manufacturing a semiconductor structure and structure thereof

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a manufacturing method of a semiconductor structure and a structure thereof, wherein the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming semiconductor channels arranged in an array along a first direction and a second direction on the substrate; forming bit lines extending along the first direction, the bit lines are located in the substrate, and each bit line is electrically connected with a plurality of semiconductor channels arranged along the first direction; forming word lines extending along the second direction, the word lines wrap part of side surfaces of the plurality of semiconductor channels arranged along the second direction, and one word line comprises two sub-word lines arranged along the first direction at intervals, and the sub-word lines cover opposite part of side surfaces of the semiconductor channels along the first direction; and forming isolation structures between adjacent word lines and between adjacent sub-word lines. The electrical performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a method for fabricating a semiconductor structure and the structure thereof. Background Technology

[0002] Memory is a storage component used to store programs and various data information. Random Access Memory (RAM) used in general computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM is a commonly used semiconductor storage device in computers, consisting of many repeating storage cells.

[0003] A memory cell typically includes a capacitor and a transistor. The drain of the transistor is connected to the bit line, and the source is connected to the capacitor. The capacitor includes a capacitor contact structure and a capacitance. The word line of the memory cell can control the opening or closing of the transistor's channel region, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0004] However, there are currently many parasitic capacitances between adjacent word lines, which affect the electrical performance of the semiconductor structure. Summary of the Invention

[0005] This disclosure provides a method for fabricating a semiconductor structure and the structure thereof, which can at least improve the electrical performance of the semiconductor structure.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, including providing a substrate; forming semiconductor channels arranged in an array along a first direction and a second direction on the substrate; forming bit lines extending along the first direction, the bit lines being located within the substrate, and each bit line being electrically connected to a plurality of semiconductor channels arranged along the first direction; forming word lines extending along the second direction, the word lines wrapping around a portion of the side surfaces of the plurality of semiconductor channels arranged along the second direction, and each word line including two sub-word lines spaced apart along the first direction, the sub-word lines covering opposite side surfaces of the semiconductor channels along the first direction; and forming an isolation structure located between adjacent word lines and between adjacent sub-word lines.

[0007] In some embodiments, the method of forming the word line includes: forming a word line conductive layer, the word line conductive layer extending along a second direction and the word line conductive layers being spaced apart between the semiconductor channels along a first direction, and the word line conductive layer covering a portion of the semiconductor channels opposite to each other along the first direction; forming a word line protective layer, the word line protective layer being located on the top surface of the word line conductive layer; the word line conductive layer and the word line protective layer constituting the word line.

[0008] In some embodiments, the method of forming the word line conductive layer includes: forming a groove extending along a second direction and the grooves being spaced apart between the semiconductor channels along a first direction; forming an initial word line conductive layer filling a portion of the groove; and etching back the initial word line conductive layer to form the word line conductive layer.

[0009] In some embodiments, the method of forming the groove includes: forming an initial groove that extends in a second direction and is spaced apart between the semiconductor channels along a first direction, the initial groove also exposing the top surface of the bit line; forming an isolation layer located on the top surface of the bit line, wherein the height of the isolation layer in a direction perpendicular to the substrate surface is less than the depth of the initial groove, and the remaining initial groove serves as a groove.

[0010] In some embodiments, the method of forming the semiconductor channel includes: forming a mask layer, and patterning the substrate using the mask layer as a mask to form the semiconductor channel; the method of forming the isolation layer includes: forming an initial isolation layer, the initial isolation layer filling the initial groove; patterning the initial isolation layer using the mask layer as a mask, and using the remaining initial isolation layer as the isolation layer.

[0011] In some embodiments, the method of forming the bit line includes: forming a sidewall layer that covers the sidewalls of the semiconductor channel arranged along the first direction; forming a bit line groove that is located within the substrate and connected to the sidewall layer; and forming a bit line, a portion of which is located within the groove and a portion of which extends from the groove toward the substrate.

[0012] In some embodiments, the method of forming the bit line includes: forming a metal silicide layer using a metal silicide process, the metal silicide layer extending from the bit line groove into the substrate; forming a bit line metal layer located on the surface of the bit line groove, the metal silicide layer and the bit line metal layer constituting the bit line.

[0013] In some embodiments, the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged sequentially, the first doped region being in contact with the bit line, and the channel region and the second doped region being located between adjacent word lines. After forming the isolation structure, the method further includes ion doping the first doped region, the channel region, and the second doped region.

[0014] According to some embodiments of this disclosure, another aspect of this disclosure also provides a semiconductor structure, including: a substrate; semiconductor channels located on the substrate and arranged in an array along a first direction and a second direction; bit lines extending along the first direction, located within the substrate, and each bit line electrically connected to a plurality of semiconductor channels arranged along the first direction; word lines extending along the second direction, wrapping around a portion of the side surface of the plurality of semiconductor channels arranged along the second direction, and one word line including two sub-word lines spaced apart along the first direction, the sub-word lines covering the opposite side surfaces of the semiconductor channels along the first direction; and an isolation structure located between adjacent word lines and between adjacent sub-word lines.

[0015] In some embodiments, the word line includes: a word line conductive layer extending along a second direction and spaced apart between the semiconductor channels along a first direction, and the word line conductive layer covering a portion of the semiconductor channel opposite to each other along the first direction; and a word line protective layer located on the top surface of the word line conductive layer; the word line conductive layer and the word line protective layer constitute the word line.

[0016] In some embodiments, the bit line includes: a metal silicide layer located within the substrate and electrically connected to the semiconductor channel; and a bit line metal layer located on the surface of the metal silicide layer.

[0017] In some embodiments, the top surface of the bit line metal layer is flush with the bottom surface of the semiconductor channel in a direction perpendicular to the substrate.

[0018] In some embodiments, the isolation structure includes: a first isolation structure located between adjacent word lines; and a second isolation structure located on the top surface of the first isolation structure.

[0019] In some embodiments, the device further includes: an isolation layer located on the top surface of the bit line and on the bottom surface of the word line, wherein the first isolation structure is an air gap formed by adjacent word lines, the second isolation structure, and the isolation layer.

[0020] In some embodiments, the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged sequentially, the first doped region being in contact with the bit line, the channel region and the second doped region being located between adjacent word lines, and the first doped region, the channel region and the second doped region having the same doped ions.

[0021] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by forming word lines that surround a portion of the side surface of a plurality of semiconductor channels arranged along a second direction, and each word line includes sub-word lines arranged at intervals along a first direction, the sub-word lines cover the opposite side surface of the semiconductor channels along the first direction, thereby forming sub-word lines arranged at intervals along the first direction on the basis of forming word lines, and also forming an isolation structure between adjacent word lines can reduce the parasitic capacitance between adjacent word lines and reduce the interference between adjacent word lines, so as to improve the overall electrical performance of the semiconductor structure. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figures 1 to 26 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0024] As is known from the background technology, as the integration density continues to shrink, the gap between word lines becomes smaller and smaller, making it easier for parasitic capacitance to be generated between adjacent word lines. However, the increase in parasitic capacitance will cause mutual interference between adjacent word lines, thereby reducing the performance of the semiconductor structure.

[0025] This disclosure provides a method for manufacturing a semiconductor structure. By forming sub-word lines at intervals along a first direction during word line formation, the sub-word lines cover the opposite sides of the semiconductor channel along the first direction. After forming the word lines, an isolation structure is formed, and the isolation structure is located between adjacent word lines and between adjacent sub-word lines. This reduces the parasitic capacitance between adjacent word lines and adjacent sub-word lines, thereby improving the electrical performance of the semiconductor structure.

[0026] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0027] Figure 1 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. A substrate 100 is provided; semiconductor channels 110 arranged in an array along a first direction X and a second direction Y are formed on the substrate 100; bit lines 120 extending along the first direction X are formed, the bit lines 120 are located within the substrate 100, and each bit line 120 is electrically connected to a plurality of semiconductor channels 110 arranged along the first direction X; word lines 130 extending along the second direction Y are formed, the word lines 130 surround a portion of the side surfaces of the plurality of semiconductor channels 110 arranged along the second direction Y, and each word line 130 includes two sub-word lines 131 spaced apart along the first direction X, the sub-word lines 131 covering the opposite side surfaces of the semiconductor channels 110 along the first direction X.

[0028] In some embodiments, a dielectric layer 140 is formed around the semiconductor channel 110, the dielectric layer 140 wrapping around the semiconductor channel 110 to prevent the semiconductor channel 110 from directly contacting the word line 130.

[0029] By forming sub-word lines 131 spaced along the first direction X to form word lines 130, and word lines 130 wrapping around part of the sidewall of semiconductor channel 110, the transmission performance of word lines 130 can be guaranteed. Furthermore, an isolation structure will be formed between adjacent word lines 130 and adjacent sub-word lines 131 to reduce the parasitic capacitance between adjacent word lines 130, thereby increasing the electrical performance of the semiconductor structure.

[0030] refer to Figure 2 , Figure 2 for Figure 1 A sectional view along the direction of the dashed line.

[0031] A substrate 100 is provided. In some embodiments, the material of the substrate 100 can be silicon, germanium, or silicon germanide, etc., and the material of the substrate 100 can also be doped. Taking silicon as an example, a trace amount of trivalent element, such as boron, indium, gallium, or aluminum, can be doped into the substrate 100 to form a P-type substrate. Similarly, a trace amount of pentavalent element, such as phosphorus, antimony, or arsenic, can be doped into the substrate 100 to form an N-type substrate. The selection of doping elements for the substrate 100 can be considered according to actual needs and product performance. This disclosure does not limit the material of the substrate 100 or the doped elements.

[0032] refer to Figures 3 to 5 In some embodiments, the method of forming the semiconductor channel 110 includes: forming a mask layer 150, and using the mask layer 150 as a mask patterning substrate 100 to form the semiconductor channel 110.

[0033] For details, please refer to Figure 3 A patterned substrate 100 is used to form initial semiconductor channels 111, which extend along a first direction X and are spaced apart along a second direction Y.

[0034] In some embodiments, the initial semiconductor channel 111 can be formed using a self-aligned double patterning (SADP) process. In other embodiments, the initial semiconductor channel 111 can also be formed using a self-aligned quadruple patterning (SAQP) process. SADP or SAQP techniques can result in a more precise pattern of the formed initial semiconductor channel 111.

[0035] refer to Figure 4 A filling layer 161 is formed, which is located between adjacent initial semiconductor channels 111. The top surface of the filling layer 161 is flush with the top surface of the initial semiconductor channel 111. It should be noted that, here, "flush" can mean that the height difference between the top surfaces is within the allowable error range, and a height difference within the allowable error range can also be considered as flush.

[0036] In some embodiments, the material of the filler layer 161 may be an insulating material such as silicon oxide or silicon nitride.

[0037] In some embodiments, the filling layer 161 also covers the top surface of the initial semiconductor channel 111, and the filling layer 161 located on the top surface of the initial semiconductor channel 111 can be removed by chemical polishing to expose the top surface of the initial semiconductor channel 111.

[0038] refer to Figure 5 A mask layer 150 is formed, and the initial semiconductor channel 111 is patterned using the mask layer 150 as a mask (see reference). Figure 4 To form semiconductor channel 110. In the patterned initial semiconductor channel 111 (reference...) Figure 4 It also includes: a graphical fill layer 161 to remove part of the fill layer 161.

[0039] In some embodiments, an oxide layer may be formed on the top surface of the initial semiconductor channel 111 before the mask layer 150 is formed. By forming the oxide layer, the stress on the initial semiconductor channel 111 can be reduced in subsequent steps.

[0040] In some embodiments, the material of the mask layer 150 may be silicon nitride or similar materials. Silicon nitride is a relatively hard material, so the shape of the mask layer 150 will not be significantly changed in subsequent steps, thereby resulting in a more accurate pattern when patterning is performed using the mask layer 150 as a mask.

[0041] The semiconductor channel 110 includes a first doped region, a channel region, and a second doped region arranged in sequence. Subsequently, the first doped region, the channel region, and the second doped region are doped to form the gate, source, and drain of a transistor.

[0042] refer to Figures 6 to 10 This forms bit line 120.

[0043] For details, please refer to Figure 6 A sidewall layer 170 is formed, covering the sidewalls of the semiconductor channel 110 arranged along the first direction X. In some embodiments, the sidewall layer 170 can be formed by consuming part of the semiconductor channel 110 through thermal oxidation. In other embodiments, other methods can be used, such as deposition followed by etching, to form the sidewall layer 170. Taking the thermal oxidation method for forming the sidewall layer 170 as an example, the sidewall layer 170 formed by thermal oxidation is relatively dense, thereby protecting the semiconductor channel 110 from being affected in the subsequent bit line formation step.

[0044] refer to Figure 7 A bitline groove 180 is formed, which is located within the substrate 100 and connected to the sidewall layer 170. In some embodiments, a portion of the substrate 100 may be etched using wet etching to form the bitline groove 180, which provides a process basis for the subsequent formation of bitlines.

[0045] In some embodiments, the width of the bit line groove 180 along the first direction X can be greater than the spacing between adjacent semiconductor channels 110, thereby requiring less substrate material for metallization during the subsequent formation of the bit line 120, which facilitates the formation of a continuous metallization layer and thus improves the transmission rate of the bit line 120. In other embodiments, the width of the bit line groove 180 along the first direction X can be equal to the spacing between adjacent semiconductor channels 110.

[0046] In some embodiments, the shape of the cross-sectional view of the bit line groove 180 along the first direction X can be an ellipse or a semicircle. In other embodiments, the shape of the cross-sectional view of the bit line groove 180 along the first direction X can also be a rectangle.

[0047] The embodiments disclosed herein do not limit the shape and width of the positioning groove 180, which can be adjusted according to the actual situation.

[0048] refer to Figures 8 to 10 Bit line 120 is formed, and the first doped region is in contact with bit line 120.

[0049] For details, please refer to Figure 8 A metal silicide layer 121 is formed using a metal silicide process, extending from the bit line groove 180 into the substrate 100. Forming the metal silicide layer 121 can reduce the resistance of the bit line 120.

[0050] In some embodiments, a metal silicide layer 121 is formed within the substrate 100 by forming a metal layer on the surface of the substrate 100 and then performing rapid thermal annealing and selective wet etching. The material of the metal layer may be, for example, a metal such as titanium, cobalt, or molybdenum.

[0051] refer to Figure 9 and Figure 10 A bit line metal layer 122 is formed, which is located on the surface of the bit line groove 180. The metal silicide layer 121 and the bit line metal layer 122 constitute the bit line 120. By forming the bit line metal layer 122, the conduction rate of the bit line 120 can be improved, thereby improving the response speed of the semiconductor structure.

[0052] In some embodiments, the bit line metal layer 122 may fill the bit line groove 180. In other embodiments, the bit line metal layer 122 may be formed only on the surface of the bit line groove 180. The embodiments of this disclosure do not limit the bit line metal layer 122 and can be adjusted according to actual needs.

[0053] In some embodiments, an initial groove 190 is formed simultaneously with the bit line 120. The initial groove 190 extends along the second direction Y and is spaced apart along the first direction X between the semiconductor channels 110. The initial groove 190 also exposes the top surface of the bit line 120.

[0054] In some embodiments, the bit line metal layer 122 fills the bit line groove 180, so the initial groove 190 only includes the gap between adjacent semiconductor channels 110. In other embodiments, the bit line metal layer 122 does not fill the bit line groove 180, and the initial groove 190 also includes a portion of the bit line groove 180.

[0055] refer to Figures 11 to 20 Word lines 130 are formed, and the channel region and the second doped region are located between adjacent word lines 130.

[0056] For details, please refer to Figure 11 and Figure 12 An initial isolation layer 201 is formed, which fills the initial groove 190.

[0057] In some embodiments, the initial insulating layer 201 may be made of materials such as silicon oxide, which has good insulating properties and is relatively soft and easy to fill.

[0058] refer to Figure 13 and Figure 14 Using mask layer 150 as the mask, the initial isolation layer 201 is patterned (refer to...). Figure 11 The remaining initial isolation layer 201 is used as isolation layer 200.

[0059] An isolation layer 200 is located on the top surface of the bit line 120, and the height of the isolation layer 200 in the direction perpendicular to the surface of the substrate 100 is less than the depth of the initial groove 190. The remaining initial groove 190 is designated as groove 191, which extends along the second direction Y and is spaced apart along the first direction X between the semiconductor channels 110. By forming the isolation layer 200, electrical connection between the bit line 120 and the subsequently formed word lines can be avoided, and by forming the groove 191, a process basis can be provided for the subsequent formation of word lines.

[0060] While patterning the initial isolation layer 201, a portion of the sidewall layer 170 is also removed to expose a portion of the sidewalls of the semiconductor channel 110, thereby providing a process basis for the subsequent formation of the gate dielectric layer.

[0061] refer to Figure 15 and Figure 16 A gate dielectric layer 210 is formed. In some embodiments, the gate dielectric layer 210 can be formed by thermal oxidation. The gate dielectric layer 210 formed by thermal oxidation has a higher density and better performance. In other embodiments, the sidewall layer is not removed when the initial isolation structure is patterned, so the sidewall layer can also be used as the gate dielectric layer.

[0062] In some embodiments, the gate dielectric layer 210 can serve as the dielectric layer 140 (see reference). Figure 1 Part of ).

[0063] It should be noted that after the various steps of the embodiments of this disclosure, the sidewall layer 170 may have larger lattice defects, resulting in poor performance as a gate dielectric layer. Therefore, the gate dielectric layer 210 can be formed by first removing part of the sidewall layer 170 and then oxidizing the semiconductor channel 110, and the performance of the formed gate dielectric layer 210 is better.

[0064] In this embodiment, the semiconductor channel 110 is oxidized and a portion of the sidewall layer 170 is removed when the sidewall layer 170 is formed. The gate dielectric layer 210 is formed by oxidizing the semiconductor channel 110. Therefore, more space can be provided when word lines are formed subsequently, thereby increasing the spacing between adjacent word lines, reducing the parasitic capacitance between adjacent word lines, and improving the performance of the semiconductor structure.

[0065] refer to Figure 17 and Figure 18 In some embodiments, the method of forming word lines 130 may include: forming word line conductive layers 133, wherein the word line conductive layers 133 extend along a second direction Y and are spaced apart between semiconductor channels 110 along a first direction X, and the word line conductive layers 133 cover the opposite side portions of the semiconductor channels 110 along the first direction X; forming word line protective layers 134, wherein the word line protective layers 134 are located on the top surface of the word line conductive layers 133; the word line conductive layers 133 and the word line protective layers 134 constitute the word lines 130. By forming the word line conductive layers 133, electrical signals can be transmitted; by forming the word line protective layers 134, the word line conductive layers 133 can be protected in subsequent steps, and the stress on the word line conductive layers 133 can be reduced.

[0066] In some embodiments, the word line conductive layer 133 may be made of tungsten, and the word line protective layer 134 may be made of silicon oxide or silicon nitride. In other embodiments, the word line conductive layer 133 may also be a multilayer stacked structure, such as including a polysilicon layer and a word line metal layer.

[0067] In some embodiments, the method of forming the word line conductive layer 133 includes: forming an initial word line conductive layer (not shown in the figure), the initial word line conductive layer filling a portion of the groove 191; and etching back the initial word line conductive layer to form the word line conductive layer 133. By forming the initial word line conductive layer first and then etching back, it is easier to control the height of the formed word line conductive layer 133, thereby adjusting the required height of the word line conductive layer 133 according to the actual situation.

[0068] refer to Figure 19 and Figure 20 The mask layer 150 is thickened to increase its width along the second direction Y. The width of the mask layer 150 can be increased by deposition, thereby providing a process basis for the subsequent formation of adjacent word lines. The spacing between adjacent word lines can be controlled by controlling the width of the mask layer 150.

[0069] refer to Figure 21 and Figure 22 The word line conductive layer 133 and the word line protective layer 134 are patterned using a mask layer 150 to form sub-word lines 131 spaced apart along the first direction X. Sub-word lines 131 located on both sides of the same semiconductor channel 110 constitute a single word line 130. Using the same mask layer 150 to pattern the word line conductive layer 133 and the word line protective layer 134 can reduce the number of mask formations and shorten the semiconductor process time.

[0070] refer to Figures 23 to 26This forms an isolation structure 160, which is located between adjacent word lines 130.

[0071] For details, please refer to Figure 23 and Figure 24 This forms a second initial isolation structure 163. The second initial isolation structure 163 can be made of a material with poor filling ability, so that the gaps between the semiconductor channels 110 are not completely filled when the second initial isolation structure 163 is formed, thereby forming an air gap between adjacent word lines 130, which can reduce the parasitic capacitance between adjacent word lines 130 and thus improve the performance of the semiconductor structure.

[0072] The second initial isolation structure 163, the word line 130, and the isolation layer 200 also form an air gap, which serves as the first isolation structure 164.

[0073] refer to Figure 25 and Figure 26 This forms a second isolation structure 162. In some embodiments, the second initial isolation structure 163 can be graphically represented (see reference). Figure 23 ), to expose the surface of the semiconductor channel 110, with the remaining second initial isolation structure 163 (reference) Figure 23 ) as the second isolation structure 162.

[0074] The filling layer 161, the second isolation structure 162, and the first isolation structure 164 together constitute the isolation structure 160.

[0075] After forming the isolation structure 160, the process further includes ion doping of the first doped region, the channel region, and the second doped region. In some embodiments, the first doped region may be heavily doped first to form a source or drain, the channel region may be lightly doped to form a gate, and the second doped region may be heavily doped to form a source or drain.

[0076] In some embodiments, the top surface of the first doped region is flush with the bottom surface of the word line 130, or the top surface of the first doped region is lower than the bottom surface of the word line 130; the bottom surface of the channel region is lower than the bottom surface of the word line conductive layer 133, and the top surface of the channel region is higher than the top surface of the word line conductive layer 133, or the bottom and top surfaces of the channel region are flush with the bottom and top surfaces of the word line conductive layer 133; the bottom surface of the second doped region is flush with the top surface of the word line conductive layer 133, or the bottom surface of the second doped region is higher than the top surface of the word line conductive layer 133.

[0077] This disclosure provides a method for fabricating a semiconductor structure by forming sub-word lines 131 spaced apart along a first direction X and extending along a second direction Y. The sub-word lines 131 extending in the second direction can realize the function of word lines 130, and by forming an isolation structure 160 including an air gap between word lines 130, the parasitic capacitance between adjacent word lines 130 can be reduced, thereby improving the electrical performance of the semiconductor structure.

[0078] Another embodiment of this disclosure also provides a semiconductor structure, which can be formed by some or all of the above steps. The semiconductor structure provided by another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiments can be referred to the corresponding descriptions of the foregoing embodiments, and will not be repeated below.

[0079] refer to Figure 1 , Figure 25 and Figure 26 This disclosure provides a semiconductor structure comprising: a substrate 100; semiconductor channels 110 located on the substrate 100 and arranged in an array along a first direction X and a second direction Y; bit lines 120 extending along the first direction X and located within the substrate 100, with each bit line 120 electrically connected to a plurality of semiconductor channels 110 arranged along the first direction X; word lines 130 extending along the second direction Y and wrapping around a portion of the side surface of the plurality of semiconductor channels 110 arranged along the second direction Y, and each word line 130 including two sub-word lines 131 spaced apart along the first direction X, the sub-word lines 131 covering opposite side surfaces of the semiconductor channels 110 along the first direction X; and an isolation structure 160 located between adjacent word lines 130 and between adjacent sub-word lines 131.

[0080] A word line 130 is formed by two sub-word lines 131 spaced apart along a first direction, and the sub-word lines 131 extend along a second direction. An isolation structure 160 isolates adjacent word lines 130 and adjacent sub-word lines 131, thereby reducing the parasitic capacitance between adjacent word lines 130 and improving the electrical performance of the semiconductor structure.

[0081] In some embodiments, the word line 130 includes: a word line conductive layer 133 extending along a second direction Y and spaced apart between semiconductor channels 110 along a first direction X, and covering portions of the semiconductor channels 110 opposite each other along the first direction X; and a word line protective layer 134 located on the top surface of the word line conductive layer 133; the word line conductive layer 133 and the word line protective layer 134 constitute the word line 130. The word line conductive layer 133 is used for signal transmission of the word line 130, and the word line protective layer 134 is used to reduce the stress on the word line conductive layer 133 when the semiconductor structure is subjected to stress, thereby protecting the word line conductive layer 133. In other embodiments, the word line may also include only the word line conductive layer.

[0082] In some embodiments, bit line 120 includes: a metal silicide layer 121 located within the substrate 100 and electrically connected to the semiconductor channel 110; and a bit line metal layer 122 located on the surface of the metal silicide layer 121. The metal silicide layer 121 can be used to reduce the contact resistance of bit line 120, thereby improving the electrical performance of the semiconductor structure, and the bit line metal layer 122 can be used to increase the transmission rate of bit line 120, thereby reducing the response time of the semiconductor structure.

[0083] In some embodiments, the top surface of the bit line metal layer 122 is flush with the bottom surface of the semiconductor channel 110 in a direction perpendicular to the substrate 100. It should be noted that this flushing can mean that the top surface of the bit line metal layer 122 is completely flush with the bottom surface of the semiconductor channel 110, or that the height difference between the top surface of the bit line metal layer 122 and the bottom surface of the semiconductor channel 110 is within an allowable error range. By setting the top surface of the bit line metal layer 122 to be flush with the bottom surface of the semiconductor channel 110, the contact area between the bit line 120 and the substrate 100 can be increased, thereby reducing the contact resistance between the bit line 120 and the substrate 100, and thus improving the electrical performance of the semiconductor structure.

[0084] In some embodiments, the isolation structure includes: a first isolation structure 164 located between adjacent word lines 130; and a second isolation structure 162 located on the top surface of the first isolation structure 164. By providing the first isolation structure 164 and the second isolation structure 162, the insulation performance between adjacent word lines 130 can be increased, thereby improving the reliability of the semiconductor structure.

[0085] In some embodiments, the system further includes: an isolation layer 200 located on the top surface of the bit line 120 and the bottom surface of the word line 130; and a first isolation structure 164 forming an air gap between adjacent word lines 130, a second isolation structure 162, and the isolation layer 200. The isolation layer 200 isolates the word line 130 from the bit line 120, preventing direct contact between them. The first isolation structure 164 is an air gap; air has a high dielectric constant, and by providing the first isolation structure 164, the insulation between adjacent word lines 130 can be improved, and the parasitic capacitance between adjacent word lines 130 can be reduced.

[0086] In some embodiments, the semiconductor channel 110 includes a first doped region, a channel region, and a second doped region arranged sequentially. The first doped region is in contact with the bit line 120, and the channel region and the second doped region are located between adjacent word lines 130. The doped ions of the first doped region, the channel region, and the second doped region are the same.

[0087] By doping the semiconductor channel 110 with the same type of ions, a junctionless transistor can be formed. A junctionless transistor is one where the dopant ions in the first doped region, the channel region, and the second doped region are of the same type, for example, both dopant ions are N-type ions. Furthermore, the dopant ions in the first doped region, the channel region, and the second doped region can be the same. Here, "junctionless" refers to the absence of a PN junction; that is, the transistor formed by the semiconductor channel 110 does not have a PN junction. Because the device is a junctionless transistor, it is advantageous to avoid the phenomenon of fabricating ultra-steep PN junctions at the nanoscale using ultra-steep source-drain concentration gradient doping processes. Therefore, it can avoid problems such as threshold voltage drift and increased leakage current caused by abrupt doping changes. It also helps suppress short-channel effects, allowing operation at the nanometer scale, thus contributing to further improvements in the integration density and electrical performance of the semiconductor structure. It is understood that the additional doping here refers to doping performed to ensure that the dopant ion types in the first and second doped regions are different from those in the channel region.

[0088] This disclosure provides a semiconductor structure including sub-word lines 131 spaced apart along a first direction X and extending along a second direction Y. By setting the sub-word lines 131 extending in the second direction, the function of word lines 130 can be realized, and the isolation structure 160 set between word lines 130 can reduce the parasitic capacitance between adjacent word lines 130, thereby improving the electrical performance of the semiconductor structure.

[0089] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; Semiconductor channels are formed on the substrate in an array arranged along a first direction and a second direction; Bit lines are formed extending along the first direction, the bit lines are located within the substrate, and each bit line is electrically connected to a plurality of semiconductor channels arranged along the first direction. A word line is formed extending along the second direction, the word line wraps around a portion of the side surface of a plurality of semiconductor channels arranged along the second direction, and one word line includes two sub-word lines spaced apart along the first direction, the sub-word lines covering the opposite portion of the side surface of the semiconductor channel along the first direction, each of the sub-word lines being located between two adjacent semiconductor channels in the second direction and wrapping around the side surface of the semiconductor channel in the second direction; An isolation structure is formed between adjacent word lines and between adjacent sub-word lines.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The method of forming the word line includes: forming a word line conductive layer, the word line conductive layer extending along a second direction and the word line conductive layer being spaced apart between the semiconductor channels along a first direction, and the word line conductive layer covering a portion of the semiconductor channel opposite to each other along the first direction; A word line protective layer is formed, which is located on the top surface of the word line conductive layer; the word line conductive layer and the word line protective layer constitute the word line.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The method for forming the word line conductive layer includes: A groove is formed, the groove extending along the second direction and the grooves being spaced apart along the first direction between the semiconductor channels; An initial word line conductive layer is formed, wherein the initial word line conductive layer fills a portion of the groove; The initial word line conductive layer is etched back to form the word line conductive layer.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The method of forming the groove includes: forming an initial groove, the initial groove extending along a second direction and the initial grooves being spaced apart between the semiconductor channels along a first direction, the initial groove also exposing the top surface of the bit line; An isolation layer is formed, which is located on the top surface of the bit line, and the height of the isolation layer in the direction perpendicular to the substrate surface is less than the depth of the initial groove, with the remaining initial groove serving as a groove.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The method of forming the semiconductor channel includes: forming a mask layer, and patterning the substrate using the mask layer as a mask to form the semiconductor channel; the method of forming the isolation layer includes: An initial isolation layer is formed, which fills the initial groove; The initial isolation layer is patterned using the mask layer as a mask, and the remaining initial isolation layer is used as the isolation layer.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The method of forming the bit line includes: forming a sidewall layer that covers the sidewalls of the semiconductor channel arranged along the first direction; A positioning groove is formed, the positioning groove being located within the substrate and connected to the sidewall layer; Bit lines are formed, with a portion of the bit lines located within the groove and a portion of the bit lines extending from the groove toward the substrate.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The method for forming the bit line includes: forming a metal silicide layer using a metal silicide process, wherein the metal silicide layer extends from the bit line groove into the substrate; A bit line metal layer is formed, the bit line metal layer is located on the surface of the bit line groove, and the metal silicide layer and the bit line metal layer constitute the bit line.

8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The semiconductor channel includes a first doped region, a channel region, and a second doped region arranged sequentially. The first doped region is in contact with the bit line, and the channel region and the second doped region are located between adjacent word lines. After forming the isolation structure, it further includes: Ion doping is performed on the first doped region, the channel region, and the second doped region.

9. A semiconductor structure, characterized in that, include: Base; A semiconductor channel, the semiconductor channel being located on the substrate, and the semiconductor channel being arranged in an array along a first direction and a second direction; Bit lines, the bit lines extending along a first direction, the bit lines located within the substrate, and each bit line being electrically connected to a plurality of semiconductor channels arranged along the first direction; A word line extends along a second direction and wraps around a portion of the side surface of a plurality of semiconductor channels arranged along the second direction. Each word line includes two sub-word lines spaced apart along a first direction. The sub-word lines cover the opposite side surface of the semiconductor channels along the first direction. Each sub-word line is located between two adjacent semiconductor channels in the second direction and wraps around the side surface of the semiconductor channels in the second direction. An isolation structure is located between adjacent word lines and between adjacent sub-word lines.

10. The semiconductor structure according to claim 9, characterized in that, The word lines include: A word line conductive layer, wherein the word line conductive layer extends along the second direction and is spaced apart between the semiconductor channels along the first direction, and the word line conductive layer covers the opposite side portions of the semiconductor channels along the first direction; A word line protective layer is located on the top surface of the word line conductive layer; the word line conductive layer and the word line protective layer constitute the word line.

11. The semiconductor structure according to claim 9, characterized in that, The bit line includes: a metal silicide layer located within the substrate, and the metal silicide layer being electrically connected to the semiconductor channel; Bit line metal layer, the bit line metal layer being located on the surface of the metal silicide layer.

12. The semiconductor structure according to claim 11, characterized in that, In a direction perpendicular to the substrate, the top surface of the bit line metal layer is flush with the bottom surface of the semiconductor channel.

13. The semiconductor structure according to claim 10, characterized in that, The isolation structure includes: a first isolation structure located between adjacent word lines; The second isolation structure is located on the top surface of the first isolation structure.

14. The semiconductor structure according to claim 13, characterized in that, Also includes: An isolation layer is located on the top surface of the bit line and on the bottom surface of the word line. The first isolation structure is an air gap formed by adjacent word lines, the second isolation structure, and the isolation layer.

15. The semiconductor structure according to claim 9, characterized in that, The semiconductor channel includes a first doped region, a channel region, and a second doped region arranged in sequence. The first doped region is in contact with the bit line. The channel region and the second doped region are located between adjacent word lines, and the doped ions of the first doped region, the channel region, and the second doped region are the same.

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