Semiconductor structure and chip

Abstract

The present disclosure provides a semiconductor structure, comprising: a first active region and a second active region, both extending along a first direction and having a first width along a second direction; a first word line drive transistor group comprising two gate dielectric regions connected to the first active region; a second word line drive transistor group comprising two gate dielectric regions connected to the first active region; a third word line drive transistor group comprising two gate dielectric regions connected to the second active region; and a fourth word line drive transistor group comprising two gate dielectric regions connected to the second active region; wherein each of the gate dielectric regions extends along the second direction and has a second width along the first direction. The embodiments of the present disclosure can improve the layout of the word line drive circuit, and improve the charge transport capability of the word line drive circuit by using the active regions with consistent size and the gate dielectric regions with consistent size.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit manufacturing technology, and more specifically, to a semiconductor structure that can improve the transmission performance of word line driving circuits, and a chip using the semiconductor structure. Background Technology

[0002] Word line driver circuits are crucial components of memory. A typical word line driver circuit comprises multiple word line driver sub-circuits. Within each sub-circuit, a main word line (MWL) drives multiple sub-word lines (SWL) via transistor-based circuitry, thus enabling the transmission of word line signals within the memory. In layout design, circuits connecting the same main word line are usually grouped together, and multiple word line driver sub-circuits are also typically grouped together, placing significant demands on layout design.

[0003] To achieve a centralized layout of word line driver circuits, adjustments are typically made to the wiring and layout to obtain better electrical signal transmission while meeting design specifications. However, the layouts in related technologies all have various problems, such as isolated areas and excessive signal line bends, leading to various performance degradations in electrical signal transmission. Therefore, a layout structure for word line driver circuits with better electrical signal transmission performance is needed.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a semiconductor structure and a chip using the semiconductor structure, which at least to some extent overcomes the problem of poor electrical signal transmission caused by word line driver circuit layout due to limitations and defects in related technologies.

[0006] According to a first aspect of this disclosure, a semiconductor structure is provided, comprising: a first active region extending along a first direction and having a first width in a second direction, the second direction being perpendicular to the first direction; a second active region extending along the first direction and having the first width in the second direction; a first word line driving transistor group formed based on the first active region, including two gate dielectric regions connected to the first active region, one of the gate dielectric regions being connected to a main word line and the other gate dielectric region being connected to a first control signal line; and a second word line driving transistor group formed based on the first active region, including two gate dielectric regions connected to the first active region, one of the gate dielectric regions being connected to a main word line and the other gate dielectric region being connected to a first control signal line; and a second word line driving transistor group formed based on the first active region, including two gate dielectric regions connected to the first active region and the other gate dielectric region being connected to a main word line. A third word line driving transistor group, formed based on the second active region, includes two gate dielectric regions connected to the second active region, one gate dielectric region connected to the main word line, and the other gate dielectric region connected to the third control signal line; a fourth word line driving transistor group, formed based on the second active region, includes two gate dielectric regions connected to the second active region, one gate dielectric region connected to the main word line, and the other gate dielectric region connected to the fourth control signal line; wherein each gate dielectric region extends along the second direction and has a second width in the first direction.

[0007] In an exemplary embodiment of this disclosure, the first word line driving transistor group includes a first transistor and a second transistor, the gate of the first transistor being a first gate dielectric region, the gate of the second transistor being a second gate dielectric region, and the portion of the first active region located between the first gate dielectric region and the second gate dielectric region being the common drain of the first transistor and the second transistor; the second word line driving transistor group includes a third transistor and a fourth transistor, the gate of the third transistor being a third gate dielectric region, the gate of the fourth transistor being a fourth gate dielectric region, and the portion of the first active region located between the third gate dielectric region and the fourth gate dielectric region being the common drain of the third transistor and the fourth transistor. The common drain of the body transistor; the third word line driving transistor group, including a fifth transistor and a sixth transistor, wherein the gate of the fifth transistor is a fifth gate dielectric region, the gate of the sixth transistor is a sixth gate dielectric region, and the portion of the second active region located between the fifth gate dielectric region and the sixth gate dielectric region is the common drain of the fifth transistor and the sixth transistor; the fourth word line driving transistor group, including a seventh transistor and an eighth transistor, wherein the gate of the seventh transistor is a seventh gate dielectric region, the gate of the eighth transistor is an eighth gate dielectric region, and the portion of the second active region located between the seventh gate dielectric region and the eighth gate dielectric region is the common drain of the seventh transistor and the eighth transistor.

[0008] In an exemplary embodiment of this disclosure, a first gate dielectric region, a second gate dielectric region, a third gate dielectric region, and a fourth gate dielectric region are sequentially arranged parallel to each other on the first active region along the first direction, and a fifth gate dielectric region, a sixth gate dielectric region, a seventh gate dielectric region, and an eighth gate dielectric region are sequentially arranged parallel to each other on the second active region along the first direction, and the first gate dielectric region, the fourth gate dielectric region, the fifth gate dielectric region, and the eighth gate dielectric region are connected to the main word line.

[0009] In an exemplary embodiment of this disclosure, the first gate dielectric region and the fifth gate dielectric region are connected, the fourth gate dielectric region and the eighth gate dielectric region are connected, the first gate dielectric region and the fifth gate dielectric region have a first spacing in the first direction, and the fourth gate dielectric region and the eighth gate dielectric region have the first spacing in the first direction.

[0010] In an exemplary embodiment of this disclosure, the second gate dielectric region and the sixth gate dielectric region have the first spacing in the first direction, and the third gate dielectric region and the seventh gate dielectric region have the first spacing in the first direction.

[0011] In an exemplary embodiment of this disclosure, the first gate dielectric region and the fifth gate dielectric region are connected by a first connection structure, the first connection structure extending along a second direction and having a third width in the first direction, the third width being smaller than the second width; the fourth gate dielectric region and the eighth gate dielectric region are connected by a second connection structure, the second connection structure extending along the second direction and having the third width in the first direction.

[0012] In an exemplary embodiment of this disclosure, the first edge of the first connection structure in the first direction is flush with the first edge of the first gate dielectric region in the first direction, and the second edge of the first connection structure in the first direction is flush with the second edge of the fifth gate dielectric region in the first direction; the first edge of the second connection structure in the first direction is flush with the first edge of the fourth gate dielectric region in the first direction, and the second edge of the second connection structure in the first direction is flush with the second edge of the eighth gate dielectric region in the first direction.

[0013] In an exemplary embodiment of this disclosure, the first control signal line and the second control signal line are the same signal line, the third control signal line and the fourth control signal line are the same signal line, the second gate dielectric region is connected to the third gate dielectric region, and the sixth gate dielectric region is connected to the seventh gate dielectric region.

[0014] In an exemplary embodiment of this disclosure, the second gate dielectric region and the third gate dielectric region are connected by a third connection structure, the third connection structure extending along the first direction and located on the side of the first active region away from the second active region in the second direction; the sixth gate dielectric region and the seventh gate dielectric region are connected by a fourth connection structure, the fourth connection structure extending along the first direction and located on the side of the second active region away from the first active region in the second direction.

[0015] In an exemplary embodiment of this disclosure, the third connection structure connects the first end of the second gate dielectric region to the first end of the third gate dielectric region, and the fourth connection structure connects the second end of the sixth gate dielectric region to the second end of the seventh gate dielectric region.

[0016] In an exemplary embodiment of this disclosure, the common drain of the first transistor and the second transistor is connected to the first sub-word line corresponding to the first word line driving transistor group via a first wire, and the common drain of the third transistor and the fourth transistor is connected to the second sub-word line corresponding to the second word line driving transistor group via a second wire. The first wire and the second wire are parallel in the first direction and are located in the same metal layer. The common drain of the fifth transistor and the sixth transistor is connected to the third sub-word line corresponding to the third word line driving transistor group via a third wire, and the common drain of the seventh transistor and the eighth transistor is connected to the fourth sub-word line corresponding to the fourth word line driving transistor group via a fourth wire. The third wire and the fourth wire are parallel in the first direction and are located in the same metal layer.

[0017] In an exemplary embodiment of this disclosure, the first wire is connected to the drain of the first P-type transistor corresponding to the first word line driving transistor group, the second wire is connected to the drain of the second P-type transistor corresponding to the second driving transistor group, the third wire is connected to the drain of the third P-type transistor corresponding to the third driving transistor group, and the fourth wire is connected to the drain of the fourth P-type transistor corresponding to the fourth driving transistor group. The first P-type transistor, the second P-type transistor, the third P-type transistor, and the fourth P-type transistor are all disposed in the first layout region, and the first active region and the second active region are both disposed in the second layout region. The first layout region and the second layout region are arranged side by side in the second direction.

[0018] In an exemplary embodiment of this disclosure, the second gate dielectric region is connected to the fifth wire, the sixth gate dielectric region is connected to the sixth wire, the fifth wire and the sixth wire are parallel in the first direction, and the fifth wire and the sixth wire are located in the same metal layer.

[0019] According to a second aspect of this disclosure, a semiconductor structure is provided for arranging memory word line driving circuits, connecting a main word line and multiple sub-word lines corresponding to multiple word line driving circuits, comprising: a first layout region for arranging multiple P-type transistors corresponding to multiple word line driving circuits, wherein the gate of each P-type transistor is connected to the main word line, the drain of each P-type transistor is connected to a sub-word line of the corresponding word line driving circuit, and the source of each P-type transistor is connected to a power supply voltage; a second layout region comprising multiple semiconductor structures as described in any of the preceding claims, wherein the semiconductor structures in the second layout region share a first active region and a second active region; a third layout region comprising multiple semiconductor structures as described in any of the preceding claims, wherein the semiconductor structures in the third layout region share a first active region and a second active region; the second layout region, the first layout region, and the third layout region are arranged sequentially side by side in a second direction.

[0020] According to a third aspect of this disclosure, a chip is provided, comprising the semiconductor structure described in any of the preceding claims.

[0021] The semiconductor structure provided in this disclosure, by setting four sets of word line driving transistors on two equally wide, straight active regions and setting the gate dielectric regions of the four sets of word line driving transistors to be of equal width, can form a uniform and consistent charge path, control the four sets of word line driving transistors to have the same electrical characteristics, improve the conductivity of the word line driving transistors, and thus improve the electrical signal transmission effect of the word line driving circuit.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] Figure 1 This is a schematic diagram of the semiconductor structure in an exemplary embodiment of this disclosure.

[0025] Figure 2AThis is the layout of the four word line driven transistor groups in this embodiment of the present disclosure.

[0026] Figure 2B One embodiment Figure 2A The circuit corresponding to the layout shown.

[0027] Figure 3 This is a schematic diagram of a semiconductor structure in one embodiment of the present disclosure.

[0028] Figure 4 yes Figure 3 The illustration shows the effect of the embodiment.

[0029] Figure 5 This is a schematic diagram of a semiconductor structure in another embodiment of the present disclosure.

[0030] Figure 6 yes Figure 5 The illustration shows the effect of the embodiment.

[0031] Figure 7 This is a schematic diagram of the overall semiconductor structure in an embodiment of this disclosure.

[0032] Figure 8 This is a schematic diagram of the shallow trench isolation structure corresponding to the semiconductor structure in the embodiments of this disclosure.

[0033] Figure 9 This is a schematic diagram of a semiconductor structure in one embodiment of the present disclosure. Detailed Implementation

[0034] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0035] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0036] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0037] Figure 1 This is a schematic diagram of the semiconductor structure in an exemplary embodiment of this disclosure.

[0038] refer to Figure 1 The semiconductor structure 100 may include:

[0039] The first active region 11 extends along a first direction and has a first width W1 in a second direction, the second direction being perpendicular to the first direction;

[0040] The second active region 12 extends along the first direction and has a first width W1 in the second direction;

[0041] The first word line driving transistor group 21 is formed based on the first active region 11 and includes two gate dielectric regions 30 connected to the first active region 11. One gate dielectric region 30 is connected to the main word line MWL, and the other gate dielectric region 30 is connected to the first control signal line CON1.

[0042] The second word line driving transistor group 22 is formed based on the first active region 11 and includes two gate dielectric regions 30 connected to the first active region 11. One gate dielectric region 30 is connected to the main word line MWL, and the other gate dielectric region 30 is connected to the second control signal line CON2.

[0043] The third word line driving transistor group 23 is formed based on the second active region 12 and includes two gate dielectric regions 30 connected to the second active region 12. One gate dielectric region 30 is connected to the main word line MWL, and the other gate dielectric region 30 is connected to the third control signal line CON3.

[0044] The fourth word line driving transistor group 24 is formed based on the second active region 12 and includes two gate dielectric regions 30 connected to the second active region 12. One gate dielectric region 30 is connected to the main word line MWL, and the other gate dielectric region 30 is connected to the fourth control signal line CON4.

[0045] Each gate dielectric region 30 extends along a second direction and has a second width W2 in a first direction.

[0046] This disclosed embodiment implements four word line driving transistor groups by using two active regions of uniform width, and sets each gate dielectric region in each word line driving transistor group to be a rectangle of the same width. This forms a uniform conductive channel and eliminates islanded areas in the layout, reducing stress in STI (Shallow Trench Isolation) and improving structural stability. It also improves the filling effect of metal wiring, reduces process defect rate, simplifies manufacturing, and increases production efficiency and product yield. Furthermore, it facilitates monitoring and optimization of device performance during WAT (Wafer Acceptable Test).

[0047] Figure 2A and Figure 2B This is a schematic diagram showing the correspondence between the semiconductor structure 100 and the word line driving circuit in an embodiment of this disclosure. Figure 2A This is the layout of the four word line driven transistor groups in this embodiment of the present disclosure. Figure 2B One embodiment Figure 2A The circuit corresponding to the layout shown.

[0048] refer to Figure 2A and Figure 2B In an exemplary embodiment of this disclosure, the first word line driving transistor group 21 includes a first transistor M11 and a second transistor M12. The gate of the first transistor M11 is a first gate dielectric region 31, the gate of the second transistor M12 is a second gate dielectric region 32, and the portion of the first active region 11 located between the first gate dielectric region 31 and the second gate dielectric region 32 is the common drain of the first transistor M11 and the second transistor M12.

[0049] The second word line driving transistor group 22 includes a third transistor M21 and a fourth transistor M22. The gate of the third transistor M21 is the third gate dielectric region 33, and the gate of the fourth transistor M22 is the fourth gate dielectric region 34. The portion of the first active region 11 located between the third gate dielectric region 33 and the fourth gate dielectric region 34 is the common drain of the third transistor M21 and the fourth transistor M22.

[0050] The third word line driving transistor group 23 includes a fifth transistor M31 and a sixth transistor M32. The gate of the fifth transistor M31 is the fifth gate dielectric region 35, and the gate of the sixth transistor M32 is the sixth gate dielectric region 36. The portion of the second active region 12 located between the fifth gate dielectric region 35 and the sixth gate dielectric region 36 is the common drain of the fifth transistor M31 and the sixth transistor M32.

[0051] The fourth word line driving transistor group 24 includes a seventh transistor M41 and an eighth transistor M42. The gate of the seventh transistor M41 is the seventh gate dielectric region 37, and the gate of the eighth transistor M42 is the eighth gate dielectric region 38. The portion of the second active region 12 located between the seventh gate dielectric region 37 and the eighth gate dielectric region 38 is the common drain of the seventh transistor M41 and the eighth transistor M42.

[0052] In an exemplary embodiment of this disclosure, the first gate dielectric region 31, the second gate dielectric region 32, the third gate dielectric region 33, and the fourth gate dielectric region 34 are sequentially arranged parallel to each other on the first active region 11 along a first direction, and the fifth gate dielectric region 35, the sixth gate dielectric region 36, the seventh gate dielectric region 37, and the eighth gate dielectric region 38 are sequentially arranged parallel to each other on the second active region 12 along the first direction. The first gate dielectric region 31, the fourth gate dielectric region 34, the fifth gate dielectric region 35, and the eighth gate dielectric region 38 are connected to the main word line MWL, the second gate dielectric region 32 is connected to the first control signal line CON1, the third gate dielectric region 33 is connected to the second control signal line CON2, the sixth gate dielectric region 36 is connected to the third control signal line CON3, and the seventh gate dielectric region 37 is connected to the fourth control signal line CON4.

[0053] refer to Figure 2B In one embodiment, the first word line driving transistor group 21 further includes a first P-type transistor MP1, the second word line driving transistor group 22 further includes a second P-type transistor MP2, the third word line driving transistor group 23 further includes a third P-type transistor MP3, and the fourth word line driving transistor group 24 further includes a fourth P-type transistor MP4. The source of the first P-type transistor MP1 is connected to the power supply, the gate is connected to the main word line MWL, and the drain is connected to the drain of the first transistor M11, and is also connected to the first sub-word line SWL1; the source of the second P-type transistor MP2 is connected to the power supply, the gate is connected to the main word line MWL, and the drain is connected to the drain of the third transistor M21, and is also connected to the second sub-word line SWL2; the source of the third P-type transistor MP3 is connected to the power supply, the gate is connected to the main word line MWL, and the drain is connected to the drain of the fifth transistor M31, and is also connected to the third sub-word line SWL3; the source of the fourth P-type transistor MP4 is connected to the power supply, the gate is connected to the main word line MWL, and the drain is connected to the drain of the seventh transistor M41, and is also connected to the fourth sub-word line SWL4.

[0054] Although in this disclosure Figure 2B The circuit shown is as Figure 2A The layout shown is from which the original plan was derived, but in other embodiments of this disclosure, Figure 2A The layout shown can also be applied to the layout of other similar circuits or other word line driving circuits to improve the electrical signal transmission effect of centrally located transistors. The layout in the embodiments of this disclosure is not based on... Figure 2B The word line driving circuit shown is limited.

[0055] Figure 3 This is a schematic diagram of a semiconductor structure in one embodiment of the present disclosure.

[0056] refer to Figure 3 In an exemplary embodiment of this disclosure, the first gate dielectric region 31 and the fifth gate dielectric region 35 are connected, the fourth gate dielectric region 34 and the eighth gate dielectric region 38 are connected, the first gate dielectric region 31 and the fifth gate dielectric region 35 have a first spacing D1 in a first direction, and the fourth gate dielectric region 34 and the eighth gate dielectric region 38 have a first spacing D1 in a first direction.

[0057] At the same time, the second gate dielectric region 32 and the sixth gate dielectric region 36 may be provided with a first spacing D1 in the first direction, and the third gate dielectric region 33 and the seventh gate dielectric region 37 may be provided with a first spacing D1 in the first direction.

[0058] In one embodiment, the first gate dielectric region 31 and the fifth gate dielectric region 35 are connected by a first connection structure 41, which extends along a second direction and has a third width W3 in the first direction, the third width W3 being smaller than the second width W2; the fourth gate dielectric region 34 and the eighth gate dielectric region 38 are connected by a second connection structure 42, which extends along a second direction and has a third width W3 in the first direction.

[0059] like Figure 3 As shown, in one embodiment, in order to reduce the increase in load on the conductor caused by excessive routing angle, the first edge of the first connection structure 41 in the first direction (the upper edge in the figure) is flush with the first edge of the first gate dielectric region 31 in the first direction, and the second edge of the first direction (the lower edge in the figure) is flush with the second edge of the fifth gate dielectric region 35 in the first direction; the first edge of the second connection structure 42 in the first direction is flush with the first edge of the fourth gate dielectric region 34 in the first direction, and the second edge of the second direction is flush with the second edge of the eighth gate dielectric region 38 in the first direction.

[0060] Figure 4 yes Figure 3 The illustration shows the effect of the embodiment.

[0061] refer to Figure 4 and Figure 2BIn an exemplary embodiment of this disclosure, the common drain of the first transistor M11 and the second transistor M12 is connected to the first sub-word line SWL1 corresponding to the first word line driving transistor group 21 via a first wire 51; the common drain of the third transistor M21 and the fourth transistor M22 is connected to the second sub-word line SWL2 corresponding to the second word line driving transistor group 22 via a second wire 52; the first wire 51 and the second wire 52 are parallel in a first direction and are located in the same metal layer; the common drain of the fifth transistor M31 and the sixth transistor M32 is connected to the third sub-word line SWL3 corresponding to the third word line driving transistor group 23 via a third wire 53; the common drain of the seventh transistor M41 and the eighth transistor M42 is connected to the fourth sub-word line SWL4 corresponding to the fourth word line driving transistor group 24 via a fourth wire 54; the third wire 53 and the fourth wire 54 are parallel in a first direction and are located in the same metal layer.

[0062] In one embodiment, the first sub-word line SWL1, the second sub-word line SWL2, the third sub-word line SWL3, and the fourth sub-word line SWL4 are disposed in the first layout region 400 and connected to the memory array from the first layout region 400. The first layout region 400 is used to set up the PMOS corresponding to the multiple word line drive transistor groups to achieve centralized layout of the PMOS (see details). Figure 9 ).

[0063] Combination Figure 2B The circuit diagram shows that the first wire 51 is connected to the drain of the first P-type transistor MP1 corresponding to the first word line driving transistor group 21, the second wire 52 is connected to the drain of the second P-type transistor MP2 corresponding to the second driving transistor group 22, the third wire 53 is connected to the drain of the third P-type transistor MP3 corresponding to the third driving transistor group 23, and the fourth wire 54 is connected to the drain of the fourth P-type transistor MP4 corresponding to the fourth driving transistor group 24. The first P-type transistor MP1, the second P-type transistor MP2, the third P-type transistor MP3, and the fourth P-type transistor MP4 are all located in the first layout area 400, and the first active area 11 and the second active area 12 are all located in the second layout area 401. The first layout area 400 and the second layout area 401 are arranged side by side in the second direction.

[0064] Depend on Figure 4 As can be seen from the illustrated embodiment, due to the fact that in Figure 3In the illustrated embodiment, the gate dielectric regions with uniform width are staggered, allowing the sub-word lines SWL1 to SWL4, which connect to the four word line drive transistor groups arranged in a centralized manner, to be routed straight on the same metal layer and connected to the first layout area 400 corresponding to the word line drive circuit. Because the traces are uniform and straight and do not require crossing layers, the layout design complexity of the wiring metal layer (i.e., the M0 layer) is reduced, the load on the conductors is reduced, the conductivity of the conductors is optimized, manufacturing complexity is reduced, and production efficiency is improved.

[0065] Therefore, setting a first spacing can avoid the increase in load caused by the bending and crossing of traces, and further improve the electrical signal transmission effect of the word line drive circuit.

[0066] Figure 5 This is a schematic diagram of a semiconductor structure in another embodiment of the present disclosure.

[0067] refer to Figure 5 In an exemplary embodiment of this disclosure, the first control signal line CON1 and the second control signal line CON2 are the same signal line, the third control signal line CON3 and the fourth control signal line CON4 are the same signal line, the second gate dielectric region 32 and the third gate dielectric region 33 are connected, and the sixth gate dielectric region 36 and the seventh gate dielectric region 37 are connected.

[0068] The second gate dielectric region 32 and the third gate dielectric region 33 are connected by a third connection structure 43, which extends along a first direction and is located on the side of the first active region 11 away from the second active region 12 in a second direction; the sixth gate dielectric region 36 and the seventh gate dielectric region 37 are connected by a fourth connection structure 44, which extends along a first direction and is located on the side of the second active region 12 away from the first active region 11 in a second direction.

[0069] By connecting the gate dielectric regions that share the same control signal lines through the third connection structure 43 and the fourth connection structure 44, the routing of control signal lines can be saved, providing more space for layout. Furthermore, compared to directly connecting the gate dielectric regions using traces, using the larger third connection structure 43 and the fourth connection structure 44 to connect the gate dielectric regions helps to achieve more uniform charge distribution between the gate dielectric regions and enhances charge transfer capability.

[0070] exist Figure 5In the illustrated embodiment, the third connection structure 43 connects the first end of the second gate dielectric region 32 to the first end of the third gate dielectric region 33, and the fourth connection structure 44 connects the second end of the sixth gate dielectric region 36 to the second end of the seventh gate dielectric region 37. By connecting the third connection structure 43 and the fourth connection structure 44 to the corners of each gate dielectric region, the total number of angles of the connected structures can be reduced, thereby reducing the increased load effect caused by excessive trace angles, reducing the difficulty of wire manufacturing, and improving production efficiency.

[0071] In other embodiments of this disclosure, if other layout considerations are taken into account, the third connection structure 43 and the fourth connection structure 44 may be connected to other parts of each gate dielectric region. Those skilled in the art can design the connection positions of each connection structure according to the actual situation, as long as it does not affect the shape of the first active region 11, the second active region 12 and each gate dielectric region.

[0072] Figure 6 yes Figure 5 The illustration shows the effect of the embodiment.

[0073] refer to Figure 6 In an exemplary embodiment of this disclosure, the second gate dielectric region 32 is connected to the fifth wire 55, and the sixth gate dielectric region 36 is connected to the sixth wire 56. The fifth wire 55 and the sixth wire 56 are parallel in a first direction and are located in the same metal layer. The fifth wire 55 is used to connect to the first control signal CON1 (the first control signal CON1 and the second control signal CON2 are the same control signal), and the sixth wire 56 is used to connect to the third control signal CON3 (the third control signal CON3 and the fourth control signal CON4 are the same control signal).

[0074] Depend on Figure 6 It can be seen that by using the third connection structure 43 and the fourth connection structure 44 to connect the gate dielectric regions connected with the same control signal, the wires connecting the control signal can be wired straight on the same metal layer. This not only improves the conductivity of the wires and optimizes the signal transmission effect, but also reduces the layout design complexity of the wiring metal layer (i.e., the M0 layer), reduces manufacturing complexity, and improves production efficiency.

[0075] Furthermore, in one embodiment, when the signal of the main word line MWL also originates from the control signal generation region 500, the first gate dielectric region 31 can be connected to the main word line MWL via the seventh conductor 57, and the fourth gate dielectric region 34 can be connected to the main word line MWL via the eighth conductor 58. Thus, the semiconductor structure provided by this disclosure embodiment allows four word line driving transistor groups connected to the same main word line to achieve straight wiring on the same metal layer during layout, reducing conductor bends, avoiding conductors crossing layers, thereby improving conductor conductivity and enhancing electrical signal transmission performance.

[0076] Figure 7 This is a schematic diagram of the overall semiconductor structure in an embodiment of this disclosure.

[0077] Depend on Figure 7 As can be seen, the semiconductor structure provided in this embodiment has relatively straight and uniform gate dielectric region and active region, and the connection between gate dielectric regions that connect the same signal is realized through multiple uniform connection structures. This can reduce the traces inside the word line driving circuit and make the charge of each gate dielectric region uniform, thereby improving the overall electrical signal transmission effect of the word line driving circuit.

[0078] Figure 8 This is a schematic diagram of the shallow trench isolation structure corresponding to the semiconductor structure in the embodiments of this disclosure.

[0079] refer to Figure 8 Because the active regions are set in a uniform and straight manner, and the active regions (blank areas in the figure) are not connected to each other, the shallow trench isolation structure 800 has a neat and complete layout during layout, and there are no islands (STI islands). This can reduce the stress between the STI and the active regions, and improve the yield and structural stability of the integrated circuit.

[0080] Figure 9 This is a schematic diagram of a semiconductor structure in one embodiment of the present disclosure.

[0081] refer to Figure 9 The semiconductor structure 900 is used to set up memory word line driver circuits, connecting the main word line MWL and multiple sub-word lines SWL corresponding to the multiple word line driver circuits, including:

[0082] The first layout area 901 is used to set multiple P-type transistors MP corresponding to multiple word line driving circuits. The gate of each P-type transistor MP is connected to the main word line MWL, the drain of each P-type transistor MP is connected to the sub-word lines SWL1 to SWL8 of the corresponding word line driving circuit, and the source of each P-type transistor is connected to the power supply voltage.

[0083] The second layout area 902 includes multiple such as Figures 1 to 7In the semiconductor structure 910 of the embodiment shown, the semiconductor structure 910 in the second layout region 902 shares the first active region 91 and the second active region 92.

[0084] The third layout area 903 includes multiple such Figures 1 to 7 In the semiconductor structure 910 of the embodiment shown, the semiconductor structure 910 in the third layout region 903 shares the first active region 93 and the second active region 94.

[0085] The second layout area 902, the first layout area 901, and the third layout area 903 are arranged side by side in the second direction.

[0086] Although Figure 9 It shows Figure 6 or Figure 7 The semiconductor structure shown, but Figures 1-5 The semiconductor structure shown is also Figure 9 Within the protection scope of the illustrated embodiment.

[0087] At the same time, combined Figure 6 The wires shown illustrate all the control signal connections for each semiconductor structure 910, as well as the control signal generation area.

[0088] from Figure 9 As can be seen from the illustrated embodiments, when the semiconductor structure described in the above embodiments is applied to the centralized layout of the word line driving circuit, the resulting word line driving circuit layout not only has uniform and straight active regions and gate dielectric regions, but also straight and uniform traces located on the same metal layer. That is, the wiring in the M0 layer is generally straight, and the traces from the NMOS layout region (second layout region 902, third layout region 903) to the PMOS layout region (first layout region 901) are without bends, which greatly reduces metal conductor layer defects (M0 defects) and improves process stability.

[0089] Meanwhile, because the traces are uniform and straight and do not require crossing layers, the layout design complexity of the wiring metal layer (i.e., the M0 layer) is reduced, the conductivity of the conductors is optimized, the manufacturing complexity is reduced, and the production efficiency is improved.

[0090] According to a third aspect of this disclosure, a chip is provided, comprising the semiconductor structure of any of the preceding claims.

[0091] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0092] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A semiconductor structure, characterized in that, include: A first active region extends along a first direction and has a first width in a second direction, wherein the second direction is perpendicular to the first direction; The second active region extends along the first direction and has the first width in the second direction; The first word line driving transistor group is formed based on the first active region and includes two gate dielectric regions connected to the first active region. One gate dielectric region is connected to the main word line, and the other gate dielectric region is connected to the first control signal line. The second word line driving transistor group is formed based on the first active region and includes two gate dielectric regions connected to the first active region. One of the gate dielectric regions is connected to the main word line, and the other gate dielectric region is connected to the second control signal line. The third word line driving transistor group is formed based on the second active region and includes two gate dielectric regions connected to the second active region. One of the gate dielectric regions is connected to the main word line, and the other gate dielectric region is connected to the third control signal line. The fourth word line driving transistor group is formed based on the second active region and includes two gate dielectric regions connected to the second active region. One gate dielectric region is connected to the main word line, and the other gate dielectric region is connected to the fourth control signal line. Each of the gate dielectric regions extends along the second direction and has a second width in the first direction; the first word line driving transistor group includes a first transistor and a second transistor, the gate of the first transistor is a first gate dielectric region, the gate of the second transistor is a second gate dielectric region, and the portion of the first active region located between the first gate dielectric region and the second gate dielectric region is the common drain of the first transistor and the second transistor; The second word line driving transistor group includes a third transistor and a fourth transistor. The gate of the third transistor is a third gate dielectric region, and the gate of the fourth transistor is a fourth gate dielectric region. The portion of the first active region located between the third gate dielectric region and the fourth gate dielectric region is the common drain of the third transistor and the fourth transistor. The third word line driving transistor group includes a fifth transistor and a sixth transistor. The gate of the fifth transistor is a fifth gate dielectric region, and the gate of the sixth transistor is a sixth gate dielectric region. The portion of the second active region located between the fifth gate dielectric region and the sixth gate dielectric region is the common drain of the fifth transistor and the sixth transistor. The fourth word line driving transistor group includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is a seventh gate dielectric region, and the gate of the eighth transistor is an eighth gate dielectric region. The portion of the second active region located between the seventh gate dielectric region and the eighth gate dielectric region is the common drain of the seventh transistor and the eighth transistor. The first gate dielectric region, the second gate dielectric region, the third gate dielectric region, and the fourth gate dielectric region are sequentially arranged parallel to each other on the first active region along the first direction. The fifth gate dielectric region, the sixth gate dielectric region, the seventh gate dielectric region, and the eighth gate dielectric region are sequentially arranged parallel to each other on the second active region along the first direction. The first gate dielectric region, the fourth gate dielectric region, the fifth gate dielectric region, and the eighth gate dielectric region are connected to the main word line. The first gate dielectric region and the fifth gate dielectric region are connected, the fourth gate dielectric region and the eighth gate dielectric region are connected, the first gate dielectric region and the fifth gate dielectric region have a first spacing in the first direction, the fourth gate dielectric region and the eighth gate dielectric region have the first spacing in the first direction, the second gate dielectric region and the sixth gate dielectric region have the first spacing in the first direction, and the third gate dielectric region and the seventh gate dielectric region have the first spacing in the first direction; the first gate dielectric region and the fifth gate dielectric region are connected by a first connection structure, the first connection structure extends along the second direction and has a third width in the first direction, the third width being smaller than the second width; the fourth gate dielectric region and the eighth gate dielectric region are connected by a second connection structure, the second connection structure extends along the second direction and has the third width in the first direction.

2. The semiconductor structure as described in claim 1, characterized in that, The first edge of the first connection structure in the first direction is flush with the first edge of the first gate dielectric region in the first direction, and the second edge of the first connection structure in the first direction is flush with the second edge of the fifth gate dielectric region in the first direction; the first edge of the second connection structure in the first direction is flush with the first edge of the fourth gate dielectric region in the first direction, and the second edge of the second connection structure in the first direction is flush with the second edge of the eighth gate dielectric region in the first direction.

3. The semiconductor structure as described in claim 1, characterized in that, The first control signal line and the second control signal line are the same signal line, the third control signal line and the fourth control signal line are the same signal line, the second gate dielectric region is connected to the third gate dielectric region, and the sixth gate dielectric region is connected to the seventh gate dielectric region.

4. The semiconductor structure as described in claim 3, characterized in that, The second gate dielectric region and the third gate dielectric region are connected by a third connection structure, which extends along the first direction and is located on the side of the first active region away from the second active region in the second direction; the sixth gate dielectric region and the seventh gate dielectric region are connected by a fourth connection structure, which extends along the first direction and is located on the side of the second active region away from the first active region in the second direction.

5. The semiconductor structure as described in claim 4, characterized in that, The third connection structure connects the first end of the second gate dielectric region to the first end of the third gate dielectric region, and the fourth connection structure connects the second end of the sixth gate dielectric region to the second end of the seventh gate dielectric region.

6. The semiconductor structure as described in claim 1, characterized in that, The common drain of the first transistor and the second transistor is connected to the first sub-word line corresponding to the first word line driving transistor group through a first wire, and the common drain of the third transistor and the fourth transistor is connected to the second sub-word line corresponding to the second word line driving transistor group through a second wire. The first wire and the second wire are parallel in the first direction and are located in the same metal layer. The common drain of the fifth transistor and the sixth transistor is connected to the third sub-word line corresponding to the third word line driving transistor group via a third wire. The common drain of the seventh transistor and the eighth transistor is connected to the fourth sub-word line corresponding to the fourth word line driving transistor group via a fourth wire. The third wire and the fourth wire are parallel in the first direction and are located in the same metal layer.

7. The semiconductor structure as described in claim 6, characterized in that, The first wire is connected to the drain of the first P-type transistor corresponding to the first word line driving transistor group; the second wire is connected to the drain of the second P-type transistor corresponding to the second word line driving transistor group; the third wire is connected to the drain of the third P-type transistor corresponding to the third driving transistor group; and the fourth wire is connected to the drain of the fourth P-type transistor corresponding to the fourth driving transistor group. The first P-type transistor, the second P-type transistor, the third P-type transistor, and the fourth P-type transistor are all disposed in the first layout region. The first active region and the second active region are both disposed in the second layout region. The first layout region and the second layout region are arranged side by side in the second direction.

8. The semiconductor structure as described in claim 1, characterized in that, The second gate dielectric region is connected to the fifth conductor, and the sixth gate dielectric region is connected to the sixth conductor. The fifth conductor and the sixth conductor are parallel in the first direction and are located in the same metal layer.

9. A semiconductor structure, characterized in that, Used to configure memory word line driver circuits, connecting the main word line and multiple sub-word lines corresponding to the multiple word line driver circuits, including: The first layout area is used to set multiple P-type transistors corresponding to multiple word line driving circuits. The gate of each P-type transistor is connected to the main word line, the drain of each P-type transistor is connected to the sub-word line of the corresponding word line driving circuit, and the source of each P-type transistor is connected to the power supply voltage. The second layout region includes a plurality of semiconductor structures as described in any one of claims 1 to 8, wherein the semiconductor structures in the second layout region share a first active region and a second active region; The third layout region includes a plurality of semiconductor structures as described in any one of claims 1 to 8, wherein the semiconductor structures in the third layout region share a first active region and a second active region; The second layout area, the first layout area, and the third layout area are arranged side by side in a second direction.

10. A chip, characterized in that, Including the semiconductor structure as described in any one of claims 1 to 9.

Images