Semiconductor device and method of manufacturing a semiconductor device

Abstract

This application discloses a semiconductor device and a method for manufacturing a semiconductor device. A semiconductor device may include: a first electrode; a second electrode; an insulating layer disposed between the first and second electrodes and including an opening with inclined sidewalls; a variable resistive layer formed in the opening, the variable resistive layer including a first surface and a second surface, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area, the variable resistive layer remaining amorphous during programming operations; and a pad disposed between the variable resistive layer and the insulating layer, and between the variable resistive layer and the first electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0017026, filed with the Korean Intellectual Property Office on February 5, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to an electronic device, and more specifically, to a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0004] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices with memory cells formed in a single layer on a substrate has reached its limit, three-dimensional semiconductor devices in which memory cells are stacked on a substrate are being proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0005] Embodiments of this disclosure provide a semiconductor device having a stable structure and improved properties, as well as a method for manufacturing the semiconductor device.

[0006] According to embodiments of the present disclosure, a semiconductor device may include: a first electrode; a second electrode; an insulating layer disposed between the first electrode and the second electrode and including an opening having inclined sidewalls; a variable resistive layer formed in the opening, the variable resistive layer including a first surface and a second surface, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area, the variable resistive layer remaining amorphous during programming operations; and a pad disposed between the variable resistive layer and the insulating layer and between the variable resistive layer and the first electrode.

[0007] According to embodiments of the present disclosure, a semiconductor device may include: a first electrode; a second electrode; a first insulating layer disposed between the first electrode and the second electrode and including a first opening having a first inclined sidewall; a second insulating layer disposed between the first insulating layer and the second electrode and including a second opening having a second inclined sidewall; a variable resistor layer including a first portion formed in the first opening and a second portion formed in the second opening, the first portion having a first sidewall slope and the second portion having a second sidewall slope different from the first sidewall slope, the variable resistor layer remaining amorphous during programming operations; and a pad disposed between the variable resistor layer and the first and second insulating layers.

[0008] According to embodiments of the present disclosure, a method of manufacturing a semiconductor device may include: forming a first electrode; forming an insulating layer on the first electrode; forming an opening through the insulating layer and having inclined sidewalls; forming a pad on the sidewalls and lower surface of the opening; forming a variable resistance layer in the opening in which the pad is formed; and forming a second electrode on the variable resistance layer, wherein the variable resistance layer includes a first surface and a second surface, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area, and the variable resistance layer remains amorphous during programming operations.

[0009] According to embodiments of the present disclosure, a method of manufacturing a semiconductor device may include: forming a first electrode; forming a first insulating layer on the first electrode; forming a second insulating layer on the first insulating layer, the second insulating layer having an etching rate different from that of the first insulating layer; forming a second opening through the second insulating layer and having a second inclined sidewall; forming a first opening through the first insulating layer and having a first inclined sidewall; forming a pad in the first opening and the second opening; forming a variable resistance layer including a first portion formed in the first opening and a second portion formed in the second opening, the first portion having a first sidewall slope and the second portion having a second sidewall slope different from the first sidewall slope, the variable resistance layer remaining amorphous during programming operations; and forming a second electrode on the variable resistance layer.

[0010] It can improve the integration density of semiconductor devices. In addition, it can provide semiconductor devices with stable structures and improved reliability. Attached Figure Description

[0011] Figure 1A and Figure 1B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2A and Figure 2B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 3A and Figure 3B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 4 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 5A , Figure 5B , Figure 5C and Figure 5D This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 6A , Figure 6B , Figure 6C and Figure 6D This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 7A , Figure 7B , Figure 7C and Figure 7D This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 8 This is an example of a configuration diagram of a microprocessor implementing a storage device according to an embodiment of the present disclosure.

[0019] Figure 9 This is an example of a configuration diagram of a processor implementing a storage device according to an embodiment of the present disclosure.

[0020] Figure 10 This is an example of a configuration diagram of a system implementing a storage device according to an embodiment of the present disclosure.

[0021] Figure 11 This is an example of a configuration diagram of a memory system that implements a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0022] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are for the purpose of describing embodiments based on the concepts disclosed herein. Embodiments based on the concepts disclosed herein may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0023] Figure 1A and Figure 1B These are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0024] Reference Figure 1A and Figure 1BThe semiconductor device may include a first electrode 11, a second electrode 12, an insulating layer 13, a pad 14, and a variable resistor layer 15. The first electrode 11 may be part of a word line or a bit line, or may be electrically connected to a word line or bit line. The first electrode 11 may include a conductive material, such as polysilicon or a metal. As one embodiment, the first electrode 11 may include polysilicon, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), silicon tantalum nitride (TaSiN), aluminum tantalum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pd), platinum (Pt), molybdenum (Mo), or ruthenium (Ru), and may include combinations thereof.

[0025] The second electrode 12 may be part of a bit line or word line, or may be electrically connected to a bit line or word line. For example, when the first electrode 11 is electrically connected to a word line, the second electrode 12 may be electrically connected to a bit line. The second electrode 12 may include a conductive material, such as polysilicon or metal. As one embodiment, the second electrode 12 may include polysilicon, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), silicon tantalum nitride (TaSiN), aluminum tantalum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pd), platinum (Pt), molybdenum (Mo), or ruthenium (Ru), and may include combinations thereof.

[0026] An insulating layer 13 may be disposed between the first electrode 11 and the second electrode 12. The insulating layer 13 may include an opening OP extending from the first electrode 11 through the insulating layer 13 to the second electrode 12. The opening OP may be aperture-shaped and may have a planar shape such as circular, elliptical, or polygonal. The cross-section of the opening OP may have an asymmetrical structure. The opening OP may have sloping sidewalls. As one embodiment, the width of the opening OP in contact with the first electrode 11 may be different from the width of the opening OP in contact with the second electrode 12. For example, the width of the opening OP in contact with the second electrode 12 may be greater than the width of the opening OP in contact with the first electrode 11.

[0027] The insulating layer 13 can insulate the first electrode 11 and the second electrode 12 from each other. The insulating layer 13 may include insulating materials such as oxides, silicon oxides, nitrides, and silicon nitrides. The insulating layer 13 may be a single layer or multiple layers.

[0028] The pad 14 can be disposed between the variable resistance layer 15 and the insulating layer 13, and between the variable resistance layer 15 and the first electrode 11. In one embodiment, the pad 14 can be disposed between the variable resistance layer 15 and the insulating layer 13, and can extend between the variable resistance layer 15 and the first electrode 11. The pad 14 can have a cup shape surrounding the lower surface of the variable resistance layer 15. The cross-section of the pad 14 can be U-shaped or V-shaped.

[0029] The pad 14 may have a substantially uniform thickness or may have a different thickness depending on the location. As one embodiment, the pad 14 may have a substantially uniform thickness at the lower surface and sidewalls of the opening OP. For example, when the pad 14 includes a first portion enclosing the sidewall 15_SW of the variable resistor layer 15 and a second portion extending from the lower surface of the variable resistor layer 15 to the upper surface of the first electrode 11, the pad 14 may have the first portion in a first direction (e.g., Figure 1A The first thickness in the horizontal direction and having a second portion in the second direction (e.g., Figure 1A A second thickness in the vertical direction (of the first and second thicknesses) such that the difference between the first and second thicknesses is equal to or less than 1%, 3%, or 5% of a given value (e.g., the average of the first and second thicknesses). As one embodiment, the pad 14 may have a thicker thickness at the lower surface of the opening OP than it does on the sidewalls. As one embodiment, the pad 14 may have a substantially uniform thickness at the lower surface of the opening OP, and may have a thickness different from that at the sidewalls. The pad 14 may have a thickness of 1 to 20 angstroms between the variable resistance layer 15 and the first electrode 11. The pad 14 may comprise nitride or silicon nitride.

[0030] A variable resistor layer 15 can be formed in the opening OP. The cross-section of the variable resistor layer 15 can have an asymmetrical structure. The variable resistor layer 15 can have sidewalls 15_SW, and the sidewalls 15_SW can have a slope of a predetermined angle θ. The slopes of the sidewalls 15_SW can be substantially uniform or locally different.

[0031] The variable resistive layer 15 may include a first surface 15_S1 facing the first electrode 11 and a second surface 15_S2 facing the second electrode 12. The area of ​​the first surface 15_S1 and the area of ​​the second surface 15_S2 may differ depending on the slope of the sidewall 15_SW. As one embodiment, the area of ​​the second surface 15_S2 may be larger than the area of ​​the first surface 15_S1.

[0032] The first surface 15_S1 can contact the pad 14, and the second surface 15_S2 can contact the second electrode 12. Therefore, the area of ​​the first surface 15_S1 can be the first contact area AR1 between the variable resistive layer 15 and the pad 14, and the area of ​​the second surface 15_S2 can be the second contact area AR2 between the variable resistive layer 15 and the second electrode 12.

[0033] Due to the asymmetric structure of the variable resistor layer 15, the first contact area AR1 can differ from the second contact area AR2. Furthermore, the difference between the first contact area AR1 and the second contact area AR2 can increase or decrease depending on the slope of the sidewall 15_SW. When the slope of the sidewall 15_SW is large, the difference between the first contact area AR1 and the second contact area AR2 can be relatively small. When the slope of the sidewall 15_SW is relatively small, the difference between the first contact area AR1 and the second contact area AR2 can be relatively large. Therefore, the difference between the first contact area AR1 and the second contact area AR2 can be adjusted by adjusting the slope of the sidewall 15_SW.

[0034] The variable resistance layer 15 may include a resistive material and may have the property of reversibly changing between different resistance states depending on the applied voltage or current.

[0035] As one implementation, the variable resistance layer 15 may comprise a transition metal oxide or a metal oxide such as a perovskite material. Therefore, data can be stored in the memory cell by creating or eliminating electrical paths in the variable resistance layer 15.

[0036] In one implementation, the variable resistance layer 15 may have an MTJ (magnetic tunnel junction) structure and may include a magnetization pinned layer, a magnetization free layer, and a tunnel barrier layer disposed therebetween. For example, the magnetization pinned layer and the magnetization free layer may comprise magnetic materials, while the tunnel barrier layer may comprise oxides such as magnesium (Mg), aluminum (Al), zinc (Zn), and titanium (Ti). Here, the magnetization direction of the magnetization free layer can be changed by the spin moment of electrons in the applied current. Therefore, data can be stored in the memory cell based on the change in the magnetization direction of the magnetization free layer relative to the magnetization direction of the magnetization pinned layer.

[0037] In one embodiment, the variable resistance layer 15 may include a phase change material and may include chalcogenides. The variable resistance layer 15 may include chalcogenide glass or chalcogenide alloys, etc. The variable resistance layer 15 may include silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), bismuth (Bi), indium (In), tin (Sn), or selenium (Se), and may include combinations thereof. In one embodiment, the variable resistance layer 15 may be Ge-Sb-Te (GST), and may be Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4, or Ge1Sb4Te7, etc. The variable resistance layer 15 can change its phase state according to a programming operation. In one embodiment, the variable resistance layer 15 may have a low-resistance crystalline state through a set operation. In one embodiment, the variable resistance layer 15 may have a high-resistance amorphous state through a reset operation. Therefore, data can be stored in a memory cell by using the resistance difference according to the phase state of the variable resistance layer 15.

[0038] In one embodiment, the variable resistance layer 15 may include a variable resistance material in which resistance changes without a phase transition, and may include a chalcogenide material. The variable resistance layer 15 may include germanium (Ge), antimony (Sb), tellurium (Te), arsenic (As), selenium (Se), silicon (Si), indium (In), tin (Sn), sulfur (S), or gallium (Ga), or combinations thereof. The variable resistance layer 15 may include a chalcogenide that remains amorphous. The variable resistance layer 15 may be amorphous and may not change to a crystalline state during programming operations. Therefore, the threshold voltage of the memory cell can be changed according to the programming voltage applied to the memory cell, and the memory cell can be programmed into at least two states. In one embodiment, when a negative programming voltage is applied to the memory cell, the variable resistance layer 15 may have a high-resistance amorphous state, and the memory cell may have a relatively high threshold voltage. In another embodiment, when a positive programming voltage is applied to the memory cell, the variable resistance layer 15 may have a low-resistance amorphous state, and the memory cell may have a relatively low threshold voltage. Therefore, data can be stored in the storage cells by utilizing the difference in threshold voltage between the storage cells.

[0039] According to the structure described above, the first electrode 11, the second electrode 12, the pad 14, and the variable resistance layer 15 can constitute a memory cell. During programming operations, current can flow through the pad 14, and data can be stored in the memory cell by performing programming operations.

[0040] Furthermore, due to the sloping sidewalls, the variable resistance layer 15 can have an asymmetric structure. Therefore, during programming operations, current paths can be locally formed in the pad 14 and the variable resistance layer 15. Consequently, the width of the threshold voltage variation can be increased, and read window margin can be ensured. For example, the width of the threshold voltage variation can correspond to the difference between a relatively high threshold voltage and a relatively low threshold voltage associated with a high-resistance amorphous state and a low-resistance amorphous state, respectively, and the variation width can be increased in a memory cell including the variable resistance layer 15 and the pad 14 according to an embodiment of the present disclosure compared to a conventional memory cell.

[0041] For reference, Figure 1A and Figure 1B The illustrated embodiment describes a case where the variable resistance layer 15 has an asymmetric structure; however, the first electrode 11 or the second electrode 12 can also have an asymmetric structure. In this case, a memory cell in which the contact area between the first electrode 11 and the variable resistance layer 15 and the contact area between the second electrode 12 and the variable resistance layer 15 are different from each other can be achieved by adjusting the shape or sidewall slope of the first electrode 11 or the second electrode 12.

[0042] Figure 2A and Figure 2B These are diagrams illustrating the structure of semiconductor devices according to embodiments of the present disclosure. For the sake of brevity, content repeated in the preceding description may be omitted.

[0043] Reference Figure 2A and Figure 2B The semiconductor device may include a first electrode 21, a second electrode 22, an insulating layer 23, a pad 24, and a variable resistor layer 25. The insulating layer 23 may include a first insulating layer 23A and a second insulating layer 23B. The first insulating layer 23A may be disposed between the first electrode 21 and the second electrode 22. The second insulating layer 23B may be disposed between the first insulating layer 23A and the second electrode 22. The first insulating layer 23A and the second insulating layer 23B may include materials with different etching rates. As one embodiment, the first insulating layer 23A may include a nitride or silicon nitride, while the second insulating layer 23B may include an oxide or silicon oxide.

[0044] The opening OP may include a first opening OP1 passing through the first insulating layer 23A and a second opening OP2 passing through the second insulating layer 23B. The first sidewall of the first opening OP1 (e.g., a first inclined sidewall) and the second sidewall of the second opening OP2 (e.g., a second inclined sidewall) may have substantially the same slope or different slopes. The sidewall slope of the first opening OP1 may be adjusted according to the etching rate of the first insulating layer 23A, while the sidewall slope of the second opening OP2 may be adjusted according to the etching rate of the second insulating layer 23B. In one embodiment, the sidewall slope of the second opening OP2 may be greater than the sidewall slope of the first opening OP1.

[0045] A pad 24 may be located within an opening OP, and a variable resistance layer 25 may be located within the pad 24. The variable resistance layer 25 may include a first portion 25_P1 formed in a first opening OP1 and a second portion 25_P2 formed in a second opening OP2. The first portion 25_P1 may include a first sidewall 25P1_SW having a first sidewall slope (e.g., a first angle θ1), and the second portion 25_P2 may include a second sidewall 25P2_SW having a second sidewall slope (e.g., a second angle θ2). The first angle θ1 and the second angle θ2 may be substantially the same or different. As one embodiment, the second sidewall slope of the second sidewall 25P2_SW may be greater than the first sidewall slope of the first sidewall 25P1_SW.

[0046] According to the structure described above, the slope of the first sidewall 25P1_SW can correspond to the sidewall slope of the first opening OP1, and the slope of the second sidewall 25P2_SW can correspond to the sidewall slope of the second opening OP2. Therefore, the sidewall slope of the variable resistance layer 25 can be adjusted according to the configuration of the insulating layer 23. The sidewall slope of the variable resistance layer 25 can be partially adjusted according to the etching rate of the multiple layers included in the insulating layer 23.

[0047] Figure 3A and Figure 3B These are diagrams illustrating the structure of semiconductor devices according to embodiments of the present disclosure. For the sake of brevity, content repeated in the preceding description may be omitted.

[0048] Reference Figure 3A and Figure 3BThe semiconductor device may include a first electrode 31, a second electrode 32, an insulating layer 33, a pad 34, and a variable resistive layer 35. The pad 34 may be located within the insulating layer 33, and the variable resistive layer 35 may be located within the pad 34. The pad 34 may have multiple portions of different thicknesses. The first thickness 34_T1 of the first portion of the pad 34 adjacent to the first electrode 31 and the second thickness 34_T2 of the second portion of the pad 34 adjacent to the second electrode 32 may be different. As one embodiment, the second thickness 34_T2 may be thicker than the first thickness 34_T1.

[0049] The pad 34 may include a first sidewall 34_SW1 in contact with the variable resistor layer 35 and a second sidewall 34_SW2 in contact with the insulating layer 33. The first sidewall 34_SW1 may have a slope of a first angle θ1, and the second sidewall 34_SW2 may have a slope of a second angle θ2. The first sidewall 34_SW1 and the second sidewall 34_SW2 may have different slopes. As one embodiment, the first angle θ1 may be greater than the second angle θ2.

[0050] The sidewall of the variable resistance layer 35 may have a slope corresponding to the first sidewall 34_SW1, and the sidewall 33_SW of the insulating layer 33 may have a slope corresponding to the second sidewall 34_SW2. Therefore, the slope of the sidewall 33_SW of the insulating layer 33 may be different from the slope of the sidewall 35_SW of the variable resistance layer 35. The slope of the sidewall 35_SW of the variable resistance layer 35 may be greater than the slope of the sidewall 33_SW of the insulating layer 33.

[0051] According to the structure described above, the slope of the sidewall 35_SW of the variable resistor layer 35 can be adjusted according to the thickness of the pad 34. Therefore, the first area of ​​the overlapping region between the bottom surface of the variable resistor layer 35 and the first electrode 31 and the second area of ​​the overlapping region between the top surface of the variable resistor layer 35 and the second electrode 32 can be adjusted by adjusting the thickness of the pad 34. For example, when viewed from above, the first area can be set within the second area.

[0052] Figure 4 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. For the sake of brevity, content repeated in the preceding description may be omitted.

[0053] Reference Figure 4 The semiconductor device may include a first electrode 41, a second electrode 42, an insulating layer 43, a pad pattern 44, and a variable resistance layer 45. The pad pattern 44 may be formed as a sidewall surrounding the variable resistance layer 45, and the variable resistance layer 45 may pass through the pad pattern 44 and contact the first electrode 41.

[0054] Due to the sloping sidewalls, the variable resistance layer 45 can have an asymmetric structure. The insulating layer 43 can be formed from a single layer or from multiple layers with different etching rates. The pad pattern 44 can have a substantially uniform thickness or can have locally different thicknesses.

[0055] Figure 5A , Figure 5B , Figure 5C and Figure 5D This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. For the sake of brevity, content repeated in the preceding description may be omitted.

[0056] Reference Figure 5A A first electrode 51 is formed. In one embodiment, a plurality of first electrodes 51 may be formed, each first electrode 51 extending parallel in a specific direction. A gap-filling layer (not shown) may be filled between the first electrodes 51. The gap-filling layer may include insulating materials such as oxides, nitrides, and air gaps.

[0057] Subsequently, an insulating layer 53 is formed on the first electrode 51. Then, an opening OP is formed through the insulating layer 53. The insulating layer 53 can be etched such that each opening OP has a sloped sidewall OP_SW. Each opening OP can expose the first electrode 51.

[0058] Reference Figure 5B A liner layer 54 is formed. The liner layer 54 can be formed on the sidewalls and lower surface of the opening OP, and can further be formed on the upper surface of the insulating layer 53. As one embodiment, the liner layer 54 can be deposited along the inner surface of the opening OP and the upper surface of the insulating layer 53.

[0059] The padding layer 54 can be formed to have a substantially uniform thickness. Alternatively, the padding layer 54 can be formed to have locally varying thicknesses. As one embodiment, the padding layer 54 can be formed to have a substantially uniform thickness on the surface of the first electrode 51 exposed through the opening OP. The padding layer 54 can be formed to have a greater thickness on the surface of the first electrode 51 compared to that on the sidewalls of the insulating layer 53. On the sidewalls of the insulating layer 53, the padding layer 54 can be formed to have a substantially uniform thickness or to increase in thickness upwards. The padding layer 54 can be formed to have a substantially uniform thickness on the upper surface of the insulating layer 53. The padding layer 54 can be formed to have a greater thickness on the upper surface of the insulating layer 53 than on the sidewalls of the insulating layer 53. The padding layer 54 can be formed to have a thickness of 1 to 20 angstroms on the lower surface of the opening OP. For example, the padding layer 54 can be formed on the lower surface of the opening OP (corresponding to...) Figure 5A On the exposed surface of the first electrode 51 Figure 5B It has a thickness of 1 to 20 angstroms in the vertical direction.

[0060] Subsequently, a variable resistance material layer 55 is formed. The variable resistance material layer 55 can be deposited on the pad layer 54. Thus, the variable resistance material layer 55 can be formed to fill the interior of the opening OP in which the pad layer 54 is formed. The variable resistance material layer 55 can also be formed on the upper surface of the insulating layer 53.

[0061] Reference Figure 5C A variable resistance layer 55A is formed. As one embodiment, the variable resistance layer 55A can be formed by planarizing the variable resistance material layer 55 until the surface of the insulating layer 53 or the pad layer 54 is exposed. The variable resistance material layer 55 can be planarized using a chemical mechanical polishing (CMP) method. As one embodiment, the variable resistance layer 55A can be formed by etching the variable resistance material layer 55 using an etch-back method. When forming the variable resistance layer 55A, the pad layer 54 can also be planarized or etched, and pad 54A can be formed. The pads 54A formed in each opening OP can be separated from each other. In this case, the pads 54A of adjacent memory cells can be separated from each other. Alternatively, the pad layer 54 can remain on the upper surface of the insulating layer 53. In this case, adjacent memory cells can share the pad layer 54.

[0062] The variable resistance layers 55A can be located separately in the opening OP and can be separated from each other. Each variable resistance layer 55A can have sloping sidewalls. The sidewall slope of the variable resistance layer 55A can reflect the sidewall slope of the insulating layer 53 or the sidewall slope of the pad 54A.

[0063] Reference Figure 5D A second electrode 52 is formed on the variable resistance layer 55A. The second electrode 52 may extend parallel to the first electrode 51 in a direction intersecting the first electrode 51.

[0064] Based on the above references Figures 5A to 5D The described manufacturing method allows for the formation of a variable resistance layer 55A with sloping sidewalls by utilizing the sidewall slope of the insulating layer 53. Furthermore, memory cells can be formed, each including a variable resistance layer 55A with sloping sidewalls. Each variable resistance layer 55A may include a first surface facing the first electrode 51 and a second surface facing the second electrode 52. The area of ​​the second surface may differ from the area of ​​the first surface. The area of ​​the second surface may be larger than the area of ​​the first surface. The variable resistance layer 55A can remain in an amorphous state during programming operations.

[0065] Figure 6A , Figure 6B , Figure 6C and Figure 6DThis is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. For the sake of brevity, content repeated in the preceding description may be omitted.

[0066] Reference Figure 6A A first electrode 61 is formed. Subsequently, an insulating layer 63 is formed on the first electrode 61. The insulating layer 63 may have a multilayer structure. In one embodiment, after forming the first insulating layer 63A on the first electrode 61, a second insulating layer 63B is formed on the first insulating layer 63A. The second insulating layer 63B may include a material with an etching rate different from that of the first insulating layer 63A.

[0067] Subsequently, an opening OP is formed through the insulating layer 63. In one embodiment, a second opening OP2 is formed through the second insulating layer 63B and exposes the first insulating layer 63A. Then, a first opening OP1 is formed through the first insulating layer 63A and exposes the first electrode 61. Thus, an opening OP, including both the first opening OP1 and the second opening OP2, can be formed.

[0068] The first opening OP1 may have a first sidewall OP1_SW, and the second opening OP2 may have a second sidewall OP2_SW. The first sidewall OP1_SW and the second sidewall OP2_SW may have different slopes. The difference in slope between the first sidewall OP1_SW and the second sidewall OP2_SW may be caused by the difference in etching rate between the first insulating layer 63A and the second insulating layer 63B. As one embodiment, the etching rate of the second insulating layer 63B may be greater than the etching rate of the first insulating layer 63A, and the slope of the second sidewall OP2_SW may be greater than the slope of the first sidewall OP1_SW.

[0069] Reference Figure 6B Subsequently, a liner layer 64 is formed. The liner layer 64 can be formed on the sidewalls and lower surface of the opening OP, and can further be formed on the upper surface of the second insulating layer 63B. As one embodiment, the liner layer 64 can be deposited along the inner surface of the first opening OP1, the inner surface of the second opening OP2, and the upper surface of the second insulating layer 63B. The liner layer 64 can be formed to have a substantially uniform thickness. Alternatively, the liner layer 64 can be formed to have locally varying thicknesses.

[0070] Subsequently, a variable resistance material layer 65 is formed. The variable resistance material layer 65 can be formed in the first opening OP1 and the second opening OP2 in which the pad layer 64 is formed. The variable resistance material layer 65 can also be formed on the upper surface of the second insulating layer 63B.

[0071] Reference Figure 6CA variable resistance layer 65A is formed. The variable resistance layer 65A can be formed by planarizing or etching the variable resistance material layer 65. Each variable resistance layer 65A may include a first portion 65A_P1 located in the first opening OP1 and a second portion 65A_P2 located in the second opening OP2. The sidewalls of the first portion 65A_P1 and the second portion 65A_P2 may have different slopes. The sidewall slope of the first portion 65A_P1 may reflect the sidewall slope of the first insulating layer 63A. The sidewall slope of the second portion 65A_P2 may reflect the sidewall slope of the second insulating layer 63B. When forming the variable resistance layer 65A, the pad layer 64 may also be planarized or etched, and a pad 64A may be formed.

[0072] Reference Figure 6D A second electrode 62 is formed on the variable resistance layer 65A.

[0073] Based on the above references Figures 6A to 6D The described manufacturing method allows for the local adjustment of the slope of the variable resistance layer 65A by using the etching rate difference between the first insulating layer 63A and the second insulating layer 63B.

[0074] Figure 7A , Figure 7B , Figure 7C and Figure 7D This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. For the sake of brevity, content repeated in the preceding description may be omitted.

[0075] Reference Figure 7A A first electrode 71 is formed. Subsequently, an insulating layer 73 is formed on the first electrode 71. The insulating layer 73 may have a single-layer or multi-layer structure. Then, an opening OP is formed through the insulating layer 73. Each opening OP may have an inclined sidewall. Subsequently, a liner layer 74 is formed. The liner layer 74 may be formed on the sidewalls and lower surface of each opening OP, and may further be formed on the upper surface of the insulating layer 73.

[0076] Reference Figure 7B The pad layer 74 is etched. Thus, pads 74A can be formed on the sidewalls of the opening OP. Each pad 74A may have a substantially uniform thickness or may have locally varying thicknesses. As one embodiment, the pad layer 74 can be etched using an etch-back method. The portion of the pad layer 74 formed on the lower surface of the opening OP can be etched, exposing the first electrode 71. Furthermore, the portion of the pad layer 74 formed on the upper surface of the insulating layer 73 can be etched. The upper surface of the insulating layer 73 can be exposed, or the pad layer 74 can be partially retained on the upper surface of the insulating layer 73. For reference, some of the pad layer 74 may remain on the lower surface of the opening OP.

[0077] Reference Figure 7C A variable resistance material layer 75 is formed. The variable resistance material layer 75 can be formed in the opening OP in which the pad 74A is formed. The variable resistance material layer 75 can also be formed on the upper surface of the insulating layer 73.

[0078] Reference Figure 7D A variable resistance layer 75A is formed. The variable resistance layer 75A can be formed by planarizing or etching the variable resistance material layer 75. Each variable resistance layer 75A may have inclined sidewalls. Subsequently, a second electrode 72 is formed on the variable resistance layer 75A.

[0079] Based on the above references Figures 7A to 7D The described manufacturing method involves forming a variable resistance material layer 75 after etching the pad layer 74. The shape or thickness of the pad 74A can be adjusted by etching the pad layer 74, thereby adjusting the sidewall slope of the variable resistance layer 75A.

[0080] The memory circuits or semiconductor devices described above can be used in various devices or systems. Figure 8 , Figure 9 , Figure 10 and Figure 11 Examples of apparatuses or systems that can implement the above-described embodiments of a memory circuit or semiconductor device are shown.

[0081] Figure 8 This is an example of a configuration diagram of a microprocessor implementing a storage device according to an embodiment of the present disclosure.

[0082] Reference Figure 8 The microprocessor 1000 can control and adjust a series of processes, including receiving data from various external devices, processing data, and sending the processing results to the external devices. It may include a memory 1010, an arithmetic unit 1020, and a controller 1030. The microprocessor 1000 can be various data processing devices, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), or an application processor.

[0083] The memory 1010 may be a processor register or a register, etc., and may store data in the microprocessor 1000. It may include various registers, such as data registers, address registers, and floating-point registers. The memory 1010 may temporarily store addresses at which data for performing operations in the arithmetic unit 1020, the data of the results of the operations, and the data used for execution are stored.

[0084] The memory 1010 may include one or more embodiments of the semiconductor device described above. For example, the memory 1010 may include one or more memory elements. A memory element may include: a first electrode; a second electrode; an insulating layer disposed between the first and second electrodes and including an opening with sloping sidewalls; a variable resistive layer formed in the opening, the variable resistive layer including a first surface and a second surface and remaining amorphous during programming operations, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area; and a pad disposed between the variable resistive layer and the insulating layer, and between the variable resistive layer and the first electrode. Therefore, the reliability of the memory 1010 can be improved, and the manufacturing process can be improved. As a result, the operating characteristics of the microprocessor 1000 can be improved.

[0085] The arithmetic unit 1020 can perform various arithmetic or logical operations based on the results obtained by decoding instructions from the controller 1030. The arithmetic unit 1020 may include one or more arithmetic logic units (ALUs).

[0086] The controller 1030 can receive signals from external devices such as the memory 1010, the arithmetic unit 1020 and the microprocessor 1000, perform instruction extraction or decoding and control of signal input / output of the microprocessor 1000, and perform processing instructed by the program.

[0087] In addition to the memory 1010, the microprocessor 1000 according to this embodiment may also include a cache memory 1040 capable of temporarily storing data input from an external device or data to be output to an external device. In this case, the cache memory 1040 can exchange data with the memory 1010, the arithmetic unit 1020, and the controller 1030 via the bus interface 1050.

[0088] Figure 9 This is an example of a configuration diagram of a processor implementing a storage device according to an embodiment of the present disclosure.

[0089] Reference Figure 9 In addition to the functions of the microprocessor described above, processor 1100 may also include various functions to improve performance and achieve versatility. Processor 1100 may include a core 1110 serving as the microprocessor, a cache memory 1120 for temporary data storage, and a bus interface 1130 for transferring data between internal and external devices. Processor 1100 may include various system-on-a-chip (SoCs), such as multi-core processors, graphics processing units (GPUs), and application processors (APs).

[0090] The core part 1110 of this embodiment may be a part for performing arithmetic and logical operations on data input from an external device, and may include a memory 1111, an arithmetic unit 1112, and a controller 1113. The memory 1111, the arithmetic unit 1112, and the controller 1113 may be substantially the same as the memory 1010, the arithmetic unit 1020, and the controller 1030 described above.

[0091] Cache memory 1120 temporarily stores data to compensate for the data processing speed difference between the high-speed core unit 1110 and the low-speed external device. Cache memory 1120 may include a primary storage unit 1121 and a secondary storage unit 1122, and may include a tertiary storage unit 1123 when high capacity is required. Cache memory 1120 may include more storage units as needed. That is, the number of storage units included in cache memory 1120 may vary depending on the design. Here, the processing speeds used for storing and identifying data in the primary, secondary, and tertiary storage units 1121, 1122, and 1123 may be the same or different. When the processing speeds of each storage unit are different, the primary storage unit may be the fastest. One or more of the primary storage unit 1121, secondary storage unit 1122, and tertiary storage unit 1123 of cache memory 1120 may include one or more embodiments of the aforementioned semiconductor device. For example, cache memory 1120 may include one or more embodiments of the aforementioned semiconductor device. For example, cache memory 1120 may include one or more memory elements. The memory element may include: a first electrode; a second electrode; an insulating layer disposed between the first and second electrodes and including an opening with sloping sidewalls; a variable resistive layer formed in the opening, the variable resistive layer including a first surface and a second surface and remaining amorphous during programming operations, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area; and a pad disposed between the variable resistive layer and the insulating layer, and between the variable resistive layer and the first electrode. Therefore, the reliability of the cache memory 1120 can be improved, and the manufacturing process can be improved. As a result, the operating characteristics of the processor 1100 can be improved.

[0092] This embodiment illustrates a case where all three level-one, level-two, and level-three storage units 1121, 1122, and 1123 are configured within the cache memory 1120. However, some or all of the three level-one, level-two, and level-three storage units 1121, 1122, and 1123 can be configured within the core unit 1110 to compensate for the processing speed differences between the core unit 1110 and external devices.

[0093] The bus interface 1130 connects the core unit 1110, the cache memory 1120, and external devices to efficiently transmit data.

[0094] The processor 1100 according to this embodiment may include a plurality of cores 1110, and the plurality of cores 1110 may share a cache memory 1120. The plurality of cores 1110 and the cache memory 1120 may be directly connected to each other or connected to each other via a bus interface 1130. All of the plurality of cores 1110 may be configured in the same way as the cores described above. The memory in each of the plurality of cores 1110 may be configured to share memory with memory outside the core 1110 via the bus interface 1130.

[0095] The processor 1100 according to this embodiment may include an embedded memory 1140 for storing data, a communication module 1150 for transmitting and receiving data with external devices in a wired or wireless manner, a memory controller 1160 for driving external storage devices, and a media processor 1170 for processing data processed by the processor 1100 and data input from external input devices and outputting the processed data to external interface devices. Furthermore, the processor 1100 may also include multiple modules and devices. In this case, multiple added modules can exchange data with the core unit 1110 and the cache memory 1120 via the bus interface 1130.

[0096] Here, the embedded memory 1140 may include non-volatile memory and volatile memory. Volatile memory may include dynamic random access memory (DRAM), mobile DRAM, static random access memory (SRAM), and memory that performs similar functions. Non-volatile memory may include read-only memory (ROM), NOR flash memory, NAND flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), spin-transfer torque random access memory (STTMRAM), magnetic random access memory (MRAM), and memory that performs similar functions.

[0097] Communication module 1150 may include modules capable of connecting to wired networks, modules capable of connecting to wireless networks, and both. Wired network modules may include local area networks (LANs), universal serial buses (USB), Ethernet, or power line communication (PLCs), serving as various devices for sending and receiving data via transmission lines. Wireless network modules may include Infrared Data Association (IrDA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), wireless LANs, Zigbee, ubiquitous sensor networks (USN), Bluetooth, radio frequency identification (RFID), Long Term Evolution (LTE), Near Field Communication (NFC), Wireless Broadband Internet (WIBRO), High-Speed ​​Downlink Packet Access (HSDPA), Wideband CDMA (WCDMA), and Ultra Wideband (UWB), serving as various devices for sending and receiving data without transmission lines.

[0098] The memory controller 1160 is used to process and manage data transferred between the processor 1100 and external storage devices operating according to different communication standards. The memory controller 1160 may include various memory controllers, such as controllers for Integrated Device Electronics (IDE), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Redundant Array of Independent Disks (RAID), Solid State Drives (SSD), External SATA (eSATA), PCMCIA, Universal Serial Bus (USB), Secure Digital (SD) cards, Mini Secure Digital (mSD) cards, Micro Secure Digital (microSD) cards, Secure Digital High Capacity (SDHC) cards, Memory Stick cards, Smart Media (SM) cards, Multimedia Cards (MMC), Embedded MMC (eMMC), and Compact Flash (CF) cards.

[0099] The media processor 1170 can process data processed by the processor 1100 and data input from external input devices as images, voice, and other formats, and can output data to external interface devices. The media processor 1170 may include a graphics processing unit (GPU), a digital signal processor (DSP), a high-definition audio (HD Audio) controller, and a high-definition multimedia interface (HDMI) controller, etc.

[0100] Figure 10 This is an example of a configuration diagram of a system implementing a storage device according to an embodiment of the present disclosure.

[0101] Reference Figure 10System 1200 is a data processing device that can perform a series of operations on data, including input, processing, output, communication, and storage. System 1200 may include a processor 1210, a main storage device 1220, an auxiliary storage device 1230, and an interface device 1240. System 1200 in this embodiment can be various electronic systems operating using a processor, such as computers, servers, personal digital assistants (PDAs), portable computers, network tablets, cordless phones, mobile phones, smartphones, digital music players, portable multimedia players (PMPs), cameras, global positioning systems (GPS), video cameras, recorders, telematics, audiovisual systems, or smart TVs.

[0102] Processor 1210 can control the analysis of input commands, the calculation and comparison of data stored in system 1200, and other processing. Processor 1210 can be substantially the same as the microprocessor 1000 or processor 1100 described above.

[0103] Main storage device 1220 is a storage space capable of moving, storing, and running program code or data from auxiliary storage device 1230 during program execution, and retaining the stored contents even when power is off. Auxiliary storage device 1230 refers to a storage device used to store program code or data. Auxiliary storage device 1230 is slower than main storage device 1220, but can store a large amount of data. Main storage device 1220 or auxiliary storage device 1230 may include one or more embodiments of the electronic device described above. For example, main storage device 1220 or auxiliary storage device 1230 may include one or more memory elements. A memory element may include: a first electrode; a second electrode; an insulating layer disposed between the first electrode and the second electrode and including an opening with inclined sidewalls; a variable resistance layer formed in the opening, the variable resistance layer including a first surface and a second surface and remaining amorphous during programming operations, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area; and a pad disposed between the variable resistance layer and the insulating layer and between the variable resistance layer and the first electrode. Therefore, the reliability of the main storage device 1220 or the auxiliary storage device 1230 can be improved, and the manufacturing process can be improved. As a result, the operating characteristics of the system 1200 can be improved.

[0104] In addition, the main storage device 1220 or the auxiliary storage device 1230 may include, for example: Figure 11 The memory system 1300 shown may include the semiconductor device of the above embodiment, or may not include the semiconductor device of the above embodiment.

[0105] The interface device 1240 can be used to exchange instructions and data between the system 1200 and external devices in this embodiment. The interface device 1240 can be a keypad, keyboard, mouse, speaker, microphone, display, various human-machine interface devices (HID), and communication devices, etc. The communication device can be basically the same as the communication module 1150 described above.

[0106] Figure 11 This is an example of a configuration diagram of a memory system that implements a memory device according to an embodiment of the present disclosure.

[0107] Reference Figure 11 The memory system 1300 may include a memory 1310 configured for storing data and having non-volatile characteristics, a controller 1320 for controlling the memory 1310, an interface 1330 for connecting to an external device, and a buffer memory 1340 for temporarily storing data so as to efficiently transfer data between the interface 1330 and the memory 1310 for input / output. The memory system 1300 may simply refer to a memory for storing data, and further, may refer to a data storage device for long-term storage of stored data. The memory system 1300 may be disk-based, such as a hard disk drive (HDD), optical disc read-only memory (CDROM), digital versatile disk (DVD), and solid-state drive (SSD), and card-based, such as a universal serial bus (USB) memory, secure digital card (SD), mini secure digital card (mSD), micro secure digital card (microSD), secure digital high capacity (SDHC) card, memory stick card, smart media (SM) card, multimedia card (MMC), embedded MMC (eMMC), and compact flash memory (CF) card.

[0108] Memory 1310 or buffer memory 1340 may include one or more embodiments of the semiconductor device described above. For example, memory 1310 or buffer memory 1340 may include one or more memory elements. A memory element may include: a first electrode; a second electrode; an insulating layer disposed between the first and second electrodes and including an opening with sloping sidewalls; a variable resistive layer formed in the opening, the variable resistive layer including a first surface and a second surface and remaining amorphous during programming operations, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area; and a pad disposed between the variable resistive layer and the insulating layer, and between the variable resistive layer and the first electrode. Therefore, the reliability of memory 1310 or buffer memory 1340 can be improved, and the manufacturing process can be improved. As a result, the operating characteristics of memory system 1300 can be improved.

[0109] The memory 1310 or buffer memory 1340 may also include various volatile or non-volatile memories, supplemented by semiconductor devices including those of the above embodiments or those without the above embodiments.

[0110] The controller 1320 can control the data exchange between the memory 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321, which performs operations such as processing commands input from outside the memory system 1300 through the interface 1330.

[0111] Interface 1330 is used to exchange instructions and data between memory system 1300 and external devices. When memory system 1300 is card-type or disk-type, interface 1330 can be compatible with interfaces used in card-type or disk-type devices, or interfaces used in devices similar to these. Interface 1330 can be compatible with one or more interfaces of different types.

Claims

1. A semiconductor device, comprising: First electrode; Second electrode; An insulating layer is disposed between the first electrode and the second electrode and includes an opening with inclined sidewalls; A variable resistance layer is formed in the opening, the variable resistance layer including a first surface and a second surface, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area, the variable resistance layer remaining amorphous during programming operation; as well as A pad is placed between the variable resistance layer and the insulating layer, and between the variable resistance layer and the first electrode. The insulating layer includes: A first insulating layer is disposed between the first electrode and the second electrode, and A second insulating layer is disposed between the first insulating layer and the second electrode, and The slope of the inclined sidewall changes at the boundary between the first insulating layer and the second insulating layer.

2. The semiconductor device of claim 1, wherein, The second area is larger than the first area.

3. The semiconductor device as claimed in claim 1, wherein, The liner has a thickness of 1 to 20 angstroms between the variable resistance layer and the first electrode.

4. The semiconductor device of claim 1, wherein, During the programming operation, current flows through the pad.

5. The semiconductor device as claimed in claim 1, wherein, The first insulating layer includes a first opening having a first sidewall with a first slope, and The second insulating layer includes a second opening having a second sidewall with a second slope different from the first slope.

6. The semiconductor device of claim 1, wherein, The first portion of the pad adjacent to the first electrode has a first thickness, and the second portion of the pad adjacent to the second electrode has a second thickness different from the first thickness.

7. The semiconductor device of claim 1, wherein, The first portion of the pad adjacent to the first electrode has a first thickness, and the second portion of the pad adjacent to the second electrode has a second thickness that is thicker than the first thickness.

8. A semiconductor device, comprising: First electrode; Second electrode; A first insulating layer is disposed between the first electrode and the second electrode and includes a first opening having a first inclined sidewall; A second insulating layer is disposed between the first insulating layer and the second electrode and includes a second opening having a second inclined sidewall; A variable resistance layer includes a first portion formed in a first opening and a second portion formed in a second opening, the first portion having a first sidewall slope, and the second portion having a second sidewall slope different from the first sidewall slope, the variable resistance layer remaining amorphous during programming operations; and A pad is placed between the variable resistance layer and the first and second insulating layers. The boundary between the first inclined sidewall and the second inclined sidewall is located at the boundary between the first insulating layer and the second insulating layer.

9. The semiconductor device of claim 8, wherein, The pad extends between the variable resistance layer and the first electrode.

10. The semiconductor device of claim 9, wherein, The liner has a thickness of 1 to 20 angstroms between the variable resistance layer and the first electrode.

11. The semiconductor device of claim 8, wherein, The variable resistance layer includes a first surface facing the first electrode and having a first area, and a second surface facing the second electrode and having a second area different from the first area.

12. The semiconductor device of claim 11, wherein, The second area is larger than the first area.

13. The semiconductor device of claim 8, wherein, During the programming operation, current flows through the pad.

14. The semiconductor device of claim 8, wherein, The first portion of the pad adjacent to the first electrode has a first thickness, and the second portion of the pad adjacent to the second electrode has a second thickness different from the first thickness.

15. The semiconductor device of claim 8, wherein, The first portion of the pad adjacent to the first electrode has a first thickness, and the second portion of the pad adjacent to the second electrode has a second thickness that is thicker than the first thickness.

16. A method for manufacturing a semiconductor device, the method comprising: Form the first electrode; An insulating layer is formed on the first electrode; An opening is formed through the insulating layer and has sloping sidewalls; A liner is formed on the sidewalls and lower surface of the opening; A variable resistance layer is formed in the opening in which the liner is formed; as well as A second electrode is formed on the variable resistance layer. The variable resistance layer includes a first surface and a second surface. The first surface faces the first electrode and has a first area, while the second surface faces the second electrode and has a second area different from the first area. The variable resistance layer remains in an amorphous state during programming operations. The insulating layer includes: A first insulating layer is disposed between the first electrode and the second electrode, and A second insulating layer is disposed between the first insulating layer and the second electrode, and The slope of the inclined sidewall changes at the boundary between the first insulating layer and the second insulating layer.

17. The method of claim 16, wherein, The second area is larger than the first area.

18. The method of claim 16, wherein, Forming the liner includes forming the liner such that the liner has a thickness of 1 to 20 angstroms at the lower surface of the opening.

19. The method of claim 16, wherein, During the programming operation, current flows through the pad.

20. The method of claim 16, wherein, Forming the insulating layer includes: The first insulating layer is formed on the first electrode; and A second insulating layer is formed on the first insulating layer, and the etching rate of the second insulating layer is different from that of the first insulating layer.

21. The method of claim 20, wherein, Forming the opening includes: Forming a second opening through the second insulating layer and having a second sidewall with a second slope; and A first opening is formed through the first insulating layer and has a first sidewall having a first slope different from the second slope.

22. The method of claim 16, wherein, Forming the liner includes depositing the liner such that a first portion of the liner adjacent to the first electrode and a second portion of the liner adjacent to the second electrode have different thicknesses.

23. A method for manufacturing a semiconductor device, the method comprising: Form the first electrode; A first insulating layer is formed on the first electrode; A second insulating layer is formed on the first insulating layer, wherein the etching rate of the second insulating layer is different from the etching rate of the first insulating layer; A second opening is formed through the second insulating layer and has a second inclined sidewall; A first opening is formed through the first insulating layer and has a first inclined sidewall; A liner is formed in the first opening and the second opening; A variable resistance layer is formed, the variable resistance layer including a first portion formed in the first opening and a second portion formed in the second opening, the first portion having a first sidewall slope, and the second portion having a second sidewall slope different from the first sidewall slope, the variable resistance layer remaining amorphous during programming operations; as well as A second electrode is formed on the variable resistance layer. The boundary between the first inclined sidewall and the second inclined sidewall is located at the boundary between the first insulating layer and the second insulating layer.

24. The method of claim 23, wherein, Forming the liner includes forming the liner on the lower surface of the first opening, the first inclined sidewall of the first opening, and the second inclined sidewall of the second opening.

25. The method of claim 24, wherein, Forming the liner includes forming the liner such that the liner has a thickness of 1 to 20 angstroms between the variable resistance layer and the first electrode.

26. The method of claim 23, wherein, Forming the first opening includes etching the first insulating layer such that the slope of the first inclined sidewall of the first opening is different from the slope of the second inclined sidewall of the second opening.

27. The method of claim 23, wherein, The variable resistance layer includes a first surface facing the first electrode and having a first area, and a second surface facing the second electrode and having a second area different from the first area.

28. The method of claim 27, wherein, The second area is larger than the first area.

29. The method of claim 23, wherein, During the programming operation, current flows through the pad.

30. The method of claim 23, wherein, Forming the liner includes depositing the liner such that a first portion of the liner adjacent to the first electrode and a second portion of the liner adjacent to the second electrode have different thicknesses.

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