A chip packaging structure, an atomizer and an electronic atomization device

Abstract

The application provides a chip packaging structure, an atomizer and an electronic atomization device. The chip packaging structure comprises a packaging body, a chip and a first conductive layer. The chip is located in the packaging body. The first conductive layer is located in the packaging body and on one side of the chip. The first conductive layer is electrically connected with the chip to serve as an electrode plate of an extended capacitor electrically connected with the chip. The extended capacitor is used to expand the capacitance of the built-in capacitor of the chip, thereby effectively resisting interference signals and improving the working stability of the chip.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and in particular to a chip packaging structure, an atomizer, and an electronic atomization device. Background Technology

[0002] Due to material limitations, the capacitor capacity inside the chip die is relatively small. In some extreme cases, the chip may be unable to effectively resist interference signals due to insufficient internal capacitance, resulting in poor chip stability. Summary of the Invention

[0003] This application provides a chip packaging structure, an atomizer, and an electronic atomization device to solve the problems of poor anti-interference ability and poor working stability caused by the small capacitance of the chip.

[0004] To address the aforementioned issues, the first technical solution provided in this application is: to provide a chip packaging structure, comprising: a package body, a chip, and a first conductive layer; the chip is located within the package body; the first conductive layer is located within the package body and on one side of the chip; wherein the first conductive layer is electrically connected to the chip to serve as an electrode plate for expanding capacitance electrically connected to the chip, and the expanding capacitance is used to expand the capacitance of the chip's built-in capacitor.

[0005] In one embodiment, the chip has an atomizer anti-counterfeiting circuit, which includes a first built-in capacitor module and a second built-in capacitor module; the first built-in capacitor module and the second built-in capacitor module are coupled to each other to form the built-in capacitor of the chip; one of the first built-in capacitor module and the second built-in capacitor module is electrically connected to the first conductive layer.

[0006] In one embodiment, the chip package structure further includes a first pin and a second pin; both the first pin and the second pin are partially located within the package and partially exposed outside the package; the chip includes connection terminals, the connection terminals including a first communication connection terminal, a second communication connection terminal, a first power supply connection terminal VDD, and a second power supply connection terminal VSS; the first communication connection terminal is electrically connected to the first pin; the second communication connection terminal is electrically connected to the second pin; one of the first power supply connection terminal and the second power supply connection terminal is electrically connected to the first conductive layer.

[0007] In one embodiment, the first power supply connection terminal is electrically connected to the first conductive layer, and the first built-in capacitor module forms the amplification capacitor with the first conductive layer through the substrate of the chip; the amplification capacitor is connected in parallel with the built-in capacitor; or the second power supply connection terminal is electrically connected to the first conductive layer, and the second built-in capacitor module forms the amplification capacitor with the first conductive layer through the substrate of the chip; the amplification capacitor is connected in parallel with the built-in capacitor.

[0008] In one embodiment, the first conductive layer is disposed on the side of the chip substrate away from the connection terminal, and an insulating dielectric layer is disposed between the first conductive layer and the chip substrate.

[0009] In one embodiment, the first conductive layer, the first pin, and the second pin are arranged at intervals on the same layer.

[0010] In one embodiment, the chip package structure further includes a first pin, a second pin, and a second conductive layer; both the first pin and the second pin are partially located within the package and partially exposed outside the package; the chip includes connection terminals, which include a first communication connection terminal, a second communication connection terminal, a first power supply connection terminal VDD, and a second power supply connection terminal VSS; the first communication connection terminal is electrically connected to the first pin; the second communication connection terminal is electrically connected to the second pin; the first conductive layer and the second conductive layer are spaced apart on the substrate of the chip on the side away from the connection terminals, and an insulating dielectric layer is disposed between the first conductive layer and the second conductive layer; the first conductive layer and the second conductive layer form the expansion capacitance through the insulating dielectric layer; one of the first power supply connection terminal and the second power supply connection terminal is electrically connected to the first conductive layer, and the other is electrically connected to the second conductive layer.

[0011] In one embodiment, the chip package structure further includes a connection layer; the first conductive layer, the connection layer, the first pin, and the second pin are disposed on the same layer at intervals on the side of the insulating dielectric layer near the chip, and the second conductive layer is disposed on the side of the insulating dielectric layer away from the chip; the connection layer is electrically connected to the second conductive layer through conductive vias on the insulating dielectric layer.

[0012] In one embodiment, the first conductive layer, the first pin, and the second pin are disposed on the same layer at intervals on the side of the insulating dielectric layer closer to the chip, and the second conductive layer is disposed on the side of the insulating dielectric layer away from the chip; the insulating dielectric layer has a first opening at the gap between the first conductive layer, the first pin, and the second pin to expose part of the second conductive layer.

[0013] In one embodiment, the first conductive layer is disposed on the side of the insulating dielectric layer close to the chip; the second conductive layer, the first pin, and the second pin are disposed on the side of the insulating dielectric layer away from the chip at intervals in the same layer; the first conductive layer and the insulating dielectric layer each have a second opening at the corresponding locations of the second conductive layer, the first pin, and the second pin, so that the second conductive layer, the first pin, and the second pin are all partially exposed.

[0014] In one embodiment, both the first conductive layer and the second conductive layer are metal sheets or metal films, and the areas of both the first conductive layer and the second conductive layer are larger than the area of ​​the chip.

[0015] In one embodiment, the first conductive layer is a metal sheet or a metal film, and the area of ​​the first conductive layer is larger than the area of ​​the chip.

[0016] To solve the above problems, the second technical solution provided in this application is: to provide an atomizer, including: an atomizing core and a chip packaging structure, wherein the chip packaging structure is electrically connected to the atomizing core, and the chip packaging structure is any of the chip packaging structures described above.

[0017] In one embodiment, the chip packaging structure is connected in parallel with the heating element of the atomizing core.

[0018] To address the aforementioned issues, the third technical solution provided in this application is: to provide an electronic atomizing device, comprising an atomizer and a battery rod, wherein the atomizer is any of the atomizers described above; the battery rod is used to control the operation of the atomizing core and to communicate with the chip in the chip packaging structure.

[0019] Unlike existing technologies, the chip packaging structure, atomizer, and electronic atomizing device provided in this application include a package body, a chip, and a first conductive layer; the chip is located inside the package body; the first conductive layer is located inside the package body and is located on one side of the chip; wherein, the first conductive layer is electrically connected to the chip to serve as an electrode plate for expanding the capacitance electrically connected to the chip, and the expanding capacitance is used to expand the capacitance of the chip's built-in capacitor, thereby effectively resisting interference signals and improving the chip's working stability. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0021] Figure 1This is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of a chip packaging structure provided in another embodiment of this application;

[0023] Figure 3 This is a schematic diagram of the internal functional modules of a chip provided in an embodiment of this application;

[0024] Figure 4 for Figure 2 A top view of the provided chip package structure;

[0025] Figure 5 This is a schematic diagram of a chip packaging structure provided in another embodiment of this application;

[0026] Figure 6 A schematic diagram of a chip packaging structure provided in another embodiment of this application.

[0027] Figure 7 for Figure 6 A top view of the provided chip package structure;

[0028] Figure 8 This is a schematic diagram of the structure of an electronic atomizing device provided in an embodiment of this application;

[0029] Figure 9 for Figure 8 A schematic diagram showing the connection between the atomizer core and the chip packaging structure of the provided atomizer. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0031] To prevent the mixing of battery mods and atomizers from different brands, most existing atomizers incorporate anti-counterfeiting features. This is achieved by embedding an anti-counterfeiting chip within the atomizer. When the atomizer is connected to the battery mod, it communicates with the battery mod via the anti-counterfeiting chip to determine compatibility. The anti-counterfeiting chip can have various packaging structures, with the one directly connected in parallel with the heating wire inside the atomizer offering the most competitive overall cost. The anti-counterfeiting chip and the two contacts of the atomizer are assembled using a press-fit method, resulting in a PCB-free, capacitor-free, and simple assembly process. Specifically, the reason why the anti-counterfeiting chip connected in parallel with the heating wire doesn't require a capacitor is that the chip's internal die contains a built-in capacitor, enabling single-wire communication. However, due to limitations in the internal wafer material, the capacitance of the anti-counterfeiting chip connected in parallel with the heating wire is relatively small. While the anti-counterfeiting chip can communicate normally under normal conditions, in some extreme interference environments, the insufficient internal capacitance of the die may prevent it from effectively resisting interference signals, leading to poor chip stability.

[0032] In view of this, the applicant, through research, discovered that simply adding a capacitor to the power port of the anti-counterfeiting chip's die to expand its capacitance can solve the problem of insufficient anti-interference capability and improve the chip's operational stability. Specifically, this application adds a structural capacitor to the anti-counterfeiting chip's die, which is co-encapsulated with the die within the package. Introducing at least one electrode of the structural capacitor to the power port of the anti-counterfeiting chip increases its capacitance and improves its operational stability. Furthermore, adding this capacitor structure not only improves the reliability of the anti-counterfeiting chip but also does not involve changes to the external interface of the package, resulting in high structural compatibility, while the increased cost is negligible.

[0033] Specifically, this application provides a chip packaging structure including a package body, a chip, and a first conductive layer. Both the chip and the first conductive layer are located within the package body, with the first conductive layer situated on one side of the chip. Specifically, the first conductive layer is electrically connected to the chip to serve as an electrode plate for expanding capacitance, which is used to increase the capacitance of the chip's built-in capacitor. That is, in the chip packaging structure of this application, a capacitor is disposed on the outside of the chip, which expands the chip's capacitance, and the chip and capacitor are packaged together within the package body. This chip packaging structure not only expands the chip's capacitance but also effectively resists interference signals, improving the chip's operational stability.

[0034] It should be noted that a parallel-plate capacitor consists of two closely spaced parallel metal plates with an insulating material (dielectric) sandwiched between them. The working principle of a parallel-plate capacitor is that when the parallel plates are connected to a voltage source, charges move due to the electric field in a conductor. However, in a parallel-plate capacitor, the insulating material (dielectric) between the plates impedes this movement, causing the charges to accumulate and store on the conductor, forming a capacitor.

[0035] The chip packaging structure of this application will be described in detail below with reference to specific embodiments.

[0036] Please see Figure 1 , Figure 1 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application. The chip packaging structure includes a package body 11, a chip 10, and a first conductive layer 13. The chip 10 is disposed within the package body 11, and the first conductive layer 13 is located within the package body 11 and on one side of the chip 10. Specifically, the chip 10 includes connection terminals, including a first communication connection terminal P1, a second communication connection terminal P2, a first power supply connection terminal VDD, and a second power supply connection terminal VSS; one of the first power supply connection terminal VDD and the second power supply connection terminal VSS is connected to the first conductive layer 13. Figure 1 In the embodiment shown, the first power supply connection terminal VDD is connected to the first conductive layer 13.

[0037] Furthermore, in this embodiment, please continue to refer to... Figure 1 The chip package structure also includes a first pin 14 and a second pin 15. Both the first pin 14 and the second pin 15 are partially located inside the package body 11 and partially exposed outside the package body 11, for connection with external circuits. The first communication connection terminal P1 is electrically connected to the first pin 14; the second communication connection terminal P2 is electrically connected to the second pin 15.

[0038] In this embodiment, the first power supply connection terminal VDD is electrically connected to the first conductive layer 13, and the substrate of the chip 10 and the first conductive layer 13 form an amplification capacitor; the amplification capacitor is connected in parallel with the built-in capacitor. Alternatively, in one embodiment, the second power supply connection terminal VSS is electrically connected to the first conductive layer 13, and the substrate of the chip 10 and the first conductive layer 13 form an amplification capacitor; the amplification capacitor is connected in parallel with the built-in capacitor.

[0039] It should be noted that the above electrical connection can be achieved using a metal wire. Specifically, for example... Figure 1 As shown, the first communication connection terminal P1 is electrically connected to the first pin 14 via metal wire ①; the second communication connection terminal P2 is electrically connected to the second pin 15 via metal wire ③; and the first power supply connection terminal VDD is electrically connected to the first conductive layer 13 via metal wire ④. The metal wire can be gold wire or copper wire.

[0040] The chip 10 may also include other connection terminals, such as current detection connection terminals and temperature detection connection terminals, for detecting the temperature and current of the heating element electrically connected to the chip package structure. Specifically, the current detection connection terminals and temperature detection connection terminals can be electrically connected to the first pin 14 and the second pin 15 respectively, or dedicated pins can be provided for connection to the current detection connection terminals and temperature detection connection terminals.

[0041] It should be noted that the formula for calculating the capacitance of a parallel plate is as follows:

[0042]

[0043] Where ε is the dielectric constant, and ε = ε₀ε r , ε is the vacuum permittivity, k is the electrostatic constant, and ε is the free space permittivity. r Let ε be the relative permittivity, S be the area of ​​the two metal plates facing each other, and d be the distance between the two metal plates. From the formula, it can be seen that, except for ε0, ε can be controlled... r The capacitance is adjusted using the (material), S, and d parameters.

[0044] According to the calculation formula of parallel plate capacitance, in this embodiment, the area of ​​the first conductive layer 13 is set to be larger than the area of ​​the chip 10, or at least the same as the area of ​​the substrate of the chip 10, so as to maximize the capacitance of the expansion capacitor.

[0045] In this embodiment, the first conductive layer 13 is disposed on the side of the substrate of the chip 10 away from the connection terminal. The substrate material can be silicon. An insulating dielectric layer 16 is also disposed between the first conductive layer 13 and the substrate of the chip 10. In other embodiments, the insulating dielectric layer 16 may be omitted, and the first conductive layer 13 may be directly disposed on the surface of the substrate of the chip 10 away from the connection terminal, with the substrate serving as the insulating dielectric layer 16. Since there is air between the substrate of the chip 10 and the first conductive layer 13, it can easily lead to capacitance instability. Preferably, an insulating dielectric layer 16 is disposed between the first conductive layer 13 and the substrate of the chip 10. The insulating dielectric layer 16 can be a polymer, such as polyimide (PI). The insulating dielectric layer 16 also serves as an adhesive, fixing the first conductive layer 13 to the substrate of the chip 10. The thickness of the insulating dielectric layer 16 is not limited and is determined according to the capacitance of the expanded capacitance. In this embodiment, the insulating dielectric layer 16 covers the entire surface of the substrate of the chip 10 away from the connection terminal. In this embodiment, the first conductive layer 13, the first pin 14, and the second pin 15 are disposed in the same layer at intervals. Specifically, the first conductive layer 13, the first pin 14, and the second pin 15 are all metal sheets. In one embodiment, a whole layer of metal sheets can be formed, and then some of the metal sheets can be etched away or cut away by means of etching and polishing, thereby forming a structure like... Figure 1The first conductive layer 13, the first pin 14, and the second pin 15 are shown.

[0046] like Figure 2 and Figure 4 As shown, Figure 2 This is a schematic diagram of a chip packaging structure provided in another embodiment of this application; Figure 4 for Figure 2 A top view of the provided chip package structure. This embodiment further includes a second conductive layer 17, with the first conductive layer 13 and the second conductive layer 17 disposed at a distance from the connection terminals on the substrate of the chip 10. The first pin 14, the second pin 15, and the first conductive layer 13 are disposed on the same layer, with the second conductive layer 17 disposed on the side of the first conductive layer 13 away from the chip 10. An insulating dielectric layer 16 is also disposed between the first conductive layer 13 and the second conductive layer 17. The first conductive layer 13 forms an expansion capacitance with the second conductive layer 17 through the insulating dielectric layer 16; one of the first power supply connection terminal VDD and the second power supply connection terminal VSS is electrically connected to the first conductive layer 13, and the other is electrically connected to the second conductive layer 17. In this embodiment, the first power supply connection terminal VDD is electrically connected to the first conductive layer 13, while the second power supply connection terminal VSS is electrically connected to the second conductive layer 17. It should be noted that the electrical connections are achieved through metal wires. Specifically, the first power supply connection terminal VDD is electrically connected to the first conductive layer 13 through metal wire ④, and the second power supply connection terminal VSS is electrically connected to the second conductive layer 17 through metal wire ②; the first communication connection terminal P1 is electrically connected to the first pin 14 through metal wire ①; and the second communication connection terminal P2 is electrically connected to the second pin 15 through metal wire ③.

[0047] For details, see Figure 3 , Figure 3 This is a schematic diagram of the internal functional modules of a chip provided in an embodiment of this application. Chip 10 includes a first communication connection terminal P1, a second communication connection terminal P2, a power rectification module, an ASIC module, a first built-in capacitor module, and a second built-in capacitor module. In this embodiment, the first built-in capacitor module is a built-in capacitor VDD module, and the second built-in capacitor module is a built-in capacitor VSS module. The first built-in capacitor module is electrically connected to the first power supply connection terminal VDD, and the second built-in capacitor module is electrically connected to the second power supply connection terminal VSS. Specifically, when the battery rod communicates with the atomizer, the signal is input to the power rectification module through the first communication connection terminal P1 and the second communication connection terminal P2. After rectification, the signal is sent to the power port of the ASIC module. To maintain stable power port voltage, built-in capacitors are added inside chip 10, and these built-in capacitors are formed by mutual coupling between the first and second built-in capacitor modules. Please continue to refer to... Figure 1The first power supply connection terminal VDD is electrically connected to the first conductive layer 13, and the first built-in capacitor module forms an amplification capacitor with the first conductive layer 13 through the substrate of the chip 10; the amplification capacitor and the built-in capacitor are connected in parallel.

[0048] For details, please continue reading. Figure 2 The chip package structure also includes a connection layer 18; the first conductive layer 13, the connection layer 18, the first pin 14, and the second pin 15 are disposed on the same layer at intervals on the side of the insulating dielectric layer 16 near the chip 10, and the second conductive layer 17 is disposed on the side of the insulating dielectric layer 16 away from the chip 10; the connection layer 18 is electrically connected to the second conductive layer 17 through a conductive via 19 on the insulating dielectric layer 16. That is, the second power supply connection terminal VSS is electrically connected to the second conductive layer 17 through the connection layer 18 and the conductive via 19.

[0049] In another embodiment, the first conductive layer 13, the first pin 14, and the second pin 15 are disposed on the same layer at intervals on the side of the insulating dielectric layer 16 near the chip 10. See [link to specific details] for details. Figure 5 , Figure 5 This is a schematic diagram of a chip packaging structure provided in another embodiment of this application. A second conductive layer 17 is disposed on the side of the insulating dielectric layer 16 away from the chip 10; the insulating dielectric layer 16 has a first opening 20 at the gap between the first conductive layer 13 and the first pin 14; the insulating dielectric layer 16 also has a first opening 20 at the gap between the first conductive layer 13 and the second pin 15, so that the second conductive layer 17 is partially exposed. The second power supply connection terminal VSS is electrically connected to the second conductive layer 17 through a metal wire ② passing through the first opening 20. In this embodiment, the insulating dielectric layer 16 has a first opening 20 at the gap between the first conductive layer 13 and the second pin 15, and the metal wire ② passes through the first opening 20 to be electrically connected to the second conductive layer 17.

[0050] In another embodiment, please refer to Figure 6 , Figure 6This is a schematic diagram of a chip packaging structure provided in another embodiment of this application. A first conductive layer 13 is disposed on the side of the insulating dielectric layer 16 near the chip 10; a second conductive layer 17, a first pin 14, and a second pin 15 are disposed on the same layer, spaced apart, on the side of the insulating dielectric layer 16 away from the chip 10. Both the first conductive layer 13 and the insulating dielectric layer 16 have second openings 21 at corresponding locations on the second conductive layer 17, the first pin 14, and the second pin 15, so that the second conductive layer 17, the first pin 14, and the second pin 15 are partially exposed. Specifically, the first power supply connection terminal VDD is connected to the first conductive layer 13 via a metal wire ④; the second power supply connection terminal VSS is connected to the second conductive layer 17 via a metal wire ② passing through the second opening 21; the first communication connection terminal P1 is connected to the first pin 14 via a metal wire ① passing through the second opening 21; and the second communication connection terminal P2 is connected to the second pin 15 via a metal wire ③ passing through the second opening 21. Please refer to... Figure 7 , Figure 7 for Figure 6 The provided top view of the chip package structure shows that the first pin 14, the second pin 15, and the second conductive layer 17 are disposed on the same layer, and the first conductive layer 13 is disposed on the side closest to the chip 10. The first power supply connection terminal VDD is connected to the first conductive layer 13 through metal wire ④, the second power supply connection terminal VSS is connected to the second conductive layer 17 through metal wire ② passing through the second opening 21, the first communication connection terminal P1 is connected to the first pin 14 through metal wire ① passing through the second opening 21, and the second communication connection terminal P2 is connected to the second pin 15 through metal wire ③ passing through the second opening 21.

[0051] It should be noted that both the first conductive layer 13 and the second conductive layer 17 are metal sheets or metal films. The metal film can be achieved through electroplating or vapor deposition. The insulating dielectric layer 16 can be made of the same material as the package 11.

[0052] According to the calculation formula of parallel plate capacitor, in one embodiment, the areas of the first conductive layer 13 and the second conductive layer 17 are both larger than the area of ​​the chip 10, so as to increase the capacitance of the expansion capacitor.

[0053] like Figure 7 As shown, the package 11 includes: a housing 111 having a receiving cavity 112; a chip 10 and a first conductive layer 13 are disposed within the receiving cavity 112, with the side of the first conductive layer 13 facing away from the chip 10 spaced apart from the housing 111. The housing 111 is made of an insulating material, and its shape and size are not limited and can be selected as needed. The package 11 further includes a filler material (not shown), which fills the receiving cavity 112 and fixes the chip 10, the first conductive layer 13, the first pin 14, and the second pin 15. The filler material is an insulating polymer, and the filler material can be the same as the material of the insulating dielectric layer 16.

[0054] See Figure 8 , Figure 8 This is a schematic diagram of an electronic atomizing device provided in one embodiment of this application. The electronic atomizing device 300 can be used in various fields, such as medical, beauty, or recreational inhalation. The electronic atomizing device 300 includes an atomizer 100 and a battery rod 200. The atomizer 100 is used to heat the atomized aerosol generating matrix, for example, to heat and atomize a combined liquid aerosol generating matrix containing flavoring substances by electric heating to form an aerosol. The battery rod 200 is electrically connected to the atomizer 100, providing power to the atomizer 100 and controlling the atomizer 100 to heat the atomized aerosol generating matrix. The atomizer 100 and the battery rod 200 can be integrally formed or detachable.

[0055] In this embodiment, a chip packaging structure 102 is provided inside the atomizer 100, wherein the chip packaging structure 102 is as described above. Figures 1 to 7 In any embodiment of the chip packaging structure, when the battery rod 200 is electrically connected to the atomizer 100, the battery rod 200 communicates with the chip in the chip packaging structure 102 to confirm whether the atomizer 100 and the battery rod 200 are compatible, preventing the mixing of battery rods and atomizers from different brands. After confirming that the atomizer 100 and the battery rod 200 are compatible, the battery rod 200 controls the atomizer 100 to work according to the control signal or the external inhalation signal.

[0056] Please see Figure 9 , Figure 9 for Figure 8 The provided atomizer provides a schematic diagram of the connection relationship between the atomizing coil and the chip packaging structure. Specifically, the atomizer 100 includes an atomizing coil 101 and a chip packaging structure 102 electrically connected to the atomizing coil 101. The chip packaging structure 102 is connected in parallel with the heating element of the atomizing coil 101. The chip packaging structure 102 is as described above. Figures 1 to 7 The chip packaging structure provided in any embodiment. The atomizing core 101 includes a heating element, which can be a heating wire or a heating film. In one specific embodiment, the chip packaging structure 102 is connected in parallel with the heating wire. Specifically, the first pin 14 is connected to end a of the heating wire, and the second pin 15 is connected to end b of the heating wire. The expansion capacitor C1 is connected in parallel with the built-in capacitor of the chip 10. Specifically, one conductive layer of the expansion capacitor C1 (e.g., the first conductive layer 13) is connected to the first power supply connection terminal VDD, and the other conductive layer (e.g., the second conductive layer 17) is connected to the second power supply connection terminal VSS.

[0057] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. An atomizer, characterized in that, include: Atomizer coil; A chip packaging structure is electrically connected to the atomizing core, and the chip packaging structure includes: Package; The chip is located within the package. The first conductive layer is located within the package and on one side of the chip; The first conductive layer is electrically connected to the built-in capacitor of the chip to serve as an electrode plate for expanding the capacitance electrically connected to the chip. The expanding capacitance is connected in parallel with the built-in capacitor and is used to expand the capacitance of the built-in capacitor of the chip.

2. The atomizer according to claim 1, characterized in that, The chip includes a first built-in capacitor module and a second built-in capacitor module; the first built-in capacitor module and the second built-in capacitor module constitute the built-in capacitor of the chip; one of the first built-in capacitor module and the second built-in capacitor module is electrically connected to the first conductive layer.

3. The atomizer according to claim 2, characterized in that, The chip packaging structure further includes a first pin and a second pin; both the first pin and the second pin are partially located within the package body and partially exposed outside the package body. The chip includes connection terminals, which include a first communication connection terminal, a second communication connection terminal, a first power supply connection terminal, and a second power supply connection terminal; the first communication connection terminal is electrically connected to the first pin; the second communication connection terminal is electrically connected to the second pin; One of the first power supply connection terminal and the second power supply connection terminal is electrically connected to the first conductive layer.

4. The atomizer according to claim 3, characterized in that, The first power supply connection terminal is electrically connected to the first conductive layer, and the first built-in capacitor module forms the amplification capacitor with the first conductive layer through the substrate of the chip; the amplification capacitor is connected in parallel with the built-in capacitor; or The second power supply connection terminal is electrically connected to the first conductive layer, and the second built-in capacitor module forms the amplification capacitor with the first conductive layer through the substrate of the chip; the amplification capacitor is arranged in parallel with the built-in capacitor.

5. The atomizer according to claim 4, characterized in that, The first conductive layer is disposed on the side of the chip substrate away from the connection terminal, and an insulating dielectric layer is disposed between the first conductive layer and the chip substrate.

6. The atomizer according to claim 4, characterized in that, The first conductive layer, the first pin, and the second pin are arranged at intervals on the same layer.

7. The atomizer according to claim 1, characterized in that, The chip packaging structure further includes a first pin, a second pin, and a second conductive layer; both the first pin and the second pin are partially located within the package body and partially exposed outside the package body. The chip includes connection terminals, which include a first communication connection terminal, a second communication connection terminal, a first power supply connection terminal, and a second power supply connection terminal; the first communication connection terminal is electrically connected to the first pin; the second communication connection terminal is electrically connected to the second pin; The first conductive layer and the second conductive layer are disposed at a distance from the connection terminal on the substrate of the chip, and an insulating dielectric layer is disposed between the first conductive layer and the second conductive layer; the first conductive layer and the second conductive layer form the expansion capacitance through the insulating dielectric layer; one of the first power supply connection terminal and the second power supply connection terminal is electrically connected to the first conductive layer, and the other is electrically connected to the second conductive layer.

8. The atomizer according to claim 7, characterized in that, The chip packaging structure further includes a connection layer; the first conductive layer, the connection layer, the first pin, and the second pin are disposed on the same layer at intervals on the side of the insulating dielectric layer closer to the chip, and the second conductive layer is disposed on the side of the insulating dielectric layer away from the chip; the connection layer is electrically connected to the second conductive layer through conductive vias on the insulating dielectric layer.

9. The atomizer according to claim 7, characterized in that, The first conductive layer, the first pin, and the second pin are disposed on the same layer at intervals on the side of the insulating dielectric layer closer to the chip, and the second conductive layer is disposed on the side of the insulating dielectric layer away from the chip; the insulating dielectric layer has a first opening at the gap between the first conductive layer, the first pin, and the second pin to expose part of the second conductive layer.

10. The atomizer according to claim 7, characterized in that, The first conductive layer is disposed on the side of the insulating dielectric layer close to the chip; the second conductive layer, the first pin, and the second pin are disposed on the side of the insulating dielectric layer away from the chip at intervals in the same layer; the first conductive layer and the insulating dielectric layer each have a second opening at the corresponding location of the second conductive layer, the first pin, and the second pin, so that the second conductive layer, the first pin, and the second pin are all partially exposed.

11. The atomizer according to claim 7, characterized in that, Both the first conductive layer and the second conductive layer are metal sheets or metal films, and the areas of both the first conductive layer and the second conductive layer are larger than the area of ​​the chip.

12. The atomizer according to claim 1, characterized in that, The first conductive layer is a metal sheet or a metal film, and the area of ​​the first conductive layer is larger than the area of ​​the chip.

13. The atomizer according to any one of claims 1-12, characterized in that, The chip packaging structure is connected in parallel with the heating element of the atomizing core.

14. An electronic atomizing device, characterized in that, include: Atomizer, wherein the atomizer is the atomizer described in any one of claims 1-13 above; A battery rod is used to control the operation of the atomizing core and to communicate with the chip in the chip package structure.

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