Semiconductor device and method of manufacturing the same

Abstract

Various embodiments of the present invention will provide a semiconductor device and a manufacturing method thereof, and more particularly, a semiconductor device including an isolation layer having an air gap to minimize stress on a substrate caused by an oxide and improve performance of a device and a manufacturing method thereof. The semiconductor device according to an embodiment of the present invention includes a plurality of isolation layers each including a trench formed in a substrate and an air gap in a lower portion of the trench, an active region including a fin body disposed between the isolation layers disposed in succession and a fin formed on the fin body, the fin having a width narrower than the fin body and extending in a first direction, a gate structure partially covering the active region and the isolation layers and extending in a second direction, and a source / drain region covering the fin on both sides of the gate structure.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0016266, filed on February 4, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to a semiconductor device and a method for manufacturing the same. More specifically, this invention relates to a semiconductor device including an isolation layer and a method for manufacturing the same, the isolation layer comprising an air gap and fin structures made of different materials. Background Technology

[0004] As semiconductor devices become increasingly integrated, the length of the gate and the length of the channel formed beneath it are decreasing. Therefore, various efforts are being made to improve the structure and manufacturing methods of semiconductor devices, thereby enhancing the operational stability and reliability of transistors, which are crucial factors in determining the performance of integrated circuits. Summary of the Invention

[0005] Various embodiments of this disclosure will provide a semiconductor device capable of minimizing stress on the substrate caused by oxides. The semiconductor device may include an isolation layer with an air gap. The semiconductor device may exhibit improved performance, including improved operational stability and reliability.

[0006] According to one embodiment of the present invention, a semiconductor device includes: a plurality of isolation layers, each isolation layer including a trench formed in a substrate and an air gap in the lower portion of the trench; an active region including a fin disposed between consecutively disposed isolation layers and a fin formed on the fin, the fin having a width narrower than the fin and extending in a first direction; a gate structure partially covering the active region and the isolation layers and extending in a second direction; and a source / drain region covering the fins on both sides of the gate structure.

[0007] According to another embodiment, a method for manufacturing a semiconductor device includes: forming a stacked structure of fins and sacrificial patterns on a substrate; forming sacrificial spacers on both sides of the stacked structure; forming a separation trench by etching an exposed portion of the substrate between the continuously disposed sacrificial spacers; and forming an isolation layer in the separation trench, the isolation layer including an air gap and a capping layer.

[0008] The effects of this invention include improving the reliability of semiconductor devices by preventing mobility degradation and stress relaxation.

[0009] These and other features and advantages of the present invention will become clearer and better understood by those skilled in the art from the following detailed description and accompanying drawings. Attached Figure Description

[0010] Figure 1A and Figure 1B This is a view showing device degradation caused by materials buried in the insulation layer.

[0011] Figure 2 This is a perspective view illustrating a semiconductor device according to an embodiment of the present invention.

[0012] Figures 3A to 3L This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0013] Various embodiments of the invention will be described with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematic representations of examples of the invention. The structures in the drawings may be modified without departing from the scope of the invention, for example, due to manufacturing requirements, tolerances, etc. Embodiments of the invention are not limited to the specific structures shown in the drawings and may include any variations in structure resulting from manufacturing processes. Furthermore, any regions and their shapes shown schematically in the drawings are intended to illustrate specific examples of the regional structures of various elements and are not intended to limit the scope of the invention.

[0014] This disclosure discloses embodiments of the invention in the form of a multi-gate transistor or a fin multi-gate transistor, also referred to herein as a fin field-effect transistor (FinFET) device. Such devices may include P-type metal-oxide-semiconductor FinFET devices or N-type metal-oxide-semiconductor FinFET devices. FinFET devices may be dual-gate devices, triple-gate devices, bulk devices, silicon-on-insulator (SOI) devices, and / or other configurations. Those skilled in the art will recognize other embodiments of useful semiconductor devices that may fall within the scope of this invention. For example, the embodiments described herein can also be applied to gate-all-around (GAA) devices, omega-gate (Ω-gate) devices, or Pi-gate (Π-gate) devices.

[0015] Figure 1A and Figure 1B This is a view showing device degradation caused by materials buried in the insulation layer. Figure 1A It is a cross-sectional view showing the stress direction of the material buried in the isolation layer. Figure 1B It is a planar diagram showing the effect of stress orientation on the material buried in the source / drain regions and isolation layers in the PMOS and NMOS regions.

[0016] like Figure 1A and Figure 1BAs shown, the active region ACT extending in the first direction can be defined by an isolation layer ISO, which can be formed on a substrate Sub. The active region ACT can include an active fin AF protruding above the isolation layer ISO. The upper surface of the active fin AF can be at a level higher than the upper surface of the isolation layer ISO. A channel fin CF can be formed on the active fin AF of the active region ACT. The active fin AF can be formed by etching a portion of the substrate Sub, and the channel fin CF can be formed by depositing and etching separate layers on the substrate Sub. A gate, extending in a second direction perpendicular to the first direction and intersecting the active region ACT, is formed on the channel fin CF. A source / drain region SD is formed on the active fin AF and the channel fin CF, located on either side of the gate. SiGe (silicon-germanium) can be applied to the channel fin CF and the source / drain region SD of a PMOS FinFET device, while SiC (silicon carbide) can be applied to the channel fin CF and the source / drain region SD of an NMOS FinFET device.

[0017] Through a series of processes, trenches are formed by etching the substrate (Sub), and then oxide gaps are filled into the trenches to form the isolation layer (ISO), thereby defining the active region (ACT). Channel fins (CF) are used as gate channels via ion implantation of impurities. Ion implantation is performed to form the gate channels, and then the gate is formed.

[0018] During ion implantation to form the gate channel, impurities used to control the threshold voltage Vt are unnecessarily doped at the interface between the active fin AF and the active region ACT adjacent to the active fin AF. Therefore, mobility may be degraded. Furthermore, when a metal gate is used as the gate, thermal stability issues may arise due to the wide variety of metal materials available.

[0019] Furthermore, device performance may degrade because the compressive stress (LCS) of the gap-filling oxide used to form the device isolation layer (ISO) is insufficient to apply adequate stress to the device. In other words, in PMOS, SiGe is applied to the source / drain regions and applies compressive stress (LCS), while in NMOS, SiC is applied to the source / drain regions and applies tensile stress (LTS), thereby improving carrier mobility and current drive capability. Despite this improved capability, the stress applied to PMOS and NMOS is reduced due to the oxide filling the gap in the isolation layer (ISO). For example, the oxide filling the device isolation layer (ISO) applies a continuous compressive stress (CS) to the active region (ACT) in a direction perpendicular to the stress direction applied to the source / drain regions of PMOS and NMOS. However, because the stress applied to PMOS and NMOS is mitigated, it is difficult to apply sufficient stress to PMOS and NMOS to improve current drive capability.

[0020] Therefore, in this embodiment, a semiconductor device and its manufacturing method are disclosed that can improve current drive capability by applying sufficient tensile or compressive stress to both the PMOS and NMOS of a FinFET device.

[0021] Figure 2 This is a perspective view illustrating a semiconductor device according to an embodiment of the present invention.

[0022] like Figure 2 As shown, the semiconductor device may include one or more isolation layers 102 formed on a substrate 101, fins 103 defined by the isolation layers 102, active regions including fins 104 formed on the fins 103, a gate structure GS formed on the upper part of the substrate 101, source / drain regions SD covering the fins 104 located on both sides of the gate structure GS, and an interlayer dielectric layer 120 filled between the gate structures GS. The isolation layers 102 and the active regions may extend in a first direction X, while the gate structure GS may extend in a second direction Y perpendicular to the first direction X. Figure 2 Two isolation layers 102 spaced apart from each other along the second direction Y are shown. Two source / drain regions SD are also spaced apart from each other along the second direction Y.

[0023] Substrate 101 may include a semiconductor substrate such as a silicon substrate. Substrate 101 may be made of a silicon-containing material. Substrate 101 may include various doping configurations depending on design requirements. Substrate 101 may include other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Substrate 101 may include compound semiconductors and / or alloy semiconductors. Substrate 101 may include a group III-V semiconductor substrate. Substrate 101 may include a compound semiconductor substrate such as GaAs (gallium arsenide), InAs (indium arsenide), or InP (indium phosphide). Substrate 101 may include a silicon-on-insulator (SOI) substrate. Substrate 101 may include conductive regions, such as wells and channels in which impurities are doped, or structures in which impurities are doped.

[0024] The isolation layer 102 may extend in a first direction X. Fins 103 may be defined by the isolation layer 102. The isolation layers 102 may be spaced apart from each other in a second direction Y by the fins 103 therebetween. The width of the isolation layer 102 may be narrower than the width of the fins 104. The isolation layer 102 may have an extremely small critical dimension.

[0025] Each isolation layer 102 may include an air gap 102B and a capping layer 102A formed on the air gap 102B. Adjacent fins 103 can be sufficiently spaced apart by forming a capping layer 102A that fills the upper portion of each isolation layer 102 and by forming an air gap 102B on the lower portion of each isolation layer 102. The capping layer 102A may include an insulating material. The capping layer 102A may include an oxide. The capping layer 102A may include a silicon oxide material with poor step coverage. The capping layer 102A may include an oxide based on tetraethyl orthosilicate (TEOS). In another embodiment, the capping layer 102A may include undoped silicate glass (USG) oxide or high-density plasma (HDP) oxide.

[0026] The active area may include fin body 103 and fin 104 formed on fin body 103.

[0027] Fin 103 may be defined by an isolation layer 102. Fin 103 may extend in a first direction X. Fins 103 may be spaced apart from each other in a second direction Y by means of the isolation layer 102. The width of fin 103 may be wider than the width of isolation layer 102. The upper surface of fin 103 may be at the same level as the upper surface of isolation layer 102. Fin 104 may protrude in a third direction Z perpendicular to the upper surface of substrate 101. The upper surface of fin 104 may be at a level higher than the upper surface of fin 103 and the upper surface of isolation layer 102. The width of fin 104 may be narrower than the width of fin 103. Fin 104 may have a width wider than isolation layer 102. Fin 104 may be formed of a material different from fin 103. Fin 104 may be a layer separate from fin 103. Fin 104 may be formed directly on fin 103.

[0028] Fin 104 may be formed of a germanium (Ge)-based semiconductor material or a tin (Sn)-based semiconductor material. The stacked structure of fin 104 / fin body 103 may include one of the following: SiGe / Si, Ge / Si, or a high-concentration SiGe / low-concentration SiGe stacked structure. In another embodiment, the stacked structure of fin 104 / fin body 103 may include a GeSn / Ge or Sn / Ge stacked structure.

[0029] A gate structure GS can be formed on the upper part of the substrate 101. The gate structure GS can extend in the second direction Y. The gate structure GS can have a linear shape extending in the second direction Y. The continuously arranged gate structures GS can be separated from each other by an interlayer dielectric layer 120. The gate structure GS can cover a portion of each of the fin 104, the isolation layer 102, and the fin body 103. The gate structure GS can directly contact the substrate 101. The upper surface of the gate structure GS can be at a higher level than the upper surface of the fin body 103 and the upper surface of the fin 104.

[0030] The gate structure GS may include a gate spacer 131, a gate dielectric layer 132, and a gate electrode 133.

[0031] A gate dielectric layer 132 may be disposed between the gate electrode 133 and the fin 103. A gate dielectric layer 132 may be disposed between the gate electrode 133 and the fin 104. A gate dielectric layer 132 may extend between the gate electrode 133 and the isolation layer 102. A gate dielectric layer 132 may extend between the gate electrode 133 and the gate spacer 131. The upper surface of the gate dielectric layer 132 may be at the same level as the upper surface of the gate electrode 133. The gate dielectric layer 132 may directly contact the substrate 101.

[0032] The gate dielectric layer 132 may include a high-dielectric (high-k) material, such as hafnium oxide (HfO2). The gate dielectric layer 132 may include one or more combinations selected from: hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium silicate (ZrSiO4), titanium oxide (TiO2), HfZrO, and tantalum oxide (Ta2O3). Alternatively, the gate dielectric layer 132 may include a high-k material, including other suitable materials. In another embodiment, the gate dielectric layer 132 may include silicon oxide or other suitable dielectric materials. The gate dielectric layer 132 may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), oxidation, and / or other suitable methods.

[0033] In another embodiment, the interface layer may be situated between the gate dielectric layer 132 and the substrate 101. The interface layer may comprise a dielectric material such as silicon oxide or silicon nitride.

[0034] Gate electrode 133 may include a conductive material. Gate electrode 133 may include a metal. Gate electrode 133 may include a conductive metal or a conductive nitride. Gate electrode 133 may include a conductive material such as W, TiN, TaN, WN, Re, Ir, Ru, Mo, Al, Cu, Co, Ni, or combinations thereof, and / or other suitable components. Depending on substrate 101, gate electrode 133 may include a first metal for an N-type FinFET and a second metal for a P-type FinFET. In another embodiment, gate electrode 133 may include polycrystalline silicon. Gate electrode 133 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), and / or other suitable processes.

[0035] Gate spacers 131 may be formed on both sidewalls of the gate structure GS. Gate spacers 131 may be spaced apart from gate electrode 133 by a gate dielectric layer 132 between gate electrode 133 and gate spacers 131. Gate spacers 131 may include dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof.

[0036] The source / drain region SD can cover the fins 104 on both sides of the gate structure GS. The source / drain region SD can cover the side and top surfaces of the fins 104. The bottom surface of the source / drain region SD can be lower than the top surface of the fins 104. The top surface of the source / drain region SD can be at a higher level than the top surface of the fins 104.

[0037] The source / drain region SD may include a fin 104 and an epitaxial layer 105 grown from the fin 104. The source / drain regions SD may be spaced apart from each other using a gate structure GS interposed therebetween. The epitaxial layer 105 may include the same material as the fin 104. The epitaxial layer 105 may be formed by selective epitaxial growth (SEG). The epitaxial layer 105 may include one of SiGe, Ge, GeSn, or Sn.

[0038] The source / drain region SD may also include impurities doped in the fin 104 and the epitaxial layer 105. The source / drain region SD may contain different impurities in the PMOS and NMOS regions, respectively. The source / drain region SD in the PMOS region may include one of B, BF2, or Ga impurities. The source / drain region SD in the NMOS region may include impurities such as As and / or Sb. In another embodiment, the epitaxial layer 105 in the NMOS region may also include additional impurities doped in situ during epitaxial growth. The epitaxial layer 105 in the NMOS region may include one of SiC, SiCP, or SiP.

[0039] The interlayer dielectric layer 120 can be formed to surround the gate structure GS and cover the source / drain region SD. The interlayer dielectric layer 120 can be formed to fill the space between adjacent gate structures GS. The interlayer dielectric layer 120 may include a single insulating material or multiple insulating materials. The upper surface of the interlayer dielectric layer 120 may be at the same level as the upper surface of the gate structure GS. In another embodiment, the interlayer dielectric layer 120 may be at a higher level than the gate structure GS.

[0040] As described above, in this embodiment, by minimizing the amount of insulating material filling the isolation layer 102, unnecessary stress applied from the insulating material to the substrate 101, and more specifically to the fin 103, can be minimized. Furthermore, by forming the width of the isolation layer 102 to be narrower than the width of the fin 103, the overall volume of the fin 103 can be increased. Therefore, the effect of dispersing stress applied from the cover layer 102A of the isolation layer 102 to the fin 103 is achieved.

[0041] Furthermore, in this embodiment, by forming the fin 104 on the fin 103 via a separate deposition process, only the fin 104 can protrude above the substrate 101. Therefore, the effects on the fin 103 and fin 104 caused by the different stress characteristics of the fins 103 and fin 104 made of different materials can be minimized. That is, the problem of the stress of the fin 104, which serves as the source / drain region SD, being reduced by the material of the fin 103 or by impurities unnecessarily doped into the fin 103 can be minimized.

[0042] Therefore, in this embodiment, a high-performance device can be achieved by applying sufficient stress to improve device performance.

[0043] Figures 3A to 3L This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 3A to 3L In the middle, A-A' is along Figure 2 The cross-sectional view taken by line A-A' at the intersection with the gate structure GS in the second direction Y, and B-B' is along... Figure 2 The cross-sectional view taken by line B-B' in the second direction Y intersecting with the interlayer dielectric layer 120, and C-C' is along... Figure 2 The cross-sectional view taken by line C-C' at the intersection with the source / drain region SD in the first direction X. Figures 3A to 3L Among the components shown, with Figure 2 The components shown can be made by components with the same name. Figure 2 The components shown are made of the same material. Detailed descriptions of the same components may be omitted.

[0044] like Figure 3A As shown, the fin material layer 12A, the first sacrificial layer 21A, the second sacrificial layer 22A, and the third sacrificial layer 23A can be formed sequentially on the substrate 11 in the order described. The mask pattern 24 can be formed on the third sacrificial layer 23A.

[0045] Substrate 11 may include a semiconductor substrate such as a silicon substrate.

[0046] The fin material layer 12A may include semiconductor materials such as silicon germanium (SiGe) or silicon carbide (SiC). For example, the fin material layer 12A and the substrate 11 of the PMOS region may include germanium-based stacked structures selected from SiGe / Si, Ge / Si and high-concentration SiGe / low-concentration SiGe, or tin-based stacked structures such as GeSn / Ge or Sn / Ge.

[0047] The first sacrificial layer 21A, the second sacrificial layer 22A, and the third sacrificial layer 23A can each be formed of materials with different etching selectivity. The first sacrificial layer 21A, the second sacrificial layer 22A, and the third sacrificial layer 23A can be formed of insulating materials. The first sacrificial layer 21A, the second sacrificial layer 22A, and the third sacrificial layer 23A can include, for example, a stacked structure of silicon oxide, silicon nitride, and silicon oxycarbide (SiOC). The first sacrificial layer 21A can be a protective layer for protecting the fin material layer 12A. The second sacrificial layer 22A can be used as an etching mask for the first sacrificial layer 21A. The third sacrificial layer 23A can be used as an etching mask for the second sacrificial layer 22A. The thicknesses of the first sacrificial layer 21A to the third sacrificial layer 23A can be different. The first sacrificial layer 21A to the third sacrificial layer 23A can be adjusted to a minimum thickness so that the uniformity of the deposited film is not degraded for the accuracy of subsequent fine patterning. This disclosure is not limited thereto, and the thicknesses of the first sacrificial layer 21A to the third sacrificial layer 23A can be adjusted as needed.

[0048] The first mask pattern 24 can be a photoresist pattern. The first mask pattern 24 can be configured in a first direction X (reference). Figure 2 Linear extensions on )

[0049] like Figure 3B As shown, the first mask pattern 24 (reference) can be used. Figure 3A The third sacrificial layer 23A (reference) Figure 3A ), second sacrificial layer 22A (reference) Figure 3A ), First Sacrificial Layer 21A (Reference) Figure 3A ) and fin material layer 12A (reference) Figure 3A The etching is performed sequentially. The first mask pattern 24 can be used as an etching mask to etch the third sacrificial layer 23A, the etched third sacrificial layer can be used as an etching mask to etch the second sacrificial layer 22A, and the etched second sacrificial layer can be used as an etching mask to etch the first sacrificial layer 21A.

[0050] Therefore, a fin 12 protruding from the substrate 11 can be formed. A stacked structure of the first sacrificial pattern 21 to the third sacrificial pattern 23 can be formed on the fin 12.

[0051] The first mask pattern 24 can be removed during the etching process used to form the third sacrificial pattern 23 to the first sacrificial pattern 21 (see reference). Figure 3A In another embodiment, after the third sacrificial pattern 23 is formed, the first mask pattern 24 can be removed by a stripping process (see reference). Figure 3A In another embodiment, after the fin 12 and the first to third sacrificial patterns 21, 22 and 23 have all been formed, the first mask pattern 24 can be removed by a stripping process (see reference). Figure 3A ).

[0052] like Figure 3C As shown, sacrificial spacers 25 can be formed on the two sidewalls of the stacked structure of fin 12 and the first sacrificial pattern 21 to the third sacrificial pattern 23.

[0053] The sacrificial spacer 25 can be used as an etching mask for etching the substrate 11. The sacrificial spacer 25 may include a material with etching selectivity relative to the third sacrificial pattern 23. The sacrificial spacer 25 may include an insulating material. The sacrificial spacer 25 may include nitrides and oxides. The sacrificial spacer 25 may include, for example, insulating materials such as SiO2, SiON, SiBN, or SiBCN.

[0054] To form the sacrificial spacer 25, the spacer etching process can be performed after forming an insulating material covering the substrate 11, which includes fins and the first sacrificial pattern 21 to the third sacrificial pattern 23.

[0055] Substrate 11 may be exposed between adjacent sacrificial spacers 25. Substrate 11 exposed between adjacent sacrificial spacers 25 may define a device separation region. Substrate 11 exposed between adjacent sacrificial spacers 25 may have a very small critical dimension. Substrate 11 exposed between adjacent sacrificial spacers 25 may have a width narrower than the sacrificial spacers 25 and the substrate 11 covered by the stacked structure.

[0056] like Figure 3D As shown, trenches 11T can be formed by etching the substrate 11 using a stacked structure of fins 12 and first sacrificial patterns 21 to third sacrificial patterns 23, and sacrificial spacers 25 as an etching mask. Trench 11T can have a line shape extending on the substrate 11 in a first direction X. Trench 11T can have lines spaced apart in a second direction Y. The width of trench 11T can be formed to be narrower than the width of the substrate 11 between adjacent trenches 11T.

[0057] The trench 11T can be formed with a slope having a positive profile in which the upper width is wider than the lower width. In another embodiment, the trench 11T can be formed by polymer passivation to have a vertical profile in which the upper and lower widths of the trench 11T are the same, or a negative profile in which the upper width of the trench 11T is narrower than the lower width.

[0058] The width of trench 11T can be adjusted to have a critical dimension such that even when the substrate 11 expands due to heat treatment performed during the semiconductor process, the two sidewalls of trench 11T can remain in contact with each other.

[0059] The active region may be defined by the groove 11T. Fins 14 spaced apart from each other by the groove 11T may also be defined. The active region may include the fins 14 and fins 12 on the fins 14.

[0060] like Figure 3E As shown, the sacrificial spacer 25 can be removed (reference). Figure 3D The sacrificial spacer 25 can be removed by wet etching. The third sacrificial pattern 23 and the second sacrificial pattern 22 can also be removed at the same time as the sacrificial spacer 25.

[0061] Subsequently, oxide layer 26 may be formed on the upper portion of substrate 11, including fin 12 and first sacrificial pattern 21. Oxide layer 26 may include silicon oxide. Oxide layer 26 may include silicon oxide with poor step coverage. Oxide layer 26 may include an oxide based on tetraethyl orthosilicate (TEOS). In another embodiment, oxide layer 26 may include undoped silicate glass (USG) or high-density plasma (HDP) oxide. In another embodiment, oxide layer 26 may include silicon oxide, excluding spin-on dielectric (SOD) and high aspect ratio process (HARP) oxides.

[0062] The oxide layer 26 can be gap-filled in the trench 11T. The oxide used to gap-fill the upper part of the trench 11T can be used as a cover layer 13A of the isolation layer 13. Air gaps 13B can be formed below the cover layer 13A. That is, an isolation layer 13 including the cover layer 13A and the air gaps 13B can be formed in the trench 11T.

[0063] The fin 14 may be defined by the isolation layer 13. The fin 14 may have a linear shape extending in a first direction X and may be spaced apart from each other in a second direction Y by the isolation layer 13.

[0064] like Figure 3F As shown, oxide layer 26 can be removed (reference). Figure 3E The oxide layer 26 can be removed by wet etching. Wet etching can be performed by an immersion process.

[0065] Subsequently, an ion implantation process (IMP) can be performed. The ion implantation process IMP can be an impurity doping process used to form channels and wells in the fin 14. The ion implantation processes IMP for forming wells and channels can be performed separately. The ion implantation process for forming channels can be performed by counter doping with a reduced threshold voltage Vt.

[0066] Prior to performing the ion implantation (IMP) process, a barrier layer mask can be formed that completely covers the substrate 11 (substrate 11 includes fins 12 and a first sacrificial pattern 21). The barrier layer mask can serve as a barrier layer to prevent surface damage to the substrate 11 during the IMP process. In another embodiment, the oxide layer 26 (see reference 26) can be removed. Figure 3E At the same time, the first sacrificial pattern 21 is removed. In another embodiment, the first sacrificial pattern 21 can be removed before performing the ion implantation process (IMP) and a barrier layer mask that completely covers the substrate 11 (substrate 11 includes fins 12) can be formed.

[0067] like Figure 3GAs shown, an etch stop layer 31A, a dummy gate layer 32A, and a dummy mask layer 33A covering the entire substrate 11 including the fin 12 can be sequentially formed on the substrate 11. The etch stop layer 31A may include a material with etch selectivity relative to the dummy gate layer 32A. The etch stop layer 31A may include, for example, silicon oxide. The dummy gate layer 32A may include, for example, polysilicon. The dummy mask layer 33A may include a material with etch selectivity relative to the dummy gate layer 32A and the etch stop layer 31A. The dummy mask layer 33A may include, for example, silicon nitride.

[0068] The second mask pattern 34 can be formed on the dummy mask layer 33A. The second mask pattern 34 can be configured as a line extending in the second direction Y. The second mask pattern 34 can have a photoresist pattern.

[0069] like Figure 3H As shown, a second mask pattern 34 (reference) can be used. Figure 3G Etching of the virtual mask layer 33A (reference) Figure 3G Therefore, a dummy mask pattern 33 can be formed. During the etching process that forms the dummy mask pattern 33, the second mask pattern 34 can be removed (see reference). Figure 3G In another embodiment, the second mask pattern 34 can be removed during a stripping process following the formation of the dummy mask pattern 33 (see reference). Figure 3G ).

[0070] Subsequently, the dummy mask pattern 33 can be used as an etching mask to sequentially etch the dummy gate layer 32A (see reference). Figure 3G ) and etch stop layer 31A (reference) Figure 3G Therefore, a stacked structure of etch stop pattern 31, dummy gate pattern 32 and dummy mask pattern 33 can be formed.

[0071] Subsequently, a gate spacer 35 can be formed on the sidewalls of the stacked structure comprising the etch stop pattern 31, the dummy gate pattern 32, and the dummy mask pattern 33. The gate spacer 35 may include an insulating material. The gate spacer 35 may include, for example, silicon nitride. The gate spacer 35 can be formed by forming a spacer material covering the entire substrate 11 including the stacked structure comprising the etch stop pattern 31, the dummy gate pattern 32, and the dummy mask pattern 33, and then performing a spacer etching process.

[0072] The stacked structure of the etch stop pattern 31, the dummy gate pattern 32, and the dummy mask pattern 33, as well as the gate spacer 35 formed on the sidewall of the stacked structure, can be referred to as a "dummy gate structure DG". The dummy gate structure DG can be a dummy pattern used to replace the metal gate (RMG) process.

[0073] The dummy gate structure DG can extend in the second direction Y and has a linear shape intersecting the fin 14, fin 12, and isolation layer 13. Both sides of the dummy gate structure DG can be etched to expose the fin 12 and substrate 11, as shown in the cut along line B-B'. Figure 3H The cross-sectional view is shown.

[0074] like Figure 3I As shown, the source / drain regions SD can be formed on both sides of the dummy gate structure DG. The source / drain regions SD may include fins 12 exposed on both sides of the dummy gate structure DG and an epitaxial layer 15 covering the fins 12. The epitaxial layer 15 can be grown from the fins 12. The epitaxial layer 15 can be formed by performing a selective epitaxial growth process using the surface of the fins 12 as a seed. The epitaxial layer 15 may include, for example, silicon germanium (SiGe) or silicon carbide (SiC).

[0075] The process of forming the source / drain region SD can include a process of doping the source / drain region SD with impurities during or after a selective epitaxial growth process. The impurity doping process can be performed to improve the electrical characteristics of the transistor including the source / drain region SD. When the transistor is N-type, the impurity can be, for example, one of phosphorus (P), As, or Sb. When the transistor is P-type, the impurity can be, for example, one of B, BF2, or Ga. This disclosure is not limited thereto and may include fins 12 made of a semiconductor material capable of applying sufficient stress to each of the N-type or P-type transistors. Furthermore, the impurities doped in the source / drain region SD of this embodiment are not limited thereto and may include suitable impurities capable of improving the mobility characteristics of the device.

[0076] like Figure 3J As shown, an interlayer dielectric layer 41 can be formed on the source / drain regions SD formed on the substrate 11. The process of forming the interlayer dielectric layer 41 may include forming an insulating layer covering the source / drain regions SD and the dummy gate structure DG on the substrate 11, and planarizing the insulating layer until the upper surface of the dummy gate structure DG is exposed. The dummy mask pattern 33 (see reference) can be removed by the planarization process. Figure 3I The interlayer dielectric layer 41 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and low-dielectric materials.

[0077] like Figure 3K As shown, this can be achieved by removing the dummy gate pattern 32 (reference). Figure 3J ) and etching stop pattern 31 (reference) Figure 3J A gap region 42 is formed in the gate spacer 35. The gap region 42 can be an empty space defined by the gate spacer 35. The upper surface of the fin 12 can be exposed by the gap region 42.

[0078] The process of forming the gap region 42 may include relative to the gate spacer 35, the interlayer dielectric layer 41, and the etch stop pattern 31 (see reference). Figure 3J Etching of the dummy gate pattern 32 under etching selective conditions (reference) Figure 3J The process of forming the gap region 42 may include removing the etch stop pattern 31 (see reference). Figure 3J The process of exposing the upper surface of fin 12.

[0079] Subsequently, as Figure 3L As shown, a filling gap region 42 can be formed (reference). Figure 3K The gate dielectric layer 51 and the gate electrode 52.

[0080] Specifically, the gate dielectric layer 51 can be formed to conformally fill the gap region 42 (see reference). Figure 3K Part of the fin 12. The gate dielectric layer 51 can be formed to cover the upper surface of the fin 12. The gate dielectric layer 51 may include a high-k material. The gate dielectric layer 51 can be formed by, for example, an atomic layer deposition process. Subsequently, a gate electrode 52 can be formed on the gate dielectric layer 51 to fill the gap region 42 (see reference). Figure 3K The remaining portion of the gate electrode 52. The gate electrode 52 may include a conductive material. The gate electrode 52 may be formed as a single layer or multiple layers. The gate electrode 52 may include a stacked structure of metal nitride and metal layers. The gate dielectric layer 51 may extend along the bottom surface and side surface of the gate electrode 52 and may be located between the gate electrode 52 and the gate spacer 35.

[0081] As described above, in this embodiment, by minimizing the amount of insulating material filling the isolation layer 13, unnecessary stress applied from the insulating material to the substrate 11, and more specifically to the fin 14, can be minimized. Furthermore, by forming the width of the isolation layer 13 to be narrower than the width of the fin 14, the overall volume of the fin 14 can be increased. Therefore, the stress distribution effect from the cover layer 13A of the isolation layer 13 to the fin 14 is achieved.

[0082] Furthermore, in this embodiment, the fin 12 can be formed on the fin body 14 by a separate deposition process, so that only the fin 12 can protrude above the substrate 11. Therefore, the effects on the fin body 14 and fin 12 caused by the different stress characteristics of the fin body 14 and fin 12 made of different materials can be minimized. That is, the problem of the stress of the fin 12, which serves as the source / drain region SD, being reduced by the material of the fin body 14 or impurities unnecessarily doped into the fin body 14 can be minimized.

[0083] Therefore, in this embodiment, a high-performance device can be achieved by applying sufficient stress to improve device performance.

[0084] Although this disclosure has been shown and described with reference to specific embodiments thereof, the invention is not limited thereto. Those skilled in the art will readily understand that various changes or modifications can be made thereto without departing from the scope of this disclosure.

Claims

1. A semiconductor device, comprising: Multiple isolation layers, each of the isolation layers including a trench formed in a substrate and an air gap in the lower part of the trench; An active region includes fins disposed between continuously disposed isolation layers and fins formed on the fins, the fins having a width narrower than the fins and extending in a first direction; A gate structure that partially covers the active region and the isolation layer and extends in a second direction; as well as Source / drain regions that cover the fins on both sides of the gate structure.

2. The semiconductor device according to claim 1, wherein, Each of the isolation layers also includes a covering layer over the air gap.

3. The semiconductor device according to claim 2, wherein, The capping layer comprises silicon oxide with poor step coverage.

4. The semiconductor device according to claim 2, wherein, The capping layer is one of undoped silicate glass oxide, tetraethyl orthosilicate oxide, or high-density plasma oxide.

5. The semiconductor device according to claim 1, wherein, The width of each isolation layer is narrower than the width of the fin.

6. The semiconductor device according to claim 1, wherein, The upper surface of the fin is at the same level as the upper surface of each of the isolation layers.

7. The semiconductor device according to claim 1, wherein, The upper surface of the fin is at a higher level than the upper surface of the isolation layer.

8. The semiconductor device according to claim 1, wherein, The fin body and the fin are made of different materials.

9. The semiconductor device according to claim 1, wherein, The fin / fin body stacked structure is one of the following semiconductor material stacked structures: SiGe / Si, Ge / Si, high-concentration SiGe / low-concentration SiGe, GeSn / Ge, and Sn / Ge.

10. The semiconductor device according to claim 1, wherein, The source / drain region includes the fins located on both sides of the gate structure and the epitaxial layer grown from the fins.

11. The semiconductor device according to claim 10, wherein, The epitaxial layer is formed by selective epitaxial growth.

12. The semiconductor device according to claim 10, wherein, The epitaxial layer comprises the same material as the fin.

13. The semiconductor device according to claim 10, wherein, The source / drain region also includes impurities doped in the fin and the epitaxial layer.

14. The semiconductor device according to claim 1, wherein, The first direction and the second direction intersect perpendicularly.

15. A method for manufacturing a semiconductor device, the method comprising: A superimposed structure of fins and sacrificial patterns is formed on the substrate; Sacrificial spacers are formed on both sides of the stacked structure; Separation trenches are formed by etching the exposed portions of the substrate between the continuously arranged sacrificial spacers; as well as An isolation layer is formed in the separating trench, the isolation layer including an air gap and a covering layer.

16. The method according to claim 15, wherein, The capping layer comprises silicon oxide with poor step coverage.

17. The method according to claim 15, wherein, The capping layer is selected from undoped silicate glass oxide, tetraethyl orthosilicate oxide, or high-density plasma oxide.

18. The method according to claim 15, wherein, Each of the sacrificial spacers comprises a material that is etch-selective relative to the substrate.

19. The method according to claim 15, wherein, Each of the sacrificial spacers comprises a nitride or an oxide.

20. The method of claim 15, wherein, Each of the sacrificial spacers comprises an insulating material selected from SiO2, SiON, SiBN, and SiBCN.

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