Semiconductor memory device

Abstract

Embodiments of the present invention provide a semiconductor memory device with high reliability without degrading the voltage controllability of word lines. One embodiment of the semiconductor memory device includes: a plurality of conductive layers stacked together in a first direction and spaced apart from each other; and a contact plug connected to a first conductive layer, which is one of the plurality of conductive layers; wherein the first conductive layer has: a first portion; a second portion spaced apart from the first portion in a second direction orthogonal to the first direction; and a third portion located between the first portion and the second portion. The semiconductor memory device includes a third region comprising a third portion and a plurality of third pillars extending along a first direction and having an insulating material therein; and the third region includes a fourth region and a fifth region; the third portion connects the first portion and the second portion in the fourth region; the third portion is connected to the contact plug in the fifth region; the width of the fourth pillar disposed in the fourth region, or the width of at least a portion of the fifth pillar disposed in the fourth region, in a third direction intersecting the first and second directions, is less than the width of the sixth pillar disposed in the fifth region in the third direction.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-017321 (filed on February 5, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] Semiconductor memory devices such as NAND (Not-And) flash memory sometimes have a three-dimensional array of memory cells. For such arrays, high reliability is required without compromising the voltage controllability of the word lines. Summary of the Invention

[0005] The embodiment provides a semiconductor memory device that achieves high reliability without compromising the voltage controllability of word lines.

[0006] A semiconductor memory device according to one embodiment includes: a plurality of conductive layers stacked together in a first direction and spaced apart from each other; and a contact plug connected to a first conductive layer, which is one of the plurality of conductive layers; wherein the first conductive layer has: a first portion; a second portion spaced apart from the first portion in a second direction orthogonal to the first direction; and a third portion located between the first portion and the second portion; and the semiconductor memory device includes: a first region including the first portion and a first pillar extending in the first portion along the first direction and having a semiconductor material, wherein the portion of the first portion opposite to the first pillar functions as a first memory cell; and a second region including the second portion and having a semiconductor material extending in the second portion along the first direction. The second post, and the portion of the second part opposite to the second post, functions as a second storage unit; and the third region, comprising the third part and a plurality of third posts extending along the first direction and having insulating material in the third part; and the third region comprising a fourth region and a fifth region; the third part connecting the first part and the second part in the fourth region; the third part connecting the contact plug in the fifth region; the width of the fourth post disposed in the fourth region among the plurality of third posts, or the width of at least a portion of the fifth post disposed in the fourth region among the plurality of third posts, in a third direction intersecting the first direction and the second direction, is less than the width of the sixth post disposed in the fifth region among the plurality of third posts in the third direction. Attached Figure Description

[0007] Figure 1 This is a perspective view illustrating the semiconductor device of the first embodiment.

[0008] Figure 2 This is a top view representing a stacked volume.

[0009] Figure 3 This is a cross-sectional view representing an example of a three-dimensional storage unit.

[0010] Figure 4 This is a cross-sectional view representing an example of a three-dimensional storage unit.

[0011] Figure 5 This is a top view showing an example of the semiconductor device according to the first embodiment.

[0012] Figure 6 It is a top-down view showing the layout of the connection area and storage unit area.

[0013] Figure 7A It is a three-dimensional diagram showing the general layout of the connected regions of block BLK.

[0014] Figure 7B It is a three-dimensional diagram showing the general layout of the connected regions of block BLK.

[0015] Figure 8A It is a top view that shows the several conductive layers of the connection area in more detail.

[0016] Figure 8B It is a top view that shows the several conductive layers of the connection area in more detail.

[0017] Figure 9A yes Figure 8A An enlarged top view of the dashed box B.

[0018] Figure 9B This is a top view showing an example of a bridging region with two rows of insulator posts.

[0019] Figure 10 It is along Figure 9A or Figure 9B A sectional view along line 10-10.

[0020] Figure 11 This is a top view showing the connection area of ​​the second embodiment.

[0021] Figure 12 This is a top view showing the connection area of ​​the third embodiment.

[0022] Figure 13 This is a top view showing the connection area of ​​the fourth embodiment.

[0023] Figure 14This is a top view showing the connection area of ​​the fifth embodiment.

[0024] Figure 15 This is a top view showing the connection area of ​​the sixth embodiment.

[0025] Figure 16 This is a top view showing the connection area of ​​the seventh embodiment.

[0026] Figure 17 This is a diagram illustrating an example of combining the second and seventh embodiments.

[0027] Figure 18 This is a diagram illustrating an example of combining the third and seventh embodiments.

[0028] Figure 19 This is a diagram illustrating an example of combining the fourth and seventh embodiments.

[0029] Figure 20 This is a diagram illustrating an example of combining the fifth and seventh embodiments.

[0030] Figure 21 This is a block diagram illustrating a configuration example of a semiconductor memory device applying any of the embodiments described above.

[0031] Figure 22 This is a circuit diagram illustrating an example of the circuit configuration of a memory cell array. Detailed Implementation

[0032] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. In the following embodiments, the vertical direction of the semiconductor substrate refers to the relative direction when the surface on which the semiconductor element is disposed is facing upwards, and may sometimes differ from the vertical direction according to gravitational acceleration. The accompanying drawings are schematic diagrams or conceptual diagrams, and the proportions of the parts may not be the same as those of the actual object. In the specification and drawings, elements identical to those described in the accompanying drawings above are labeled with the same symbols, and detailed descriptions are appropriately omitted.

[0033] (First Embodiment)

[0034] Figure 1 This is a perspective view illustrating the semiconductor memory device 100 of the first embodiment. Figure 2 This is a top view showing laminate 2. In this specification, the lamination direction of laminate 2 is defined as the Z-axis direction. One direction orthogonal to the Z-axis direction is defined as the Y-axis direction. The direction orthogonal to both the Z and Y axes is defined as the X-axis direction. Figure 3 and Figure 4 These are cross-sectional views of an example of a three-dimensional storage unit. Figure 5This is a top view showing an example of the semiconductor memory device 100 according to the first embodiment. For example... Figures 1-5 As shown, the semiconductor memory device 100 of the first embodiment is a non-volatile memory having a three-dimensional memory cell array.

[0035] The semiconductor memory device 100 includes a substrate 1, a laminate 2, a plate-shaped portion 3, a plurality of columnar portions CL, and a plurality of insulating columns CLHR.

[0036] The substrate 1 includes a semiconductor wafer (substrate) 10, an insulating film 11, a conductive film 12, and a semiconductor portion 13. The insulating film 11 is disposed on the semiconductor wafer 10. The conductive film 12 is disposed on the insulating film 11. The semiconductor portion 13 is disposed on the conductive film 12. The semiconductor wafer 10 is, for example, a silicon wafer. The conductivity type of the semiconductor wafer 10 is, for example, p-type. A device separation region 10i is, for example, disposed on the surface region of the semiconductor wafer 10. The device separation region 10i is, for example, an insulating region containing a silicon oxide film, and an active region AA is defined on the surface region of the semiconductor wafer 10. The source and drain regions of a transistor Tr are disposed in the active region AA. The transistor Tr constitutes a CMOS (Complementary Metal Oxide Semiconductor) circuit as a control circuit for non-volatile memory. The insulating film 11, for example, contains a silicon oxide film and insulates the transistor Tr. A wiring 11a is disposed within the insulating film 11. The wiring 11a is electrically connected to the transistor Tr. The conductive film 12 contains a conductive metal, such as tungsten (W). The semiconductor portion 13 contains, for example, n-type silicon. A portion of the semiconductor portion 13 may also contain undoped silicon.

[0037] The stacked body 2 is positioned above the semiconductor section 13 in the Z-axis direction. The stacked body 2 is constructed by alternately stacking multiple conductive layers 21 (as multiple first conductive layers) and multiple insulating layers 22 (as multiple first insulating layers) in the Z-axis direction. The conductive layers 21 are stacked with insulating layers 22 spaced apart from each other. The conductive layers 21 contain a conductive metal, such as tungsten. The insulating layers 22 contain, for example, silicon oxide. The insulating layers 22 insulate the conductive layers 21 from each other. The number of conductive layers 21 and insulating layers 22 is arbitrary. The insulating layers 22 may also be gaps, for example. An insulating film 2g is provided between the stacked body 2 and the semiconductor section 13, for example. The insulating film 2g may contain, for example, a silicon oxide film. The insulating film 2g may also contain a high dielectric material with a higher relative dielectric constant than silicon oxide. The high dielectric material may also be an oxide, such as a hafnium oxide film.

[0038] The conductive layer 21 includes at least one source-side selected gate (SGS), multiple word lines (WL), and at least one drain-side selected gate (SGD). The source-side selected gate (SGS) is the gate electrode of the source-side selected transistor (STS). The word line (WL) is the gate electrode of the memory cell (MC). The drain-side selected gate (SGD) is the gate electrode of the drain-side selected transistor (STD). The source-side selected gate (SGS) is disposed in the lower region of the stacked layer 2. The drain-side selected gate (SGD) is disposed in the upper region of the stacked layer 2. The lower region refers to the region of the stacked layer 2 closest to the substrate portion 1, and the upper region refers to the region of the stacked layer 2 furthest from the substrate portion 1. The word line (WL) is disposed between the source-side selected gate (SGS) and the drain-side selected gate (SGD).

[0039] The thickness of the insulating layer 22 that insulates the source-side select gate SGS from the word line WL in the Z-axis direction among the multiple insulating layers 22 can, for example, be thicker than the thickness of the insulating layer 22 that insulates the word lines WL from each other in the Z-axis direction. Furthermore, a cover insulating film may be provided on the uppermost insulating layer 22 that is furthest from the substrate portion 1. The cover insulating film may, for example, contain silicon oxide.

[0040] Semiconductor memory device 100 has multiple memory cells MC connected in series between a source-side selection transistor STS and a drain-side selection transistor STD. The structure formed by connecting the source-side selection transistor STS, memory cells MC, and drain-side selection transistor STD in series is called a "memory string" or "NAND string". The memory string is connected to a bit line BL, for example, via a contact Cb. The bit line BL is positioned above the stack 2 and extends along the Y-axis.

[0041] The laminate 2 contains multiple deep slits (ST) and multiple shallow slits (SHE). For example... Figure 2 As shown, the slit ST extends along the X-axis in the planar layout. In addition, in the cross-section of the Z-direction (lamination direction), the slit ST extends from the upper end of the laminate 2 through the laminate 2 to the substrate 1 and is disposed within the laminate 2. Figure 2 A plate-shaped portion 3 is disposed within the slit ST. The plate-shaped portion 3 may be an insulating film, such as a silicon oxide film. Alternatively, the plate-shaped portion 3 may be made of a conductive metal, such as a conductive material (e.g., tungsten, copper), which is electrically connected to the semiconductor portion 13, and is electrically insulated from the laminate 2 by the insulating film. The slit SHE extends approximately parallel to the slit ST along the X-axis in a planar layout. Furthermore, in a cross-section along the Z-direction, the slit SHE extends from the upper end of the laminate 2 to the middle of the laminate 2. An insulator 4 is disposed within the slit SHE, for example. The insulator 4 may be an insulating film, such as a silicon oxide film.

[0042] like Figure 2As shown, the stacked layer 2 includes a stepped portion 2s and a memory cell array (MCA). The stepped portion 2s is disposed at the edge of the stacked layer 2. The memory cell array (MCA) is sandwiched or surrounded by the stepped portion 2s. A slit ST extends from the stepped portion 2s at one end of the stacked layer 2, through the memory cell array (MCA), to the stepped portion 2s at the other end of the stacked layer 2. The slit ST is disposed at least within the memory cell array (MCA).

[0043] The portion of the stacked material 2 sandwiched between two slits ST (plate-like portions 3) is called a block BLK. A block, for example, constitutes the smallest unit for data erasure. Slit SHE (insulator 4) is disposed within the block. The stacked material 2 between the slits ST and SHE is called a finger. A drain-side select gate SGD is separated for each finger. Therefore, during data writing and reading, the drain-side select gate SGD can be used to select one finger within the block.

[0044] like Figure 5 As shown, the memory cell array (MCA) includes cell regions and other areas. Within a cell region, multiple columnar sections (CLs) are disposed within memory apertures (MH). In the areas outside the cell regions, tap regions (Tap), stepped areas (SSAs), and bridging areas (BRAs) are disposed. The tap regions (Tap) are located in blocks (BLKs) adjacent to the stepped areas (SSAs) and bridging areas (BRAs) in the Y direction, separated by a slit (ST). Figure 6 As shown, the tap area (Tap) can be positioned between the element areas in the X direction. The stepped area (SSA) and bridging area (BRA) can also be positioned between the element areas in the X direction. The stepped area (SSA) is an area with multiple contact plugs (CC). For example... Figure 6 As shown, the bridging region BRA is provided to electrically connect the wiring layers of word lines WL of adjacent blocks BLK in the X direction, separated by the step region SSA. The tap region Tap is the area where contact plugs C4 are provided. Contact plugs CC and C4 each extend, for example, along the Z-axis direction. Contact plug CC is electrically connected to, for example, conductive layer 21. Contact plug C4 is electrically connected to, for example, wiring 11a to supply power to transistor Tr. Contact plugs CC and C4 are made of, for example, low-resistance metals such as copper or tungsten. The bridging region BRA is defined for at least the uppermost word line WL, and more specifically, the topmost word line WL.

[0045] Insulating films (not shown) are provided around the contact plugs CC and C4, respectively. This provides electrical insulation between the contact plugs CC and C4 and the laminate 2. Thus, while maintaining insulation from the laminate 2, the contact plugs CC and C4 can electrically connect wiring above the laminate 2 to wiring below the laminate 2. The insulating films may be, for example, silicon oxide films.

[0046] Multiple columnar portions CL are respectively disposed within memory vias MH provided within the stacked body 2. The memory vias MH extend from the top end of the stacked body 2 along the stacking direction (Z-axis direction) of the stacked body 2, penetrating the stacked body 2 and extending into the stacked body 2 and the semiconductor portion 13. For example... Figure 3 and Figure 4 As shown, the plurality of columnar portions CL each include a semiconductor body 210, a memory film 220, and a core layer 230, which serve as semiconductor pillars. The semiconductor body 210 extends within the stacked body 2 along the stacking direction (Z direction) of the stacked body 2. The semiconductor body 210 is electrically connected to the semiconductor portion 13. The memory film 220 has a charge trapping portion between the semiconductor body 210 and the conductive layer 21. The portion of the conductive layer 21 facing the semiconductor body 210 functions as a memory cell. One columnar portion CL is selected from each finger portion, and the selected plurality of columnar portions CL are connected to a bit line BL via a contact Cb. The columnar portions CL are respectively provided, for example... Figure 5 Within the cell region.

[0047] like Figure 3 and Figure 4 As shown, the shape of the memory aperture MH in the XY plane is, for example, a circle or an ellipse. A barrier insulating film 21a, constituting part of the memory film 220, may be disposed between the conductive layer 21 and the insulating layer 22. The barrier insulating film 21a is, for example, a silicon oxide film or a metal oxide film. An example of a metal oxide is aluminum oxide. A barrier film 21b may be disposed between the conductive layer 21 and the insulating layer 22, and between the conductive layer 21 and the memory film 220. The barrier film 21b, for example, is a multilayer structure film of titanium nitride and titanium when the conductive layer 21 is tungsten. The barrier insulating film 21a suppresses reverse tunneling of charge from the conductive layer 21 to the memory film 220 side. The barrier film 21b improves the adhesion between the conductive layer 21 and the barrier insulating film 21a.

[0048] The semiconductor body 210 is, for example, cylindrical in shape. The semiconductor body 210 contains, for example, silicon. The silicon is, for example, polycrystalline silicon formed by crystallizing amorphous silicon. The semiconductor body 210 is, for example, undoped silicon. Alternatively, the semiconductor body 210 may also be p-type silicon. The semiconductor body 210 serves as the channel for the drain-side selection transistor (STD), the memory cell (MC), and the source-side selection transistor (STS).

[0049] The portion of the memory film 220, excluding the barrier insulating film 21a, is disposed between the inner wall of the memory aperture MH and the semiconductor body 210. The memory film 220 is, for example, cylindrical. Multiple memory cells MC have storage regions between the semiconductor body 210 and the conductive layer 21, which forms the word line WL, and are stacked in the Z-axis direction. The memory film 220 includes, for example, a covering insulating film 221, a charge trapping film 222, and a tunnel insulating film 223. The semiconductor body 210, the charge trapping film 222, and the tunnel insulating film 223 each extend along the Z-axis direction.

[0050] An insulating film 221 is disposed between the insulating layer 22 and the charge trapping film 222. The insulating film 221 may be, for example, silicon oxide. The insulating film 221 is provided to protect the charge trapping film 222 from etching when the sacrificial film disposed between the insulating layers 22 is replaced with the conductive layer 21 during the manufacturing process. The insulating film 221 may also be removed from between the conductive layer 21 and the memory film 220 during the replacement step. In this case, such as Figure 3 and Figure 4 As shown, a barrier insulating film 21a is provided, for example, between the conductive layer 21 and the charge trapping film 222. Alternatively, if a replacement step is not used when forming the conductive layer 21, the covering insulating film 221 may not be provided.

[0051] A charge trapping film 222 is disposed between the barrier insulating film 21a, the covering insulating film 221, and the tunnel insulating film 223. The charge trapping film 222, for example, comprises silicon nitride and has trapping portions that trap charges within the film. The portion of the charge trapping film 222 sandwiched between the conductive layer 21 (which forms the word line WL) and the semiconductor body 210 constitutes the storage region of the memory cell MC as a charge trapping section. The threshold voltage of the memory cell MC varies depending on whether there is charge in the charge trapping section or the amount of charge trapped in the charge trapping section. Thus, the memory cell MC can store information.

[0052] A tunnel insulating film 223 is disposed between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating film 223 may be made of silicon oxide, or silicon oxide and silicon nitride, for example. The tunnel insulating film 223 acts as a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor body 210 into the charge trapping section (writing operation) and when holes are injected from the semiconductor body 210 into the charge trapping section (erasing operation), electrons and holes respectively pass through (tunnel) the potential barrier of the tunnel insulating film 223.

[0053] The core layer 230 embeds the internal space of the cylindrical semiconductor body 210. The core layer 230 is, for example, columnar. The core layer 230 uses an insulating film such as silicon oxide film.

[0054] Figure 5 Multiple insulating pillars CLHR shown are respectively disposed within holes HR provided in the laminate 2. The holes HR extend from the upper end of the laminate 2 along the Z-axis, penetrating the laminate 2 and extending into the laminate 2 and the semiconductor section 13. The insulating pillars CLHR are, for example, made of an insulating material such as a silicon oxide film. Furthermore, each insulating pillar CLHR may have the same structure as the columnar portion CL. Each insulating pillar CLHR is disposed, for example, in the tap region, the stepped region SSA, and the bridging region BRA. When the sacrificial film (not shown) is replaced with the conductive layer 21 (replacement step), the insulating pillars CLHR function as support members to retain the gaps formed in the stepped region and the tap region. The holes HR of the insulating pillar CLHR have a larger diameter (width in the X or Y direction) than the columnar portion CL.

[0055] like Figure 1 As shown, the semiconductor memory device 100 further includes a semiconductor section 14. The semiconductor section 14 is located between the stacked layer 2 and the semiconductor section 13. The semiconductor section 14 is disposed between the insulating layer 22 closest to the semiconductor section 13 and the insulating film 2g. The conductivity type of the semiconductor section 14 is, for example, n-type. The semiconductor section 14 functions, for example, as a source-side select gate (SGS).

[0056] Figure 6 This is a schematic top view showing the layout of the connection area 101 and the storage cell area 100a. The storage cell area 100a includes two adjacent storage cell areas, a first storage cell area 100a_1 and a second storage cell area 100a_2. The first storage cell area 100a_1 and the second storage cell area 100a_2 each contain multiple blocks BLK. In the Y direction, the multiple blocks BLK are respectively separated by slits ST extending along the X direction.

[0057] Both the first storage cell region 100a_1 and the second storage cell region 100a_2 have the plurality of columnar portions CL (memory holes MH) and have a plurality of storage cells arranged in three dimensions. The storage cells are formed at the intersections of a plurality of word lines WL and columnar portions CL.

[0058] For convenience, the block BLK belonging to the first storage unit area 100a_1 will be denoted as block BLK_1. Similarly, the block BLK belonging to the second storage unit area 100a_2 will be denoted as block BLK_2.

[0059] The connection region 101 is located in the X direction, which intersects the Z direction, between the first storage cell region 100a_1 and the second storage cell region 100a_2. Each block BLK has a tap region (Tap), a step region (SSA), and a bridging region (BRA). The step region (SSA) and the bridging region (BRA) are also referred to as step regions (SSA), etc., in the following text.

[0060] As described above, the tap area (Tap) and the stepped area (SSA), etc., are adjacent in the Y direction, separated by a slit (ST). Figure 6 As shown, the tap area and the stepped area SSA are alternately arranged in the Y direction. Additionally, although not shown, the tap area and the stepped area SSA are also alternately arranged in the X direction. That is, the tap area and the stepped area SSA are alternately arranged in the Y direction separated by a slit ST, and alternately arranged in the X direction separated by a memory area Cell (block BLK).

[0061] In the stepped region SSA, the select gate line (source-side select gate) SGS and multiple word lines WL each have a stepped shape formed by sequentially setting a step difference in the X direction from the lower layer. In other words, in the stepped region SSA, the select gate line SGS and multiple word lines WL each have a stepped portion (also called a step, stepped section, or lead-out section) at their ends that does not overlap with the lower wiring layer (conductive layer). On each stepped portion are formed... Figure 5 The contact plug CC. The select gate line SGS and multiple word lines WL can be voltaged separately via the contact plug CC. In this way, the stepped region SSA is configured as a stepped region, which is used to connect multiple contacts to multiple conductive layers connected to the select gate line SGS and multiple word lines WL respectively.

[0062] In addition, the contact plug CC is electrically connected to the upper wiring (not shown) via the upper layer wiring. Figure 5 The contact plug C4 in the tap area is electrically connected to the line decoder located below the memory cell array via the contact plug C4. Thus, the line decoder can control the voltage of each conductive layer 21 (word line WL) via the contact plug CC. The diameters of the contact plugs CC and C4 are larger than the diameter of the insulator post CLHR.

[0063] In the bridging region BRA, multiple third conductive layers, each corresponding to the select gate line SGS and multiple word lines WL, are deposited at intervals along the Z direction. These third conductive layers electrically connect the conductive layers 21 (select gate line SGS and multiple word lines WL) of the first memory cell region 100a_1 to the conductive layers 21 (select gate line SGS and multiple word lines WL) of the second memory cell region 100a_2. Therefore, the first and second memory cell regions 100a_1 and 100a_2 can function as a single memory cell array (MCA).

[0064] In this way, by arranging the connection region 101 in the middle of the memory cell array MCA, the contact plug CC can be located in the middle of the word line WL wiring, thereby shortening the distance from the contact plug CCa to the end of the word line WL. As a result, the semiconductor memory device 100 can quickly supply power to the end of the word line WL via the contact plug CC, thus making it easier to control the voltage of the word line WL. Furthermore, since memory cell regions 100a_1 and 100a_2 can be arranged on both sides of a single connection region 101, operating speed can be maintained, and the size (memory capacity) of the memory cell array MCA can be increased.

[0065] The bridging region BRA has the same stacked structure as the first and second memory cell regions 100a_1 and 100a_2. Therefore, the stacked structure of the bridging region BRA is formed by alternately stacking multiple conductive layers 21 and multiple insulating layers 22 in the Z-axis direction. That is, the multiple conductive layers 21, which are multiple third conductive layers, are stacked at intervals separated from each other by insulating layers 22. The insulating layer 22 may also be an air gap, as described above.

[0066] Figure 7A and Figure 7B This is a perspective view showing the general layout of the connection area 101 of a certain BLK. The stepped area SSA of the connection area 101 is set in a stepped shape to connect multiple contact plugs CC to each of multiple conductive layers 21 (word lines WL). In the bridging area BRA, multiple conductive layers 21 electrically connect the conductive layers 21 (word lines WL) of the first and second memory cell areas 100a_1 and 100a_2.

[0067] The bridging region BRA is located within the connection region 101, adjacent to the stepped region SSA in the Y direction (a direction substantially perpendicular to the extension direction of the slit ST), and is not etched into a stepped shape. Therefore, the bridging region BRA has the same number of conductive layers 21 and the same number of insulating layers 22 as the stacked layers 2 of the first and second memory cell regions 100a_1 and 100a_2.

[0068] Figure 8A and Figure 8B This is a top view showing in more detail the conductive layers 21 of the connection region 101. Figure 8A This indicates the stacking state of conductive layer 21. Figure 8B The layers of conductive layer 21 are shown separately. Figure 8A and Figure 8B The diagram shows five conductive layers 21. Of course, the number of conductive layers 21 can be four or fewer, or six or more. Furthermore, in... Figure 8A and Figure 8B The image shows a single block BLK section, with details omitted. Figure 5The diagram shows the columnar section CL (memory hole MH), the insulator column CLHR, and the slit SHE.

[0069] like Figure 8A As shown, the stepped region SSA of the connection region 101 is formed in a stepped shape such that the surfaces (steps) of each conductive layer 21 are visible from the Z direction. The surface (step) of each conductive layer 21 has a width (area) sufficient for the contact plug CC to connect from the Z direction. Figure 8A In the stepped area SSA, the stepped sections are arranged in an opposing manner on both sides of the connecting area 101 in the X direction. For example... Figure 8A and Figure 8B As shown, one contact plug CC is provided in each layer of the conductive layer 21 of the stepped region SSA, and is connected to the stepped surface of the conductive layer 21. For example, in Figure 8A and Figure 8B In the example shown, the contact plug CC is alternately connected to the left and right steps of the stepped region SSA. More specifically, in the uppermost conductive layer 21, the contact plug CC is connected to the step surface of the left step of the stepped region SSA. In the second conductive layer 21, the contact plug CC is connected to the step surface of the right step of the stepped region SSA. In the third conductive layer 21, the contact plug CC is connected to the step surface of the left step of the stepped region SSA. In the fourth conductive layer 21, the contact plug CC is connected to the step surface of the right step of the stepped region SSA. In the fifth (lowest) conductive layer 21, the contact plug CC is connected to the step surface of the left step of the stepped region SSA.

[0070] Alternatively, the stepped area SSA may be provided only on one side of the connection area 101 in the X direction. In this case, the contact plug CC is connected to the stepped surface of the stepped portion provided on one side of the connection area 101.

[0071] Since one contact plug CC is provided in each of the conductive layers 21, the conductive layer 21 of the memory cell region not connected to the contact plug CC is electrically connected to the contact plug CC via the bridging region BRA. For example, no contact plug CC is provided in the uppermost conductive layer 21 of the right second memory cell region 100a_2. Therefore, the uppermost conductive layer 21 of the right second memory cell region 100a_2 is electrically connected to the contact plug CC provided in the uppermost conductive layer 21 of the left second memory cell region 100a_2 via the uppermost conductive layer 21 of the bridging region BRA. In addition, no contact plug CC is provided in the second conductive layer 21 of the left second memory cell region 100a_2. Therefore, the second conductive layer 21 of the left second memory cell region 100a_2 is electrically connected to the contact plug CC provided in the second conductive layer 21 of the right second memory cell region 100a_2 via the second conductive layer 21 of the bridging region BRA. In this manner, one of the memory cell regions 100a_1 and 100a_2 located on both sides of the connection region 101 is electrically connected to a contact plug CC disposed in the other memory cell region via a bridging region BRA. Therefore, if the resistance of each conductive layer 21 of the bridging region BRA becomes high, the voltage controllability of the memory cell regions 100a_1 and 100a_2 deteriorates. Therefore, each conductive layer 21 of the bridging region BRA is preferably low in resistance. That is, a bridging region BRA with a width W in the Y direction is preferred.

[0072] On the other hand, if the width W in the Y direction of the bridging region BRA is increased, the stepped region SSA will become narrower. In this case, the stepped region SSA is narrowed while maintaining the Z-direction recess depth, resulting in a higher aspect ratio. Therefore, when the stepped region SSA is embedded using a silicon oxide film (e.g., TEOS (Tetraethyl orthosilicate)), porosity may be generated within the silicon oxide film. In this case, there is a concern that contact plugs CC may short-circuit with other contact plugs CC through these porosity.

[0073] Therefore, in this embodiment, as Figure 9A or Figure 9B As shown, change the size or configuration of the insulator post CLHR in the connection area 101.

[0074] Figure 9A yes Figure 8A An enlarged top view of the dashed box B. Figure 9A The diagram shows... Figure 5The insulating pillars CLHR shown are multiple insulating pillars extending along the stacking direction (Z direction) within the stacked body of the conductive layer 21 of the bridging region BRA and the stepped region SSA of the connection region 101. Figure 9A For convenience, the insulator post CLHR located in the bridging region BRA is referred to as CLHR_1, and the insulator post CLHR located in the step region SSA is referred to as CLHR_2. When defining CLHR_1 and CLHR_2, at least the bridging region BRA and step region SSA associated with the uppermost word line WL must be used. More specifically, when defining CLHR_1 and CLHR_2, for example, the bridging region BRA and step region SSA associated with the uppermost word line may be used.

[0075] In this embodiment, the insulator pillars CLHR are arranged in a staggered manner (in a hexagonal lattice). However, the arrangement of the insulator pillars CLHR is not limited to this; for example, they can also be arranged in a square lattice or a rectangular lattice.

[0076] The stacked body of storage cell regions 100a_1, 100a_2 and connection region 101 is formed by first forming a stacked body of insulating layer 22 (e.g., silicon oxide film) and sacrificial film (e.g., silicon nitride film), and then replacing the sacrificial film (not shown) with conductive layer 21 (e.g., tungsten). During the replacement step of replacing the sacrificial film with conductive layer 21, gaps are formed between the insulating layers 22 for embedding the conductive layer 21. Insulator pillars CLHR function as support members to maintain these gaps between the insulating layers 22 formed in the connection region 101. Without insulator pillars CLHR, there is a concern that the insulating layers 22 might bend or collapse under their own weight due to lack of support. Therefore, the insulator pillars CLHR are arranged approximately evenly in the connection region 101. Thus, during the step of replacing the sacrificial film with conductive layer 21, the insulator pillars CLHR can support the insulating layers 22 and maintain the gaps between the insulating layers 22.

[0077] In this embodiment, when viewed from the stacking direction (Z direction) of the conductive layer 21, the diameter R1 of the insulating pillar CLHR_1 disposed in the bridging region BRA is smaller than the diameter R2 of the insulating pillar CLHR_2 disposed in the stepped region SSA. Therefore, the resistance value of the conductive layer 21 in the bridging region BRA can be reduced without widening the width WBRA of the conductive layer 21 in the bridging region BRA. By reducing the resistance value of the conductive layer 21 in the bridging region BRA, it becomes easier to control the voltage of the conductive layer 21 (word line WL) of the first and second memory cell regions 100a_1 and 100a_2 via the contact plug CC. As a result, the read, write, and erase operations of the selected memory cell can be performed at high speed. Furthermore, the diameter R1 of the insulating pillar CLHR_1 only needs to be smaller than the diameter R2, and they can be different from each other.

[0078] also, Figure 9A In this configuration, only one column of insulator posts CLHR_1, arranged in the X direction extending from the bridging region BRA, overlaps with the bridging region BRA. However, multiple columns of insulator posts CLHR_1 may overlap with the bridging region BRA. For example, Figure 9B This is a top view showing an example of a bridging region BRA extending in the X direction and having two rows of insulator pillars CLHR_1. In this case, since the laminate 2 of the bridging region BRA is supported by multiple rows of insulator pillars CLHR_1, the conductive layer 21 of the laminate 2 can be supported more reliably. In addition, by making the diameter R1 of the multiple rows of insulator pillars CLHR_1 smaller than the diameter R2 of the insulator pillars CLHR_2 of the stepped region SSA, the resistance value of the bridging region BRA can be reduced.

[0079] Figure 10 It is along Figure 9A or Figure 9B A cross-sectional view along line 10-10 (Y direction). Figure 10 The diagram shows a stepped region SSA containing a contact plug CC and an insulator pillar CLHR_2, and a bridging region BRA containing an insulator pillar CLHR_1. The contact plug CC is located in a stepped region TRA within the stepped region SSA. In the stepped region TRA, the contact plug CC is connected to the underlying conductive layer 21. In both the stepped region SSA and the bridging region BRA, the insulator pillars CLHR_1 and CLHR_2 penetrate the laminate 2 of the conductive layer 21 in the Z-direction. In the stepped region SSA, the conductive layer 21 is formed in a stepped shape, with the relatively larger diameter insulator pillar CLHR_2 penetrating the stepped conductive layer 21. In the bridging region BRA, the conductive layer 21 is located at the top layer of the laminate 2, with the relatively smaller diameter insulator pillar CLHR_1 penetrating all the conductive layers 21 of the laminate 2.

[0080] In this way, by reducing the diameter R1 of the insulating pillar CLHR_1 of the bridging region BRA, the resistance value of the conductive layer 21 of the bridging region BRA can be reduced without increasing the width WBRA of the bridging region BRA. Furthermore, the diameter R1 of the insulating pillar CLHR_1 is preferably of a size sufficient to support the conductive layer 21 of the laminate 2. A suitable value for the diameter R1 varies depending on the number or thickness of the conductive layer 21.

[0081] If the width WBRA of the bridging region BRA is increased, the area of ​​the stepped region SSA will become narrower, making it easier for the silicon oxide film 150 embedded in the stepped region SSA to develop porosity. For example, if the stepped region SSA located in the middle portion of the memory cell array MCA is widened, the resistance of the bridging region BRA connecting the memory cell array MCAs on both sides of the stepped region SSA will increase, and the word line resistance will rise. Increased word line resistance may worsen the voltage controllability of the word line WL. On the other hand, if the stepped region SSA is narrowed to widen the bridging region BRA, there is a concern that porosity may develop in the silicon oxide film embedded in the stepped region SSA. This would lead to a decrease in the reliability of the semiconductor memory device.

[0082] In view of this, according to this embodiment, the resistance value of the conductive layer 21 of the bridging region BRA can be substantially reduced without widening the width WBRA of the bridging region BRA. Therefore, the formation of pores in the silicon oxide film 150 can be suppressed, and the voltage of the conductive layer 21 (word line WL) can be easily controlled.

[0083] (Second Implementation)

[0084] Figure 11 This is a top view showing the connection region 101 in the second embodiment. In the second embodiment, the diameter R1 of the insulator post CLHR_1, which at least partially overlaps with the bridging region BRA, is smaller than the diameter R2 of the insulator post CLHR_2 provided in the stepped region SSA. Figure 11In this embodiment, the first column of insulator pillars CLHR_1a arranged in the X direction completely overlaps with the bridging region BRA, and a portion of the second column of insulator pillars CLHR_1b adjacent to the first column of insulator pillars overlaps with the bridging region BRA. That is, when viewed from the Z direction, the second column of insulator pillars CLHR_1b is located at the interface between the bridging region BRA and the stepped region SSA. Therefore, the diameter R1 of the insulator pillars CLHR_1a included in the bridging region BRA and the diameter R1 of the insulator pillars CLHR_1b located at the interface between the bridging region BRA and the stepped region SSA are both smaller than the diameter R2 of the insulator pillar CLHR_2. This allows for a further reduction in the resistance value of the conductive layer 21 in the bridging region BRA without widening the width WBRA of the conductive layer 21 in the bridging region BRA. Furthermore, the diameters of the insulator pillars CLHR_1a and CLHR_1b only need to be smaller than the diameter R2, and can be different from each other. Other configurations in the second embodiment can be the same as the corresponding configuration in the first embodiment. Therefore, the second embodiment can also achieve the effects of the first embodiment.

[0085] In the second embodiment, a portion of the second row of insulator posts CLHR_1b overlaps at the boundary between the bridging region BRA and the stepped region SSA. However, the second row of insulator posts CLHR_1b may not overlap as long as it is located near the boundary between the bridging region BRA and the stepped region SSA. For example, assuming that the insulator posts CLHR_1b have the same diameter R2 as the insulator posts CLHR_2, the insulator posts CLHR_1b may sometimes overlap at the boundary between the bridging region BRA and the stepped region SSA. On the other hand, in this case, reducing the diameter of the insulator posts CLHR_1b may also result in a situation where the insulator posts CLHR_1b do not overlap at the boundary between the bridging region BRA and the stepped region SSA. In this case, the second row of insulator posts CLHR_1b is located near the boundary between the bridging region BRA and the stepped region SSA, but does not overlap.

[0086] (Third Implementation)

[0087] Figure 12 This is a top view showing the connection region 101 in the third embodiment. In the third embodiment, the diameter R1 of the insulator post CLHR_1b, which partially overlaps with the bridging region BRA, is smaller than the diameter R2 of the insulator post CLHR_2 provided in the stepped region SSA. On the other hand, in Figure 12In this embodiment, the diameter of all the insulating pillars CLHR_1a overlapping the bridging region BRA is approximately equal to the diameter R2 of the insulating pillars CLHR_2 of the stepped region SSA. Similarly, the diameter R1 of the insulating pillars CLHR_1b overlapping the interface between the bridging region BRA and the stepped region SSA can be reduced only. In this case, the resistance value of the conductive layer 21 of the bridging region BRA can be reduced to some extent without widening the width WBRA of the conductive layer 21. Other configurations in the second embodiment can be the same as the corresponding configuration in the first embodiment. Therefore, the second embodiment also achieves the effects of the first embodiment.

[0088] The third embodiment is similar to the second embodiment, in that the second column of insulator posts CLHR_1b is located near the junction between the bridging region BRA and the stepped region SSA, and does not overlap.

[0089] (Fourth implementation)

[0090] Figure 13 This is a top view showing the connection region 101 of the fourth embodiment. In the fourth embodiment, when viewed from the Z direction, the insulator column CLHR_1 that overlaps with the bridging region BRA is approximately elliptical in the extension direction of the bridging region BRA (i.e., the extension direction of the junction between the bridging region BRA and the stepped region SSA: the X direction). This major axis can be equal to or greater than the diameter R2 of the insulator column CLHR_2 of the stepped region SSA. On the other hand, the minor axis R1 of the insulator column CLHR_1 is smaller than the diameter R2 of the insulator column CLHR_2 provided in the stepped region SSA. As a result, the actual width of the conductive layer 21 of the bridging region BRA can be increased without increasing the width WBRA of the conductive layer 21 in the bridging region BRA, thereby further reducing the resistance value. Other configurations of the fourth embodiment can be the same as the corresponding configuration of the first embodiment. Therefore, the fourth embodiment can also obtain the effects of the first embodiment.

[0091] In addition, Figure 13 In this context, only one column of insulator posts CLHR_1 arranged in the X direction extending from the bridging region BRA overlaps with the bridging region BRA. However, as referenced... Figure 9B As explained, the insulator pillars CLHR_1 overlapping with the bridging region BRA can also be in multiple rows. In this case, since the laminate 2 of the bridging region BRA is supported by multiple rows of insulator pillars CLHR_1, the conductive layer 21 of the laminate 2 can be supported more reliably. In addition, by making the minor diameter R1 of the multiple rows of insulator pillars CLHR_1 smaller than the diameter R2 of the insulator pillars CLHR_2 of the stepped region SSA, the resistance value of the bridging region BRA can be reduced.

[0092] (Fifth Embodiment)

[0093] Figure 14 This is a top view showing the connection region 101 in the fifth embodiment. In the fifth embodiment, the insulator pillars CLHR_1a and CLHR_1b, which at least partially overlap with the bridging region BRA, are approximately elliptical in shape with a major axis in the extending direction of the bridging region BRA (i.e., the extending direction of the junction between the bridging region BRA and the stepped region SSA: the X direction). That is, the fifth embodiment is a combination of the second and fourth embodiments.

[0094] Figure 14 In this configuration, the first column of insulator posts CLHR_1a arranged in the X direction completely overlaps with the bridging region BRA, and a portion of the second column of insulator posts CLHR_1b adjacent to the insulator posts CLHR_1a also overlaps with the bridging region BRA. That is, when viewed from the Z direction, the second column of insulator posts CLHR_1b is located at the interface between the bridging region BRA and the stepped region SSA. Therefore, the minor diameter R1 of the insulator posts CLHR_1a included in the bridging region BRA and the minor diameter R1 of the insulator posts CLHR_1b located at the interface between the bridging region BRA and the stepped region SSA are both smaller than the diameter R2 of the insulator post CLHR_2.

[0095] The major axis of the insulator pillars CLHR_1a and CLHR_1b in the X direction can be equal to or greater than the diameter R2 of the insulator pillar CLHR_2 in the stepped region SSA. On the other hand, the minor axis R1 of the insulator pillars CLHR_1a and CLHR_1b in the Y direction is smaller than the diameter R2 of the insulator pillar CLHR_2 provided in the stepped region SSA. As a result, the actual width of the conductive layer 21 in the bridging region BRA can be increased without increasing the width WBRA of the conductive layer 21 in the bridging region BRA, thereby further reducing the resistance value. Other configurations of the fifth embodiment can be the same as the corresponding configuration of the first embodiment. Therefore, the fifth embodiment can also obtain the effects of the first embodiment.

[0096] In the fifth embodiment, a portion of the second row of insulator posts CLHR_1b overlaps at the boundary between the bridging region BRA and the stepped region SSA. However, the second row of insulator posts CLHR_1b may also be located near the boundary between the bridging region BRA and the stepped region SSA without overlapping. For example, assuming that the minor diameter of the insulator post CLHR_1b has the same diameter R2 as the insulator post CLHR_2, the insulator post CLHR_1b may sometimes overlap at the boundary between the bridging region BRA and the stepped region SSA. On the other hand, in this case, reducing the minor diameter of the insulator post CLHR_1b also results in a situation where the insulator post CLHR_1b does not overlap at the boundary between the bridging region BRA and the stepped region SSA. In this case, the second row of insulator posts CLHR_1b is located near the boundary between the bridging region BRA and the stepped region SSA, but without overlapping.

[0097] (Sixth Embodiment)

[0098] Figure 15 This is a top view showing the connection region 101 in the sixth embodiment. In the sixth embodiment, when viewed from the Z direction, the second row of insulator posts CLHR_1b is located near the boundary between the bridging region BRA and the stepped region SSA, but its position is offset towards the stepped region SSA. That is, the insulator posts CLHR_1b located near the boundary between the bridging region BRA and the stepped region SSA are positioned near the insulator posts CLHR_2 located in the stepped region SSA, compared to the insulator posts CLHR_1a located in the bridging region BRA. In other words, the spacing of the second row of insulator posts CLHR_1b deviates in the -Y direction. The spacing P1 between insulator posts CLHR_1b and CLHR_2 is narrower than the spacing P3 between insulator posts CLHR_1b and CLHR_1a. As a result, the second row of insulator posts CLHR_1b does not overlap with the bridging region BRA. Alternatively, the overlap between the second row of insulator posts CLHR_1b and the bridging region BRA becomes smaller. Furthermore, the distance P1 between the insulator pillar CLHR_1b and the adjacent insulator pillar CLHR_2 is narrower than the distance P2 between the insulator pillars CLHR_2. In this way, by causing a deviation in the spacing of the insulator pillars CLHR_1b near the interface between the bridging region BRA and the stepped region SSA, the resistance value of the conductive layer 21 in the bridging region BRA can be further reduced without widening the width WBRA of the conductive layer 21 in the bridging region BRA. Other configurations in the sixth embodiment can be the same as the corresponding configuration in the first embodiment. Therefore, the sixth embodiment also achieves the effects of the first embodiment.

[0099] (Seventh Embodiment)

[0100] Figure 16 This is a top view showing the connection region 101 of the seventh embodiment. In the seventh embodiment, when viewed from the Z direction, the second row of insulator posts CLHR_1b is located closest to the junction between the bridging region BRA and the stepped region SSA, but its position is offset towards the stepped region SSA and located within the stepped region SS. The first row of insulator posts CLHR_1a, which overlaps with the bridging region BRA, has a diameter R2 that is approximately the same as that of the insulator posts CLHR_2 in the stepped region SSA. Other configurations of the seventh embodiment are the same as the corresponding configuration of the sixth embodiment. Therefore, when viewed from the Z direction, the spacing P1 between the insulator post CLHR_1b located within the stepped region SSA and closest to the junction between the bridging region BRA and the stepped region SSA and the adjacent insulator post CLHR_2 is narrower than the spacing P2 between the insulator posts CLHR_2 located within the stepped region SSA and adjacent to the insulator post CLHR_1b. In addition, the spacing P1 is narrower than the spacing P3 between the insulator posts CLHR_1a and CLHR_1b located in the bridging region BRA.

[0101] In this case, by adjusting the spacing of the insulating pillars CLHR_1b located near the interface between the bridging region BRA and the stepped region SSA, the second row of insulating pillars CLHR_1b is made to not overlap with the bridging region BRA. Alternatively, the overlap between the second row of insulating pillars CLHR_1b and the bridging region BRA is reduced. Therefore, the resistance value of the conductive layer 21 in the bridging region BRA can be reduced to some extent without widening the width WBRA of the conductive layer 21 in the bridging region BRA.

[0102] (Example of variation)

[0103] The seventh embodiment can be combined not only with the first embodiment, but also with the second to fifth embodiments. For example, Figure 17 This diagram illustrates an example combining the second and seventh embodiments. Figure 17 When viewed from the Z direction, the diameter R1 of the first and second column insulator pillars CLHR_1a and CLHR_1b is smaller than the diameter R2 of the second column insulator pillar CLHR_2. Furthermore, the second column insulator pillar CLHR_1b is located near the interface between the bridging region BRA and the stepped region SSA, but its position is offset towards the stepped region SSA. Therefore, the resistance value can be further reduced without widening the width WBRA of the conductive layer 21 in the bridging region BRA.

[0104] For example, Figure 18 This diagram illustrates an example combining the third and seventh embodiments. Figure 18When viewed from the Z direction, the diameter of the first column of insulator pillars CLHR_1a is approximately equal to the diameter R2 of the second column of insulator pillars CLHR_2. However, the diameter R1 of the second column of insulator pillars CLHR_1b is smaller than the diameter R2 of the second column of insulator pillars CLHR_2, and the position of the second column of insulator pillars CLHR_1b is offset towards the stepped region SSA side. As a result, the second column of insulator pillars CLHR_1b no longer overlaps with the bridging region BRA. Alternatively, the overlap between the second column of insulator pillars CLHR_1a and the bridging region BRA becomes smaller. Therefore, it is possible to reduce the resistance of the conductive layer 21 of the bridging region BRA to some extent without widening the width WBRA of the conductive layer 21 in the bridging region BRA.

[0105] For example, Figure 19 This diagram illustrates an example combining the fourth and seventh embodiments. Figure 19 In the diagram, when viewed from the Z-direction, the insulator column CLHR_1a that overlaps with the bridging region BRA is approximately elliptical in the extension direction (X-direction) of the bridging region BRA. On the other hand, the minor axis R1 of insulator column CLHR_1a is smaller than the diameter R2 of insulator column CLHR_2 located in the stepped region SSA. The diameter of the second column insulator column CLHR_1b is approximately equal to the diameter R2 of insulator column CLHR_2, but the position of the second column insulator column CLHR_1b is offset towards the stepped region SSA. Therefore, the second column insulator column CLHR_1b no longer overlaps with the bridging region BRA. Alternatively, the overlap between the second column insulator column CLHR_1 and the bridging region BRA becomes smaller.

[0106] With this configuration, the resistance value of the conductive layer 21 in the bridging region BRA can be further reduced without increasing the width WBRA of the conductive layer 21 in the bridging region BRA.

[0107] For example, Figure 20 This diagram illustrates an example combining the fifth and seventh embodiments. Figure 20 In the diagram, when viewed from the Z-direction, both insulator pillars CLHR_1a and CLHR_1b are approximately elliptical in shape with a major axis in the extension direction (X-direction) of the bridging region BRA. Furthermore, the position of the second row of insulator pillars CLHR_1b is offset towards the stepped region SSA. Therefore, the second row of insulator pillars CLHR_1b no longer overlaps with the bridging region BRA. Alternatively, the overlap between the second row of insulator pillars CLHR_1a and CLHR_1b and the bridging region BRA is reduced.

[0108] With this configuration, the resistance value of the conductive layer 21 in the bridging region BRA can be further reduced without increasing the width WBRA of the conductive layer 21 in the bridging region BRA.

[0109] Figure 21 This is a block diagram illustrating a configuration example of a semiconductor memory device employing any of the embodiments described above. The semiconductor memory device 100 is a NAND flash memory capable of non-volatile data storage and is controlled by an external memory controller 1002. Communication between the semiconductor memory device 100 and the memory controller 1002 supports, for example, NAND interface standards.

[0110] like Figure 21 As shown, the semiconductor memory device 100 includes, for example, a memory cell array (MCA), an instruction register 1011, an address register 1012, a sequencer 1013, a driver module 1014, a line decoder module 1015, and a sense amplifier module 1016.

[0111] A memory cell array (MCA) comprises multiple blocks BLK(0) to BLK(n) (n being an integer greater than or equal to 1). A block BLK is a collection of multiple memory cells capable of non-volatile data storage, used for example as a data erasure unit. Additionally, the MCA includes multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed structure of the MCA will be described below.

[0112] Instruction register 1011 stores instructions (CMD) received by semiconductor memory device 100 from memory controller 1002. Instructions (CMD) contain commands, such as causing sequencer 1013 to perform read operations, write operations, erase operations, etc.

[0113] Address register 1012 stores address information ADD received by semiconductor memory device 100 from memory controller 1002. Address information ADD includes, for example, block address BAdd, page address PAdd, and column address CAdd. For example, block address BAdd, page address PAdd, and column address CAdd are used to select block BLK, word line, and bit line, respectively.

[0114] The sequencer 1013 controls the overall operation of the semiconductor memory device 100. For example, based on the instruction CMD stored in the instruction register 1011, the sequencer 1013 controls the driver module 1014, the line decoder module 1015, and the sense amplifier module 1016 to perform read operations, write operations, erase operations, etc.

[0115] The driver module 1014 generates the voltages used in read operations, write operations, erase operations, etc. Then, the driver module 1014 applies the generated voltages to the signal lines corresponding to the selected word lines, for example, based on the page address PAdd stored in the address register 1012.

[0116] The row decoder module 1015 has multiple row decoders RD. Based on the block address BAdd stored in the address register 1012, the row decoder RD selects one block BLK within the corresponding memory cell array MCA. Then, for example, the row decoder RD transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line within the selected block BLK.

[0117] During a write operation, the sensing amplifier module 1016 applies the desired voltage to each bit line based on the write data DAT received from the memory controller 1002. Conversely, during a read operation, the sensing amplifier module 1016 determines the data stored in the memory cell based on the voltage of the bit lines and transmits the determination result as read data DAT to the memory controller 1002.

[0118] The semiconductor memory device 100 and memory controller 1002 described above can also be combined to form a single semiconductor device. For example, SD (Secure Digital) can be cited as such a semiconductor device. TM Memory cards such as memory cards, or SSDs (solid state drives), etc.

[0119] Figure 22 This is a circuit diagram illustrating an example of the circuit configuration of a memory cell array (MCA). It extracts one block BLK from the multiple block BLKs contained in the MCA. For example... Figure 22 As shown, block BLK contains multiple string components SU(0) to SU(k) (k is an integer greater than or equal to 1).

[0120] Each string component SU contains multiple NAND strings NS associated with each bit line BL(0) to BL(m) (where m is an integer greater than or equal to 1). Each NAND string NS contains, for example, memory cell transistors MT(0) to MT(15) and select transistors ST(1) and ST(2). The memory cell transistor MT contains a control gate and a charge storage layer, which non-volatilely stores data. The select transistors ST(1) and ST(2) are used to select the string component SU during various operations.

[0121] In each NAND string NS, memory cell transistors MT(0) to MT(15) are connected in series. The drain of selector transistor ST(1) is connected to the associated bit line BL, and the source of selector transistor ST(1) is connected to one end of the series-connected memory cell transistors MT(0) to MT(15). The drain of selector transistor ST(2) is connected to the other end of the series-connected memory cell transistors MT(0) to MT(15). The source of selector transistor ST(2) is connected to the source line SL.

[0122] In the same BLK, the control gates of the memory cell transistors MT(0) to MT(15) are all connected to word lines WL(0) to WL(7). The gates of the select transistors ST(1) in the string components SU(0) to SU(k) are all connected to the select gate lines SGD(0) to SGD(k). The gate of the select transistor ST(2) is all connected to the select gate line SGS.

[0123] In the circuit configuration of the memory cell array (MCA) described above, the bit line BL is shared by the NAND strings NS in each string component SU that are assigned the same column address. The source line SL is shared, for example, among multiple blocks BLK.

[0124] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string component SU is called a cell component CU. For example, the storage capacity of a cell component CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". Depending on the number of bits of data stored by the memory cell transistors MT, a cell component CU can have a storage capacity of 2 pages or more.

[0125] Furthermore, the memory cell array MCA included in the semiconductor memory device 100 of this embodiment is not limited to the circuit configuration described above. For example, the number of memory cell transistors MT and selection transistors ST(1) and ST(2) included in each NAND string NS can be designed to be arbitrary. The number of string components SU included in each BLK can be designed to be arbitrary.

[0126] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are also included within the scope of the invention as described in the claims and their equivalents.

[0127] [Explanation of Symbols]

[0128] 100a: Semiconductor device

[0129] 1: Base part

[0130] 2: Laminated body

[0131] 3: plate-shaped part

[0132] CL: columnar part

[0133] CLHR: Insulator Post

[0134] 10: Substrate

[0135] MCA: Memory Cell Array

[0136] 21: Conductive layer

[0137] 22: Insulation layer

[0138] BRA: Bridging Area

[0139] 100a_1, 100a_2: Storage cell area

[0140] CC: Contact plug

[0141] ST: narrow slit.

Claims

1. A semiconductor memory device, characterized in that... include: Multiple conductive layers are spaced apart from each other and stacked in the first direction; as well as The contact plug is connected to one of the plurality of conductive layers, namely the first conductive layer; and The first conductive layer has: a first portion; and a second portion spaced apart from the first portion in a second direction orthogonal to the first direction. And part 3, located between part 1 and part 2; The semiconductor memory device includes: The first region includes: the first part, and a first pillar extending along the first direction in the first part and having a semiconductor material, wherein the portion of the first part opposite to the first pillar functions as a first memory cell; The second region includes: the second portion, and a second pillar extending along the first direction in the second portion and having a semiconductor material, wherein the portion of the second portion opposite to the second pillar functions as a second memory cell; and The third region includes: the third portion, and a plurality of third pillars extending along the first direction in the third portion and having insulation; and The third region includes the fourth region and the fifth region; The third part connects the first part and the second part in the fourth region; The third part is connected to the contact plug in the fifth region; The plurality of third pillars includes: a fourth pillar, which is at least partially disposed within the fifth region and is closest to the boundary between the fourth and fifth regions; a fifth pillar, which is disposed within the fifth region and is closest to the fourth pillar; and a sixth pillar, which is disposed within the fourth region and is closest to the boundary between the fourth and fifth regions; and The first interval between the fourth column and the fifth column is narrower than the second interval between the fourth column and the sixth column.

2. The semiconductor memory device according to claim 1, characterized in that: The plurality of third pillars further include a seventh pillar, which is disposed within the fifth region and is located on the opposite side of the fourth pillar and closest to the fifth pillar; and The first interval is narrower than the third interval between the seventh column and the sixth column.

Images