Methods for manufacturing memory, memory and storage system

Abstract

This invention discloses a method for fabricating a memory, a memory, and a memory system. The method includes: providing a first stacked layer and a second stacked layer located on the first stacked layer; forming a first channel via penetrating the second stacked layer and the first stacked layer in a core region; forming a third stacked layer on the second stacked layer; the first, second, and third stacked layers each include a plurality of alternately stacked interlayer sacrificial layers and interlayer insulating layers; forming a second channel via at least penetrating the third stacked layer in the core region, and the first channel via is connected to the second channel via; forming a channel structure in the first and second channel vias; replacing the interlayer sacrificial layers in the first and third stacked layers with gate layers, and retaining at least the interlayer sacrificial layers in the second stacked layer in the core region. This invention can reduce the leakage risk between the channel structure and the gate word line and increase the process window of the second channel via.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a memory, a memory, and a storage system. Background Technology

[0002] If there is an overlay misalignment between the upper and lower channel vias in the memory, there may be a risk of leakage between the channel structure and the gate word line after the channel structure is formed in the upper and lower channel vias. In order to reduce the risk of leakage between the channel structure and the gate word line, the process window of the upper channel via is made smaller. Summary of the Invention

[0003] This invention provides a method for manufacturing a memory, a memory, and a memory that can reduce the risk of leakage between the channel structure and the gate word line, and increase the process window of the second channel via.

[0004] This invention provides a method for manufacturing a memory, the memory including a core region, the method comprising:

[0005] A first stacking layer is provided, and a second stacking layer is located on the first stacking layer;

[0006] A first channel hole is formed in the core region, penetrating the second stacked layer and the first stacked layer;

[0007] A third stacked layer is formed on the second stacked layer; the first stacked layer, the second stacked layer and the third stacked layer each include a plurality of alternately stacked interlayer sacrificial layers and interlayer insulating layers;

[0008] A second channel hole is formed in the core region, at least penetrating the third stacked layer, and the first channel hole is connected to the second channel hole;

[0009] A channel structure is formed in the first channel hole and the second channel hole;

[0010] The interlayer sacrificial layers in the first and third stacked layers are replaced with gate layers, while at least the interlayer sacrificial layers in the second stacked layer of the core region are retained.

[0011] Furthermore, prior to the step of forming the third stacked layer on the second stacked layer, the method further includes:

[0012] An isolation structure is formed at least in the core region, extending through the second stacked layer;

[0013] The step of replacing the interlayer sacrificial layer in the first stacked layer and the third stacked layer with a gate layer includes:

[0014] A gate gap is formed that extends through the third stacked layer, the isolation structure, and the first stacked layer;

[0015] Through the gate gap, the interlayer sacrificial layer in the first stacked layer and the third stacked layer is replaced with a gate layer.

[0016] Furthermore, the memory also includes a first step region located outside the core region;

[0017] The isolation structure also extends through the second stacked layer of the first step area and covers the first step area.

[0018] Furthermore, prior to the step of forming a first channel hole through the second stacked layer and the first stacked layer in the core region, the method further includes:

[0019] A first mask layer is formed on the second stacked layer;

[0020] Through the first mask layer, at least in the core region, a first isolation opening is formed that penetrates the second stacked layer, and the isolation structure is formed in the first isolation opening.

[0021] Furthermore, the first mask layer includes a GLSA mask opening with a back gate self-alignment structure and an isolation mask opening;

[0022] The step of forming the isolation opening through the second stacked layer, at least in the core region, via the first mask layer includes:

[0023] A GLSA opening is formed through the GLSA mask opening, penetrating the second stacked layer, and a first isolation opening is formed through the isolation mask opening, at least in the core region, penetrating the second stacked layer.

[0024] Further, the step of forming a first channel hole through the second stacked layer and the first stacked layer in the core region includes:

[0025] A first stop layer is formed on the second stacked layer, and the first stop layer fills the first isolation opening;

[0026] A first virtual opening and a first channel opening are formed in the first stop layer. The orthographic projection of the first virtual opening on the second stack layer is located inside the first isolation opening, and the bottom of the first virtual opening is located inside the first stop layer. The first channel opening is located in the core region, and the orthographic projection of the first channel opening on the second stack layer is located outside the first isolation opening. The first channel opening penetrates the first stop layer.

[0027] A first channel hole is formed in the core region through the first channel opening, penetrating the second stacked layer and the first stacked layer;

[0028] Remove the first stop layer.

[0029] Further, the step of forming the first virtual opening and the first channel opening in the first stop layer includes:

[0030] A second mask layer is formed on the first stop layer, the second mask layer including a virtual mask opening and a channel mask opening;

[0031] The first virtual opening is formed in the first stop layer through the virtual mask opening, and the first channel opening is formed in the first stop layer through the channel mask opening.

[0032] Further, the step of forming an isolation structure through the second stacked layer at least in the core region includes:

[0033] An isolation layer is formed on the inner surface of the first isolation opening and the inner surface of the first channel hole;

[0034] A sacrificial layer is filled into the first isolation opening and the first channel hole, so that the isolation layer and the sacrificial layer in the first isolation opening constitute the isolation structure.

[0035] Furthermore, prior to the step of forming the channel structure in the first channel hole and the second channel hole, the method further includes:

[0036] The sacrificial layer in the first trench is removed through the second trench.

[0037] Furthermore, the method also includes:

[0038] The sacrificial layer in the first isolation opening is removed through the gate gap;

[0039] An insulating layer is filled into the gate gap and the first isolation opening to form a slit structure.

[0040] Furthermore, the method also includes:

[0041] An insulating layer is filled into the grid gaps to form a slit structure.

[0042] Furthermore, the memory also includes a second step region, and the first step region is located between the core region and the second step region; the gate gap also penetrates the second stacked layer of the second step region;

[0043] The method further includes:

[0044] When replacing the interlayer sacrificial layer in the first stacked layer and the third stacked layer with a gate layer, the interlayer sacrificial layer in the second stacked layer of the second step region is replaced with a gate layer through the gate gap.

[0045] Further, the step of forming a second channel hole in the core region that at least penetrates the third stacked layer includes:

[0046] A second isolation opening is formed on the third stacked layer;

[0047] A second stop layer is formed on the third stacked layer, and the second stop layer fills the second isolation opening;

[0048] A second virtual opening and a second channel opening are formed in the second stop layer. The orthographic projection of the second virtual opening on the third stack layer is located within the second isolation opening, and the bottom of the second virtual opening is located within the second stop layer. The second channel opening is located in the core region, and the orthographic projection of the second channel opening on the third stack layer is located outside the second isolation opening. The second channel opening penetrates the second stop layer.

[0049] A second channel hole is formed in the core region through the second channel opening, at least penetrating the third stacked layer;

[0050] Remove the second stop layer.

[0051] Furthermore, after the step of forming the channel structure in the first channel hole and the second channel hole, the method further includes:

[0052] The upper surface of the third stacked layer and the upper surface of the channel structure are ground so that the ground upper surface of the third stacked layer is flush with the ground upper surface of the channel structure.

[0053] Furthermore, the second channel hole penetrates the third stacked layer and extends into the second stacked layer.

[0054] Accordingly, the present invention also provides a memory including a core region;

[0055] The memory includes:

[0056] First stack layer;

[0057] A second stack layer located on the first stack layer, wherein the second stack layer of the core region includes a plurality of alternately stacked interlayer sacrificial layers and interlayer insulating layers;

[0058] A third stack layer is located on the second stack layer, and both the first stack layer and the third stack layer include multiple alternately stacked gate layers and interlayer insulating layers;

[0059] A channel structure that runs through the first stack layer, the second stack layer, and the third stack layer in the core area.

[0060] Furthermore, the memory also includes:

[0061] An isolation structure that extends at least through a second stack layer of the core region;

[0062] A slit structure that runs through the third stack layer, the isolation structure, and the first stack layer.

[0063] Furthermore, the memory also includes a first step region located outside the core region;

[0064] The isolation structure also extends through the second stack layer of the first step area and covers the first step area.

[0065] Furthermore, the memory also includes a second step region, and the first step region is located between the core region and the second step region;

[0066] The second stacked layer of the second step region includes multiple alternately stacked gate layers and interlayer insulating layers, and the slit structure also extends through the second stacked layer of the second step region.

[0067] Furthermore, the isolation structure includes a sacrificial layer and an isolation layer disposed around the sacrificial layer; the slit structure penetrates the sacrificial layer and the isolation layer.

[0068] Furthermore, the second channel structure penetrates the third stack layer and extends into the second stack layer.

[0069] Furthermore, the isolation structure includes an isolation layer, the slit structure penetrates the isolation layer, and the slit structure has protrusions on opposite sides, the isolation layer covering the protrusions.

[0070] Accordingly, the present invention also provides a storage system including the aforementioned memory and a controller electrically connected to the memory.

[0071] This invention provides a method for manufacturing a memory, a memory, and a storage system. It enables the formation of a first channel via penetrating a second stacked layer and a first stacked layer in the core region, and the formation of a second channel via penetrating at least a third stacked layer in the core region. A channel structure is formed in the first and second channel vias. The interlayer sacrificial layer in the first and third stacked layers is replaced with a gate layer, while at least the interlayer sacrificial layer in the second stacked layer of the core region is retained (i.e., the interlayer sacrificial layer in the second stacked layer of the core region is not replaced with a gate layer). This reduces the risk of leakage between the channel structure and the gate word line at the connection between the second and first channel vias when there is an overlay misalignment, lowers detection costs, and increases the process window of the second channel via. Attached Figure Description

[0072] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0073] Figure 1 This is a schematic diagram of a region arrangement in a memory provided in an embodiment of the present invention;

[0074] Figure 2 A schematic flowchart illustrating a method for manufacturing a memory according to an embodiment of the present invention;

[0075] Figures 3a to 3p A schematic diagram of a method for manufacturing a memory according to an embodiment of the present invention;

[0076] Figures 4a to 4c Another structural schematic diagram of the method for manufacturing a memory provided in an embodiment of the present invention;

[0077] Figure 5 This is a schematic diagram of a storage system provided in an embodiment of the present invention. Detailed Implementation

[0078] The specific structural and functional details disclosed herein are merely representative and are intended to describe exemplary embodiments of the invention. However, the invention can be embodied in many alternative forms and should not be construed as being limited solely to the embodiments set forth herein.

[0079] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0080] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0081] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0082] See Figure 1 This is a schematic diagram of the region arrangement of a memory provided in an embodiment of the present invention. The memory may include a core region and step regions. The step regions may be located on opposite sides of the core region, that is, there may be two step regions, and one step region is connected to each opposite side of the core region. Each step region may include a first step region USS (e.g., upper step region) and a second step region LSS (e.g., lower step region), with the first step region USS located between the core region and the second step region LSS.

[0083] See Figure 2 This is a flowchart illustrating the method for manufacturing a memory according to an embodiment of the present invention.

[0084] like Figure 2 As shown, the method for manufacturing a memory provided in this embodiment of the invention includes steps 101 to 106, as detailed below:

[0085] Step 101: Provide a first stacking layer and a second stacking layer located on the first stacking layer.

[0086] like Figure 3a As shown, a first stacked layer 2a can be formed on a substrate 1, and a second stacked layer 2b can be formed on the first stacked layer 2a. The substrate 1 is located in the core region, the first step region (USS), and the second step region (LSS). The substrate 1 can be a substrate, such as a silicon substrate, or a substrate including semiconductors of other elements or compound semiconductors. The substrate 1 can also include multiple stacked film layers, which is not specifically limited here.

[0087] Both the first stacked layer 2a and the second stacked layer 2b include multiple interlayer sacrificial layers 22 and interlayer insulating layers 21 alternately stacked along a first direction Z, where Z is the direction perpendicular to the upper surface of the substrate 1. The first stacked layer 2a and the second stacked layer 2b can together constitute a first stack structure (e.g., a lower stack structure), which is located in the core region, the first step region (USS), and the second step region (LSS). The number of stacked layers of the interlayer sacrificial layer 22 and the interlayer insulating layer 21 in the first stack structure is not limited, for example, 48 layers, 64 layers, 128 layers, etc. The interlayer sacrificial layer 22 can be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride, and the interlayer insulating layer 21 can be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0088] After forming the second stacked layer 2b, a first isolation opening can be formed in the second stacked layer 2b. Specifically, the method further includes:

[0089] A first mask layer is formed on the second stacked layer;

[0090] A first isolation opening is formed through the first mask layer, at least in the core region, penetrating the second stacked layer.

[0091] Combination Figure 3b As shown, Figure 3b This is a top view of the first mask layer 3. Figure 3a for Figure 3bA cross-sectional schematic diagram at the dashed line AA'. A first mask layer 3 is formed on the second stacked layer 2b. The first mask layer 3 is located in the core region, the first step region (USS), and the second step region (LSS). The first mask layer 3 can be photoresist. The first mask layer 3 has an isolation mask opening 30, which is located at least in the core region. That is, the isolation mask opening 30 can be located only in the core region, or in the core region and the first step region (USS), or in the core region, the first step region (USS), and the second step region (LSS). Figure 3b As shown, the isolation mask opening 30 is located in the core region and the first stepped region (USS). Specifically, the isolation mask opening 30 penetrates the core region in the second direction X, and penetrates the first stepped region (USS) in the third direction Y. For example, the isolation mask opening 30 can completely cover the first stepped region (USS). The second direction X refers to the arrangement direction of the core region and the stepped region, and the third direction Y is perpendicular to the first direction Z and the second direction X, respectively.

[0092] like Figure 3c As shown, a first isolation opening 23 is formed in the second stacked layer 2b through the isolation mask opening 30 in the first mask layer 3, such that the first isolation opening 23 is located at least in the core region. That is, the first isolation opening 23 can be located only in the core region, or it can be located in the core region and the first step region USS, or it can be located in the core region, the first step region USS, and the second step region LSS. For example, the first isolation opening 23 is located in the core region and the first step region USS, and the first isolation opening 23 penetrates the interlayer sacrificial layer 22 in the second stacked layer 2b in the first direction Z, penetrates the core region in the second direction X, and penetrates the first step region USS in the third direction Y, such that the first isolation opening 23 can completely cover the first step region USS.

[0093] The first mask layer 3 can be an independent mask layer, meaning that the first mask layer 3 and the GLSA (Gate Last Self Align) mask layer can be different mask layers. The GLSA mask layer has GLSA mask openings, and the first mask layer 3 has isolation mask openings 30. First, through the GLSA mask openings in the GLSA mask layer, GLSA openings (not shown in the figure) are formed on the second stacked layer 2b. The GLSA openings serve as calibration marks for subsequent etching. Then, through the isolation mask openings 30 in the first mask layer 3, a first isolation opening 23 is formed on the second stacked layer 2b.

[0094] The first mask layer 3 can also be obtained by improving the GLSA mask layer, that is, the first mask layer 3 and the GLSA mask layer can be the same mask layer. The first mask layer 3 has a GLSA mask opening (not shown in the figure) and an isolation mask opening 30. Specifically, the step of forming the isolation opening through the first mask layer, at least in the core region, penetrating the second stacked layer, includes:

[0095] A GLSA opening is formed through the GLSA mask opening, penetrating the second stacked layer, and a first isolation opening is formed through the isolation mask opening, at least in the core region, penetrating the second stacked layer.

[0096] By using the GLSA mask opening and the isolation mask opening 30 in the first mask layer 3, the GLSA opening (not shown in the figure) and the first isolation opening 23 can be formed simultaneously in the second stacked layer 2b to avoid increasing the manufacturing process.

[0097] like Figure 3c As shown, after the first isolation opening 23 is formed in the second stacked layer 2b, the first mask layer 3 is removed.

[0098] Step 102: Form a first channel hole in the core region that penetrates the second stacked layer and the first stacked layer.

[0099] The first stack layer 2a and the second stack layer 2b constitute a first stack structure, and the first channel hole (e.g., the lower channel hole) penetrates at least through the first stack structure and is located in the core region.

[0100] The first channel hole can be formed through a first channel opening in the first stop layer. Specifically, the step of forming the first channel hole through the second stacked layer and the first stacked layer in the core region in step 102 includes:

[0101] A first stop layer is formed on the second stacked layer, and the first stop layer fills the first isolation opening;

[0102] A first virtual opening and a first channel opening are formed in the first stop layer. The orthographic projection of the first virtual opening on the second stack layer is located inside the first isolation opening, and the bottom of the first virtual opening is located inside the first stop layer. The first channel opening is located in the core region, and the orthographic projection of the first channel opening on the second stack layer is located outside the first isolation opening. The first channel opening penetrates the first stop layer.

[0103] A first channel hole is formed in the core region through the first channel opening, penetrating the second stacked layer and the first stacked layer;

[0104] Remove the first stop layer.

[0105] The first channel opening in the first stop layer can be implemented using a second mask layer. Specifically, the step of forming the first virtual opening and the first channel opening in the first stop layer includes:

[0106] A second mask layer is formed on the first stop layer, the second mask layer including a virtual mask opening and a channel mask opening;

[0107] The first virtual opening is formed in the first stop layer through the virtual mask opening, and the first channel opening is formed in the first stop layer through the channel mask opening.

[0108] like Figure 3d As shown, a first stop layer 4 is formed on the second stacked layer 2b, and the first stop layer 4 fills the first isolation opening 23 in the second stacked layer 2b. The first stop layer 4 is located in the core region, the first step region (USS), and the second step region (LSS). The first stop layer 4 can be a carbon layer. Then, a second mask layer 5 is formed on the first stop layer 4, and the second mask layer 5 is located in the core region, the first step region (USS), and the second step region (LSS). The second mask layer 5 may include an anti-reflective layer 51 and a photoresist layer 52 sequentially located on the first stop layer 4. The anti-reflective layer 51 can be silicon oxynitride (SiON).

[0109] The photoresist layer 52 has virtual mask openings 53 and channel mask openings 54. The virtual mask openings 53 and channel mask openings 54 can be the same size and shape, and can be uniformly distributed in the core region and the first step region (USS). Figure 3e As shown, Figure 3e This is a top view of photoresist layer 52. Figure 3d for Figure 3e A cross-sectional view at the dashed line BB'. The orthographic projection of the virtual mask opening 53 onto the second stacked layer 2b lies within the first isolation opening 23. When the first isolation opening 23 is located in the core region and the first step region USS, the virtual mask opening 53 can also be located in the core region and the first step region USS. The orthographic projection of the channel mask opening 54 onto the second stacked layer 2b lies outside the first isolation opening 23, and the channel mask opening 54 is located in the core region.

[0110] like Figure 3fAs shown, the first stop layer 4 is etched through a virtual mask opening 53 to form a first virtual opening 41 in the first stop layer 4, and simultaneously etched through a channel mask opening 54 to form a first channel opening 42 in the first stop layer 4. The first virtual opening 41 and the first channel opening 42 can have the same size, shape, and depth, and can be evenly distributed in the core region and the first step region USS. The first channel opening 42 is located in the core region, and its orthographic projection on the second stacked layer 2b is outside the first isolation opening 23, penetrating the first stop layer 4. The orthographic projection of the first virtual opening 41 on the second stacked layer 2b is inside the first isolation opening 23. When the first isolation opening 23 is located in the core region and the first step region USS, the first virtual opening 41 can also be located in the core region and the first step region USS. Since the first stop layer 4 fills the first isolation opening 23, the first virtual opening 41 does not penetrate the first stop layer 4; that is, the bottom of the first virtual opening 41 is located within the first stop layer 4. After forming the first virtual opening 41 and the first channel opening 42 in the first stop layer 4, the second mask layer 5 is removed.

[0111] Then, as Figure 3g As shown, since the first channel opening 42 penetrates the first stop layer 4, the second stacked layer 2b, the first stacked layer 2a, and the substrate 1 are etched through the first channel opening 42 to form the first channel hole 61, which penetrates the second stacked layer 2b and the first stacked layer 2a and extends into the substrate 1. However, the first virtual opening 41 does not penetrate the first stop layer 4, therefore the second stacked layer 2b cannot be etched through the first virtual opening 41. That is, the first channel hole 61 is formed only in the core region through the first stop layer 4. After forming the first channel hole 61, the first stop layer 4 is removed.

[0112] It should be noted that, in combination Figure 3e , Figure 3f and Figure 3gAs shown, the region corresponding to the first isolation opening 23 (or the first virtual opening 41) can be the first region 43, and the region corresponding to the first channel opening 42 can be the second region 44 (i.e., the region in the core region excluding the first region 43). If the first stop layer only has the first channel opening and not the first virtual opening, the thickness of the first stop layer 4 in the first region 43 and the second region 44 will be different, that is, the thickness of the first stop layer in the first region 43 will be larger, and the thickness of the first stop layer in the second region 44 will be smaller. Consequently, when etching the first channel hole through the first stop layer, the etching residue is likely to accumulate in the first channel hole at the junction of the first region 43 and the second region 44, thus affecting the etching of the first channel hole. In this embodiment, the first virtual opening 41 and the first channel opening 42 are formed in the first stop layer 4 to avoid the difference in thickness of the first stop layer 4 in the first region 43 and the second region 44, thereby avoiding the accumulation of etching residue in the first channel hole 61 at the junction of the first region 43 and the second region 44, and preventing the etching of the first channel hole 61 from being affected. Moreover, the first stop layer 4 has a simple structure, which does not require special design for the first channel hole 61, reducing design risks and reducing the etching difficulty of the first channel hole 61.

[0113] Furthermore, the method also includes:

[0114] An isolation structure is formed at least in the core region, extending through the second stacked layer.

[0115] The isolation structure 7 can be formed in the first isolation opening 23. When the first isolation opening 23 is located in the core region, the isolation structure 7 is located in the core region, and the isolation structure 7 penetrates the core region in the second direction X and penetrates the interlayer sacrificial layer 22 in the second stack layer 2b in the first direction Z; when the first isolation opening 23 is located in the core region and the first step region USS, the isolation structure 7 is located in the core region and the first step region USS, and the isolation structure penetrates the core region in the second direction X and penetrates the first step region USS in the third direction Y. If the isolation structure 7 completely covers the first step region USS, the isolation structure 7 penetrates the interlayer sacrificial layer 22 in the second stack layer 2b in the first direction Z.

[0116] Specifically, the step of forming an isolation structure through the second stacked layer at least in the core region includes:

[0117] An isolation layer is formed on the inner surface of the first isolation opening and the inner surface of the first channel hole;

[0118] A sacrificial layer is filled into the first isolation opening and the first channel hole, so that the isolation layer and the sacrificial layer in the first isolation opening constitute the isolation structure.

[0119] like Figure 3h As shown, after forming the first isolation opening 23 and the first channel hole 61, an isolation layer 71 is formed on the inner surfaces (including sidewalls and bottom) of the first isolation opening 23 and the first channel hole 61. The isolation layer 71 may also extend to the upper surface of the second stacked layer 2b. The isolation layer 71 can be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. Then, a sacrificial layer 72 is filled into the first isolation opening 23 and the first channel hole 61, and the sacrificial layer 72 is chemically mechanically polished (CMP) so that the upper surface of the sacrificial layer 72 is flush with the upper surface of the second stacked layer 2b. The sacrificial layer 72 can be a non-conductive material, and the sacrificial layer 72 is easily etched when the gate gap is subsequently formed. The isolation layer 71 and the sacrificial layer 72 in the first isolation opening 23 constitute the isolation structure 7.

[0120] Step 103: Form a third stacked layer on the second stacked layer; the first stacked layer, the second stacked layer and the third stacked layer each include a plurality of alternately stacked interlayer sacrificial layers and interlayer insulating layers.

[0121] like Figure 3i As shown, a third stacked layer 2c is formed on the second stacked layer 2b. The third stacked layer 2c is located in the core region, the first step region (USS), and the second step region (LSS). The third stacked layer 2c includes multiple interlayer sacrificial layers 22 and interlayer insulating layers 21 that are alternately stacked along the first direction Z. The number of stacked layers of interlayer sacrificial layers 22 and interlayer insulating layers 21 in the third stacked layer 2c is not limited, for example, 48 layers, 64 layers, 128 layers, etc. The third stacked layer 2c can constitute a second stack structure (e.g., an upper stack structure).

[0122] Step 104: Form a second channel hole that penetrates at least the third stacked layer in the core area, and the first channel hole is connected to the second channel hole.

[0123] In this embodiment of the invention, a second isolation opening can be formed first on the third stacked layer 2c, and then a second channel hole can be formed in the third stacked layer 2c. Specifically, the step 104 of forming a second channel hole in the core region that at least penetrates the third stacked layer includes:

[0124] A second isolation opening is formed in the third stacked layer;

[0125] A second stop layer is formed on the third stacked layer, and the second stop layer fills the second isolation opening;

[0126] A second virtual opening and a second channel opening are formed in the second stop layer. The orthographic projection of the second virtual opening on the third stack layer is located within the second isolation opening, and the bottom of the second virtual opening is located within the second stop layer. The second channel opening is located in the core region, and the orthographic projection of the second channel opening on the third stack layer is located outside the second isolation opening. The second channel opening penetrates the second stop layer.

[0127] A second channel hole is formed in the core region through the second channel opening, at least penetrating the third stacked layer;

[0128] Remove the second stop layer.

[0129] like Figure 3i As shown, a second isolation opening 24 is formed in the third stacked layer 2c. The second isolation opening 24 can be located in the interlayer insulating layer 21 at the top of the third stacked layer 2c (i.e., the side of the third stacked layer 2c facing away from the substrate 1). The method of forming the second isolation opening 24 is similar to the method of forming the first isolation opening 23, and will not be described in detail here. The second isolation opening 24 can be located in the core region and the first step region USS, and the second isolation opening 24 penetrates the core region in the second direction X and penetrates the first step region USS in the third direction Y, such that the second isolation opening 24 can completely cover the first step region USS. The orthographic projection of the second isolation opening 24 on the second stacked layer 2b can completely coincide with the first isolation opening 23.

[0130] Then, as Figure 3jAs shown, a second stop layer 8 is formed on the third stacked layer 2c, and the second stop layer 8 fills the second isolation opening 24. The second stop layer 8 is located in the core region, the first step region (USS), and the second step region (LSS). The second stop layer 8 can be a carbon layer. The second stop layer 8 has a second virtual opening 81 and a second channel opening 82. The size, shape, and depth of the second virtual opening 81 and the second channel opening 82 can be the same, and the second virtual opening 81 and the second channel opening 82 can be evenly distributed in the core region and the first step region (USS). The second channel opening 82 is located in the core region, and the orthographic projection of the second channel opening 82 on the third stacked layer 2c is outside the second isolation opening 24, and the second channel opening 82 penetrates the second stop layer 8. The orthographic projection of the second virtual opening 81 on the third stacked layer 2c is inside the second isolation opening 24. When the second isolation opening 24 is located in the core region and the first step region (USS), the second virtual opening 81 can also be located in the core region and the first step region (USS). Since the second stop layer 8 fills the second isolation opening 24, the second virtual opening 81 does not penetrate the second stop layer 8; that is, the bottom of the second virtual opening 81 is located within the second stop layer 8. The method of forming the second virtual opening 81 and the second channel opening 82 in the second stop layer 8 is similar to the method of forming the first virtual opening 41 and the first channel opening 42 in the first stop layer 4, and will not be described in detail here.

[0131] like Figure 3k As shown, since the second channel opening 82 penetrates the second stop layer 8, at least the third stacked layer 2c is etched through the second channel opening 82 to form a second channel hole 62, which penetrates at least the third stacked layer 2c. For example, Figure 3k There is no overlay deviation between the second channel hole 62a and the first channel hole 61a. The second channel hole 62a penetrates the third stacked layer 2c and is connected to the first channel hole 61a. Figure 3k There is an overlay misalignment between the second channel hole 62b and the first channel hole 61b. The second channel hole 62b penetrates the third stacked layer 2c and extends into the second stacked layer 2b, connecting with the first channel hole 61b. However, the second virtual opening 81 does not penetrate the second stop layer 8. Therefore, the third stacked layer 2c cannot be etched through the second virtual opening 81. That is, through the second stop layer 8, the second channel hole 62 is formed only in the core region, and the second channel hole 62 is connected to the first channel hole 61. After forming the second channel hole 62, the second stop layer 8 is removed. Then, through the second channel hole 62, the sacrificial layer 72 in the first channel hole 61 is removed.

[0132] Combination Figure 3j and Figure 3kAs shown, a second virtual opening 81 and a second channel opening 82 are formed in the second stop layer 8 to avoid the difference in thickness between the second stop layer 8 in the first region 43 and the second region 44. This prevents etching residue from accumulating in the second channel hole 62 at the junction of the first region 43 and the second region 44, thus preventing the etching of the second channel hole 62 from being affected. Moreover, the second stop layer 8 has a simple structure, requiring no special design for the second channel hole 62, reducing design risks and the etching difficulty of the second channel hole 62.

[0133] Step 105: Form a channel structure in the first channel hole and the second channel hole.

[0134] like Figure 3l As shown, after forming the interconnected first channel hole 61 and second channel hole 62, a channel structure 6 is formed in the first channel hole 61 and the second channel hole 62. The channel structure located in the first channel hole 61 can be a first channel structure 60a, and the channel structure located in the second channel hole 62 can be a second channel structure 60b.

[0135] The channel structure 6 may include a channel layer 63 and a storage medium layer 64 disposed around the channel layer 63. The storage medium layer 64 includes a tunnel layer (not shown) disposed around the periphery of the channel layer 63, a charge storage layer (not shown) disposed around the periphery of the tunnel layer, and a charge blocking layer (not shown) disposed around the periphery of the charge storage layer. The channel layer 63 may be polysilicon, etc.; the tunnel layer may be an oxide such as silicon oxide, silicon nitride, or silicon oxynitride; the charge storage layer may be an insulating layer containing quantum dots or nanocrystals or compounds containing nitrogen and silicon; and the charge blocking layer may be an oxide such as silicon oxide. The channel structure 6 may also include a spacer layer 65 surrounded by the channel layer 63, the spacer layer 65 being an oxide such as silicon oxide. The channel structure 6 may also include a plug 66 located at the top of the channel structure 6, the plug 66 being connected to the channel layer 63, and the plug 66 being polysilicon, etc.

[0136] After forming the channel structure 6, the method further includes:

[0137] The upper surface of the third stacked layer and the upper surface of the channel structure are ground so that the ground upper surface of the third stacked layer is flush with the ground upper surface of the channel structure.

[0138] like Figure 3l As shown, the interlayer insulating layer 21 at the top of the third stacked layer 2c and the plug 66 in the channel structure 6 are ground so that the upper surface of the third stacked layer 2c is flush with the upper surface of the channel structure 6. After grinding, the third stacked layer 2c no longer has the second isolation opening 24.

[0139] Step 106: Replace the interlayer sacrificial layer in the first stacked layer and the third stacked layer with a gate layer, and retain at least the interlayer sacrificial layer in the second stacked layer of the core region.

[0140] In this embodiment of the invention, the interlayer sacrificial layer 22 in the first stacked layer 2a and the third stacked layer 2c can be replaced with a gate layer through the gate gap. Through the isolation structure 7, the interlayer sacrificial layer 22 in the second stacked layer 2b of the core region can be prevented from being replaced, thereby at least retaining the interlayer sacrificial layer 22 in the second stacked layer 2b of the core region.

[0141] Specifically, step 106, which involves replacing the interlayer sacrificial layer in the first stacked layer and the third stacked layer with a gate layer, includes:

[0142] A gate gap is formed that extends through the third stacked layer, the isolation structure, and the first stacked layer;

[0143] Through the gate gap, the interlayer sacrificial layer in the first stacked layer and the third stacked layer is replaced with a gate layer.

[0144] like Figure 3m As shown, a gate gap 90 is formed, located in the core region, the first step region (USS), and the second step region (LSS), and extends through the core region, the first step region (USS), and the second step region (LSS) along the second direction X. Since the isolation structure 7 is located at least in the core region, the gate gap 90 penetrates the third stacked layer 2c, the isolation structure 7, and the first stacked layer 2a in the core region, and extends into the substrate 1. It should be noted that the orthographic projection of the gate gap 90 in the core region onto the isolation structure 7 is located within the isolation structure 7 to ensure that the gate gap 90 in the core region is isolated from the second stacked layer 2b.

[0145] When the isolation structure 7 is only located in the core region, since the second stacked layer 2b of the core region has the isolation structure 7, while the second stacked layer 2b of the first step region USS and the second step region LSS does not have the isolation structure 7, the gate gap 90 penetrates the third stacked layer 2c, the isolation structure 7 and the first stacked layer 2a in the core region and extends into the substrate 1. The gate gap 90 penetrates the third stacked layer 2c, the second stacked layer 2b and the first stacked layer 2a in the first step region USS and the second step region LSS and extends into the substrate 1.

[0146] When the isolation structure 7 is located in the core region and the first step region USS, since the core region and the first step region USS have the isolation structure 7, while the second step region LSS does not, the gate gap 90 penetrates the third stacked layer 2c, the isolation structure 7, and the first stacked layer 2a in the core region and the first step region USS and extends into the substrate 1. The gate gap 90 penetrates the third stacked layer 2c, the second stacked layer 2b, and the first stacked layer 2a in the second step region LSS and extends into the substrate 1. The interlayer sacrificial layer 22 in the third stacked layer 2c, the interlayer sacrificial layer 22 in the first stacked layer 2a, and the interlayer sacrificial layer 22 in the second stacked layer 2b of the second step region LSS can be removed through the gate gap 90.

[0147] When the isolation structure 7 is located in the core region, the first step region (USS), and the second step region (LSS), since the entire region (including the core region, the first step region (USS), and the second step region (LSS)) has the isolation structure 7, the gate gap 90 penetrates the third stacked layer 2c, the isolation structure 7, and the first stacked layer 2a throughout the entire region and extends into the substrate 1. The interlayer sacrificial layer 22 in the third stacked layer 2c and the interlayer sacrificial layer 22 in the first stacked layer 2a can be removed through the gate gap 90.

[0148] In one implementation, such as Figure 3n As shown, the interlayer sacrificial layer 22 in the third stacked layer 2c and the first stacked layer 2a can be removed through the gate gap 90. Furthermore, when the isolation structure 7 is only located in the core region, since the gate gap 90 and the second stacked layer 2b are isolated in the core region by the isolation structure 7, the interlayer sacrificial layer 22 in the second stacked layer 2b of the core region cannot be removed; that is, the interlayer sacrificial layer 22 in the second stacked layer 2b of the core region is retained. However, the second stacked layer 2b of the first stepped region USS and the second stepped region LSS does not have the isolation structure 7, therefore, the interlayer sacrificial layer 22 in the second stacked layer 2b of the first stepped region USS and the second stepped region LSS can also be removed through the gate gap 90.

[0149] When the isolation structure 7 is located in the core region and the first stepped region USS, since the gate gap 90 is isolated from the second stacked layer 2b in the core region and the first stepped region USS by the isolation structure 7, the interlayer sacrificial layer 22 in the second stacked layer 2b in the core region and the first stepped region USS cannot be removed, that is, the interlayer sacrificial layer 22 in the second stacked layer 2b in the core region and the first stepped region USS is retained. However, the second stacked layer 2b in the second stepped region LSS does not have the isolation structure 7, so the interlayer sacrificial layer 22 in the second stacked layer 2b in the second stepped region LSS can also be removed through the gate gap 90.

[0150] When the isolation structure 7 is located in the core region, the first step region USS, and the second step region LSS, since the gate gap 90 and the second stacked layer 2b are isolated from each other in the entire region (including the core region, the first step region USS, and the second step region LSS) by the isolation structure 7, the interlayer sacrificial layer 22 in the second stacked layer 2b in the entire region cannot be removed, that is, the interlayer sacrificial layer 22 in the second stacked layer 2b in the entire region is retained.

[0151] Then, a gate layer 25 is formed between the interlayer insulating layers 21 of the third stacked layer 2c and between the interlayer insulating layers 21 of the first stacked layer 2a through the gate gap 90, thereby replacing the interlayer sacrificial layers 22 in the third stacked layer 2c and the first stacked layer 2a with gate layers 25, converting the third stacked layer 2c into a third stacked layer 20c and the first stacked layer 2a into a first stacked layer 20a. Additionally, when the isolation structure 7 is only located in the core region, a gate layer 25 is simultaneously formed between the interlayer insulating layers 21 of the second stacked layer 2b in the first step region USS and the second step region LSS, converting the second stacked layer 2b into a second stacked layer 20b. When the isolation structure 7 is located in both the core region and the first step region USS, as... Figure 3p As shown, a gate layer 25 is formed between the interlayer insulating layers 21 of the second stacked layer 2b of the second step region LSS, thereby transforming the second stacked layer 2b into a second stacked layer 20b.

[0152] Then, an insulating layer is filled into the gate gap 90 to form the slit structure 9.

[0153] In another implementation, such as Figure 4a As shown, when the interlayer sacrificial layer 22 in the third stacked layer 2c and the first stacked layer 2a can be removed through the gate gap 90, the sacrificial layer 72 in the first isolation opening 23 is also removed. Additionally, when the isolation structure 7 is only located in the core region, the interlayer sacrificial layer 22 in the second stacked layer 2b of the first step region USS and the second step region LSS is also removed. When the isolation structure 7 is located in both the core region and the first step region USS, the interlayer sacrificial layer 22 in the second stacked layer 2b of the second step region LSS is also removed.

[0154] Then, as Figure 4bAs shown, a gate layer 25 is formed between the interlayer insulating layers 21 in the third stacked layer 2c and the first stacked layer 2a, thereby replacing the interlayer sacrificial layers 22 in the third stacked layer 2c and the first stacked layer 2a with the gate layer 25, transforming the third stacked layer 2c into a third stacked layer 20c and the first stacked layer 2a into a first stacked layer 20a. Additionally, when the isolation structure 7 is only located in the core region, a gate layer 25 is simultaneously formed between the interlayer insulating layers 21 in the second stacked layer 2b of the first step region USS and the second step region LSS, transforming the second stacked layer 2b into a second stacked layer 20b. When the isolation structure 7 is located in both the core region and the first step region USS, as... Figure 4c As shown, a gate layer 25 is formed between the interlayer insulating layers 21 of the second stacked layer 2b of the second step region LSS, thereby transforming the second stacked layer 2b into a second stacked layer 20b.

[0155] Then, an insulating layer is filled into the gate gap 90 and the first isolation opening 23 to form the slit structure 9.

[0156] The memory fabrication method provided in this embodiment of the invention retains at least the interlayer sacrificial layer 22 in the second stacked layer 2b of the core region, that is, the second stacked layer 2b of the core region does not have a gate layer, so that when there is an overlay deviation between the second channel hole 62 and the first channel hole 61, the channel structure 6 will not be connected to the gate word line, thereby avoiding the leakage risk between the channel structure 6 and the gate word line, reducing the detection cost, and increasing the process window of the second channel hole 62.

[0157] Accordingly, embodiments of the present invention also provide a memory that can be formed using the above-described memory manufacturing method.

[0158] like Figure 1 As shown, the memory provided in this embodiment may include a core region and step regions. The step regions may be located on opposite sides of the core region, that is, there may be two step regions, and one step region is connected to each opposite side of the core region. Each step region may include a first step region USS (e.g., upper step region) and a second step region LSS (e.g., lower step region), with the first step region USS located between the core region and the second step region LSS.

[0159] like Figure 3o and 4b As shown, the memory may include a substrate 1, a first stack layer 20a, a second stack layer 20b, a third stack layer 20c, an isolation structure 7, a slit structure 9, and a channel structure 6.

[0160] In this design, substrate 1 is located within the core region, the first step region (USS), and the second step region (LSS). Substrate 1 can be a substrate, such as a silicon substrate, or a substrate containing other elemental semiconductors or compound semiconductors. Substrate 1 may also include multiple stacked film layers; no specific limitation is made here.

[0161] The first stacked layer 20a is located on the substrate 1, the second stacked layer 20b is located on the first stacked layer 20a, and the third stacked layer 20c is located on the second stacked layer 20b. The first stacked layer 20a, the second stacked layer 20b, and the third stacked layer 20c all cover the entire region (including the core region, the first step region USS, and the second step region LSS). Both the first stacked layer 20a and the third stacked layer 20c may include multiple gate layers 25 and interlayer insulating layers 21 alternately stacked in the first direction Z. The second stacked layer 20b of the core region includes multiple interlayer sacrificial layers 22 and interlayer insulating layers 21 alternately stacked in the first direction Z. The interlayer sacrificial layer 22 may be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride; the interlayer insulating layer 21 may be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride; and the gate layer 25 may be tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide.

[0162] The isolation structure 7 is located at least in the core region, and the isolation structure 7 extends at least through the interlayer sacrificial layer 22 in the second stack layer 20b of the core region. When the isolation structure 7 is located only in the core region, the second stack layer 20b of the first step region USS and the second step region LSS includes multiple interlayer insulating layers 21 and gate layers 25 alternately stacked along the first direction Z. When the isolation structure 7 is located in both the core region and the first step region USS, as... Figure 3p and Figure 4c As shown, the second stack layer 20b of the first step region USS includes multiple interlayer sacrificial layers 22 and interlayer insulating layers 21 alternately stacked along the first direction Z. The second stack layer 20b of the second step region LSS includes multiple interlayer insulating layers 21 and gate layer 25 alternately stacked along the first direction Z. When the isolation structure 7 is located in the core region, the first step region USS, and the second step region LSS, the second stack layer 20b of the first step region USS and the second step region LSS includes multiple interlayer sacrificial layers 22 and interlayer insulating layers 21 alternately stacked along the first direction Z.

[0163] The isolation structure 7 may include a sacrificial layer 72 and an isolation layer 71 disposed around the sacrificial layer 72. The isolation structure 7 may also include only the isolation layer 71. The sacrificial layer 72 may be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride, and the isolation layer 71 may be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0164] The slit structure 9 is located in the core region, the first step region (USS), and the second step region (LSS). The slit structure 9 penetrates the third stack layer 20c and the first stack layer 20a. Additionally, when the isolation structure 7 is only located in the core region, the slit structure 9 penetrates the isolation structure 7 in the core region, and penetrates the second stack layer 20b in the first step region (USS) and the second step region (LSS). When the isolation structure 7 is located in both the core region and the first step region (USS), the slit structure 9 penetrates the isolation structure 7 in both the core region and the first step region (USS), and penetrates the second stack layer 20b in the second step region (LSS). When the isolation structure 7 is located in the core region, the first step region (USS), and the second step region (LSS), the slit structure 9 penetrates the isolation structure 7 throughout the entire region (including the core region, the first step region (USS), and the second step region (LSS)). The slit structure 9 can be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0165] When the isolation structure 7 includes a sacrificial layer 72 and an isolation layer 71, such as Figure 3o As shown, the slit structure 9 penetrates both the sacrificial layer 72 and the isolation layer 71. When the isolation structure 7 includes the isolation layer 71, as... Figure 4b As shown, the slit structure 9 penetrates the isolation layer 71, and the slit structure 9 has protrusions on opposite sides at the second stack layer 20b, with the isolation layer 71 covering the protruding surfaces.

[0166] The channel structure 6 is located in the core region and penetrates the first stack layer 20a, the second stack layer 20b, and the third stack layer 20c. Specifically, the channel structure 6 includes a first channel structure 60a and a second channel structure 60b. The first channel structure 60a is located in the core region and penetrates both the second stack layer 20b and the first stack layer 20a. The second channel structure 60b is located in the core region and penetrates at least the third stack layer 20c. When there is no overlay misalignment between the second channel structure 60b and the first channel structure 60a, the second channel structure 60b penetrates the third stack layer 20c and connects to the first channel structure 60a. When there is an overlay misalignment between the second channel structure 60b and the first channel structure 60a, the second channel structure 60b penetrates the third stack layer 20c and extends into the second stack layer 20b, connecting to the first channel structure 60a.

[0167] Both the first channel structure 60a and the second channel structure 60b include a channel layer 63 and a storage medium layer 64 disposed around the channel layer 63. The storage medium layer 64 includes a tunnel layer (not shown) disposed around the periphery of the channel layer 63, a charge storage layer (not shown) disposed around the periphery of the tunnel layer, and a charge blocking layer (not shown) disposed around the periphery of the charge storage layer. The channel layer 63 can be polysilicon, etc.; the tunnel layer can be an oxide such as silicon oxide, silicon nitride, or silicon oxynitride; the charge storage layer can be an insulating layer containing quantum dots or nanocrystals or compounds containing nitrogen and silicon; and the charge blocking layer can be an oxide such as silicon oxide. The channel structure 6 may also include a spacer layer 65 surrounded by the channel layer 63, the spacer layer 65 being an oxide such as silicon oxide. The channel structure 6 may also include a plug 66 located at the top of the channel structure 6, the plug 66 being connected to the channel layer 63, and the plug 66 being polysilicon, etc. In this structure, the channel layer 63 of the first channel structure 60a is connected to the channel layer 63 of the second channel structure 60b.

[0168] Since the second stack layer 20b of the core region includes an interlayer sacrificial layer 22 and an interlayer insulating layer 21, meaning that the second stack layer 20b of the core region does not have a gate word line, even if there is an overlay deviation between the second channel structure 60b and the first channel structure 60a, causing the second channel structure 60b to extend into the second stack layer 20b, it will not cause leakage between the junction of the first channel structure 60a and the second channel structure 60b and the gate word line, thus reducing leakage detection costs and increasing the process window of the second channel structure 60b.

[0169] See Figure 5 This is a schematic diagram of the storage system provided in an embodiment of the present invention.

[0170] like Figure 5 As shown in the figure, this embodiment of the invention also provides a storage system, which includes a memory 300 and a controller 400. The memory 300 and the controller 400 are electrically connected, and the controller 400 is used to control the memory 300 to store data. The memory 300 is the memory in the above embodiment, and will not be described in detail here. The controller 400 can be a controller well known to those skilled in the art, and will not be described in detail here.

[0171] The storage system can be applied to terminal products such as computers, televisions, set-top boxes, and vehicles.

[0172] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a memory, characterized in that, The memory includes a core region, and the method includes: A first stacked layer is provided, and a second stacked layer is located on the first stacked layer, wherein both the first stacked layer and the second stacked layer include a plurality of alternately stacked interlayer sacrificial layers and interlayer insulating layers; A first channel hole is formed in the core region, penetrating the second stacked layer and the first stacked layer; An isolation structure is formed at least in the core region, and the isolation structure extends at least through the interlayer sacrificial layer in the second stacked layer along the stacking direction of the first stacked layer and the second stacked layer. A third stacked layer is formed on the second stacked layer; each of the third stacked layers includes a plurality of alternately stacked interlayer sacrificial layers and interlayer insulating layers; A second channel hole is formed in the core region, at least penetrating the third stacked layer, and the first channel hole is connected to the second channel hole; A channel structure is formed in the first channel hole and the second channel hole; The interlayer sacrificial layer in the first stacked layer and the third stacked layer is replaced with a gate layer, while at least the interlayer sacrificial layer in the second stacked layer of the core region is retained; The step of replacing the interlayer sacrificial layer in the first stacked layer and the third stacked layer with a gate layer includes: A gate gap is formed that extends through the third stacked layer, the isolation structure, and the first stacked layer; Through the gate gap, the interlayer sacrificial layer in the first stacked layer and the third stacked layer is replaced with a gate layer.

2. The method for manufacturing a memory according to claim 1, characterized in that, The interlayer sacrificial layer comprises any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride, and the interlayer insulating layer comprises any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

3. The method for manufacturing a memory according to claim 1, characterized in that, The memory also includes a first step area located outside the core area; The isolation structure also extends through the second stacked layer of the first step area and covers the first step area.

4. The method for manufacturing a memory according to claim 1 or 3, characterized in that, Prior to the step of forming a first channel hole through the second stacked layer and the first stacked layer in the core region, the method further includes: A first mask layer is formed on the second stacked layer; Through the first mask layer, at least in the core region, a first isolation opening is formed that penetrates the second stacked layer, and the isolation structure is formed in the first isolation opening.

5. The method for manufacturing a memory according to claim 4, characterized in that, The first mask layer includes a GLSA mask opening with a back gate self-alignment structure and an isolation mask opening; The step of forming the isolation opening through the second stacked layer, at least in the core region, via the first mask layer includes: A GLSA opening is formed through the GLSA mask opening, penetrating the second stacked layer, and a first isolation opening is formed through the isolation mask opening, at least in the core region, penetrating the second stacked layer.

6. The method for manufacturing a memory according to claim 4, characterized in that, The step of forming a first channel hole through the second stacked layer and the first stacked layer in the core region includes: A first stop layer is formed on the second stacked layer, and the first stop layer fills the first isolation opening; A first virtual opening and a first channel opening are formed in the first stop layer. The orthographic projection of the first virtual opening on the second stack layer is located inside the first isolation opening, and the bottom of the first virtual opening is located inside the first stop layer. The first channel opening is located in the core region, and the orthographic projection of the first channel opening on the second stack layer is located outside the first isolation opening. The first channel opening penetrates the first stop layer. A first channel hole is formed in the core region through the first channel opening, penetrating the second stacked layer and the first stacked layer; Remove the first stop layer.

7. The method for manufacturing a memory according to claim 6, characterized in that, The step of forming a first virtual opening and a first channel opening in the first stop layer includes: A second mask layer is formed on the first stop layer, the second mask layer including a virtual mask opening and a channel mask opening; The first virtual opening is formed in the first stop layer through the virtual mask opening, and the first channel opening is formed in the first stop layer through the channel mask opening.

8. The method for manufacturing a memory according to claim 4, characterized in that, The step of forming an isolation structure through the second stacked layer at least in the core region includes: An isolation layer is formed on the inner surface of the first isolation opening and the inner surface of the first channel hole; A sacrificial layer is filled in the first isolation opening and the first channel hole, and the isolation layer and the sacrificial layer in the first isolation opening constitute the isolation structure.

9. The method for manufacturing a memory according to claim 8, characterized in that, Prior to the step of forming a channel structure in the first channel hole and the second channel hole, the method further includes: The sacrificial layer in the first trench is removed through the second trench.

10. The method for manufacturing a memory according to claim 8, characterized in that, The method further includes: The sacrificial layer in the first isolation opening is removed through the gate gap; An insulating layer is filled into the gate gap and the first isolation opening to form a slit structure.

11. The method for manufacturing a memory according to claim 1 or 3, characterized in that, The method further includes: An insulating layer is filled into the grid gaps to form a slit structure.

12. The method for manufacturing a memory according to claim 3, characterized in that, The memory also includes a second step region, and the first step region is located between the core region and the second step region; the gate gap also penetrates a second stacked layer of the second step region; The method further includes: When replacing the interlayer sacrificial layer in the first stacked layer and the third stacked layer with a gate layer, the interlayer sacrificial layer in the second stacked layer of the second step region is replaced with a gate layer through the gate gap.

13. The method for manufacturing a memory according to claim 1, characterized in that, The step of forming a second channel hole in the core region that at least penetrates the third stacked layer includes: A second isolation opening is formed on the third stacked layer; A second stop layer is formed on the third stacked layer, and the second stop layer fills the second isolation opening; A second virtual opening and a second channel opening are formed in the second stop layer. The orthographic projection of the second virtual opening on the third stack layer is located within the second isolation opening, and the bottom of the second virtual opening is located within the second stop layer. The second channel opening is located in the core region, and the orthographic projection of the second channel opening on the third stack layer is located outside the second isolation opening. The second channel opening penetrates the second stop layer. A second channel hole is formed in the core region through the second channel opening, at least penetrating the third stacked layer; Remove the second stop layer.

14. A memory, characterized in that, Including a core region, the memory includes: First stack layer; A second stack layer located on the first stack layer, wherein the second stack layer of the core region includes a plurality of alternately stacked interlayer sacrificial layers and interlayer insulating layers; An isolation structure, along the stacking direction of the first stack layer and the second stack layer, at least penetrates the interlayer sacrificial layer in the second stack layer of the core region; A third stack layer is located on the second stack layer, and both the first stack layer and the third stack layer include multiple alternately stacked gate layers and interlayer insulating layers; A channel structure penetrating the first stack layer, the second stack layer, and the third stack layer in the core area; and A slit structure that runs through the third stack layer, the isolation structure, and the first stack layer.

15. The memory according to claim 14, characterized in that, The interlayer sacrificial layer comprises any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride, and the interlayer insulating layer comprises any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

16. The memory according to claim 14, characterized in that, The memory also includes a first step area located outside the core area; The isolation structure also extends through the second stack layer of the first step area and covers the first step area.

17. The memory according to claim 16, characterized in that, The memory also includes a second step region, and the first step region is located between the core region and the second step region; The second stacked layer of the second step region includes multiple alternately stacked gate layers and interlayer insulating layers, and the slit structure also extends through the second stacked layer of the second step region.

18. The memory according to claim 14, characterized in that, The isolation structure includes a sacrificial layer and an isolation layer disposed around the sacrificial layer; the slit structure extends through the sacrificial layer and the isolation layer.

19. The memory according to claim 14, characterized in that, The isolation structure includes an isolation layer, the slit structure extends through the isolation layer, and the slit structure has protrusions on opposite sides, the isolation layer covering the protrusions.

20. A storage system, characterized in that, It includes the memory as described in any one of claims 14 to 19, and a controller electrically connected to the memory.

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