A silicon carbide Schottky diode and its manufacturing method

Abstract

A silicon carbide Schottky diode and its manufacturing method are disclosed. This relates to the semiconductor field. The diode includes an epitaxial layer disposed on the front side of a silicon carbide substrate and an ohmic contact electrode on the back side; a lower metal layer is disposed on the ohmic contact electrode; it further includes: a P-type doped region extending downward from the top of the epitaxial layer; a first field oxide disposed on the top of the epitaxial layer; a second field oxide disposed on the top of the epitaxial layer, located to the side of the first field oxide; a front metal contact electrode disposed above the P-type doped region and connected to the first field oxide on its side; and an upper metal layer disposed above the front metal contact electrode. This invention reduces the influence of external charges or electric fields on the device surface, effectively protecting the long-term voltage withstand stability and reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more specifically to a silicon carbide Schottky diode and its manufacturing method. Background Technology

[0002] As a third-generation semiconductor material, silicon carbide has a critical breakdown field strength that is 10 times that of Si, a band gap and thermal conductivity that are 3 times that of Si, and an intrinsic carrier concentration that is only one-tenth that of Si. These significant advantages make silicon carbide an ideal material for manufacturing high-voltage, high-power, high-frequency, and high-temperature resistant devices.

[0003] Silicon carbide power devices typically include JBS, MPS, MOSFET, JFET, and IGBT. After chip manufacturing, the industry conducts chipprobe testing to identify defective chips. As is well known, the reliability of power semiconductors is a crucial product characteristic, and the ability to operate in high humidity environments is a key indicator of device reliability. However, for high-voltage silicon carbide devices, the reverse avalanche voltage is typically above 1400V. During chipprobe testing, this can cause air ionization between the front electrode and the scribe line on the wafer, leading to arcing and damaging the wafer and testing equipment. Therefore, the extremely high avalanche voltage poses a significant challenge to wafer testing. Furthermore, to meet market demands, products with higher reliability must be developed for greater market competitiveness, especially those operating in HV-H3TRB (High-Voltage, High-Temperature, High-Humidity, Reverse Bias) environments. Therefore, the design and fabrication of these devices are highly complex and challenging. Summary of the Invention

[0004] To address the above problems, this invention provides a silicon carbide Schottky diode and its manufacturing method that can avoid arcing during CP testing and greatly enhance the robustness of the device under H3TRB conditions.

[0005] The technical solution of this invention is: a silicon carbide Schottky diode, comprising an epitaxial layer disposed on the front side of a silicon carbide substrate and an ohmic contact electrode disposed on the back side; a lower metal layer is disposed on the ohmic contact electrode; and further comprising:

[0006] P-type doped region, the P-type doped region extending downward from the top of the epitaxial layer;

[0007] Field oxygen one, wherein the field oxygen one is disposed on the top of the epitaxial layer;

[0008] Field oxygen two is disposed on the top of the epitaxial layer, located to the side of field oxygen one.

[0009] A front metal contact electrode is disposed above the P-type doped region and connected to the field oxygen on its side.

[0010] An upper metal layer is disposed above the front metal contact electrode;

[0011] A passivation layer is disposed above the metal layer and the field oxygen layer; and

[0012] The PI adhesive is located on the top of the device and extends downward through the passivation layer to the epitaxial layer; the PI adhesive is spaced from the side of the device to form a scribe line.

[0013] Specifically, the passivation layer includes:

[0014] Passivation layer one, wherein the passivation layer one is disposed above the upper metal layer and the field oxygen one;

[0015] Passivation layer two is disposed above field oxygen two.

[0016] Specifically, the first passivation layer and the second passivation layer are composed of a semi-insulating polycrystalline silicon layer and a silicon nitride layer from bottom to top.

[0017] Specifically, the field oxygen and passivation layer are adapted to the dicing channel region.

[0018] Specifically, the first field oxygen layer and the second field oxygen layer, and the first passivation layer and the second passivation layer are respectively spaced apart;

[0019] The passivation layer is wrapped around the field oxygen;

[0020] The passivation layer two is wrapped around the field oxygen two.

[0021] A method for manufacturing a silicon carbide Schottky diode includes the following steps:

[0022] S001. An epitaxial layer is grown on a silicon carbide substrate;

[0023] S002, A P-type doped region is formed in the epitaxial layer by ion implantation;

[0024] S003. Deposit field oxygen I and field oxygen II on the front side of the device;

[0025] S004. Form a metal contact electrode on the front side of the device;

[0026] S005. Deposit a metal layer on top of the metal contact electrode as an electrode lead-out;

[0027] S006. Passivation layer 1 and passivation layer are fabricated at the device terminal positions respectively;

[0028] S007. Fabricate a PI adhesive layer at the device terminal;

[0029] S008. Fabricate ohmic contact electrodes on the back side of a silicon carbide substrate;

[0030] S009. Deposit a metal layer on the ohmic contact electrode to complete the device fabrication.

[0031] Specifically, in step S002, a P-type doped region is formed by one-time ion implantation, with Al as the doped impurity. The implantation temperature is 400-600℃, and after implantation, ion activation is performed by high-temperature annealing at 1600-1900℃.

[0032] Specifically, in step S003, a layer of SiO2 is deposited in advance by chemical vapor deposition, and then field oxygen one and field oxygen two are formed by etching.

[0033] Specifically, in step S006, before fabricating passivation layer one and passivation layer two, a SiPOS film and a silicon nitride film are deposited sequentially from bottom to top, and then passivation layer one and passivation layer two are formed by etching.

[0034] The beneficial effects of this invention are as follows:

[0035] 1. In this invention, the field oxygen layer II and the passivation layer II cover the area below the scribe line. When reverse voltage is applied, especially when the voltage is above 1000V, the equipotential surface of the back electrode will be on the surface of the scribe line. However, since there is field oxygen (SiO2) and passivation layer (silicon nitride) in the scribe line, their relative permittivity is high and their insulation performance is good. Ionization will not occur between the upper metal layer of the wafer and the surface of the scribe line, thus avoiding the above-mentioned arcing phenomenon.

[0036] 2. In this invention, the wafer is decomposed into individual chips in the dicing area 13. After packaging and testing, the devices are tested and verified using HV-H3TRB. Field oxygen has strong water absorption due to its material properties, while the silicon nitride and PI adhesive layers in the passivation layer have excellent waterproofing properties. If the passivation layer and PI adhesive layer cannot effectively protect the field oxygen, the entire passivation layer and PI layer cannot effectively isolate moisture. Because the device terminal continuously absorbs moisture through the field oxygen under high humidity conditions, the field ring portion containing moisture will experience excessive leakage current under high withstand voltage conditions, easily leading to water electrolysis and device failure. By depositing field oxygen layer one and field oxygen layer two, and passivation layer one and passivation layer two in segments at the edge region of the dicing area, with gaps between each pair, the encapsulated passivation structure with the outer silicon nitride layer effectively protects the field oxygen and prevents moisture from entering the terminal through the field oxygen. Simultaneously, the top PI adhesive also has excellent waterproofing performance, further improving the reliability of the device under HV-H3TRB.

[0037] 3. The resistivity of SiPOS in the passivation layer is much lower than that of organic insulating materials. At high temperatures, the mobile ions in the outer organic material are transported to the two electrodes under the action of an electric field. Since the semi-insulating layer itself has a large number of charge carriers, induced charges are generated in it, causing the electric field lines of the charges in the organic material to terminate in the semi-insulating layer and not reach the surface of the die. To a certain extent, it plays the role of shielding charges and uniform electric field, reducing the influence of external charges or electric fields on the device surface, and can effectively protect the long-term stability and reliability of the device. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of the present invention.

[0039] Figure 2 This is a schematic diagram of the structure of the epitaxial layer grown in step S001.

[0040] Figure 3 This is a schematic diagram of the p-type doped region after ion implantation in step S002.

[0041] Figure 4 This is a schematic diagram of the structure of deposition field oxygen one and field oxygen two in step S003.

[0042] Figure 5 This is a schematic diagram of the structure for forming the front metal contact electrode in step S004.

[0043] Figure 6 This is a schematic diagram of the structure of the thickened metal deposited in step S005.

[0044] Figure 7 This is a schematic diagram of the structure of passivation layer one and passivation layer two fabricated in step S006.

[0045] Figure 8 This is a schematic diagram of the PI adhesive structure made in step S007.

[0046] Figure 9 This is a schematic diagram of the structure of the ohmic contact electrode fabricated in step S008.

[0047] Figure 10 This is a schematic diagram of the structure of the thickened metal deposited in step S009;

[0048] Figure 11 This is an actual photo of the chip that was arcing before the improvement;

[0049] Figure 12 These are actual photos showing the improved version without any sparking.

[0050] In the figure, 1 is the silicon carbide substrate, 2 is the epitaxial layer, 3 is the P-type doped region, 4 is field oxygen 1, 5 is field oxygen 2, 6 is the front metal contact electrode, 7 is the upper metal layer, 8 is passivation layer 1, 9 is passivation layer 2, 10 is PI adhesive, 11 is the ohmic contact electrode, 12 is the lower metal layer, and 13 is the dicing track. Detailed Implementation

[0051] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0052] The present invention is as follows Figure 1-12 As shown; taking a SiC Schottky diode as an example, a typical device fabrication process includes:

[0053] A silicon carbide Schottky diode includes an epitaxial layer 2 disposed on the front side of a silicon carbide substrate 1 and an ohmic contact electrode 11 disposed on the back side; a lower metal layer 12 is disposed on the ohmic contact electrode 11; and further includes:

[0054] P-type doped region 3, which extends downward from the top of epitaxial layer 2;

[0055] Field oxygen 4 is disposed on the top of the epitaxial layer 2. It can prevent damage to the P-type doped region 3 during metal etching and form a field plate with the front metal contact electrode 6 and the upper metal layer 7 to adjust the electric field.

[0056] Field oxygen 2 5 is disposed on the top of the epitaxial layer 2, located on the side of field oxygen 1 4, covering the entire scribe line area 13. It has a relatively high permittivity and good insulation performance, which can effectively prevent arcing.

[0057] A front metal contact electrode 6 is disposed above the P-type doped region 3 and is connected to the field oxygen 4 on its side.

[0058] Upper metal layer 7, which is disposed above the front metal contact electrode 6;

[0059] A passivation layer is disposed above the metal layer 7 and the field oxygen 4; and

[0060] PI adhesive 10 is located at the top (or terminator) of the device and extends downward through the passivation layer to the epitaxial layer 2. The PI adhesive 10 is spaced from the side of the device, forming a dicing channel 13. The dicing channel 13 is used by a wafer dicing device to break down the wafer into individual chips for device packaging and testing.

[0061] Specifically, the passivation layer includes:

[0062] Passivation layer 8 is disposed above the upper metal layer 7 and the field oxygen 4;

[0063] Passivation layer 2 9 is disposed above field oxygen 2 5.

[0064] Passivation layer 8 and passivation layer 9 are respectively disposed above the field oxygen (field oxygen 4 or field oxygen 5), with their bottom parts contacting the epitaxial layer 2 and their sides contacting the front metal contact electrode and the upper metal layer, respectively. Because the silicon nitride in the passivation layer has good waterproofing properties, covering the field oxygen with the passivation layer can effectively prevent moisture from entering the field oxygen, thus improving the reliability of the device.

[0065] Specifically, the passivation layer (including passivation layer 8 and passivation layer 9) is composed of a semi-insulating polycrystalline silicon (SIPOS) layer and a silicon nitride layer from bottom to top.

[0066] The resistivity of SiPOS in the passivation layer is significantly lower than that of the organic insulating material. At high temperatures, mobile ions in the outer organic material are transported to the electrodes under the influence of an electric field. Since the semi-insulating layer itself has a large number of charge carriers, induced charges are generated within it. This causes the electric field lines of the charges in the organic material to terminate in the semi-insulating layer and not reach the surface of the die, thus shielding the charges and homogenizing the electric field to a certain extent. This reduces the influence of external charges or electric fields on the device surface, effectively protecting the device's long-term voltage withstand stability and reliability. Furthermore, the upper silicon nitride layer has excellent waterproofing properties, effectively preventing moisture ingress and further improving the device's reliability.

[0067] Specifically, the field oxygen 2 5 and the passivation layer 9 are adapted to the scribe line 13 region.

[0068] In this case, the mid-field oxygen 2 5 and passivation layer 9 cover the entire slit track 13 area, and both are high dielectric constant materials.

[0069] Specifically, the field oxygen 4 and field oxygen 5, and the passivation layer 8 and passivation layer 9 are respectively spaced apart;

[0070] The passivation layer 8 is wrapped around the field oxygen 4;

[0071] The passivation layer 29 is wrapped around the field oxygen 25.

[0072] Because the silicon nitride in the passivation layer has a good waterproof effect, the passivation layer can effectively prevent water vapor from entering the field oxygen by covering the field oxygen, while the spaced structure ensures that the outermost layer is a passivation layer with a good waterproof effect.

[0073] A method for manufacturing a silicon carbide Schottky diode includes the following steps:

[0074] S001. An epitaxial layer 2 with a thickness of 5-15 μm is grown on a silicon carbide substrate 1; (Refer to...) Figure 2 As shown; the silicon carbide substrate 1 and the silicon carbide epitaxial layer 2 are typically N-type conductive.

[0075] S002, A P-type doped region 3 is formed in the epitaxial layer 2 by ion implantation; Refer to Figure 3 As shown;

[0076] This process involves ion implantation, which can be a single or multiple implantation. The dopant is typically Al, and the implantation temperature is between 400-600℃. Upon completion, a 0.4-1.0 μm P-type doped junction is usually formed. The implantation energy range is 30-500 keV, and the implantation dose range is 1E12-1E16 cm⁻². After implantation, high-temperature annealing at 1600-1900℃ is required for ion activation.

[0077] S003. A layer of SiO2 is deposited on the front side of the device (above epitaxial layer 2) using chemical vapor deposition, followed by wet etching to form segmented deposition of field oxygen 4 and field oxygen 5; the field oxygen thickness of field oxygen 4 and field oxygen 5 is 0.5-2 μm; Reference Figure 4 As shown;

[0078] S004, reference Figure 5 As shown; a metal contact electrode 6 is formed on the front side of the device;

[0079] S005, A 1-6 μm thick upper metal layer 7 is deposited above the metal contact electrode 6 as an electrode lead-out; (Refer to...) Figure 6 As shown;

[0080] S006. Passivation layer 8 and passivation layer 9 are fabricated at the device terminal locations, respectively; refer to Figure 7 As shown;

[0081] In this invention, passivation layer 8 and passivation layer 9 are both double-layer structures, including a layer of semi-insulating polycrystalline silicon (SIPOS) and a layer of inorganic passivation layer of silicon nitride material.

[0082] S007, reference Figure 8 As shown; a PI adhesive layer 10 is fabricated at the device terminal position. This layer is an organic passivation layer mainly composed of polyimide.

[0083] S008, Reference Figure 9 As shown, an ohmic contact electrode 11 is fabricated on the back side of a silicon carbide substrate 1. The fabrication sequence needs to be adjusted depending on whether wafer thinning is performed. Typically, taking the thinning process as an example, the back ohmic electrode 11 will be placed after the thinning process and the ohmic alloy will be completed by laser annealing.

[0084] S009. Deposit a 1-3µm lower metal layer 12 on the ohmic contact electrode 11 to complete the device fabrication, referring to... Figure 10 As shown.

[0085] Specifically, in step S002, a P-type doped region is formed by one-time ion implantation, with Al as the doped impurity. The implantation temperature is 400-600℃, and after implantation, ion activation is performed by high-temperature annealing at 1600-1900℃.

[0086] Specifically, in step S003, a layer of SiO2 is deposited in advance by chemical vapor deposition, and then field oxygen 4 and field oxygen 5 are formed by etching.

[0087] Specifically, before fabricating passivation layer 8 and passivation layer 9 in step S006, a SIPOS film and a silicon nitride film are deposited sequentially from bottom to top.

[0088] Figure 1 The morphology of field oxygen 4, field oxygen 5, passivation layer 8, and passivation layer 9 is typically designed as a segmented structure formed by deposition and etching. The right side of passivation layer 8 completely encapsulates field oxygen 4, and the left side of passivation layer 9 completely encapsulates field oxygen 5. Passivation layers 8 and 9 maintain a certain distance between them. The silicon nitride outside the passivation layers provides excellent waterproofing, and the segmented passivation structure effectively prevents moisture from entering field oxygen 4.

[0089] Regarding the information disclosed in this case, the following points need to be clarified:

[0090] (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design.

[0091] (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments;

[0092] The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A silicon carbide Schottky diode, comprising an epitaxial layer (2) disposed on the front side of a silicon carbide substrate (1) and an ohmic contact electrode (11) disposed on the back side; wherein a lower metal layer (12) is disposed on the ohmic contact electrode (11); characterized in that, Also includes: The P-type doped region (3) extends downward from the top of the epitaxial layer (2); the doped impurity of the P-type doped region (3) is Al, the doping depth is 0.4-1.0 μm, and the cross-section is a rectangular structure with several intervals; the P-type doped region (3) is formed by ion implantation at a temperature of 400-600℃, and is activated by high-temperature annealing at 1600-1900℃ after implantation. Field oxygen one (4), said field oxygen one (4) is disposed on the top of the epitaxial layer (2); Field oxygen 2 (5) is disposed on the top of the epitaxial layer (2), located on the side of field oxygen 1 (4), with a thickness of 0.5-2μm, adapted to the scribe line (13) region and covering the area below the scribe line (13); A front metal contact electrode (6) is disposed above the P-type doped region (3) and its side is connected to the field oxygen (4). An upper metal layer (7) is disposed above the front metal contact electrode (6); The passivation layer includes a first passivation layer (8) and a second passivation layer (9); the first passivation layer (8) is disposed above the upper metal layer (7) and the first field oxygen layer (4), and the second passivation layer (9) is disposed above the second field oxygen layer (5); both passivation layers include a semi-insulating polycrystalline silicon layer and a silicon nitride layer from bottom to top, and completely cover the top and sides of the first field oxygen layer (4) and the second field oxygen layer (5), respectively, with no gap between the two layers and tightly bonded together; PI adhesive (10) is located on the top of the device and extends downward through the passivation layer to the epitaxial layer (2); the PI adhesive (10) forms a waterproof seal for the terminal area of ​​the device; the PI adhesive (10) is spaced from the side of the device to form a scribe line (13). Field oxygen layer 2 (5) and passivation layer 2 (9) cover the area below the slicing channel.

2. A method for manufacturing a silicon carbide Schottky diode, used to manufacture the silicon carbide Schottky diode of claim 1, characterized in that, Includes the following steps: S001. An epitaxial layer (2) is grown on a silicon carbide substrate (1). S002, A P-type doped region (3) is formed in the epitaxial layer (2) by ion implantation; In step S002, a P-type doped region is formed by one-time ion implantation, with Al as the doped impurity. The implantation temperature is 400-600℃. After implantation, ion activation is performed by high-temperature annealing at 1600-1900℃. S003, deposit field oxygen one (4) and field oxygen two (5) on the front side of the device. In step S003, a layer of SiO2 is deposited by chemical vapor deposition, and then field oxygen one (4) and field oxygen two (5) are formed by etching. S004. Form a metal contact electrode on the front side of the device (6). S005. A metal layer (7) is deposited on top of the metal contact electrode (6) as an electrode lead-out; S006. Passivation layer one (8) and passivation layer two (9) are fabricated at the device terminal positions respectively. Before fabricating passivation layer one (8) and passivation layer two (9) in step S006, a SiPOS film and a silicon nitride film are deposited sequentially from bottom to top, and then passivation layer one (8) and passivation layer two (9) are formed by etching. S007. Fabricate PI adhesive (10) at the device terminal position. S008. An ohmic contact electrode (11) is fabricated on the back side of a silicon carbide substrate (1). S009. Deposit a metal layer (12) on the ohmic contact electrode (11) to complete the device fabrication; The morphology of field oxygen 1 (4), field oxygen 2 (5), passivation layer 1 (8) and passivation layer 2 (9) is formed into a segmented structure through deposition and etching. The side of passivation layer 1 (8) completely covers field oxygen 1 (4), and the side of passivation layer 2 (9) completely covers field oxygen 2 (5).

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