Three-primary-color light-emitting diode chip and preparation method thereof

Abstract

The present disclosure provides a three-primary-color light-emitting diode chip and a preparation method thereof, belonging to the field of optoelectronic manufacturing technology. The three-primary-color light-emitting diode chip includes a substrate, an epitaxial structure and an insulating structure stacked in sequence, the epitaxial structure includes a first epitaxial layer, a second epitaxial layer and a third epitaxial layer stacked in sequence on the substrate, and the insulating structure is located on the surface of the third epitaxial layer away from the substrate; the surface of the insulating structure has a plurality of light-emitting holes, and the plurality of light-emitting holes include a first light-emitting hole exposing the first epitaxial layer, a second light-emitting hole exposing the second epitaxial layer, and a third light-emitting hole exposing the third epitaxial layer. The present disclosure can improve the uniformity of the three-primary-color light-emitting diode chip when mixing colors and improve the light mixing effect.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a three-primary-color light-emitting diode chip and a preparation method thereof. Background Art

[0002] The three-primary-color light-emitting diode is an electronic component that uses the three-primary-color principle to make the light-emitting diode emit light of different colors. The three-primary-color light-emitting diode has the characteristics of self-luminescence, high brightness, high contrast, high responsiveness and power saving.

[0003] In the related art, a three-primary-color light-emitting diode generally includes an epitaxial structure, a first solder joint block and a second solder joint block. The epitaxial structure includes three stacked blue epitaxial layers, green epitaxial layers and red epitaxial layers, and two adjacent epitaxial layers are connected by a bonding layer.

[0004] However, this arrangement of stacking three epitaxial layers causes the light emitted by the three epitaxial layers to pass through different numbers of epitaxial layers when emitted, so there is a problem of poor uniformity when mixing lights of different colors. Summary of the invention

[0005] The disclosed embodiment provides a three-primary-color light-emitting diode chip and a method for manufacturing the same, which can improve the uniformity of the three-primary-color light-emitting diode chip when mixing colors and improve the light mixing effect. The technical solution is as follows:

[0006] An embodiment of the present disclosure provides a three-primary-color light-emitting diode chip, which includes a substrate, an epitaxial structure and an insulating structure stacked in sequence, the epitaxial structure including a first epitaxial layer, a second epitaxial layer and a third epitaxial layer stacked in sequence on the substrate, and the insulating structure is located on a surface of the third epitaxial layer away from the substrate; the surface of the insulating structure has a plurality of light exit holes, and the plurality of light exit holes include a first light exit hole exposing the first epitaxial layer, a second light exit hole exposing the second epitaxial layer, and a third light exit hole exposing the third epitaxial layer.

[0007] In one implementation of the embodiment of the present disclosure, the multiple light-emitting holes are distributed into multiple hole groups, and the multiple hole groups are distributed in an array, and each of the hole groups includes at least one of the first light-emitting holes, at least one of the second light-emitting holes, and at least one of the third light-emitting holes.

[0008] In another implementation of the embodiment of the present disclosure, one of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer is used to emit red light, and in the same hole group, the cross-sectional area of ​​the light-emitting hole exposing the epitaxial layer used to emit red light is the largest.

[0009] In another implementation of the embodiment of the present disclosure, the shapes of the cross sections of the first light exit hole, the second light exit hole, and the third light exit hole are all different.

[0010] In another implementation of the embodiment of the present disclosure, a surface of the first epitaxial layer close to the substrate has a first bonding layer, and a surface of the substrate close to the first epitaxial layer has a second bonding layer; the first bonding layer and the second bonding layer both include a Sn layer and Au blocks embedded in the Sn layer at intervals, and the Au blocks of the first bonding layer are relatively connected to the Au blocks of the second bonding layer.

[0011] In another implementation of the embodiment of the present disclosure, the first epitaxial layer has a first electrode and a second electrode on two opposite sides, the first electrode is close to the substrate, the second epitaxial layer has a third electrode and a fourth electrode on two opposite sides, the third electrode is close to the first epitaxial layer, and the third epitaxial layer has a fifth electrode and a sixth electrode on two opposite sides, and the fifth electrode faces the second epitaxial layer; the surface of the third epitaxial layer has a first groove exposing the second electrode, the third electrode and the fifth electrode, and a second groove exposing the first electrode, and a third groove exposing the fourth electrode; the third epitaxial layer also has a first welding point block, a second welding point block, a third welding point block and a fourth welding point block, the first welding point block is respectively connected to the second electrode, the third electrode and the fifth electrode through the first groove, the second welding point block is connected to the first electrode through the second groove, the third welding point block is connected to the fourth electrode through the third groove, and the fourth welding point block is connected to the sixth electrode.

[0012] In another implementation of the embodiment of the present disclosure, the first epitaxial layer includes a first n-type layer, a first light-emitting layer and a first p-type layer sequentially stacked on the substrate; the second epitaxial layer includes a second p-type layer, a second light-emitting layer and a second n-type layer sequentially stacked on the first p-type layer; the third epitaxial layer includes a third p-type layer, a third light-emitting layer and a third n-type layer sequentially stacked on the second n-type layer.

[0013] In another implementation of the embodiment of the present disclosure, a surface of the insulating structure away from the epitaxial structure has a light-shielding film, and the light-shielding film has a through hole exposing the first light output hole, the second light output hole and the third light output hole.

[0014] In another implementation of the embodiment of the present disclosure, the thickness of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all 1 μm to 3 μm.

[0015] An embodiment of the present disclosure provides a method for preparing a three-primary-color light-emitting diode chip, the method comprising: providing a substrate; forming an epitaxial structure on the substrate, the epitaxial structure comprising a first epitaxial layer, a second epitaxial layer and a third epitaxial layer sequentially stacked on the substrate; forming an insulating structure on a surface of the third epitaxial layer away from the substrate, the surface of the insulating structure having a first light emitting hole exposing the first epitaxial layer, a second light emitting hole exposing the second epitaxial layer, and a third light emitting hole exposing the third epitaxial layer.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] The disclosed embodiment provides a three-primary-color light-emitting diode chip including a substrate, an epitaxial structure and an insulating structure stacked in sequence, wherein the epitaxial structure includes a first epitaxial layer, a second epitaxial layer and a third epitaxial layer stacked in sequence on the substrate, and a first light output hole, a second light output hole and a third light output hole are provided on the surface of the insulating structure, the first light output hole exposes the first epitaxial layer to transmit light emitted by the first epitaxial layer through the first light output hole, the second light output hole exposes the second epitaxial layer to transmit light emitted by the second epitaxial layer through the second light output hole, and the third light output hole exposes the third epitaxial layer to transmit light emitted by the third epitaxial layer through the third light output hole.

[0018] By setting the three light emitting holes to transmit different colors of light respectively, a very uniform light mixing effect can be achieved. Moreover, since the light emitting holes are arranged at intervals, a very pure display effect can also be obtained, which significantly improves the light mixing effect of the three-primary-color light emitting diode chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 is a top view of a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0021] Figure 2 yes Figure 1 AA section diagram provided;

[0022] Figure 3 It is a structural schematic diagram of a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0023] Figure 4 yes Figure 1 BB cross-section provided;

[0024] Figure 5 yes Figure 1 The CC cross-section provided;

[0025] Figure 6 is a schematic diagram of the distribution of an insulation structure and solder joint blocks provided by an embodiment of the present disclosure;

[0026] Figure 7 is a schematic structural diagram of a first bonding layer provided in an embodiment of the present disclosure;

[0027] Figure 8 It is a flow chart of a method for preparing a three-primary-color light-emitting diode chip provided in an embodiment of the present disclosure.

[0028] The descriptions of the marks in the figure are as follows:

[0029] 10. Substrate;

[0030] 201, first groove; 202, second groove; 203, third groove;

[0031] 21, first epitaxial layer; 211, first n-type layer; 212, first light-emitting layer; 213, first p-type layer;

[0032] 22, second epitaxial layer; 221, second n-type layer; 222, second light-emitting layer; 223, second p-type layer;

[0033] 23, third epitaxial layer; 231, third n-type layer; 232, third light-emitting layer; 233, third p-type layer;

[0034] 31, first bonding layer; 311, Sn layer; 312, Au block; 32, second bonding layer; 33, third bonding layer; 34, fourth bonding layer;

[0035] 41. first electrode; 42. second electrode; 43. third electrode; 44. fourth electrode; 45. fifth electrode; 46. sixth electrode; 47. first metal strip; 48. second metal strip; 49. third metal strip;

[0036] 50, hole group; 51, first light exit hole; 52, second light exit hole; 53, third light exit hole;

[0037] 61. Insulation structure; 610. Through hole; 62. First insulation layer; 63. Second insulation layer;

[0038] 71, first welding point block; 72, second welding point block; 73, third welding point block; 74, fourth welding point block;

[0039] 80. Light-shielding film. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0041] Figure 1 It is a top view of a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure. Figure 2 yes Figure 1 Provided AA cross-section diagram. Figure 1 , 2 As shown, the three-primary-color light-emitting diode chip includes a substrate 10, an epitaxial structure and an insulating structure 61 stacked in sequence. The epitaxial structure includes a first epitaxial layer 21, a second epitaxial layer 22 and a third epitaxial layer 23 stacked in sequence on the substrate 10. The insulating structure 61 is located on the surface of the third epitaxial layer 23 away from the substrate 10.

[0042] like Figure 2 As shown, the surface of the insulating structure 61 has a plurality of light exit holes, including a first light exit hole 51 exposing the first epitaxial layer 21 , a second light exit hole 52 exposing the second epitaxial layer 22 , and a third light exit hole 53 exposing the third epitaxial layer 23 .

[0043] The disclosed embodiment provides a three-primary-color light-emitting diode chip including a substrate 10, an epitaxial structure and an insulating structure 61 stacked in sequence, wherein the epitaxial structure includes a first epitaxial layer 21, a second epitaxial layer 22 and a third epitaxial layer 23 stacked in sequence on the substrate 10, and a first light exit hole 51, a second light exit hole 52 and a third light exit hole are provided on the surface of the insulating structure 61, the first light exit hole 51 exposes the first epitaxial layer 21 to transmit light emitted by the first epitaxial layer 21 through the first light exit hole 51, the second light exit hole 52 exposes the second epitaxial layer 22 to transmit light emitted by the second epitaxial layer 22 through the second light exit hole 52, and the third light exit hole 53 exposes the third epitaxial layer 23 to transmit light emitted by the third epitaxial layer 23 through the third light exit hole 53.

[0044] By setting the three light emitting holes to transmit different colors of light respectively, a very uniform light mixing effect can be achieved. Moreover, since the light emitting holes are arranged at intervals, a very pure display effect can also be obtained, which significantly improves the light mixing effect of the three-primary-color light emitting diode chip.

[0045] Figure 3 Schematic diagram of the structure of a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure. Figure 3As shown, the first epitaxial layer 21 includes a first n-type layer 211, a first light-emitting layer 212, and a first p-type layer 213 sequentially stacked on the substrate 10. The second epitaxial layer 22 includes a second p-type layer 223, a second light-emitting layer 222, and a second n-type layer 221 sequentially stacked on the first p-type layer 213. The third epitaxial layer 23 includes a third p-type layer 233, a third light-emitting layer 232, and a third n-type layer 231 sequentially stacked on the second n-type layer 221.

[0046] In the above implementation, the p-type layer of the first epitaxial layer 21 faces away from the substrate 10 , the p-type layer of the second epitaxial layer 22 faces toward the substrate 10 , and the p-type layer of the third epitaxial layer 23 faces toward the substrate 10 .

[0047] In the embodiment of the present disclosure, the first epitaxial layer 21 is a red epitaxial layer and may include a GaAs layer, an etching stop layer, a first n-type layer 211, an AlInP carrier confinement layer, a first light emitting layer 212, a first p-type layer 213 and a window layer stacked in sequence.

[0048] The first n-type layer 211 may be an n-type AlGaInP current spreading layer, and the first p-type layer 213 may be a p-type AlInP layer.

[0049] Optionally, the first light emitting layer 212 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately, wherein the Al content in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer is different. The first light emitting layer 212 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers alternately stacked.

[0050] As an example, in the embodiment of the present disclosure, the first light emitting layer 212 includes five periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers that are alternately stacked.

[0051] Optionally, the thickness of the first light emitting layer 212 may be 150 nm to 200 nm.

[0052] Exemplarily, the thickness of the first epitaxial layer is 1 μm to 3 μm. For example, the thickness of the first epitaxial layer is 2 μm. Reducing the thickness of the epitaxial layer in this way can reduce the difficulty in the etching process and improve the light mixing effect, while reducing costs.

[0053] In the embodiment of the present disclosure, the second epitaxial layer 22 is a green epitaxial layer, and may include a GaN buffer layer, a high temperature GaN layer, a second n-type layer 221, a second light emitting layer 222, a second p-type layer, and an InGaN window layer stacked in sequence.

[0054] The second n-type layer 221 may be an n-type GaN layer, and the second p-type layer 223 may be a p-type GaN layer.

[0055] Optionally, the second light emitting layer 222 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the second light emitting layer 222 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0056] As an example, in the embodiment of the present disclosure, the second light emitting layer 222 includes 5 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0057] Optionally, the thickness of the second light emitting layer 222 may be 150 nm to 200 nm.

[0058] Exemplarily, the thickness of the second epitaxial layer 22 is 1 μm to 3 μm. For example, the thickness of the second epitaxial layer 22 is 2 μm. Reducing the thickness of the epitaxial layer in this way can reduce the difficulty in the etching process and improve the light mixing effect, while reducing the cost.

[0059] In the embodiment of the present disclosure, the third epitaxial layer 23 is a blue epitaxial layer and may include a GaN buffer layer, a high temperature GaN layer, a third n-type layer 231, a third light emitting layer 232, a third p-type layer 233 and an InGaN window layer stacked in sequence.

[0060] The third n-type layer 231 may be an n-type GaN layer, and the third p-type layer 233 may be a p-type GaN layer.

[0061] Optionally, the third light emitting layer 232 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately, wherein the Al content in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer is different. The third light emitting layer 232 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers alternately stacked.

[0062] As an example, in the embodiment of the present disclosure, the third light emitting layer 232 includes 5 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers that are alternately stacked.

[0063] Optionally, the thickness of the third light emitting layer 232 may be 150 nm to 200 nm.

[0064] Exemplarily, the thickness of the third epitaxial layer 23 is 1 μm to 3 μm. For example, the thickness of the third epitaxial layer 23 is 2 μm. Reducing the thickness of the epitaxial layer in this way can reduce the difficulty in the etching process and improve the light mixing effect, while reducing the cost.

[0065] Alternatively, if Figure 2 , 4 As shown, the first epitaxial layer 21 has a first electrode 41 and a second electrode 42 on two opposite sides, and the first electrode 41 faces the substrate 10. Figure 2 , 5 As shown, the second epitaxial layer 22 has a third electrode 43 and a fourth electrode 44 on two opposite sides, and the third electrode 43 faces the first epitaxial layer 21. Figure 2 , 6 As shown, the third epitaxial layer 23 has a fifth electrode 45 and a sixth electrode 46 on two opposite surfaces, and the fifth electrode 45 faces the second epitaxial layer 22 .

[0066] like Figure 1 , 2 As shown, the surface of the third epitaxial layer 23 has a first groove 201 exposing the second electrode 42 , the third electrode 43 and the fifth electrode 45 , a second groove 202 exposing the first electrode 41 , and a third groove 203 exposing the fourth electrode 44 .

[0067] like Figure 1 As shown, the third epitaxial layer 23 also has a first solder point block 71, a second solder point block 72, a third solder point block 73 and a fourth solder point block 74. The first solder point block 71 is connected to the second electrode 42, the third electrode 43 and the fifth electrode 45 respectively through the first groove 201, the second solder point block 72 is connected to the first electrode 41 through the second groove 202, the third solder point block 73 is connected to the fourth electrode 44 through the third groove 203, and the fourth solder point block 74 is connected to the sixth electrode 46.

[0068] like Figure 2 , 3 As shown, the first groove 201 extends from the third epitaxial layer 23 at least to the second electrode 42 to expose the second electrode 42, the third electrode 43 and the fifth electrode 45. The second electrode 42, the third electrode 43 and the fifth electrode 45 are all p-electrodes.

[0069] like Figure 1 , 2 As shown, the three-primary-color light-emitting diode chip further includes: a first metal strip 47 , and the first metal strip 47 is connected to the first soldering point block 71 .

[0070] like Figure 1 , 2 As shown, the surface of the third n-type layer 231 has an insulating structure 61 , the first solder joint block 71 is located on the insulating structure 61 , the first metal strip 47 is located in the first groove 201 and is connected to the second electrode 42 , the third electrode 43 and the fifth electrode 45 .

[0071] In the above implementation, the first metal strip 47 extends to the second electrode 42, the third electrode 43 and the fifth electrode 45 through the first groove 201 on the surface of the third epitaxial layer 23. In this way, the first metal strip 47 is used as a conductive structure to connect the first soldering point block 71 to the three second electrodes 42, the third electrode 43 and the fifth electrode 45 respectively, so that the first soldering point block 71 is electrically connected to the p-electrodes of the three epitaxial layers.

[0072] Exemplarily, the second electrode 42 may include one of an alloy layer formed of Au and Be, an Au layer, a Ti layer, and a W layer, and the first metal strip 47 may also be one of an alloy layer formed of Au and Be, an Au layer, a Ti layer, and a W layer.

[0073] As an example, the thickness of the alloy layer formed of Au and Be is 300 angstroms to 700 angstroms, for example, the thickness of the alloy layer formed of Au and Be is 500 angstroms.

[0074] As an example, the thickness of the Au layer is 1000 angstroms to 3000 angstroms, for example, the thickness of the Au layer is 2000 angstroms.

[0075] As an example, the thickness of the Ti layer is 300 angstroms to 700 angstroms, for example, the thickness of the Ti layer is 500 angstroms.

[0076] As an example, the thickness of the W layer is 2000 angstroms to 5000 angstroms, for example, the thickness of the W layer is 3000 angstroms.

[0077] Exemplarily, the third electrode 43 and the fifth electrode 45 may each include one of a Cr layer, an Al layer, a Ti layer, and a W layer.

[0078] As an example, the thickness of the Cr layer is 50 angstroms to 200 angstroms, for example, the thickness of the Cr layer is 100 angstroms.

[0079] As an example, the thickness of the Al layer is 1000 angstroms to 3000 angstroms, for example, the thickness of the Al layer is 2000 angstroms.

[0080] As an example, the thickness of the Ti layer is 300 angstroms to 700 angstroms, for example, the thickness of the Ti layer is 500 angstroms.

[0081] As an example, the thickness of the W layer is 2000 angstroms to 5000 angstroms, for example, the thickness of the W layer is 3000 angstroms.

[0082] Figure 4 yes Figure 1 Provided BB cross-section diagram. Figure 1 , 4As shown, the second groove 202 extends from the third epitaxial layer 23 to at least the first electrode 41 to expose the first electrode 41, wherein the first electrode 41 is an n-electrode. The second groove 202 has a first insulating layer 62 extending from the third epitaxial layer 23 to the first n-type layer 211.

[0083] like Figure 1 , 4 As shown, the three-primary-color light-emitting diode chip further includes a second metal strip 48 , and the second metal strip 48 is connected to the second soldering point block 72 .

[0084] like Figure 1 , 4 As shown, the second soldering point block 72 is located on the insulating structure 61 , and the second metal strip 48 is located in the second groove 202 and connected to the first electrode 41 .

[0085] In the above implementation, the second metal strip 48 extends to the first electrode 41 through the second groove 202 on the surface of the third epitaxial layer 23. In this way, the second metal strip 48 is used as a conductive structure to connect the second soldering point block 72 and the first electrode 41 together, thereby achieving electrical connection between the second soldering point block 72 and the first electrode 41. In this way, after the first soldering point block 71 and the second soldering point block 72 are energized, the first epitaxial layer 21 can emit light normally.

[0086] Exemplarily, the first electrode 41 includes one of an alloy layer formed of Au and Ge, a Pt layer, and an Au layer. The second metal strip 48 may also include one of an alloy layer formed of Au and Ge, a Pt layer, and an Au layer.

[0087] As an example, the thickness of the alloy layer formed by Au and Ge is 50 angstroms to 150 angstroms, for example, the thickness of the alloy layer formed by Au and Ge is 100 angstroms.

[0088] As an example, the thickness of the Pt layer is 300 angstroms to 700 angstroms, for example, the thickness of the Pt layer is 500 angstroms.

[0089] As an example, the thickness of the Au layer is 8000 angstroms to 12000 angstroms, for example, the thickness of the Au layer is 10000 angstroms.

[0090] Exemplarily, the first insulating layer 62 is a silicon oxide layer, and the thickness of the first insulating layer 62 is 1800 angstroms to 2200 angstroms. As an example, the thickness of the first insulating layer 62 is 2000 angstroms.

[0091] Figure 5 yes Figure 1 Provided CC cross-section diagram. Figure 1 , 5As shown, the third groove 203 extends from the third epitaxial layer 23 to at least the fourth electrode 44 to expose the fourth electrode 44, wherein the fourth electrode 44 is an n-electrode. The third groove 203 has a second insulating layer 63, which extends from the third epitaxial layer 23 to the second n-type layer 221.

[0092] like Figure 1 , 5 As shown, the three-primary-color light-emitting diode chip further includes: a third metal strip 49 , and a third soldering point block 73 is connected to the third metal strip 49 .

[0093] like Figure 1 , 5 As shown, the third soldering point block 73 is located on the insulating structure 61 , and the third metal strip 49 is located in the third groove 203 and connected to the second n-type layer 221 .

[0094] In the above implementation, the third metal strip 49 extends to the fourth electrode 44 through the third groove 203 on the surface of the third epitaxial layer 23. In this way, the third metal strip 49 is used as a conductive structure to connect the third soldering block 73 and the fourth electrode 44 together, thereby achieving electrical connection between the third soldering block 73 and the fourth electrode 44. In this way, after the third electrode 43 and the fourth electrode 44 are energized, the second epitaxial layer 22 can emit light normally.

[0095] Exemplarily, the fourth electrode 44 includes one of a Cr layer, a Pt layer, and an Au layer, and the third metal strip 49 may also include one of a Cr layer, a Pt layer, and an Au layer.

[0096] As an example, the thickness of the Cr layer is 50 angstroms to 150 angstroms, for example, the thickness of the Cr layer is 100 angstroms.

[0097] As an example, the thickness of the Pt layer is 300 angstroms to 700 angstroms, for example, the thickness of the Pt layer is 500 angstroms.

[0098] As an example, the thickness of the Au layer is 2000 angstroms to 4000 angstroms, for example, the thickness of the Au layer is 3000 angstroms.

[0099] Exemplarily, the second insulating layer 63 is a silicon oxide layer, and the thickness of the second insulating layer 63 is 1800 angstroms to 2200 angstroms. As an example, the thickness of the second insulating layer 63 is 2000 angstroms.

[0100] In one implementation of the present disclosure, Figure 6 FIG. 6 is a schematic diagram of the distribution of an insulating structure 61 and a solder joint block provided in an embodiment of the present disclosure. Figure 6As shown, the insulating structure 61 covers the surface of the third epitaxial layer 23 , and has a through hole 610 exposing the sixth electrode 46 . The fourth solder joint block 74 is located on the insulating structure 61 and extends into the through hole 610 to connect with the sixth electrode 46 .

[0101] In the above implementation, the insulating structure 61 is a film layer structure covering the surface of the entire third n-type layer 231 of the third epitaxial layer 23, and the surface of the insulating structure 61 is provided with a through hole 610 exposing the sixth electrode 46, and the through hole 610 is used to place the fourth welding point block 74 so that the fourth welding point block 74 can be directly electrically connected to the sixth electrode 46, and the first welding point block 71, the second welding point block 72, and the third welding point block 73 are all arranged on the insulating structure 61 to insulate the first welding point block 71, the second welding point block 72, and the third welding point block 73 from the third n-type layer 231.

[0102] Exemplarily, the sixth electrode 46 includes one of a Cr layer, a Pt layer, and an Au layer.

[0103] As an example, the thickness of the Cr layer is 50 angstroms to 150 angstroms, for example, the thickness of the Cr layer is 100 angstroms.

[0104] As an example, the thickness of the Pt layer is 300 angstroms to 700 angstroms, for example, the thickness of the Pt layer is 500 angstroms.

[0105] As an example, the thickness of the Au layer is 2000 angstroms to 4000 angstroms, for example, the thickness of the Au layer is 3000 angstroms.

[0106] Exemplarily, the insulating structure 61 is a silicon oxide layer, and the thickness of the insulating structure 61 is 1800 angstroms to 2200 angstroms. As an example, the thickness of the insulating structure 61 is 2000 angstroms.

[0107] Among them, the first soldering point block 71, the second soldering point block 72, the third soldering point block 73 and the fourth soldering point block 74 are all arranged on the surface of the third epitaxial layer 23, the first soldering point block 71 is respectively connected to the second electrode 42, the third electrode 43 and the fifth electrode 45, the second soldering point block 72 is connected to the first electrode 41, the third soldering point block 73 is connected to the fourth electrode 44, and the fourth soldering point block 74 is connected to the sixth electrode 46. In this way, by energizing the four soldering points, the two electrodes of each epitaxial layer can be energized, so that the three epitaxial layers can be normally energized and emit light.

[0108] Optionally, a transparent conductive layer can be provided between each epitaxial layer and the electrode, and the transparent conductive layer can be an indium tin oxide (ITO) film layer. The indium tin oxide film layer has good transmittance and low resistivity. Using the indium tin oxide film layer as the transparent conductive layer can allow more light to be transmitted from the transparent conductive layer, thereby ensuring the effect; at the same time, due to the low resistivity, it is also convenient for carrier conduction and improves the injection efficiency.

[0109] Alternatively, if Figure 6 As shown, multiple light exit holes are distributed into multiple hole groups 50, and multiple hole groups 50 are distributed in an array, and each hole group 50 includes at least one first light exit hole 51, at least one second light exit hole 52, and at least one third light exit hole 53. By setting multiple hole groups 50, each hole group 50 is distributed at intervals, so that the hole groups 50 can be evenly distributed on the surface of the chip. Since each hole group 50 can transmit three different colors of light, the chip can form a very uniform light mixing effect.

[0110] Optionally, the cross-sectional shapes of the first light exit hole 51, the second light exit hole 52 and the third light exit hole 53 are all different, so as to quickly distinguish what kind of light the light exit holes transmit and confirm whether all the light exit holes in the same hole group 50 are prepared.

[0111] For example, Figure 6 As shown, the first light exit hole 51 is a circular hole and is used to transmit red light, the second light exit hole 52 is a rectangular hole and is used to transmit green light, and the third light exit hole 53 is a triangle and is used to transmit blue light.

[0112] As an example, one of the first epitaxial layer 21, the second epitaxial layer 22, and the third epitaxial layer 23 is used to emit red light, and the cross-sectional area of ​​the light-emitting hole exposing the epitaxial layer for emitting red light is the largest in the same hole group 50. That is, in the same hole group 50, the cross-sectional area of ​​the light-emitting hole for transmitting red light is larger than the cross-sectional area of ​​the light-emitting hole for transmitting green light, and the cross-sectional area of ​​the light-emitting hole for transmitting red light is larger than the cross-sectional area of ​​the light-emitting hole for transmitting blue light.

[0113] Since the epitaxial layer is close to the substrate 10 and far away from the light emitting surface, the red light emission is lower. By setting the cross-sectional area of ​​the red light to be larger, the luminous efficiency of the red light can be guaranteed, so that the three colors of light can be combined through the light emitting hole to obtain very uniform mixed light, thereby improving the mixed light effect.

[0114] At the same time, the distribution distances of the three light emitting holes in the same hole group 50 can be flexibly adjusted according to the light emitting efficiency of the three color extensions at different times, or the distribution distances between different hole groups 50 can be adjusted to achieve appropriate light distribution.

[0115] Alternatively, if Figure 2 As shown, the surface of the insulating structure 61 away from the epitaxial structure has a light shielding film 80, and the light shielding film 80 has through holes that expose the first light exit hole 51, the second light exit hole 52, and the third light exit hole 53. The light shielding film 80 is used to block the transmission of each epitaxial layer from areas other than the light exit holes to ensure that the light passing through each light exit hole can obtain a good light mixing effect.

[0116] Alternatively, if Figure 2 As shown, the surface of the first epitaxial layer 21 facing the substrate 10 has a first bonding layer 31 , and the surface of the substrate 10 facing the first epitaxial layer 21 has a second bonding layer 32 .

[0117] Figure 7 FIG. 1 is a schematic diagram of the structure of a first bonding layer 31 provided in an embodiment of the present disclosure. Figure 7 As shown, the first bonding layer 31 and the second bonding layer 32 both include a Sn layer 311 and Au blocks 312 spaced and embedded in the Sn layer 311 , and the Au blocks 312 of the first bonding layer 31 are connected to the Au blocks 312 of the second bonding layer 32 .

[0118] The first bonding layer 31 and the second bonding layer 32 are arranged into a structure in which Au blocks 312 are embedded at intervals in the Sn layer 311, wherein the Au blocks 312 are made into dots to reduce the stress of gold and utilize the advantage of Au's strong bonding strength, and Sn is made into a form of full-surface coverage to ensure the protection of the gold blocks and further improve the bonding strength.

[0119] The first bonding layer 31 and the second bonding layer 32 are bonded by alignment and ultrasonic method. Specifically, the gold blocks of the first bonding layer and the second bonding layer 32 to be bonded are aligned, heated and ultrasonicated to achieve bonding, so as to avoid the problem of excessive stress caused by excessive temperature.

[0120] In the embodiment of the present disclosure, a third bonding layer 33 is disposed between the first epitaxial layer 21 and the second epitaxial layer 22 , and a fourth bonding layer 34 is disposed between the second epitaxial layer 22 and the third epitaxial layer 23 .

[0121] Optionally, the materials used to make the third bonding layer 33 and the fourth bonding layer 34 may both include one of phosphosilicate glass, borosilicate glass and borophosphosilicate glass.

[0122] Since phosphosilicate glass, borosilicate glass and borophosphosilicate glass have good toughness, they can effectively prevent the bonding layer from forming dark scratches under the pressure applied during bonding. At the same time, phosphosilicate glass, borosilicate glass and borophosphosilicate glass are transparent materials like silicon dioxide and do not absorb light.

[0123] Figure 8FIG. 1 is a flow chart of a method for preparing a tri-primary color light emitting diode chip provided by an embodiment of the present disclosure. Figure 8 As shown, the preparation method comprises:

[0124] Step S1: providing a substrate 10.

[0125] The substrate 10 may be a GaAs substrate or a sapphire substrate.

[0126] Step S2: forming an epitaxial structure on the substrate 10 .

[0127] The epitaxial structure includes a first epitaxial layer 21 , a second epitaxial layer 22 and a third epitaxial layer 23 .

[0128] Step S2 may include the following steps:

[0129] Step 1: Grow the red light epitaxial layer.

[0130] In the disclosed embodiment, a red light epitaxial layer is grown by MOCVD (Metal-organic Chemical Vapor Deposition) method. Growing the red light epitaxial layer may include sequentially epitaxially growing an etching stop layer, a third n-type layer 231, an AlInP carrier confinement layer, a third light emitting layer 232, a third p-type layer 233, and a window layer on a GaAs substrate.

[0131] The corrosion stop layer may be a SiOx layer, a SiNx layer or a TiOx layer. The third n-type layer 231 may be an n-type AlGaInP current spreading layer, the third p-type layer 233 may be a p-type AlInP layer, the window layer may be a GaP layer, and the third light-emitting layer 232 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer that are alternately grown, and the Al content in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer is different.

[0132] When growing the red light epitaxial layer, a first electrode 41 and a second electrode 42 are formed on two opposite sides of the infrared light epitaxial layer.

[0133] Step 2: Grow the green light epitaxial layer.

[0134] In the disclosed embodiment, a green epitaxial layer is grown by MOCVD method, which may include sequentially growing an etching stop layer, an n-type layer, an AlInP carrier confinement layer, a multi-quantum well layer, a p-type layer and a window layer on a GaAs substrate.

[0135] The corrosion stop layer can be a SiOx layer, a SiNx layer or a TiOx layer. The second n-type layer 221 can be an n-type GaN layer, the second p-type layer 223 can be a p-type GaN layer, the window layer can be a GaP layer, and the second light-emitting layer 222 includes an InGaN quantum well layer and a GaN quantum barrier layer grown alternately.

[0136] When growing the green epitaxial layer, a third electrode 43 and a fourth electrode 44 are formed on two opposite sides of the green epitaxial layer.

[0137] Step 3: Grow the blue light epitaxial layer.

[0138] In the embodiment of the present disclosure, a MOCVD method is used to grow a blue light epitaxial layer, which may include sequentially epitaxially growing an etching stop layer, a first n-type layer 211, an AlInP carrier confinement layer, a first light emitting layer 212, a first p-type layer 213 and a window layer on a GaAs substrate.

[0139] The corrosion stop layer can be a SiOx layer, a SiNx layer or a TiOx layer. The first n-type layer 211 can be an n-type GaN layer, the first p-type layer 213 can be a p-type AlInP layer, the window layer can be a GaP layer, and the first light-emitting layer 212 includes an InGaN quantum well layer and a GaN quantum barrier layer grown alternately.

[0140] When the blue light epitaxial layer is grown, a fifth electrode 45 and a sixth electrode 46 are formed on two opposite sides of the blue light epitaxial layer.

[0141] After the growth of the three epitaxial layers is completed, the green epitaxial layer is bonded to the blue epitaxial layer with the blue epitaxial layer as a reference, a fourth bonding layer 34 is formed between the blue epitaxial layer and the green epitaxial layer, and the GaAs substrate on the blue epitaxial layer is removed; then, the red epitaxial layer is bonded to the green epitaxial layer, a third bonding layer 33 is formed between the green epitaxial layer and the red epitaxial layer, and the GaAs substrate on the red epitaxial layer is removed.

[0142] After bonding the three epitaxial layers together, the process also includes: forming a first bonding layer 31 on the surface of the red epitaxial layer away from the blue epitaxial layer, forming a second bonding layer 32 on the substrate 10, and bonding the first bonding layer 31 and the second bonding layer 32 to bond the red epitaxial layer to the substrate 10.

[0143] The substrate 10 may be a sapphire substrate. That is, step S2 includes epitaxially growing three epitaxial layers, and then bonding the three epitaxial layers and transferring them together onto the sapphire substrate.

[0144] Step S3: An insulating structure 61 is formed on the surface of the third epitaxial layer 23 away from the substrate 10 , wherein the surface of the insulating structure 61 has a first light emitting hole 51 exposing the first epitaxial layer 21 , a second light emitting hole 52 exposing the second epitaxial layer 22 , and a third light emitting hole 53 exposing the third epitaxial layer 23 .

[0145] After step S3 , the process includes: preparing a first soldering point block 71 , a second soldering point block 72 , a third soldering point block 73 and a fourth soldering point block 74 on the third epitaxial layer 23 .

[0146] Among them, the first welding point block 71 is connected to the second electrode 42, the third electrode 43 and the fifth electrode 45 respectively through the first groove 201, the second welding point block 72 is connected to the first electrode 41 through the second groove 202, the third welding point block 73 is connected to the fourth electrode 44 through the third groove 203, and the fourth welding point block 74 is connected to the sixth electrode 46.

[0147] Finally, the substrate of the blue light epitaxial layer is thinned to form a base plate 10 .

[0148] The substrate of the blue light epitaxial layer is a sapphire substrate, and the thickness of the substrate 10 formed after thinning is 150 μm.

[0149] The sapphire is subjected to invisible cutting and cracking, which can effectively reduce the loss of brightness, and a three-primary-color light-emitting diode chip is obtained through testing.

[0150] The above does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.

Claims

1. A three-primary-color light-emitting diode chip, characterized in that: The three-primary-color light-emitting diode chip comprises a substrate (10), an epitaxial structure and an insulating structure (61) which are stacked in sequence, the epitaxial structure comprising a first epitaxial layer (21), a second epitaxial layer (22) and a third epitaxial layer (23) which are stacked in sequence on the substrate (10), and the insulating structure (61) is located on a surface of the third epitaxial layer (23) away from the substrate (10); The surface of the insulating structure (61) has a plurality of light exit holes, the plurality of light exit holes comprising a first light exit hole (51) exposing the first epitaxial layer (21), a second light exit hole (52) exposing the second epitaxial layer (22), and a third light exit hole (53) exposing the third epitaxial layer (23); the plurality of light exit holes are distributed into a plurality of hole groups (50); the plurality of hole groups (50) are distributed in an array, and each of the hole groups (50) comprises at least one of the first light exit holes (51), at least one of the second light exit holes (52), and at least one of the third light exit holes (53); The first epitaxial layer (21) is used for emitting red light, and in the same hole group (50), the cross-sectional area of ​​the light-emitting hole exposing the epitaxial layer for emitting red light is the largest.

2. The three-primary-color light-emitting diode chip according to claim 1, characterized in that: The cross-sectional shapes of the first light exit hole (51), the second light exit hole (52) and the third light exit hole (53) are all different.

3. The three-primary-color light-emitting diode chip according to claim 1 or 2, characterized in that: The surface of the first epitaxial layer (21) close to the substrate (10) has a first bonding layer (31), and the surface of the substrate (10) close to the first epitaxial layer (21) has a second bonding layer (32); The first bonding layer (31) and the second bonding layer (32) both comprise a Sn layer (311) and Au blocks (312) embedded in the Sn layer (311) at intervals, and the Au blocks (312) of the first bonding layer (31) are relatively connected to the Au blocks (312) of the second bonding layer (32).

4. The three-primary-color light-emitting diode chip according to claim 1 or 2, characterized in that: Two opposite surfaces of the first epitaxial layer (21) are provided with a first electrode (41) and a second electrode (42), the first electrode (41) being close to the substrate (10), two opposite surfaces of the second epitaxial layer (22) are provided with a third electrode (43) and a fourth electrode (44), the third electrode (43) being close to the first epitaxial layer (21), and two opposite surfaces of the third epitaxial layer (23) are provided with a fifth electrode (45) and a sixth electrode (46), the fifth electrode (45) being directed toward the second epitaxial layer (22); The surface of the third epitaxial layer (23) has a first groove (201) exposing the second electrode (42), the third electrode (43) and the fifth electrode (45), a second groove (202) exposing the first electrode (41), and a third groove (203) exposing the fourth electrode (44); The third epitaxial layer (23) also has a first welding point block (71), a second welding point block (72), a third welding point block (73) and a fourth welding point block (74); the first welding point block (71) is respectively connected to the second electrode (42), the third electrode (43) and the fifth electrode (45) through the first groove (201); the second welding point block (72) is connected to the first electrode (41) through the second groove (202); the third welding point block (73) is connected to the fourth electrode (44) through the third groove (203); and the fourth welding point block (74) is connected to the sixth electrode (46).

5. The three-primary-color light-emitting diode chip according to claim 1 or 2, characterized in that: The first epitaxial layer (21) comprises a first n-type layer (211), a first light-emitting layer (212) and a first p-type layer (213) which are sequentially stacked on the substrate (10); The second epitaxial layer (22) comprises a second p-type layer (223), a second light-emitting layer (222) and a second n-type layer (221) which are sequentially stacked on the first p-type layer (213); The third epitaxial layer (23) includes a third p-type layer (233), a third light-emitting layer (232) and a third n-type layer (231) which are sequentially stacked on the second n-type layer (221).

6. The three-primary-color light-emitting diode chip according to claim 1 or 2, characterized in that: A surface of the insulating structure (61) away from the epitaxial structure has a light shielding film (80), and the light shielding film (80) has through holes that expose the first light output hole (51), the second light output hole (52), and the third light output hole (53).

7. The three-primary-color light-emitting diode chip according to claim 1 or 2, characterized in that: The thickness of the first epitaxial layer (21), the second epitaxial layer (22) and the third epitaxial layer (23) are all 1 μm to 3 μm.

8. A method for preparing a three-primary-color light-emitting diode chip, characterized in that: The preparation method comprises: providing a substrate; forming an epitaxial structure on the substrate, the epitaxial structure comprising a first epitaxial layer, a second epitaxial layer and a third epitaxial layer sequentially stacked on the substrate; An insulating structure is formed on a surface of the third epitaxial layer away from the substrate, the surface of the insulating structure having a first light exit hole exposing the first epitaxial layer, a second light exit hole exposing the second epitaxial layer, and a third light exit hole exposing the third epitaxial layer, the multiple light exit holes are distributed into multiple hole groups, the multiple hole groups are distributed in an array, each of the hole groups includes at least one of the first light exit holes, at least one of the second light exit holes, and at least one of the third light exit holes; the first epitaxial layer is used to emit red light, and in the same hole group, the light exit hole exposing the epitaxial layer used to emit red light has the largest cross-sectional area.

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