Thin film transistor and display panel using thin film transistor

Abstract

A display panel according to an embodiment of the present specification includes a substrate, an active electrode on the substrate and including a source region, a drain region, and a channel region, and an active upper electrode disposed on the active electrode and having a curved shape. The active upper electrode and the channel region of the active electrode can overlap each other, and the channel region can have the same shape as the active upper electrode. Accordingly, a driving element included in the display panel can generate a high driving current, and an integration density in a pixel can be improved.

Description

Technical Field

[0001] This disclosure relates to thin-film transistors, and more specifically, to thin-film transistors capable of generating high drive currents and display panels using the same thin-film transistors. Background Technology

[0002] Liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), and quantum dot displays (QDs), which have been widely used to date, have gradually expanded their application scope.

[0003] In the above-mentioned display device, multiple light-emitting elements are disposed on a substrate to realize an image, and a driving element for supplying driving signals or driving current is disposed on the substrate together with the light-emitting elements to control each light-emitting element to emit light individually, so that the multiple light-emitting elements disposed on the substrate are interpreted and displayed on the substrate according to the arrangement of the information to be expressed.

[0004] Since liquid crystal displays (LCDs) are not self-emissive, a backlight unit is required to emit light from the rear surface of the LCD. The backlight unit may increase the thickness of the LCD, potentially limiting its implementation in various designs (e.g., flexible or circular), and may reduce brightness and response time.

[0005] Meanwhile, display devices with self-emissive elements can be made thinner than display devices with built-in light sources, thereby enabling flexible and foldable display devices. Display devices with self-emissive elements can include organic light-emitting display devices that include organic materials as the light-emitting layer and LED display devices that use LEDs (light-emitting diodes) as the light-emitting elements. Since self-emissive display devices, such as organic light-emitting display devices or LED display devices, do not require a separate light source, they can be used as thinner or various types of display devices.

[0006] However, in organic light-emitting display devices using organic materials, defective pixels, such as those oxidized between the organic light-emitting layer and the electrodes due to oxygen and moisture penetration, are prone to occur. Therefore, various technical configurations are required to minimize oxygen and moisture penetration.

[0007] To address the aforementioned issues, display devices that use LEDs made of inorganic materials as light-emitting elements have recently been researched and developed. These light-emitting display devices are attracting attention as the next generation of display devices due to their high definition and high reliability.

[0008] Detailed description of this disclosure

[0009] Technical issues

[0010] LEDs are semiconductor devices that emit light when an electric current flows through them, and are widely used in various display devices such as lighting, televisions, signage displays, and tiling displays. An LED device consists of an n-type electrode, a p-type electrode, and an active layer between them. Both the n-type and p-type electrodes are formed of semiconductors. When current flows through the n-type and p-type electrodes, electrons from the n-type electrode and holes from the p-type electrode combine in the active layer to emit light.

[0011] LED elements are formed from compound semiconductors such as GaN, which allows for the injection of high current due to the properties of inorganic materials, thus achieving high brightness, and also provides high reliability due to their low sensitivity to environments such as heat, humidity, and oxygen.

[0012] In addition, since the internal quantum efficiency of LED elements is 90%, which is higher than that of organic light-emitting display devices, LED elements can display high-brightness images and have the advantage of realizing low-power display devices.

[0013] Furthermore, unlike organic light-emitting display devices, LED elements use inorganic materials and are minimally affected by oxygen and moisture, thus eliminating the need for separate encapsulation films or substrates to reduce oxygen and moisture penetration. Therefore, its advantage lies in reducing the non-display area of ​​the display device, i.e., the edge area created by the application of encapsulation films or substrates.

[0014] However, compared to liquid crystal displays or organic light-emitting displays, light-emitting elements such as LEDs require relatively high drive currents. A pixel driving circuit includes a driving element for providing a constant current to the light-emitting element. Furthermore, the light-emitting element emits light by receiving drive current from the pixel driving circuit connected to it.

[0015] To generate high drive current, the shape of the active electrode can be modified and designed, and typically, the drive current can be increased by making the width of the active electrode larger. In this case, the length of the active electrode is a value in the direction of carrier movement, and carriers move from the source region to the drain region of the active electrode. The width of the active electrode refers to the width of the path along which the carriers move. Specifically, the length and width of the active electrode refer to the length and width of the channel region, which is the path along which the carriers move.

[0016] However, when the width of the active electrode is made larger, the area occupied by the driving element in the pixel increases, thus limiting the reduction of pixel area when a high-resolution display panel is required.

[0017] Therefore, the inventors of this disclosure recognized the above-mentioned problems and invented a drive element capable of generating high drive current and a display panel using the drive element.

[0018] The problem to be solved by embodiments of this disclosure is to provide a thin-film transistor that can increase the integration density in a pixel while generating a high drive current.

[0019] The purpose of this disclosure is not limited to the purposes mentioned above, and other purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0020] Technical solutions

[0021] In one embodiment of the display panel according to the present disclosure, the display panel includes: a substrate; an active electrode above the substrate and including a source region, a drain region, and a channel region; and an active top electrode in a curved shape above the active electrode. The active top electrode and the channel region of the active electrode overlap each other, and the channel region may have the same shape as the active top electrode. Therefore, the driving elements included in the display panel can generate high driving current and can improve the integration density in the pixels.

[0022] In one embodiment of the display panel according to this disclosure, the display panel includes: an active electrode comprising a source region, a drain region, and a channel region; an active upper electrode above the active electrode, overlapping the active electrode, and implemented in a curved shape; and an active lower electrode below the active electrode and overlapping the active electrode. The active upper electrode and the active lower electrode serve as source electrodes, drain electrodes, or gate electrodes. Therefore, the driving elements included in the display panel can generate high drive current and can improve the integration density in the pixels.

[0023] Details of other implementation methods are included in the detailed embodiments and accompanying drawings.

[0024] The effect of this public information

[0025] According to embodiments of this disclosure, a display panel includes a thin-film transistor in which the source electrode or drain electrode is implemented in a bent shape, enabling the supply of a high drive current to the light-emitting element, thereby improving brightness.

[0026] Furthermore, according to embodiments of this disclosure, by implementing overlapping thin-film transistors and capacitors, the integration density in pixels can be increased, thereby realizing a high-resolution display device.

[0027] Furthermore, according to embodiments of this disclosure, by making the width of the channel region of the active electrode of the thin-film transistor longer than the length of the channel region, the thin-film transistor can provide a high driving current to the light-emitting element.

[0028] Since the content of this disclosure, which describes the problem to be solved, the solution to the problem, and the effects described above, does not specify the essential features of the claims, the scope of the claims is not limited to the matters described in the content of this disclosure. Attached Figure Description

[0029] Figure 1 This is a plan view showing a display panel according to one embodiment of the present disclosure.

[0030] Figure 2 This is a circuit diagram illustrating a pixel driving circuit and a light-emitting element according to one embodiment of the present disclosure.

[0031] Figure 3 This is a planar view of a subpixel according to one embodiment of the present disclosure.

[0032] Figure 4 This is a plan view illustrating a portion of a pixel driving circuit according to one embodiment of the present disclosure.

[0033] Figure 5 It is along Figure 4 The cross-sectional view taken from A-A'.

[0034] Figures 6 to 12 It shows the manufacturing process. Figure 4 A view of the method of the component shown.

[0035] Figure 13 This is a plan view illustrating a portion of a pixel driving circuit according to one embodiment of the present disclosure.

[0036] Figure 14 It is along Figure 13 The cross-sectional view taken from B-B'.

[0037] Figures 15 to 20 It shows the manufacturing process. Figure 13 A view of the method of the component shown.

[0038] Figure 21 This is a plan view illustrating a portion of a pixel driving circuit according to one embodiment of the present disclosure.

[0039] Figure 22 It is along Figure 21 The cross-sectional view taken from C-C'.

[0040] Figure 23 This is a plan view illustrating a portion of a pixel driving circuit according to one embodiment of the present disclosure.

[0041] Figure 24 It is along Figure 23 The cross-sectional view taken from D-D'.

[0042] Figure 25 This is a plan view illustrating a portion of a pixel driving circuit according to one embodiment of the present disclosure.

[0043] Figure 26 It is along Figure 25 The cross-sectional view taken from E-E'. Detailed Implementation

[0044] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but will be implemented in various different forms. These embodiments are provided only to ensure that the disclosure is complete and to fully inform those skilled in the art of the scope of this disclosure.

[0045] The shapes, dimensions, scales, angles, numbers, etc., disclosed in the accompanying drawings used to explain embodiments of this disclosure are illustrative, and this disclosure is not limited to the matters shown. Throughout this disclosure, the same reference numerals refer to the same parts. Furthermore, in describing this disclosure, detailed descriptions of related prior art will be omitted if it is determined that such detailed descriptions would unnecessarily obscure the subject matter of this disclosure. When using terms such as "comprising," "having," or "constituting" in this disclosure, additional parts may be added unless "only" is used. When parts are described in the singular, unless specifically and explicitly stated otherwise, it includes cases where a plural number is included.

[0046] When interpreting a component, even if there is no separate explicit description, it is interpreted as including the tolerance range.

[0047] When describing positional relationships, for example, when describing the positional relationship between two parts as "on top of", "above", "below", "on the side", etc., one or more other parts may be located between the two parts unless "exactly", "directly" or "adjacent" is used.

[0048] When describing temporal relationships, such as when using phrases like "after," "next," "next," or "before," these relationships can include discontinuous cases unless "exactly" or "directly" is used.

[0049] Features of various embodiments of this disclosure may be combined or integrated in part or in whole with each other, and may be technically interlocked and driven in various ways. The embodiments may be implemented independently of each other or may be implemented together in a related relationship.

[0050] In this disclosure, the gate driving portion and pixel driving circuit formed on the substrate of the display panel can be implemented as n-type or p-type thin-film transistors. For example, the thin-film transistor can be implemented as a transistor with a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) structure. A transistor is a three-electrode device including a gate electrode, a source electrode, and a drain electrode. The source electrode provides charge carriers to the transistor. In the transistor, charge carriers begin to migrate from the source electrode. The drain electrode is the electrode through which charge carriers leave the transistor to the outside.

[0051] For example, in a transistor, charge carriers move from the source electrode to the drain electrode. In the case of an n-type transistor, since the charge carriers are electrons, the voltage at the source electrode is lower than the voltage at the drain electrode to allow movement from the source to the drain. In an n-type transistor, since electrons move from the source to the drain, the current flows from the drain to the source. In the case of a p-type transistor, since the charge carriers are holes, the voltage at the source electrode is higher than the voltage at the drain electrode, allowing holes to move from the source to the drain. Because holes move from the source to the drain in a p-type transistor, the current flows from the source to the drain. The source and drain electrodes of a transistor are not fixed and can change depending on the applied voltage. Therefore, the source and drain electrodes can be referred to as the first electrode and the second electrode, or the second electrode and the first electrode, respectively.

[0052] In the following text, the gate on-voltage is the voltage of the gate signal that enables the transistor to turn on, and the gate off-voltage is the voltage that enables the transistor to turn off.

[0053] In the following description, a thin-film transistor and a display panel according to one embodiment of the present disclosure will be described with reference to the accompanying drawings. In this context, the thin-film transistor is simply referred to as a transistor. Furthermore, since the source electrode and drain electrode of the transistor, including the driving transistor, are determined according to the direction of the current, the source electrode mentioned below can be changed to a drain electrode, and the drain electrode can be changed to a source electrode.

[0054] Figure 1 This is a plan view showing a display panel according to one embodiment of the present disclosure. Figure 2 This is a circuit diagram illustrating a pixel driving circuit and a light-emitting element according to one embodiment of the present disclosure. Furthermore, Figure 3 This is a planar view of a subpixel according to one embodiment of the present disclosure.

[0055] According to one embodiment of the present disclosure, a display panel 10 includes a substrate divided into a display area 10a and a non-display area 10b having a plurality of unit pixels UP.

[0056] A unit pixel UP can be composed of multiple sub-pixels SP1, SP2 and SP3 on the front surface of the substrate, and can typically include sub-pixels SP1, SP2 and SP3 that emit red light, blue light and green light, but is not limited thereto, and can also include sub-pixels that emit white light, etc.

[0057] The substrate is an array substrate on which transistors are formed, and includes plastic or glass materials.

[0058] The substrate according to the example may include an opaque or colored polyimide material. In this case, a backplate coupled to the rear surface of the substrate may also be included to hold the display panel 10 in a planar state. The backplate according to this example may include a plastic material, such as polyethylene terephthalate. The substrate according to this example may be a glass substrate. For example, the glass substrate may be a thin glass substrate with a thickness of 100 μm or less and may have flexible properties. Additionally, the substrate may be divided into two or more substrates or two or more layers.

[0059] The non-display area 10b can be defined as the area on the substrate other than the display area 10a, and can have a width (or size) that is relatively narrower than the display area 10a, and can be defined as a border area.

[0060] Each of the plurality of unit pixels UP is disposed in the display area 10a. In this case, each of the plurality of unit pixels UP is arranged in the display area 10a to have a predetermined first reference pixel spacing along the X-axis direction and a predetermined second reference pixel spacing along the Y-axis direction. Each of the first reference pixel spacing and the second reference pixel spacing can be defined as the distance between the center portions of adjacent unit pixels UP in the X-axis direction or the Y-axis direction.

[0061] Furthermore, similar to the first reference pixel spacing and the second reference pixel spacing, the distance between the sub-pixels SP1, SP2 and SP3 that constitute the unit pixel UP can also be defined as the first reference sub-pixel spacing and the second reference sub-pixel spacing.

[0062] In the display panel 10 including the LED element 50, the width of the non-display area 10b can be smaller than the pixel pitch or sub-pixel pitch, and for example, when a tiled display device is implemented using the display panel 10 having a non-display area 10b with a length equal to or less than the pixel pitch or sub-pixel pitch, a tiled display device with essentially no border area can be implemented since the non-display area 10b is smaller than the pixel pitch or sub-pixel pitch.

[0063] To achieve a tiled display or multi-screen display device with virtually no or reduced bezel area, the display panel 10 can maintain a constant first reference pixel pitch, a second reference pixel pitch, a first reference subpixel pitch, and a second reference subpixel pitch. However, by defining the display area 10a into multiple parts and making the lengths of the aforementioned pitches different in each part, such that the pixel pitch in the part adjacent to the non-display area 10b can be wider than the pixel pitch in other parts, the size of the bezel area can be relatively smaller than the pixel pitch. In this case, since display panels 10 with different pixel pitches may cause image distortion, considering the setting of the pixel pitch, image processing is performed by comparing and sampling with adjacent parts, thereby reducing the bezel area and eliminating image distortion.

[0064] Reference Figure 2 and Figure 3 The configuration of sub-pixels SP1, SP2, and SP3 constituting a unit pixel UP of the display panel 10 and the driving circuitry is described. Pixel driving lines are disposed on the substrate to supply signals to each of the plurality of sub-pixels SP1, SP2, and SP3. According to one embodiment of the present disclosure, the pixel driving lines can be divided into a horizontal axis 30 and a vertical axis 20. The horizontal axis 30 may include scan lines 31 and 32 and an emitter line 34, and the vertical axis 20 may include a data line 28 and power lines 22, 24, and 26. The scan lines include a first scan line 31 providing a first scan signal Scan1, a second scan line 32 providing a second scan signal Scan2, and an emitter line 34 providing an emitter signal EM, and the power lines include a high-potential power line 22 providing a high-potential power supply voltage Vdd, a low-potential power supply line 24 providing a low-potential power supply voltage Vss, and an initialization voltage line 26 providing an initialization voltage Vini. The scan lines and emitter lines can be collectively referred to as gate lines.

[0065] Gate lines are disposed on the substrate and extend for a longer period along the horizontal axis X of the substrate while being spaced apart from each other at regular intervals along the vertical axis Y.

[0066] The data lines are disposed on the substrate to intersect the gate lines, and are extended relatively long along the vertical axis Y of the substrate while being spaced apart from each other at regular intervals along the horizontal axis X.

[0067] Power lines are disposed on the substrate parallel to data line 28 and can be formed together with data line 28. Furthermore, the power lines provide externally supplied pixel driving power to the adjacent sub-pixels SP1, SP2, and SP3, respectively. For example, one power line 22, 24, and 26 can be provided for each of the multiple unit pixels UP. In this case, at least three sub-pixels SP1, SP2, and SP3 constituting a unit pixel UP share a single power line 22, 24, and 26. Therefore, the number of power lines used to drive each of the sub-pixels SP1, SP2, and SP3 can be reduced, and the aperture ratio of each unit pixel UP can be increased, or the size of each unit pixel can be reduced, by reducing the number of power lines.

[0068] Each of sub-pixels SP1, SP2, and SP3 is disposed in a sub-pixel region defined by gate lines 31, 32, and 34 and data line 28. Furthermore, each of sub-pixels SP1, SP2, and SP3 can be defined as the region of the smallest unit that actually emits light.

[0069] At least three adjacent subpixels SP1, SP2, and SP3 can constitute a unit pixel UP for displaying color. For example, a unit pixel UP includes red subpixels SP1, green subpixels SP2, and blue subpixels SP3 that are adjacent to each other along the horizontal axis X, and may also include white subpixels for enhancing brightness. Although the arrangement of subpixels shown in this disclosure is striped, it is not limited thereto.

[0070] Each of a plurality of sub-pixels SP1, SP2 and SP3 according to one embodiment of the present disclosure includes a pixel driving circuit 40 and an LED element 50.

[0071] Pixel driving circuit 40 is disposed in a circuit region defined in each of sub-pixels SP1, SP2, and SP3, and is connected to adjacent gate lines 31, 32, and 34, data line 28, and power lines 22, 24, and 26. Based on the pixel driving power supplied through power lines 22, 24, and 26, pixel driving circuit 50 responds to scan pulses provided through gate lines 31, 32, and 34, and controls the current flowing through LED element 50 according to the data voltage provided through data line 28.

[0072] A pixel driving circuit 40 according to one embodiment of the present disclosure includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a driving transistor DT, and a capacitor Cst. The first transistor T1 to the fifth transistor T5 and the driving transistor DT can be implemented as PMOS type thin-film transistors, and the response characteristics of the pixel driving circuit 40 can be ensured by such transistors. However, the spirit of the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the fifth transistor T5 and the driving transistor DT can be implemented as an NMOS type thin-film transistor with good cutoff current characteristics, and the remaining transistors can be implemented as PMOS type thin-film transistors with good response characteristics.

[0073] LED element 50 is mounted in each of the sub-pixels SP1, SP2, and SP3. LED element 50 is electrically connected to the pixel driving circuit 40 and the low-potential power line 24 of the corresponding sub-pixel, thereby emitting light due to current flowing from the pixel driving circuit 40, specifically the driving transistor DT, to the low-potential power line 24. According to one embodiment of this disclosure, the LED element 24 can be an optical element or a light-emitting diode chip emitting any of red, green, blue, and white light. Here, the light-emitting diode chip can have a scale from 1 to 100 micrometers, but is not limited thereto, and can have a size smaller than the size of the remaining light-emitting area in the regions of the sub-pixels SP1, SP2, and SP3 excluding the circuit area occupied by the pixel driving circuit 40.

[0074] The driving transistor DT is a driving element that controls the current flowing through the LED element 50 according to the gate-source voltage of the driving transistor DT. The driving transistor DT includes a gate electrode connected to a first node N1, a source electrode connected to a high-potential power supply line 22, and a drain electrode connected to a second node N2. The driving transistor DT can be implemented as a transistor using a novel gate structure according to one embodiment of the present disclosure to provide a high driving current to the LED element 50.

[0075] The first transistor T1 is connected between the first node N1 and the second node N2 and is controlled according to the first scan signal Scan1. The gate electrode of the first transistor T1 is connected to the first scan line 31 to which the first scan signal Scan1 is applied. When the driving transistor DT is turned on, the first transistor T1 is diode-connected by connecting the gate electrode and the drain electrode of the driving transistor DT. In this case, the first transistor T1 senses and compensates for the threshold voltage factor of the driving transistor DT.

[0076] The second transistor T2 is connected between data line 28 and the third node N3, and is controlled according to the first scan signal Scan1. The gate electrode of the second transistor T2 is connected to the first scan line 31. The second transistor T2 is turned on to apply the data voltage Vdata to the third node N3.

[0077] The third transistor T3 is connected between the second node N2 and the LED element 50, and is controlled according to the emission signal EM provided through the emission line 34. The third transistor T3 is turned on to provide the current flowing through the driving transistor DT to the LED element 50. The third transistor T3 controls the LED element 50, which has a low emission threshold voltage, not to emit light due to the initialization voltage Vini.

[0078] The fourth transistor T4 is connected between the third node N3 and the initialization voltage line 26, and is controlled according to the transmit signal EM. The fourth transistor T4 is turned on to provide the initialization voltage Vini supplied to the third node N3 through the initialization voltage line 26, thereby initializing the voltage of the third node N3.

[0079] The fifth transistor T5 is connected between the second node N2 and the initialization voltage line 26, and is controlled according to the second scan signal Scan2 supplied through the second scan line 32. The fifth transistor T5 is turned on to provide the initialization voltage Vini to the second node N2, thereby discharging the voltage of the second node N2.

[0080] The capacitor Cst is located in the overlapping region of the first node N1 and the third node N3 to store a voltage corresponding to the data voltage Vdata supplied to the gate electrode of the driving transistor DT, and to turn on the driving transistor DT by the stored voltage.

[0081] Next, the operation of the pixel driving circuit 40 will be described. Figure 2The operation of the pixel driving circuit 40 can be divided into a first initialization cycle, a second initialization cycle, a compensation cycle, a hold cycle, and an emission cycle. In the first initialization cycle, since the emission signal EM and the second scan signal Scan2 are in a gate-on state, the voltage of the third node N3 is initialized, and the LED element 50 remains in an emitting state. In the second initialization cycle, the emission signal EM is switched to a gate-off voltage, the first scan signal Scan1 is switched to a gate-on voltage, and the second scan signal Scan2 remains in a gate-on voltage, causing the LED element 50 to stop emitting light and the data voltage Vdata to be applied to the third node N3. In the compensation cycle, the second scan signal Scan2 is switched to a gate-off voltage, and the first transistor T1 is turned on, causing the driving transistor DT to perform a diode connection to execute the threshold voltage compensation process. In the hold cycle, since the first scan signal Scan1, the second scan signal Scan2, and the emission signal EM are all in a gate-off voltage state, the voltage applied in the previous cycle is maintained at each node. During the emission cycle, the emission signal EM is switched to a gate-on voltage, and the LED element 50 emits light due to the driving current supplied from the driving transistor DT. In this case, the initialization voltage Vini is lower than the high-potential power supply voltage but higher than the low-potential power supply voltage. Since the driving current of the pixel driving circuit 40 described above is not affected by the high-potential power supply voltage, uniform image quality can be achieved in a high-resolution display device.

[0082] According to one embodiment of this disclosure, the pixel driving circuit 40 is not limited to the configuration of the first transistor T1 to the fifth transistor T5, the driving transistor DT and the capacitor Cst described above, and may also include auxiliary transistors and / or auxiliary capacitors controlled by an additional transmission signal EM.

[0083] Reference Figure 3 Gate lines 31 and 32, emitter line 34, data line 28, and power lines 22, 24, and 26 are disposed in a sub-pixel, while pixel driving circuit 40 and LED element 50 are disposed in different regions. The sub-pixel according to one embodiment of this disclosure is not limited to... Figure 3 The accompanying diagram shows that the pixel driving circuit 40 can be arranged to overlap with the LED element 50. In this case, the area utilization of the sub-pixels is improved, thereby enabling the pixel size required in a high-resolution display panel.

[0084] Figure 4 This is a plan view illustrating a portion of a pixel driving circuit according to one embodiment of the present disclosure. Furthermore, Figure 5 It is along Figure 4 The cross-sectional view taken from A-A'.

[0085] like Figure 2 As shown, each sub-pixel SP1, SP2, and SP3 of the display panel 10 according to one embodiment of the present disclosure includes a pixel driving circuit 40 and an LED element 50. Among the various components constituting the pixel driving circuit 40, a driving transistor DT, which applies a driving current (or light-emitting current) to the LED element 50, a first transistor T1 connected to the gate electrode of the driving transistor DT, and a capacitor Cst will be described.

[0086] Figure 4 This is a plan view of a driving transistor DT including an active upper electrode implemented in a U-shape. The driving transistor DT includes an active lower electrode 113, an active upper electrode 117, an active electrode 115D, a source electrode, and a drain electrode 119A. In one embodiment of the driving transistor DT according to this disclosure, since the active lower electrode 113 and the active upper electrode 117 serve as gate electrodes, the driving transistor DT is implemented as a dual-gate transistor. Furthermore, the first transistor T1 includes a gate electrode 131, an active electrode 115D, a source electrode, and a drain electrode.

[0087] The source electrode of the driving transistor DT is directly connected to the high-potential power line 122 via contact hole CH14, and the drain electrode 119A is connected to the third transistor T3 via contact hole CH16. In some cases, the third transistor T3 can be omitted, and the drain electrode 119A of the driving transistor DT can be connected to the anode electrode of the LED element 50.

[0088] In the driving transistor DT, an active lower electrode 113 is disposed at the lower part and an active upper electrode 117 is disposed at the upper part relative to the active electrode 115D of the driving transistor DT, and the active lower electrode 113 and the active upper electrode 117 are in contact with each other. A cap electrode 111 overlapping with the active lower electrode 113 is disposed below the active lower electrode 113 of the driving transistor DT. The active lower electrode 113 and the cap electrode 111 overlap to form a capacitor Cst. The cap electrode 111 may be referred to as the lower electrode.

[0089] The gate electrodes 113 and 117 of the driving transistor DT are electrically connected to the source or drain region of the active electrode 115S of the first transistor T1 via the connecting electrode 119C. The source or drain electrode of the first transistor T1 connected to the gate electrodes 113 and 117 of the driving transistor DT does not need to be separately provided, and can be achieved by directly connecting the connecting electrode 119C to the active electrode 115S of the first transistor T1.

[0090] The gate electrode 131 of the first transistor T1 is disposed above and overlaps with the active electrode 115S.

[0091] As described above, the active upper electrode 117 of the driving transistor DT is implemented as a U-shaped structure. The channel region of the driving transistor DT is formed with the same shape as the active upper electrode 117, and can achieve... Figure 12 The channel width W is greater than the channel length L of the driving transistor DT. Because the drive current of the driving transistor DT is... Figure 12 The channel width W is proportional to and in line with Figure 12 The channel length L is inversely proportional to the channel length, so it can be achieved by... Figure 12 The channel width W increases more than Figure 12 A larger channel length L increases the drive current, allowing the heat concentration area to be evenly distributed, thereby improving the reliability of the drive transistor DT.

[0092] In a driving transistor DT according to one embodiment of the present disclosure, gate electrode 113 and gate electrode 117 are implemented in a U-shape, thereby increasing... Figure 12 The channel width W is increased, while the area occupied by the driving transistor DT is reduced.

[0093] Furthermore, since the driving transistor DT is implemented as a dual-gate transistor and the cap electrode 111 is located below the driving transistor DT, the capacitor Cst can be formed to overlap with the driving transistor DT. Therefore, there is no need to prepare a separate area for forming the capacitor Cst in the sub-pixel, thereby reducing the area occupied by the pixel driving circuit.

[0094] Figures 6 to 12 It shows the manufacturing process. Figure 4 A view showing the method of the component. (Refer to...) Figure 5 Describe together Figures 6 to 12 .

[0095] Reference Figure 6 The cap electrode 111 is patterned and formed on the substrate 110. A first insulating layer 112 is formed on the cap electrode 111 above the entire surface of the substrate 110.

[0096] Reference Figure 7An active lower electrode 113 is formed on the cap electrode 111 and the first insulating layer 112. The active lower electrode 113 is formed to overlap with the cap electrode 111. The cap electrode 111 and the active lower electrode 113 overlap each other to form a capacitor. The cap electrode 111 and the active lower electrode 113 are the electrodes that realize the capacitor Cst. Therefore, the cap electrode 111 is connected to the second transistor T2 and the fourth transistor T4, and the active lower electrode 113 is the gate electrode of the driving transistor DT, and also an electrode of the capacitor Cst. The cap electrode 111 and the active lower electrode 113 can be semiconductors such as silicon (Si) or conductive metals, such as any one, two or more alloys of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or multiple layers thereof. Furthermore, a second insulating layer 114 is formed on the active lower electrode 113.

[0097] Reference Figure 8 Active electrodes 115D and 115S are formed on the second insulating layer 114. The active electrode 115D of the driving transistor DT is formed in the region of the active lower electrode 113, overlapping with the active lower electrode 113. Furthermore, the active electrode 115S of the first transistor T1 is formed on the same layer as the active electrode 115D of the driving transistor DT and is spaced apart from each other, but is formed adjacent to the active lower electrode 113 for easy contact with the active lower electrode 113. The active electrodes 115D and 115S can be formed from any semiconductor material such as amorphous silicon, polycrystalline silicon, oxide, and organic materials, but are not limited thereto. A third insulating layer 116 is formed on the active electrodes 115D and 115S.

[0098] Reference Figure 9 The CH11 contact hole CH11 is formed in the second insulating layer 114 and the third insulating layer 116, so that the surface of the active lower electrode 113 can be exposed.

[0099] Reference Figure 10 The active upper electrode 117 and the gate electrode 131 of the first transistor T1 are patterned and formed on a third insulating layer 116 including a CH11 contact hole CH11 exposed to air. The active upper electrode 117 is the gate electrode of the driving transistor DT and contacts the active lower electrode 113 through the CH11 contact hole CH11. The active upper electrode 117 is patterned in a U-shape and overlaps with the active electrode 115D of the driving transistor DT. The gate electrode 131 of the first transistor T1 is formed to overlap with the active electrode 115D of the first transistor T1 and spaced apart from the active upper electrode 117. Furthermore, the gate electrode 131 of the first transistor T1 is formed to extend along the horizontal axis and can be shared with adjacent sub-pixels on the horizontal axis. The first transistor T1 is implemented as a top-gate transistor.

[0100] Next, refer to Figure 5 and Figure 10 Doping is performed to form active electrodes 115D and 115S that do not overlap with the active upper electrode 117 and the gate electrode 131 of the first transistor T1 as the source and drain regions, respectively. In this case, since the transistor described as an example of an embodiment according to this disclosure is a PMOS, it can be implemented as P-doped. In the case of the active upper electrode 117, the active electrode 115D of the drive transistor DT, which does not overlap with the active upper electrode 117, is provided inside and outside the U-shape relative to the active upper electrode 117, and this region is doped. By providing the source and drain electrodes inside and outside the U-shape that does not overlap with the active electrode 115D of the drive transistor DT via doping, and not at the beginning and end of the U-shape, the channel width is formed to be longer than the channel length, so that the drive transistor DT can generate a high current. Furthermore, the drive transistor DT is implemented as a dual-gate transistor due to the active lower electrode 113 and the active upper electrode 117, thereby generating a high current.

[0101] A fourth insulating layer 118 is formed on the active upper electrode 117 and the gate electrode 131 of the first transistor T1. The fourth insulating layer 118 can be used to protect the driving transistor DT and the first transistor T1. After the fourth insulating layer 118 is formed, in order to activate the implanted ions and reduce the density of trapped states, a heat treatment such as hydrogenation can be applied to improve the performance of the transistor.

[0102] The first insulating layer 112, the second insulating layer 114, the third insulating layer 116 and the fourth insulating layer 118 mentioned above can be formed as a single layer or multiple layers made of inorganic insulating materials, and can be formed of silicon oxide (SiOx), silicon nitride (sinx) and the like.

[0103] Reference Figure 11 Contact holes CH14 and CH15 are formed in the third insulating layer 116 and the fourth insulating layer 118 to expose the active electrode 115D of the driving transistor DT. Contact hole CH14 allows the source electrode of the driving transistor DT to be contacted, and contact hole CH15 allows the drain electrode of the driving transistor DT to be contacted.

[0104] Contact hole CH13 is formed in the fourth insulating layer 118 to expose the active upper electrode 117, and contact hole CH12 is formed in the third insulating layer 116 and the fourth insulating layer 118 to expose the active electrode 115S of the first transistor T1. Contact holes CH12 and CH13 allow the active electrode 115S of the first transistor T1 and the active upper electrode 117 of the driving transistor DT to contact each other through connection electrodes.

[0105] Reference Figure 12 A high-potential power line 122 is patterned and formed on a fourth insulating layer 118, including a CH14 contact hole CH14 exposed to air. The source electrode of the driving transistor DT is integrally formed with the high-potential power line 122 through the CH14 contact hole CH14. The driving transistor DT receives a high-potential voltage Vdd through the high-potential power line 122. Furthermore, a drain electrode 119A is patterned and formed on the fourth insulating layer 118, including a CH15 contact hole CH15 exposed to air. The drain electrode 119A is formed to overlap with the active electrode 115D of the driving transistor DT, and is disposed inside the active upper electrode 117 so as not to overlap with the active upper electrode 117.

[0106] By placing a curved active top electrode above the active electrode 115D of the driving transistor DT, placing the drain electrode inside the active top electrode 117 of the driving transistor DT, and placing the source electrode outside the active top electrode 117 of the driving transistor DT, the driving transistor DT can be implemented with a channel width W longer than the channel length L. Therefore, the driving transistor DT can generate a high current.

[0107] Additionally, the connection electrode 119C is patterned and formed on a fourth insulating layer 118, including CH12 contact holes CH12 and CH13 contact holes exposed to air. The connection electrode 119C connects the active electrode 115S of the first transistor T1 and the active upper electrode 117 of the driving transistor DT. Simultaneously, the first transistor T1 is also connected to the active lower electrode 113 of the driving transistor DT, which serves as one electrode of the capacitor Cst, thereby enabling… Figure 2 Pixel driving circuit 40.

[0108] The high-potential power line 122, the drain electrode 119A of the driving transistor DT, and the connection electrode 119C can be semiconductors such as silicon (Si) or conductive metals, such as any one, two or more alloys of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or multiple layers thereof.

[0109] A passivation layer can be formed on the high-potential power line 122, the drain electrode 119A of the driving transistor DT, and the connection electrode 119C. In some cases, the passivation layer may separately include a protective layer that protects the pixel driving circuit 40 and a planarization layer that smooths out the step differences of the pixel driving circuit 40.

[0110] The CH16 contact hole is formed in the passivation layer, and the drain electrode 119A of the driving transistor DT can contact the third transistor T3 or the LED element 50 through the CH16 contact hole. The electrode in contact with the drain electrode 119A of the driving transistor DT can be formed of a transparent conductive material. The transparent conductive material can be ITO (indium tin oxide), IZO (indium zinc oxide), etc., but is not limited to these.

[0111] Figure 13 This is a plan view illustrating a portion of a pixel driving circuit according to one embodiment of the present disclosure, and will be compared with... Figure 4 Similarly, the driving transistor DT, the first transistor T1, and the capacitor Cst are described. Furthermore, Figure 14 It is along Figure 13 A cross-sectional view taken at point B-B'. Figure 13 and Figure 14 The components shown can be briefly described or omitted. Figure 4 and Figure 5 The structure and features of repeating components.

[0112] Figure 13 This is a plan view of a driving transistor including an active upper electrode implemented in a U-shape. The driving transistor DT includes an active lower electrode 213, an active electrode 215D, an active upper electrode 217, and a drain electrode 219A. In a driving transistor DT according to one embodiment of the present disclosure, since the active upper electrode 217 is used as the source electrode and the active lower electrode 213 is used as the gate electrode, the driving transistor DT is implemented as a bottom-gate transistor. Furthermore, the first transistor T1 includes a gate electrode 231, an active electrode 215D, a source electrode, and a drain electrode.

[0113] The active upper electrode 217 of the driving transistor is implemented by connecting a high-potential power line 222 via contact holes CH22 and CH23, and the drain electrode 219A is connected to the third transistor T3 via contact hole CH24. In some cases, the third transistor T3 can be omitted, and the drain electrode 219A of the driving transistor DT can be connected to the anode electrode of the LED element 50.

[0114] In the driving transistor DT, an active lower electrode 213 is disposed at the lower part and an active upper electrode 217 is disposed at the upper part relative to the active electrode 215D of the driving transistor DT. A cap electrode 211 overlapping with the active lower electrode 213 is disposed below the active lower electrode 213 of the driving transistor DT. The active lower electrode 213 and the cap electrode 211 overlap each other to form a capacitor Cst. The cap electrode 211 may be referred to as the lower electrode.

[0115] The active lower electrode 213 of the driving transistor DT is electrically connected to the source or drain region of the active electrode 215S of the first transistor T1 via the connecting electrode 219C. The source or drain electrode of the first transistor T1 connected to the active lower electrode 213 of the driving transistor DT does not need to be separately provided, and can be implemented by directly connecting the connecting electrode 119C to the active electrode 115S of the first transistor T1. Furthermore, the gate electrode 231 of the first transistor T1 is disposed above and overlaps with the active electrode 215S.

[0116] The active upper electrode 217 of the driving transistor DT is implemented in a U-shape, as the electrode name suggests. By applying a high-potential supply voltage, the active upper electrode 217 serves as the source electrode, and by placing the drain electrode inside the active upper electrode 217, a [missing information - likely a specific electrode configuration] can be achieved. Figure 12 The channel width W is greater than Figure 12 The driving transistor DT has a channel length L. Because the driving current of the driving transistor DT is related to... Figure 12 The channel width W is proportional to and is Figure 12 The channel length L is inversely proportional to the channel length, therefore it can be achieved by... Figure 12 The channel width W increases more than Figure 12 A larger channel length L increases the drive current, allowing the heat concentration area to be evenly distributed, thereby improving the reliability of the drive transistor DT.

[0117] The source electrode of the driving transistor DT is implemented in a U-shape, thereby increasing the channel width W while reducing the area occupied by the driving transistor DT. Furthermore, since the driving transistor DT is implemented as a bottom-gate transistor and the cap electrode 211 is located below the driving transistor DT, the capacitor Cst can be formed overlapping the driving transistor DT. Therefore, it is not necessary to prepare a separate area for forming the capacitor Cst in the sub-pixel, thereby reducing the area occupied by the pixel driving circuit.

[0118] Figures 15 to 20 It shows the manufacturing process. Figure 13 A view showing the method of the component. (Refer to...) Figure 14 Describe together Figures 15 to 20 Furthermore, the part can be omitted or simplified. Figures 6 to 12 The description repeats the parts.

[0119] Reference Figure 15 The cap electrode 211 is patterned and formed on the substrate 210. A first insulating layer 212 is formed on the cap electrode 211 above the entire surface of the substrate 210.

[0120] Reference Figure 16 An active lower electrode 213 is formed on the cap electrode 211 and the first insulating layer 212. The active lower electrode 213 is formed to overlap with the cap electrode 211. The cap electrode 211 and the active lower electrode 213 overlap each other to form a capacitor. The cap electrode 211 and the active lower electrode 213 are the electrodes that realize the capacitor Cst. Therefore, the cap electrode 211 is connected to the second transistor T2 and the fourth transistor T4, and the active lower electrode 213 is the gate electrode of the driving transistor DT and is also an electrode of the capacitor Cst. The cap electrode 211 and the active lower electrode 213 can be semiconductors such as silicon (Si) or conductive metals, such as any one, two or more alloys of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or multiple layers thereof. Furthermore, a second insulating layer 214 is formed on the active lower electrode 213.

[0121] Reference Figure 17 Active electrodes 215D and 215S are formed on the second insulating layer 214. The active electrode 215D of the driving transistor DT is formed in the region of the active lower electrode 213, overlapping with the active lower electrode 213. Furthermore, the active electrode 215S of the first transistor T1 is formed on the same layer as the active electrode 215D of the driving transistor DT and spaced apart from the active electrode 215D, but the active electrode 215S of the first transistor T1 is formed to partially overlap with the active lower electrode 213 for easy contact with the active lower electrode 213. A third insulating layer 216 is formed on the active electrodes 215D and 215S.

[0122] Reference Figure 18 The active upper electrode 217 and the gate electrode 231 of the first transistor T1 are patterned and formed on the third insulating layer 216. The active upper electrode 217 is the source electrode of the driving transistor DT and is patterned into a U-shape to overlap with the active electrode 215D of the driving transistor DT. The gate electrode 231 of the first transistor T1 is formed to overlap with the active electrode 215D of the first transistor T1 and to be spaced apart from the active upper electrode 217. Furthermore, the gate electrode 231 of the first transistor T1 is formed to extend along the horizontal axis and can be shared with adjacent sub-pixels on the horizontal axis. The first transistor T1 is implemented as a top-gate transistor.

[0123] Next, refer to Figure 14 and Figure 18Doping is performed to form active electrodes 215D and 215S that do not overlap with the active upper electrode 117 and the gate electrode 231 of the first transistor T1, serving as the source and drain regions, respectively. In this case, since the transistor described as an example of an embodiment according to this disclosure is a PMOS, it can be implemented as P-doped. During doping, the active upper electrode 217 is used as a mask to dope the active electrode 215D of the driving transistor DT. The doped region is the area that does not overlap with the active upper electrode 217 relative to the U-shape, both inside and outside the U-shape. By forming the outer and inner parts of the U-shape that do not overlap with the active upper electrode 217 as the source and drain regions, respectively, via doping, the active electrode 215D of the driving transistor DT can form a U-shaped channel. Therefore, the channel width of the driving transistor DT is formed to be longer than the channel length, allowing the driving transistor DT to generate a high current.

[0124] A fourth insulating layer 218 is formed on the active upper electrode 217 and the gate electrode 231 of the first transistor T1. The fourth insulating layer 218 can be used to protect the driving transistor DT and the first transistor T1. After the fourth insulating layer 218 is formed, a heat treatment for hydrogenation can be performed to activate the implanted ions and reduce the density of trapped states, thereby improving the performance of the transistor.

[0125] Reference Figure 19 A CH23 contact hole is formed in the third insulating layer 216 and the fourth insulating layer 218 to expose the source region of the active electrode 215D of the driving transistor DT. A CH22 contact hole is formed in the fourth insulating layer 218 to expose the active upper electrode 217 of the driving transistor DT. The active upper electrode 217 is connected to the source region of the active electrode 215D of the driving transistor DT through the CH23 and CH22 contact holes, and receives a high-potential voltage from the high-potential power line 222.

[0126] The CH21 contact hole CH21 is formed by etching the third insulating layer 216, the fourth insulating layer 218, and the active electrode 215S of the first transistor T1, thereby exposing the active lower electrode 213. The active lower electrode 213 of the driving transistor DT and the active electrode 215S of the first transistor T1 can be connected through the CH21 contact hole CH21.

[0127] A CH24 contact hole is formed in the third insulating layer 216 and the fourth insulating layer 218 to expose the drain region of the active electrode 215D of the driving transistor DT. The drain electrode can contact the drain region of the driving transistor DT through the CH24 contact hole.

[0128] Reference Figure 20A high-potential power line 222 is patterned and formed on a fourth insulating layer 218, which includes CH22 contact holes CH22 and CH23 contact holes exposed to air. The high-potential power line 222 contacts the active upper electrode 217 via an electrode branching from the line. Furthermore, a drain electrode 219A is patterned and formed on the fourth insulating layer 218, which includes CH24 contact holes exposed to air. The drain electrode 219A is formed to overlap with the drain region of the active electrode 215D of the driving transistor DT, and is disposed inside the active upper electrode 217 so as not to overlap with the active upper electrode 217.

[0129] By forming the source electrode of the driving transistor DT into a U-shaped structure and placing it above and overlapping the active electrode 215D of the driving transistor DT, the channel width W of the driving transistor DT can be made longer than the channel length L. Therefore, the driving transistor DT can generate high current.

[0130] Additionally, the connection electrode 219C is patterned and formed on a fourth insulating layer 218, including a CH21 contact hole CH21 exposed to air. The connection electrode 219A connects the active electrode 215S of the first transistor T1 and the active lower electrode 213 of the driving transistor DT. Simultaneously, the first transistor T1 is also connected to the active lower electrode 213 of the driving transistor DT, which serves as an electrode of the capacitor Cst, thereby enabling… Figure 2 Pixel driving circuit 40.

[0131] The passivation layer can be formed on the high-potential power line 222, the drain electrode 219A of the driving transistor DT, and the connection electrode 219C. In some cases, the passivation layer may consist of a protective layer that protects the pixel driving circuit 40 and a planarization layer that smooths out the step differences of the pixel driving circuit 40.

[0132] The CH25 contact hole CH25 is formed in the passivation layer, and the drain electrode 219A of the driving transistor DT can contact the third transistor T3 or the LED element 50 through the CH25 contact hole CH25. The electrode in contact with the drain electrode 219A of the driving transistor DT can be formed of a transparent conductive material.

[0133] Figure 21 This is a plan view showing a portion of a pixel driving circuit according to one embodiment of the present disclosure, and a driving transistor and a first transistor T1 will be described. Figure 22 It is along Figure 21 The cross-sectional view taken from C-C'.

[0134] Figure 21This is a plan view of a driving transistor including an active upper electrode implemented in an O-shape. The driving transistor DT includes an active lower electrode 313, an active upper electrode 317, an active electrode 315D, a source electrode, and a drain electrode 319A. In one embodiment of the driving transistor DT according to this disclosure, the active upper electrode 317 serves as the gate electrode, and the driving transistor DT is implemented as a top-gate transistor. Furthermore, the first transistor T1 includes a gate electrode 331, an active electrode 315D, a source electrode, and a drain electrode.

[0135] The source electrode of the driving transistor DT is directly connected to the high-potential power supply line 322 via the CH34 contact hole CH34, and the drain electrode 319A is connected to the third transistor T3 via the CH35 contact hole CH35. In some cases, the third transistor T3 can be omitted, and the drain electrode 319A of the driving transistor DT can be connected to the anode electrode of the LED element 50.

[0136] A driving transistor DT is formed on substrate 310, such that an active lower electrode 313 is disposed at the lower part and an active upper electrode 317 is disposed at the upper part relative to the active electrode 315D of the driving transistor DT. The active lower electrode 313 overlaps with the active upper electrode 317 and active electrode 315D of the driving transistor DT. In some cases, the active lower electrode 313 can be omitted.

[0137] An active lower electrode 313 is formed on a first insulating layer 312 formed on a substrate 310. The first insulating layer 312 increases the adhesion of the active lower electrode 313 to the substrate 310. In some cases, the first insulating layer 312 can be omitted. Furthermore, a second insulating layer 314 is formed on the active lower electrode 313.

[0138] The active electrode 315D of the driving transistor DT and the active electrode 315S of the first transistor T1 are formed on the second insulating layer 314. The active electrode 315D of the driving transistor DT is configured to partially overlap with the active lower electrode 313. Furthermore, the active electrode 315S of the first transistor T1 is formed on the same layer as the active electrode 315D of the driving transistor DT and is spaced apart from the active electrode 315D, and is formed adjacent to the active upper electrode 317 to facilitate easy contact with the active upper electrode 317 of the driving transistor DT. A third insulating layer 316 is formed on the active electrodes 315S and 315D.

[0139] The active upper electrode 317 of the driving transistor DT and the gate electrode 331 of the first transistor T1 are formed on the third insulating layer 316. The active upper electrode 317 of the driving transistor DT is disposed above and overlaps with the active electrode 315D of the driving transistor DT, and the gate electrode 331 of the first transistor T1 is disposed above and overlaps with the active electrode 315S of the first transistor T1. In this case, the first transistor T1 and the driving transistor DT can be implemented as top-gate transistors.

[0140] The active upper electrode 317 of the driving transistor DT is implemented in a sealed annular structure. The source and drain regions can be disposed outside and inside the O-shape, respectively, to contact the source and drain electrodes. Doping is performed to form active electrodes 315D and 315S that do not overlap with the gate electrode 331 and active upper electrode 317 of the first transistor T1 as the source and drain regions. In this case, since the transistor described as an example of an embodiment according to this disclosure is a PMOS, it can be implemented as P-doped. By connecting the drain and source electrodes to the inside and outside of the active upper electrode 317, which is conductive through doping, respectively, the driving transistor DT with a channel width greater than the channel length can be realized.

[0141] Since the drive current of the driving transistor DT is directly proportional to the channel width W and inversely proportional to the channel length L, increasing the channel width W to be larger than the channel length L increases the drive current and makes its distribution more uniform. Furthermore, because the heat concentration area can be evenly distributed, the reliability of the driving transistor DT can be improved. In addition, by implementing the gate electrode of the driving transistor DT as an O-shape, the area occupied by the driving transistor DT is reduced, thus making it easier to apply this driving transistor to high-resolution display panels.

[0142] Next, a fourth insulating layer 318 is formed on the active upper electrode 317 of the driving transistor DT and the gate electrode 331 of the first transistor T1. A contact hole CH31 is formed in the third insulating layer 316 and the fourth insulating layer 318 to expose the source or drain region of the active electrode 315S of the first transistor T1. Furthermore, a contact hole CH32 is formed in the fourth insulating layer 318 to expose the active upper electrode 317. The contact holes CH31 and CH32 allow the source region of the first transistor T1 and the gate electrode of the driving transistor DT to contact each other via connection electrodes.

[0143] Contact holes CH34 and CH35 are formed in the third insulating layer 316 and the fourth insulating layer 318 to expose the source and drain regions of the active electrode 315D of the driving transistor DT. Contact hole CH34 allows the source region of the driving transistor to contact the high-potential power line 332, and contact hole CH35 allows the drain region of the driving transistor DT to contact the drain electrode 319A.

[0144] CH33 contact holes are formed in the second insulating layer 314, the third insulating layer 316, and the fourth insulating layer 318 to expose the active lower electrode 313. The CH33 contact holes allow the active lower electrode 313 to contact the high-potential power line 322, preventing the active lower electrode 313 from floating.

[0145] A high-potential power line 322, a drain electrode 319A of the driving transistor DT, and a connection electrode 319C are patterned and formed on a fourth insulating layer 318. The high-potential power line 322 may be formed along a vertical axis including contact holes CH34 and CH33. The drain electrode 319A of the driving transistor DT covers contact hole CH35, and the connection electrode 319C covers contact holes CH31 and CH32.

[0146] The passivation layer can be formed on the high-potential power line 322, the drain electrode 319A of the driving transistor DT, and the connection electrode 319C. In some cases, the passivation layer may consist of a protective layer that protects the pixel driving circuit 40 and a planarization layer that smooths out the step differences of the pixel driving circuit 40.

[0147] Figure 23 This is a plan view illustrating a portion of a pixel driving circuit according to one embodiment of the present disclosure. Figure 24 It is along Figure 23 The cross-sectional view taken from D-D'. Because Figure 23 yes Figure 4 and Figure 21 The modified implementation method can therefore be simplified or omitted. Figure 4 , Figure 5 , Figures 6 to 12 , Figure 21 and Figure 22 Repeated description.

[0148] Figure 23This is a plan view of a driving transistor including an active upper electrode implemented in an O-shape. The driving transistor DT includes an active lower electrode 413, an active upper electrode 417, an active electrode 415D, a source electrode, and a drain electrode 419A. In one embodiment of the driving transistor DT according to this disclosure, since the active lower electrode 413 and the active upper electrode 417 serve as gate electrodes, the driving transistor DT is implemented as a dual-gate transistor. Furthermore, the first transistor T1 includes a gate electrode 431, an active electrode 415D, a source electrode, and a drain electrode.

[0149] The source electrode of the driving transistor DT is directly connected to the high-potential power line 422 via the CH43 contact hole CH43, and the drain electrode 419A is connected to the third transistor T3 via the CH44 contact hole CH44. In some cases, the third transistor T3 can be omitted, and the drain electrode 419A of the driving transistor DT can be connected to the anode electrode of the LED element 50.

[0150] In the driving transistor DT, an active lower electrode 413 is disposed at the lower part and an active upper electrode 417 is disposed at the upper part relative to the active electrode 415D of the driving transistor DT, and the active lower electrode 413 and the active upper electrode 417 are in contact with each other. A cap electrode 411 overlapping with the active lower electrode 413 is disposed below the active lower electrode 413 of the driving transistor DT. The active lower electrode 413 and the cap electrode 411 overlap each other to form a capacitor Cst.

[0151] The gate electrodes 413 and 417 of the driving transistor DT are electrically connected to the source or drain region of the active electrode 415S of the first transistor T1 via the connecting electrode 419C. The source or drain electrode of the first transistor T1 connected to the gate electrodes 413 and 417 of the driving transistor DT does not need to be set separately, and can be achieved by directly connecting the connecting electrode 419C to the active electrode 415S of the first transistor T1.

[0152] The gate electrode 431 of the first transistor T1 is disposed above and overlaps with the active electrode 415S.

[0153] The active upper electrode 417 of the driving transistor DT is connected to Figure 21 The active upper electrode 317 of the driving transistor DT included in the diagram is implemented with the same shape. The source and drain regions can be disposed outside and inside the active upper electrode 417, respectively, to contact the source and drain electrodes. This can be achieved by forming the source and drain regions via doping in the active electrode 415D, and by connecting the drain and source electrodes to the inside and outside of the conductive active upper electrode 417, respectively. Figure 21 The channel width W is greater than Figure 21The driving transistor DT has a channel length L. Therefore, the driving current of the driving transistor DT can be increased, the distribution of the driving current can be made more uniform, and the heat concentration area can be evenly distributed, thereby improving the reliability of the driving transistor DT. In addition, by realizing the gate electrode of the driving transistor DT as an O-shape, the area occupied by the driving transistor DT is reduced, and the driving transistor can be easily applied to high-resolution display panels. Furthermore, since the driving transistor DT is realized as a dual-gate transistor and the cap electrode 411 is placed below the driving transistor DT, the capacitor Cst can be formed overlapping with the driving transistor DT. Therefore, it is not necessary to prepare a separate area for forming the capacitor Cst in the sub-pixel, thereby reducing the area occupied by the pixel driving circuit.

[0154] A cap electrode 411 is formed on the substrate 410. A first insulating layer 412 is formed on the cap electrode 411. An active lower electrode 413 is formed on the first insulating layer 412. A second insulating layer 414 is formed on the active lower electrode 413. The active electrode 415D of the driving transistor DT and the active electrode 415S of the first transistor T1 are formed on the second insulating layer 414. A third insulating layer 416 is formed on the active electrodes 415D and 415S. The active upper electrode 417 of the driving transistor DT and the gate electrode 431 of the first transistor T1 are formed on the third insulating layer 416. A fourth insulating layer 418 is formed on the gate electrodes 417 and 413. A connection electrode 419C is formed on the fourth insulating layer 418. In this case, the source or drain region of the active electrode 415S of the first transistor T1 overlaps with the active lower electrode 413, so that a CH41 contact hole CH41 for providing a connection electrode 419C in the overlapping region can be formed.

[0155] Contact hole CH41 is formed in the second insulating layer 414, the active electrode 415S of the first transistor T1, the third insulating layer 416, and the fourth insulating layer 418 to expose the surface of the active lower electrode 413 and the side surface of the active electrode 415S of the first transistor T1. Contact hole CH42 is formed in the fourth insulating layer 418 to expose the active upper electrode 417. Connecting electrode 419C is formed including contact hole CH41 and contact hole CH42, and it contacts and is electrically connected to the active lower electrode 413, the active upper electrode 417, and the active electrode 415S of the first transistor T1. In this case, the active electrode 415S of the first transistor T1 and the active lower electrode 413 of the driving transistor are connected as one unit through the same contact hole, but this is not limited to this, as in... Figure 4 and Figure 5In the same structure, the active electrode 415S of the first transistor T1 and the active lower electrode 413 of the driving transistor can be connected through different contact holes.

[0156] Contact holes CH43 and CH44 are formed in the third insulating layer 416 and the fourth insulating layer 418 to expose the active electrode 415D of the driving transistor DT. Contact hole CH43 allows the source electrode of the driving transistor DT to be contacted, and contact hole CH44 allows the drain electrode of the driving transistor DT to be contacted. The source electrode of the driving transistor DT is integrally formed with a high-potential power line 422 through contact hole CH43. The driving transistor DT receives a high-potential voltage Vdd through the high-potential power line 422.

[0157] Figure 25 This is a plan view illustrating a portion of a pixel driving circuit according to one embodiment of the present disclosure. Figure 26 It is along Figure 25 The cross-sectional view taken from E-E'. Because Figure 25 yes Figure 13 and Figure 21 The modified implementation method can therefore be simplified or omitted. Figure 13 , Figure 14 , Figures 15 to 20 , Figure 21 and Figure 22 Repeated description.

[0158] Figure 25 This is a plan view of a driving transistor including an active upper electrode implemented in an O-shape. The driving transistor DT includes an active lower electrode 513, an active upper electrode 517, an active electrode 515D, a source electrode, and a drain electrode 519A. In one embodiment of the driving transistor DT according to this disclosure, since the active upper electrode 517 serves as the source electrode and the active lower electrode 513 serves as the gate electrode, the driving transistor DT is implemented as a bottom-gate transistor. Furthermore, the first transistor T1 includes a gate electrode 531, an active electrode 515D, a source electrode, and a drain electrode.

[0159] The active upper electrode 517 of the driving transistor DT is connected to the high-potential power line 522 via contact holes CH52 and CH53, and the drain electrode 519A is connected to the third transistor T3 via contact hole CH54. In some cases, the third transistor T3 can be omitted, and the drain electrode 519A of the driving transistor DT can be connected to the anode electrode of the LED element 50.

[0160] In the driving transistor DT, the active lower electrode 513 is disposed at the lower part and the active upper electrode 517 is disposed at the upper part relative to the active electrode 515D of the driving transistor DT. The cap electrode 511, which overlaps with the active lower electrode, is disposed below the active lower electrode 513 of the driving transistor DT. The active lower electrode 513 and the cap electrode 511 overlap each other to form a capacitor Cst.

[0161] The active lower electrode 513 of the driving transistor DT is electrically connected to the source or drain region of the active electrode 515S of the first transistor T1 via the connecting electrode 519C. The source or drain electrode of the first transistor T1 connected to the active lower electrode 513 of the driving transistor DT does not need to be separately provided, and can be achieved by directly connecting the connecting electrode 519C to the active electrode 515S of the first transistor T1. Furthermore, the gate electrode 531 of the first transistor T1 is disposed above and overlaps with the active electrode 515S.

[0162] The active upper electrode 517 of the driving transistor DT is connected to Figure 21 The driving transistor DT is implemented with the same shape as the active top electrode 317. The source region and drain region can be disposed outside and inside the active top electrode 517, respectively, so as to contact the source electrode and drain electrode. By forming the source region and drain region by doping in the active electrode 515D, and connecting the drain electrode and source electrode to the inside and outside of the conductive active top electrode 517, a driving transistor DT with a channel width greater than the channel length can be realized. Therefore, the driving current of the driving transistor DT can be increased, the distribution of the driving current can be made more uniform, and the heat concentration area can be evenly distributed, thereby improving the reliability of the driving transistor DT. In addition, by realizing the gate electrode of the driving transistor DT as O-shaped, the area occupied by the driving transistor DT is reduced, and the driving transistor can be easily applied to a high-resolution display panel. In addition, since the capacitor Cst can be formed overlapping with the driving transistor DT by disposing the cap electrode 511 below the driving transistor DT, it is not necessary to prepare a separate area for forming the capacitor Cst in the sub-pixel, thereby reducing the area occupied by the pixel driving circuit.

[0163] A cap electrode 511 is formed on the substrate 510. A first insulating layer 512 is formed on the cap electrode 511. An active lower electrode 513 is formed on the first insulating layer 512. A second insulating layer 514 is formed on the active lower electrode 513. The active electrode 515D of the driving transistor DT and the active electrode 515S of the first transistor T1 are formed on the second insulating layer 514. A third insulating layer 516 is formed on the active electrodes 515D and 515S. The active upper electrode 517 of the driving transistor DT and the gate electrode 531 of the first transistor T1 are formed on the third insulating layer 516. A fourth insulating layer 518 is formed on the gate electrodes 517 and 513. A connection electrode 519C is formed on the fourth insulating layer 518. In this case, the source or drain region of the active electrode 515S of the first transistor T1 overlaps with the active lower electrode 513, so that a CH51 contact hole CH51 for providing a connection electrode 519C in the overlapping region can be formed.

[0164] Contact hole CH51 is formed in the second insulating layer 514, the active electrode 515S of the first transistor T1, the third insulating layer 516, and the fourth insulating layer 518 to expose the surface of the active lower electrode 513 and the side surface of the active electrode 515S of the first transistor T1. Connecting electrode 519C is formed to include contact hole CH51, and connecting electrode 519C contacts and is electrically connected to the active lower electrode 513 and the active electrode 515S of the first transistor T1.

[0165] Contact holes CH52 and CH54 are formed in the third insulating layer 516 and the fourth insulating layer 518 to expose the active electrode 515D of the driving transistor DT. Contact hole CH52 allows the source electrode of the driving transistor DT to be contacted, and contact hole CH54 allows the drain electrode of the driving transistor DT to be contacted. The source electrode of the driving transistor DT is integrally formed with a high-potential power line 522 passing through contact hole CH52. The driving transistor DT receives a high-potential voltage Vdd through the high-potential power line 522. Furthermore, contact hole CH53 is formed in the fourth insulating layer 518 to expose the active upper electrode 517 of the driving transistor DT. The high-potential power line 522 contacts the active upper electrode 517 through an electrode branching from this line. By forming the source electrode of the driving transistor DT into an O-shaped structure and making the source electrode above and overlapping the active electrode 515D of the driving transistor DT, the driving transistor DT can achieve... Figure 21 The channel width W is greater than Figure 21 The channel length L is long. Therefore, the driving transistor DT can generate high current.

[0166] This concludes the description of a method for manufacturing some components of a pixel driving circuit according to one embodiment of the present disclosure.

[0167] In one embodiment of the display panel according to the present disclosure, the display panel includes: a substrate; an active electrode above the substrate and including a source region, a drain region, and a channel region; and an active top electrode in a curved shape above the active electrode. The active top electrode and the channel region of the active electrode may overlap each other, and the channel region may have the same shape as the active top electrode. Therefore, the driving elements included in the display panel can generate high driving current and can improve the integration density in the pixels.

[0168] According to another feature of this disclosure, the display panel may further include a lower electrode below the substrate and an active lower electrode between the substrate and the active electrode, and the lower electrode and the active lower electrode may overlap each other to be implemented as a capacitor.

[0169] According to another feature of this disclosure, the display panel may further include a lower electrode between the substrate and the active electrode, and the active upper electrode and the active lower electrode may be connected to each other by a connecting electrode to be implemented as a dual-gate transistor.

[0170] In one embodiment of the display panel according to this disclosure, the display panel includes: an active electrode including a source region, a drain region, and a channel region; an active upper electrode that is above the active electrode, overlaps with the active electrode, and is implemented in a curved shape; and an active lower electrode that is below the active electrode and overlaps with the active electrode. The active upper electrode and the active lower electrode serve as source electrodes, drain electrodes, or gate electrodes. Therefore, the driving elements included in the display panel can generate high drive current and can improve the integration density in the pixels.

[0171] In one embodiment of the display panel according to this disclosure, the display panel includes: a substrate; a lower electrode above the substrate; an active electrode above the lower electrode and including a source region, a drain region, and a channel region; a drain electrode contacting the drain region of the active electrode; a source electrode or an upper gate electrode above the active electrode; and an active lower electrode below the active electrode. Furthermore, the lower electrode, the active lower electrode, and the channel regions of the active electrodes overlap each other, and the source electrode or upper gate electrode is implemented in a curved shape. Therefore, the driving elements included in the display panel can generate high driving current and can improve the integration density in the pixels.

[0172] According to another feature of this disclosure, the lower electrode and the active lower electrode can overlap each other to be implemented as a capacitor.

[0173] According to another feature of this disclosure, the upper gate electrode and the active lower electrode can be connected to each other via a connection electrode to be implemented as a dual-gate transistor.

[0174] According to another feature of this disclosure, the source electrode or upper gate electrode may overlap with the active electrode, and the active electrode has a region that does not overlap with the source electrode or upper gate electrode. Furthermore, the non-overlapping region of the active electrode can be divided into two regions: an inner region of the curved shape of the source electrode or upper gate electrode and an outer region of the curved shape. The inner region of the active electrode can be a drain region, and the outer region of the active electrode can be a source region.

[0175] According to another feature of this disclosure, the curved shape can be injected as a U-shape or an O-shape.

[0176] According to another feature of this disclosure, the display panel may also include LED elements and a high-potential power line providing a high-potential voltage, wherein the source electrode may be integrated with the high-potential power line and the drain electrode may be connected to the LED elements.

[0177] According to another feature of this disclosure, the high-potential power line can branch out to contact the source electrode in a curved shape.

[0178] In one embodiment of the thin-film transistor according to this disclosure, the thin-film transistor includes: an active electrode comprising a source region, a drain region, and a channel region; an electrode above and overlapping the active electrode; and an electrode below and overlapping the active electrode. Furthermore, the electrode below the active electrode is a gate electrode, and the electrode above the active electrode is implemented in a bent shape to serve as either a source electrode or a gate electrode. Therefore, the thin-film transistor can generate a high drive current.

[0179] According to another feature of this disclosure, the channel region may be the region that overlaps with the electrode above the active electrode.

[0180] According to another feature of this disclosure, the channel region may have a width and a length, and the width of the channel region may be greater than the length of the channel region.

[0181] According to another feature of this disclosure, the electrode above the active electrode and the electrode below the active electrode can be connected to each other.

[0182] According to another feature of this disclosure, the electrode implemented in a curved shape can be U-shaped or O-shaped. Furthermore, the electrode implemented in a curved shape can divide the active electrode into two regions.

[0183] According to another feature of this disclosure, the electrode above the active electrode can be the source electrode, and the electrode below the active electrode can be the gate electrode.

[0184] Although embodiments of the present disclosure have been described in more detail above with reference to the accompanying drawings, the present disclosure is not limited to these embodiments, and various modifications can be made within this scope without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical spirit of the present disclosure, but rather to be illustrative, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of protection of this disclosure should be interpreted by the claims, and all technical ideas within the scope of the claims should be interpreted as included within the scope of this disclosure.

Claims

1. A display panel, comprising: substrate; An active electrode is located above the substrate and includes a source region, a drain region, and a channel region. An active upper electrode that is curved above the active electrode; Drain electrode in contact with the drain region; Source electrode that contacts the source region; as well as An LED element coupled to the source electrode or the drain electrode, the LED element comprising an inorganic material as a light-emitting layer. The active upper electrode and the channel region of the active electrode overlap each other, and the channel region has the same shape as the active upper electrode. The thin-film transistor, including the active electrode, the bent active upper electrode, and the source electrode, is disposed above the substrate, and the bent active upper electrode serves as the gate electrode of the thin-film transistor. In this embodiment, only one of the drain electrode and the source electrode is coupled to the LED element comprising the inorganic material and overlaps with the active upper electrode, which is in a curved shape.

2. The display panel according to claim 1, further comprising: The lower electrode above the substrate; as well as The active lower electrode between the substrate and the active electrode, The lower electrode and the active lower electrode overlap each other to be implemented as a capacitor.

3. The display panel according to claim 1, further comprising: The active lower electrode between the substrate and the active electrode, The active upper electrode and the active lower electrode are connected to each other via a connecting electrode to be implemented as a dual-gate transistor.

4. The display panel according to claim 1, in, The region of the active electrode that does not overlap with the active upper electrode is divided into the inner region and the outer region of the channel region.

5. The display panel according to claim 4, in, The internal region of the active electrode is the drain region, and the external region of the active electrode is the source region.

6. The display panel according to claim 1, in, The curved shape is O-shaped.

7. The display panel according to claim 1, further comprising: High-potential power lines provide high-potential voltage. The source electrode and the high-potential power line are integrated, and the drain electrode is connected to the LED element.

8. A display panel, comprising: substrate; An active electrode is located above the substrate and includes a source region, a drain region, and a channel region. An active upper electrode that is curved above the active electrode; and High-potential power lines provide high-potential voltage. The thin-film transistor, including the active electrode and the bent-shaped active upper electrode, is disposed above the substrate, and the bent-shaped active upper electrode is the source electrode of the thin-film transistor. The high-potential power line branches out to contact the source electrode, which is in a curved shape.

9. A thin-film transistor, comprising: Active electrodes, including source region, drain region, and channel region; An active upper electrode that is above the active electrode, overlaps with the active electrode, and is realized in a curved shape in a plan view; Drain electrode in contact with the drain region; Source electrode that contacts the source region; as well as The lower active electrode is located below the active electrode and overlaps with the active electrode. The active upper electrode, which is curved in shape, serves as the gate electrode, and The source electrode and the drain electrode do not have a curved shape and are spaced apart from the active upper electrode, which has a curved shape.

10. The thin-film transistor according to claim 9, in, The channel region is the area that overlaps with the active upper electrode.

11. The thin-film transistor according to claim 9, in, The channel area has a width and a length, and the width of the channel area is greater than the length of the channel area.

12. The thin-film transistor according to claim 9, in, The active upper electrode and the active lower electrode are connected to each other.

13. The thin-film transistor according to claim 9, in, The active upper electrode is U-shaped.

14. The thin-film transistor according to claim 13, in, The active upper electrode divides the active electrode into two regions.

15. The thin-film transistor of claim 9, further comprising a lower electrode overlapping the active lower electrode. in, The active lower electrode is disposed between the active electrode and the lower electrode.

16. A display device, comprising: Display panel; High-potential power lines that provide high-potential voltage; as well as Thin-film transistors coupled to the display panel, the thin-film transistors comprising: Active electrodes, including source region, drain region, and channel region; An active upper electrode that overlaps with the active electrode and is implemented in a curved shape above the active electrode; and The lower active electrode is located below the active electrode and overlaps with the active electrode. The active upper electrode, which is curved in shape, serves as the source electrode, and The high-potential power line branches out to contact the active upper electrode, which is in a curved shape.

17. The display device according to claim 16, wherein, The channel region is the area that overlaps with the active upper electrode.

18. The display device according to claim 16, wherein, The channel area has a width and a length, and the width of the channel area is greater than the length of the channel area.

19. The display device according to claim 16, wherein, The active upper electrode and the active lower electrode are coupled to each other.

20. The display device according to claim 16, further comprising a lower electrode overlapping the active lower electrode. in, The active lower electrode is disposed between the active electrode and the lower electrode.

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