Stepped field plate proximate to a conductive channel and associated methods of manufacture

Abstract

A transistor includes a semiconductor layer structure (24), a source electrode (30) and a drain electrode (30) on the semiconductor layer structure, a gate (32) on a surface of the semiconductor layer structure between the source electrode and the drain electrode, and a field plate (33). The field plate includes a first portion (33a) adjacent to the gate and a second portion (33b) adjacent to the source electrode or the drain electrode. The second portion of the field plate is farther from the surface of the semiconductor layer structure than the first portion of the field plate, and is closer to the surface of the semiconductor layer structure than an extended portion (32a) of the gate. Related apparatus and methods of manufacture are also discussed.

Description

[0001] Claiming priority

[0002] This application claims the benefit of priority to U.S. Patent Application No. 16 / 600,825, filed October 14, 2019, with the United States Patent and Trademark Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to semiconductor devices, and more particularly, to transistors including field plates and related manufacturing methods. Background Technology

[0004] Materials such as silicon (Si) and gallium arsenide (GaAs) have found wide applications in low-power semiconductor devices, and in the case of Si, low-frequency applications. However, for example, these materials may be less suitable for high-power and / or high-frequency applications due to their relatively small band gaps (1.12 eV for Si and 1.42 eV for GaAs at room temperature) and relatively low breakdown voltages.

[0005] For high-power, high-temperature, and / or high-frequency applications and devices, wide-bandgap semiconductor materials such as silicon carbide (SiC) (e.g., a bandgap of approximately 2.996 eV for αSiC at room temperature) and group III nitrides (e.g., a bandgap of approximately 3.36 eV for gallium nitride (GaN) at room temperature) can be used. Typically, these materials can exhibit higher electric field breakdown strength and higher electron saturation velocity compared to GaAs and Si.

[0006] Devices of particular interest for high-power and / or high-frequency applications are high electron mobility transistors (HEMTs), also known as modulation-doped field-effect transistors (MODFETs). In HEMT devices, a two-dimensional electron gas (2DEG) can be formed at a heterojunction of two semiconductor materials with different bandgap energies. The material with the smaller bandgap can have a higher electron affinity than the material with the wider bandgap. The 2DEG is an accumulation layer in the undoped material with the smaller bandgap and can contain a relatively high surface electron concentration, for example, exceeding 10⁻⁶. 13 carriers / cm 2 Furthermore, electrons originating from the wider bandgap semiconductor can transfer to the 2DEG, allowing for relatively high electron mobility due to reduced ionized impurity scattering. This combination of relatively high carrier concentration and carrier mobility enables HEMTs to have relatively large transconductance and can provide performance advantages over metal-semiconductor field-effect transistors (MESFETs) for high-frequency applications.

[0007] HEMTs fabricated in gallium nitride / alkaline gallium nitride (GaN / AlGaN) material systems can generate substantial radio frequency (RF) power due to a combination of material properties such as relatively high breakdown field, relatively wide bandgap, relatively large conduction band offset, and / or relatively high saturation electron drift velocity. Different types of HEMTs in GaN / AlGaN systems have been demonstrated. For example, U.S. Patent Nos. 5,192,987 and 5,296,395 describe AlGaN / GaN HEMT structures and fabrication methods. Additionally, U.S. Patent No. 6,316,793 to Sheppard et al. describes an HEMT device having a semi-insulating silicon carbide substrate, an AlN buffer layer on the substrate, an insulating GaN layer on the buffer layer, an AlGaN barrier layer on the GaN layer, and a passivation layer on the AlGaN active structure. In addition, U.S. Patent No. 7,045,404 to Sheppard et al. describes a HEMT device that includes a protective layer and / or a low-damage trench fabrication technique, which can reduce damage to the semiconductor in the gate region of the transistor that may occur during the annealing of the ohmic contacts of the device.

[0008] Electron trapping and the resulting discrepancy between DC and RF characteristics can be a limiting factor in the performance of these devices. Silicon nitride (SiN) passivation has been employed to mitigate this trapping problem, resulting in high-performance devices with power densities exceeding 10 W / mm² at 10 GHz. For example, U.S. Patent No. 6,586,781 to Wu et al. describes methods and structures for reducing trapping effects in GaN-based transistors. However, charge trapping may remain a problem due to the high electric fields present in these structures.

[0009] Field plates are used to enhance the performance of GaN-based HEMTs at microwave frequencies and exhibit improved performance compared to non-field plate devices. Some field plate approaches may involve attaching the field plate to the gate of the transistor, with the field plate on top of the drain side of the channel. This configuration can result in a reduction of the electric field on the gate-drain side of the transistor, thereby increasing the breakdown voltage and reducing high-field trapping effects. However, transistors with gate-drain field plates may exhibit relatively poor reliability performance, especially in Class C (or higher) operation where the electric field on the source side of the gate becomes significant. Summary of the Invention

[0010] According to some embodiments, a transistor includes a semiconductor layer structure, a source electrode and a drain electrode on the semiconductor layer structure, a gate electrode on the surface of the semiconductor layer structure between the source electrode and the drain electrode, and a field plate. The field plate includes a first portion adjacent to the gate electrode and a second portion adjacent to the source electrode or drain electrode. The second portion of the field plate is further away from the surface of the semiconductor layer structure than the first portion of the field plate, and closer to the surface of the semiconductor layer structure than an extension of the gate electrode adjacent to the surface of the semiconductor layer structure.

[0011] In some embodiments, a second portion of the field plate may be adjacent to the drain electrode.

[0012] In some embodiments, the transistor may further include a spacer insulator layer comprising a plurality of spacer layers stacked on the surface of the semiconductor layer, the plurality of spacer layers defining a first thickness, a second thickness, and a third thickness that respectively separate a first portion of the field plate, a second portion of the field plate, and an extension of the gate from the surface of the semiconductor layer structure.

[0013] In some embodiments, the third thickness defined by the plurality of spacer layers may be substantially uniform on opposite sides of the gate. In some embodiments, the plurality of spacer layers may define substantially coplanar surfaces on opposite sides of the gate, and an extension of the gate may extend laterally toward a first portion of the field plate along one of the substantially coplanar surfaces.

[0014] In some embodiments, the plurality of spacer layers may include: a first spacer layer having a groove in its surface; a second spacer layer including a first portion in the groove and a second portion on the surface of the first spacer layer outside the groove; and a third spacer layer having substantially coplanar surfaces on the second spacer layer, with a field plate between the second spacer layer and the third spacer layer. The first and second portions of the second spacer layer may be located between the first and second portions of the field plate and the surface of the semiconductor layer structure, respectively.

[0015] In some embodiments, the respective upper surfaces of the first portion of the field plate and the second portion of the second spacer layer may be substantially coplanar.

[0016] In some embodiments, the first and second portions of the field plate may be constrained below the substantially coplanar surfaces of the third spacer layer.

[0017] In some embodiments, the extension of the gate may include sidelobe portions that extend laterally along substantially coplanar surfaces on opposite sides of the gate. In some embodiments, the opposite sidelobe portions of the gate may be substantially symmetrical.

[0018] In some embodiments, sidewall spacers can separate the gate from one or more of a plurality of spacer layers on its opposite side. A first portion of the field plate can extend laterally toward the gate and be separated from the gate by one of the sidewall spacers.

[0019] In some embodiments, the field plate may be a first field plate, and a second field plate may be provided on the surface of the spacer insulating layer and extending through a portion thereof to contact the first field plate. In some embodiments, the second field plate may extend laterally toward the drain electrode beyond a second portion of the first field plate.

[0020] In some embodiments, the first portion of the field plate and the extension portion of the gate may extend laterally toward each other and are non-overlapping in a direction perpendicular to the surface of the semiconductor layer structure.

[0021] In some embodiments, the semiconductor layer structure may include stacked buffer and barrier layers, and the buffer and barrier layers are configured to define a two-dimensional electron gas (2DEG) channel layer at the heterojunction therebetween.

[0022] According to some embodiments, the transistor includes: a semiconductor layer structure; a source electrode and a drain electrode on the semiconductor layer structure; a gate electrode on a surface of the semiconductor layer structure between the source electrode and the drain electrode; and a field plate between the gate electrode and the source electrode or the drain electrode. The field plate is closer to the surface of the semiconductor layer structure than a lateral extension of the gate electrode, and the lateral extension of the gate electrode does not overlap with the field plate.

[0023] In some embodiments, the field plate may include a first portion adjacent to the gate and a second portion adjacent to the source or drain electrode. The second portion may be further away from the surface of the semiconductor layer structure than the first portion.

[0024] In some embodiments, the spacer insulator layer may include a plurality of spacer layers stacked on the surface of the semiconductor layer to define a first thickness, a second thickness, and a third thickness that respectively separate a first portion of the field plate, a second portion of the field plate, and a lateral extension of the gate from the surface of the semiconductor layer structure.

[0025] In some embodiments, a plurality of spacer layers may define substantially coplanar surfaces on opposite sides of the gate, and the lateral extension of the gate may include sidelobe portions extending laterally directly along the substantially coplanar surfaces on opposite sides of the gate.

[0026] In some embodiments, the plurality of spacer layers may include: a first spacer layer having a groove in its surface; a second spacer layer including a first portion in the groove and a second portion on the surface of the first spacer layer outside the groove; and a third spacer layer having substantially coplanar surfaces on the second spacer layer, with a field plate between the second spacer layer and the third spacer layer. The first and second portions of the second spacer layer may be located between the first and second portions of the field plate and the surface of the semiconductor layer structure, respectively.

[0027] In some embodiments, the field plate may be a first field plate, and a second field plate may be provided on the surface of the spacer insulating layer and extending through a portion thereof to contact the first field plate. In some embodiments, the second field plate may extend laterally toward the drain electrode beyond a second portion of the first field plate.

[0028] According to some embodiments, the transistor includes: a channel layer and a barrier layer defining a heterojunction therebetween; a source electrode and a drain electrode on the barrier layer; a gate on the barrier layer, the gate including sidelobe portions extending laterally from opposite sides of the gate toward the source electrode and the drain electrode, respectively; a field plate on the barrier layer between the gate and the drain electrode; and a spacer insulator layer including a plurality of spacer layers with a field plate between the plurality of spacer layers. The spacer layers are stacked on the barrier layer on opposite sides of the gate and separate the sidelobe portions of the gate from the barrier layer.

[0029] In some embodiments, a plurality of spacer layers may define substantially coplanar surfaces on opposite sides of the gate, wherein sidelobe portions of the gate extend laterally on the substantially coplanar surfaces.

[0030] In some embodiments, the spacer layer may have a substantially uniform thickness on the opposite side of the gate.

[0031] In some embodiments, the field plate may include a first portion adjacent to the gate and a second portion adjacent to the drain electrode, and the second portion may be further away from the surface of the barrier layer than the first portion. In some embodiments, the second portion of the field plate may be closer to the surface of the barrier layer than the sidelobe portion of the gate.

[0032] In some embodiments, a plurality of spacer layers may be stacked to define a first thickness, a second thickness, and a third thickness that respectively separate a first portion of the field plate, a second portion of the field plate, and a sidelobe portion of the gate from the surface of the barrier layer.

[0033] In some embodiments, the first portion of the field plate and one of the sidelobe portions of the gate may extend laterally toward each other and may not overlap in a direction perpendicular to the surface of the barrier layer.

[0034] In some embodiments, sidewall spacers can separate the gate from a plurality of spacer layers on opposite sides. A first portion of the field plate can extend laterally toward the gate and can be separated from the gate by one of the sidewall spacers.

[0035] According to some embodiments, a method of manufacturing a transistor includes: forming a channel layer and a barrier layer defining a heterojunction therebetween; forming a source electrode, a drain electrode, and a gate electrode on the barrier layer, wherein the gate electrode includes sidelobe portions extending laterally from opposite sides of the gate electrode toward the source electrode and the drain electrode, respectively; and forming a spacer insulator layer and a field plate on the barrier layer. The spacer insulator layer includes a plurality of spacer layers, with a field plate between the plurality of spacer layers. The spacer layers are stacked on the barrier layer on opposite sides of the gate electrode and separate the sidelobe portions of the gate electrode from the barrier layer.

[0036] In some embodiments, a plurality of spacer layers may be formed to define substantially coplanar surfaces on opposite sides of the gate, with sidelobe portions of the gate extending laterally directly on the substantially coplanar surfaces.

[0037] In some embodiments, the field plate may be formed to include a first portion adjacent to the gate and a second portion adjacent to the drain electrode, wherein the second portion is further away from the surface of the barrier layer than the first portion.

[0038] In some embodiments, forming the spacer insulator layer and the field plate may include: forming a first spacer layer, the first spacer layer including a groove in its surface; forming a second spacer layer, the second spacer layer including a first portion in the groove and a second portion on the surface of the first spacer layer outside the groove; forming a first portion and a second portion of the field plate on the first portion and the second portion of the second spacer layer, respectively; and forming a third spacer layer on the second spacer layer and the first and second portions of the field plate.

[0039] In some embodiments, the field plate may be a first field plate. The method may further include: forming an opening extending through a third spacer layer to expose at least one of a first portion or a second portion of the first field plate; and forming a second field plate on the third spacer layer and extending the second field plate into the opening to contact the first field plate.

[0040] Other apparatuses and methods according to some embodiments will become apparent to those skilled in the art upon review of the following drawings and detailed description. All such additional embodiments, in addition to any and all combinations of the embodiments described above, are intended to be included within this specification and are within the scope of the invention, and are protected by the appended claims. Attached Figure Description

[0041] Figure 1 This is a schematic cross-section of a unit cell of a transistor device including a buried field plate according to some embodiments of the present invention.

[0042] Figures 2-12 This is a schematic cross-sectional view illustrating an exemplary intermediate manufacturing step in a method for manufacturing a transistor device according to some embodiments of the present invention.

[0043] Figure 13 This is a schematic cross-section of a unit cell of a transistor device including a buried field plate according to a further embodiment of the present invention.

[0044] Figure 14 This is a schematic cross-section of a unit cell of a transistor device including a buried field plate according to a further embodiment of the present invention.

[0045] Figure 15 This is a schematic cross-section of a unit cell of a transistor device including a buried field plate according to a further embodiment of the present invention. Detailed Implementation

[0046] A field plate is a conductive structure that can be configured to alter the electric field distribution in the channel region of a transistor device to improve the device's operating characteristics (e.g., breakdown voltage, gain, maximum operating frequency). For example, in HEMT or other semiconductor-based field-effect transistor (FET) devices, a large electric field may occur in the gate-drain region during normal operation. A field plate can be configured to reduce the peak electric field in the active region of the device at a given bias voltage. Such a field plate can not only manage the field distribution but may also affect the drain-source and gate-drain capacitances C. ds C gd Both. The field plate between the gate and drain (also known as the gate-drain region) can also be configured as an active region of the modulation device, resulting in a reduction of surface trapping effects that could affect proper device operation under large radio frequency (RF) signals. More generally, the field plate can be used to mitigate the adverse effects that may occur when the device operates under high electric fields (low breakdown voltage, charge trapping, low reliability).

[0047] Embodiments of the present invention provide specific configurations and manufacturing methods for field plate structures that can reduce capacitance, trapping effects, and / or peak electric field distribution. In particular, embodiments of the present invention allow for the fabrication of stepped or graded field plate structures, thereby reducing the spacing or interval between the conductive channel and the field plate. In some embodiments, a field plate can be provided between the gate and drain, thereby reducing the gate-drain capacitance C. gd And the peak electric field near the drain supply voltage.

[0048] For example, a buried field plate may include a first portion adjacent to the gate and a second portion adjacent to the drain electrode, the first portion being separated from the surface of the semiconductor layer structure (wherein conductive channels are induced or otherwise defined) by a first distance or spacing, and the second portion being separated from the surface of the semiconductor layer by a second distance or spacing greater than the first distance or spacing. Recesses in the spacer layer adjacent to the gate may be used to define the first and second portions of the buried field plate in a stepped geometry (first and second stepped portions at different distances or spacings from the semiconductor layer surface) and / or a hierarchical geometry (hierarchical portions extending from or connecting one of the stepped portions). In some embodiments, additional sidewall spacers may be included to control the lateral spacing between the gate and the field plate. As used herein, the term "lateral" refers to a direction substantially parallel to the main surface of the semiconductor layer structure. Moreover, some embodiments may include a second or additional field plate extending through one or more spacer layers to contact the buried field plate, thereby defining a second "step" in a stepped or hierarchical field plate structure. Providing a buried field plate close to the gate and / or conductive channels can enhance or improve C gd And the trapping effect is reduced. Stepped or graded field plate structures can also reduce the peak electric field near the drain supply voltage.

[0049] Figure 1 This is a schematic cross-section of a unit cell of a transistor structure including a buried field plate according to some embodiments of the present invention. Specifically, Figure 1 An example of a HEMT including a landfill slab with a stepped or graded structure as described herein is illustrated.

[0050] HEMTs include a channel layer and a barrier layer on the channel layer. Source and drain electrodes can be formed in ohmic contact with the barrier layer. A gate is formed on the surface of the barrier layer between the source and drain electrodes, and a spacer insulator layer is formed above the barrier layer. Depending on the configuration, the spacer insulator layer can be formed before or after the gate formation. The spacer insulator layer can be a dielectric layer, undoped, or depleted Al. x Ga 1-x A layer or combination of N (0≤x≤1) material. A conductive field plate is formed in the spacer insulating layer and extends a distance Lf from the gate toward the source or drain electrode. The field plate may be electrically connected to the source electrode. In some cases, the electrical connection between the field plate and the source electrode may be outside the active region of the device. The field plate can reduce the peak electric field in the device, resulting in an increase in breakdown voltage and a reduction in charge trapping. The reduction in electric field can also produce other benefits, such as reduced leakage current and enhanced reliability.

[0051] HEMTs may include semiconductor layer structures based on group III nitrides, but other material systems may also be used. It should be noted that while this document primarily describes the fabrication of HEMTs, the elements and concepts of the embodiments described herein can be applied to a variety of different types of transistor structures, including but not limited to metal-semiconductor field-effect transistors (MESFETs) and metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs).

[0052] Now for reference Figure 1 HEMT 100 includes a GaN-based or other Group III nitride-based semiconductor layer structure 24 on a substrate 10. Group III nitrides can refer to semiconductor compounds formed between nitrogen and elements in Group III of the periodic table, such as aluminum (Al), gallium (Ga), and / or indium (In), to form binary (e.g., GaN), ternary (e.g., AlGaN, AlInN), and quaternary (e.g., AlInGaN) compounds. Therefore, materials such as Al... x Ga 1-x These compounds are described using formulations such as N, where 0 ≤ x ≤ 1. The substrate 10 may include silicon carbide, silicon, sapphire, spinel, zinc oxide, gallium arsenide, zinc oxide, or any other material capable of supporting the growth of group III nitride materials. Compared to sapphire, silicon carbide has a closer lattice match to group III nitrides and can allow for the formation of higher quality group III nitride films thereon. Silicon carbide also has very high thermal conductivity, making the total output power of group III nitride devices on silicon carbide potentially unrestricted by the heat dissipation of the substrate (potentially, in some cases, devices could be formed on sapphire).

[0053] Optional buffer, nucleation, and / or transition layers may also be formed on the substrate 10. For example, a nucleation layer 15 may be formed on the substrate 10 to reduce lattice mismatch between the substrate 10 and the next layer of the semiconductor layer structure 24. The formation and composition of the nucleation layer 15 may depend on the material used for the substrate 10. For example, Al may be grown on the substrate 10 via an epitaxial growth method. z Ga 1-zThe nucleation layer 15 (N(0≤z≤1)) is grown using epitaxial methods such as MOCVD (metal-organic chemical vapor deposition), HVPE (hydride vapor phase epitaxy), or MBE (molecular beam epitaxy). Methods for forming the nucleation layer 15 on various substrates are described in U.S. Patent No. 5,290,393 to Nakamura and U.S. Patent No. 5,686,738 to Moustakas. Methods for forming the nucleation layer on a silicon carbide substrate are described in U.S. Patent Nos. 5,393,993, 5,523,589, and 5,739,554 to Edmond et al.

[0054] The semiconductor layer structure 24 of HEMT 100 includes a channel layer 20 and a barrier layer 22. The channel layer 20 may be formed on the nucleation layer 15. The barrier layer 22 may be formed on the channel layer 20 opposite to the nucleation layer 15 and the substrate 10. One or both of the channel layer 20 and the barrier layer 22 may include sublayers, including doped or undoped (i.e., "unintentionally doped") layers of group III nitride materials, comprising a material composition that may be stepwise or progressively graded. In some embodiments, the channel layer 20 may include Al x Ga y In (1-x-y) One or more layers of N, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1. For example, channel layer 20 may be a GaN layer. In some embodiments, barrier layer 22 may include Al. x Ga 1-x N or Al x In y Ga 1-x-y One or more layers of N, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1. The semiconductor layer structure 24 may be an epitaxial structure comprising these and / or other layers formed on the substrate 10 via an epitaxial growth method. For example, the same or similar methods used to grow the nucleation layer 15 can be used to form the channel layer and barrier layers 20, 22. Electrical isolation between devices can be achieved by mesa etching or ion ionization outside the active region of the HEMT 100.

[0055] In the HEMT device 100, the channel layer 20 and the barrier layer 22 can be formed of materials with different band gaps, thereby defining a heterojunction at the interface between the channel layer 20 and the barrier layer 22. Specifically, when both the channel layer 20 and the barrier layer 22 are formed of group III nitride layers, the channel layer 20 can be a GaN layer, and the barrier layer 22 can be an AlGaN layer. A 2DEG conduction channel 40 can be induced at the heterojunction between the channel layer 20 and the barrier layer 22, and the channel layer 20, the 2DEG conduction channel 40, and the barrier layer 22 typically form the active region of the HEMT 100.

[0056] In other embodiments, the channel layer 20 and the barrier layer 22 may have different lattice constants. For example, the barrier layer 22 may be a relatively thin layer with a smaller lattice constant than the channel layer 20, such that the barrier layer 22 "stretches" at the interface between them. Thus, a pseudocrystalline HEMT (pHEMT) device can be provided. Example HEMT structures are illustrated in U.S. Patent No. 6,316,793 to Sheppard et al., U.S. Patent No. 6,586,781 to Wu et al., U.S. Patent No. 6,548,333 to Smith, U.S. Application Publication No. 2002 / 0167023 to Prashant et al., and U.S. Application Publication No. 2003 / 0020092 to Parikh et al. Example HEMT structures based on other nitrides are illustrated in U.S. Patent No. 5,192,987 to Kahn et al. and U.S. Patent No. 5,296,395 to Kahn et al.

[0057] Source and drain electrodes 30 are formed on semiconductor layer structure 24 to define ohmic contacts with barrier layer 22. Gate 32 is formed on the surface of barrier layer 22 between source and drain electrodes 30. When gate 32 is biased at an appropriate level, current can flow between source and drain electrodes 30 through a 2DEG conduction channel 40 at the heterojunction defined by channel layer 20 and barrier layer 22.

[0058] Forming the gate 32 may include depositing a dielectric or other spacer insulator layer 25, etching through the spacer insulator layer 25 using a mask and / or other sacrificial layers, and depositing the gate into the etched portion of the spacer insulator layer 25. The formation of the source and drain electrodes 30 may be performed similarly, as described by examples in the foregoing patents and disclosures. In some embodiments, the gate 32 may include one or more extensions laterally extending over portions of the spacer insulator layer 25, for example, defining opposing sidelobe portions 32a, 32b of a T-shape (also referred to herein as a “T-gate”). The gate 32 and the sidelobe portions 32a, 32b may define multiple different lengths (L...). G1 and LG2 In some embodiments, the sidelobe portions 32a, 32b may extend substantially symmetrically onto the spacer insulating layer 25 on opposite sides of the gate 32.

[0059] like Figure 1 As shown, the spacer insulator layer 25 includes a plurality of spacer layers 26, 27, and 28 sequentially stacked on the surface 24s of the semiconductor layer structure 24. The spacer insulator layer 25 also includes a buried field plate 33 on one side of the gate 32 between the spacer layers 26, 27, and 28. The buried field plate 33 comprises a metal or other conductive material, such as copper, gold, and / or a composite metal. In some embodiments, the buried field plate 33 may be positioned between the gate 32 and the drain electrode 30 to reduce peak values ​​or otherwise redistribute the electric field to reduce the gate-drain capacitance C. gd And / or reduce the trapping effect on the drain side of HEMT 100. In some embodiments, a buried field plate having a similar stepped structure (not shown) may be additionally or alternatively positioned between the gate 32 and the source electrode 30.

[0060] The buried field plate 33 has a stepped profile comprising two or more portions, illustrated herein by reference to an example of a first stepped portion 33a adjacent to the gate 32 and a second stepped portion 33b adjacent to the drain electrode 30. The stepped portions 33a, 33b of the field plate 33 may be defined by a continuous layer or by a stack of discontinuous layers. That is, the stepped portions 33a, 33b of the field plate 33 may be defined by a single layer or multiple layers. In some embodiments, the stepped portions 33a, 33b may include discontinuities between them. Each stepped portion 33a, 33b of the field plate 33 is positioned at a different distance or spacing from the surface 24s (and thus, the underlying conductive channel 40). The field plate 33, including the first and second stepped portions 33a and 33b at closer and farther distances or spacings from the conductive channel 40, can allow for a reduction in C. gd This includes the trapping effect and the reduction of the peak electric field near the drain electrode 30.

[0061] In particular, such as Figure 1 As shown, spacer layers 26 and 27 can be stacked sequentially to define different thicknesses between the first and second portions 33a and 33b of the burial field plate 33 and the surface 24s, to provide different spacings S1 and S2. For example, spacer layer 26 may include grooves therein such that when spacer layer 27 and burial field plate 33 are sequentially formed on spacer layer 26 and in the grooves, portion 33a of field plate 33 is closer to surface 24s than portion 33b.

[0062] Additionally, spacer layers 26, 27, and 28 may separate the sidelobe portions 32a and 32b from the surface 24s on opposite sides of the gate 32. For example, spacer layers 26, 27, and 28 may define substantially uniform thickness or spacing S3 and / or coplanar surfaces on opposite sides of the gate 32, with the sidelobe portions 32a and 32b of the gate 32 extending onto these coplanar surfaces. In some embodiments, the sidelobe portion 32a of the gate 32 and the stepped portion 33a of the field plate 33 may overlap and be partially separated by the third spacer layer 28. In some embodiments, the sidelobe portion 32a of the gate 32 and the stepped portion 33a of the field plate 33 may be non-overlapping in a direction perpendicular to the surface 24s.

[0063] The spacer layers 26, 27, and 28 can be configured to position the second step portion 33b of the buried field plate 33 further away from the surface 24s of the semiconductor layer structure 24 (and thus the conductive channel 40) than the first step portion 33a, and closer to the surface 24s of the semiconductor layer structure 24 than the sidelobe portions 32a and 32b of the gate 32. More generally, the spacer insulator layer 25 can be a multilayer stack, with the stacked layers 26, 27, and 28 having corresponding thicknesses that can be configured to control the distance or spacing between the gate sidelobe portions 32a and 32b and the surface 24s, control the distance or spacing between the field plate step portions 33a and 33b and the surface 24s, and / or control the distance or spacing between the gate sidelobe portions 32a and 32b and the field plate step portions 33a and 33b.

[0064] HEMT 100 may also include an additional or second field plate 34 extending through the upper spacer layer 29 to contact the first and / or second stepped portions 33a, 33b of the buried field plate 33. The second field plate 34 may also have a stepped or graded structure, wherein the first portion 34a is closer to the surface 24s of the semiconductor layer structure 24 than the second portion 34b. The first portion 34a of the second field plate 34 may also be closer to the drain electrode 30, and may allow for further control of C. gd The trapping effect and / or the peak electric field near the drain electrode 30.

[0065] Despite Figure 1 The figure illustrates a planar HEMT configuration of the gate 32 and the source and drain electrodes 30 on the surface 24s of the barrier layer 22. However, it will be understood that the buried field plate 33 with a stepped or graded field structure according to embodiments of the invention can be used for other HEMT configurations, such as recessed gate HEMTs (where the source and drain electrodes 30 are raised relative to the gate 32 on the surface 24s) and recessed source / drain HEMTs (where the source and drain electrodes 30 extend beyond the surface 24s toward the channel layer 20).

[0066] Figures 2-12This is a schematic cross-sectional view illustrating an exemplary intermediate manufacturing step in a method for manufacturing a transistor device according to some embodiments of the present invention. Figures 2-12 The example illustration depicts the fabrication of a buried field plate with a stepped or hierarchical structure between the gate and drain electrodes of a transistor device; however, it should be understood that in some embodiments, similar fabrication steps may be additionally or alternatively used to fabricate a field plate (not shown) between the gate and source electrodes.

[0067] like Figure 2 As shown, a first spacer layer 26 is formed on the surface 24s of a semiconductor layer structure 24 including a barrier layer 22, which defines a heterojunction with the underlying channel layer 20. As discussed above, the channel layer 20 and the barrier layer 22 can be epitaxial structures (e.g., including group III nitride materials) formed via epitaxial growth methods. A nucleation layer 15 can be formed on the substrate 10 (e.g., a SiC substrate) to reduce lattice mismatch with the substrate 10. The first spacer layer 26 can be a dielectric or other insulating layer formed on the barrier layer 22 in a blanket manner. For example, the first spacer layer 26 can be a silicon nitride or silicon oxide layer formed by high-quality sputtering and / or vapor deposition methods.

[0068] exist Figure 3 In this process, a hole or recess 26r is defined in the first spacer layer 26. For example, the recess 26r can be optically defined and opened using a mask that exposes a portion of the spacer layer 26. The lateral position and / or width of the recess 26r can be selected to provide stepped portions 33a, 33b of the buried field plate 33 at desired distances from the gate and drain electrodes to be formed in subsequent steps. In some embodiments, the recess 26r may extend through the spacer layer 26 to expose the surfaces 24s of the semiconductor layer structure 24.

[0069] exist Figure 4 In this process, a second spacer layer 27 is formed on the first spacer layer 26. The second spacer layer 27 may extend conformally along the surface of the first spacer layer 26 and extend into the groove 26r along the bottom surface and sidewalls of the groove 26r to define a step difference between portions of the second spacer layer 27 inside and outside the groove 26r. The second spacer layer 27 may also be a dielectric or other insulating layer (e.g., a silicon nitride or silicon oxide layer) and may be formed by methods similar to or different from those used for the first spacer layer 26.

[0070] Figure 5The formation of the field plate 33 on the second spacer layer 27 is illustrated. For example, a metal or other conductive layer can be formed on a portion of the second spacer layer 27 using a mask and / or patterning process. The step difference defined by the portion of the second spacer layer 27 inside and outside the recess 26r in the first spacer layer 26 results in a field plate 33 comprising first and second portions 33a and 33b in a stepped configuration. The stepped portions 33a and 33b can be connected. The thickness of the second spacer layer 27 in the recess 26r defines a first distance or spacing S1 separating the first portion 33a of the buried field plate 33 from the surface 24s, while the combined thickness of the second spacer 27 on the surface of the first spacer layer 26 outside the recess 26r defines a second distance or spacing S2 separating the second portion 33b of the buried field plate 33 from the surface 24s.

[0071] The first portion 33a of the field plate 33 may extend laterally by a distance L on the second spacer layer 27 toward one side of the device (e.g., the source side). fs The second portion 33b of the field plate 33 may extend laterally by a distance L on the second spacer layer 27 toward the other side of the device (e.g., the drain side). fd L fs and L fd The distances can be the same or different. In some embodiments, portions 33a and 33b of the field plate 33 at different distances S1 and S2 from the surface 24s may be discontinuous. For example, the first portion 33a may be formed on a portion of the second spacer layer 27 in the groove 26r, and the second portion 33b may be formed separately on the surface of the second spacer layer 27 outside the groove, or may otherwise include discontinuities from the first portion 33a. That is, the first and second portions 33a and 33b of the field plate 33 may be defined by a single continuous layer or by multiple stacked layers.

[0072] Through Figure 3 A groove 26r is formed in the middle. Figure 4 In the groove 26r, a second spacer layer 27 is formed and Figure 5 A first portion 33a of a buried field plate 33 is formed in the groove 26r, and the first portion 33a of the field plate 33 is closer to the surface 24s than the second portion 33b of the field plate 33. The reduced thickness S1 of the dielectric or other spacer insulating layer 25 between the portion 33a of the field plate 33 and the surface 24s can reduce the capacitance caused by providing the field plate 33 between the gate and drain electrodes (e.g., relative to a planar field plate with a uniform spacing S2 to the surface 24s).

[0073] exist Figure 6In this configuration, a third spacer layer 28 is formed on the second spacer layer 27 and the field plate 33. The third spacer layer 28 may conformally extend along the surfaces of the stepped portions 33a, 33b of the second spacer layer 27 and the field plate 33 to define the buried field plate configuration. The third spacer layer 28 may also be a dielectric or other insulating layer (e.g., a silicon nitride or silicon oxide layer) and may be formed by a method similar to or different from that of the first and / or second spacer layers 26 and / or 27. The first, second, and third spacer layers 26, 27, and 28 may collectively define the spacer insulating layer 25 as described herein.

[0074] The spacer layers 26, 27, and 28 of the spacer insulator layer 25 described herein may be dielectric materials, such as silicon nitride, aluminum nitride, silicon dioxide, and / or other suitable materials. Other materials may also be used for layers 26, 27, and 28 of the spacer insulator layer 25. For example, spacer layers 26, 27, and 28 may also include magnesium oxide, scandium oxide, aluminum oxide, and / or aluminum oxynitride. Spacer layers 26, 27, and 28 may have the same or different thicknesses. In some embodiments, the first spacer layer 26 may have a smaller thickness than the second spacer layer 27, and / or the second spacer layer 27 may have a smaller thickness than the third spacer layer 28. The spacer insulator layer 25 may include a portion P having a substantially uniform thickness or spacing S3 relative to the surface 24s of the semiconductor layer structure 24 and a portion having a non-uniform thickness or spacing S4.

[0075] As described above, although the field plate 33, which includes two stepped portions 33a and 33b, is illustrated with reference to it, the stepped or tiered field plate according to embodiments of the present invention may include additional stepped portions. For example, still referring to... Figure 6 Additional holes or grooves (not shown) may be formed in the third spacer layer 28 to expose at least a portion of the second portion 33b of the field plate, and additional stepped portions (not shown) of the field plate 33 may be formed on the second portion 33b of the field plate 33 exposed by the additional grooves and on the surface of the third spacer layer 28 outside the additional grooves. More generally, although the manufacture of a spacer insulator layer 25 comprising three spacer layers 26, 27, 28 and a field plate 33 comprising two steps 33a, 33b has been illustrated with reference to the manufacture of such a spacer insulator layer 25, comprising three spacer layers 26, 27, 28 and a field plate 33 comprising two steps 33a, 33b, will be understood that a spacer insulator layer 25 having more than three spacer layers and a field plate 33 having more than two stepped portions may be manufactured according to the embodiments described herein.

[0076] Figure 7 The diagram illustrates the formation of a hole or opening 25o in a portion P of the spacer insulating layer 25, where a gate can be formed in a subsequent step. For example, an opening 25o can be optically defined and opened using a mask that exposes a portion of the third spacer layer 28. Figure 7As shown, opening 25o extends through spacer layers 28, 27, 26 to expose a portion of the surface 24s of semiconductor layer structure 24 (i.e., the surface of barrier layer 22). Opening 25o can be formed using a patterned mask and low-damage etching relative to barrier layer 22. Opening 25o can be offset between the source and drain electrodes, such that opening 25o, and subsequently the gate electrode, can be closer to the source electrode than the drain electrode. Furthermore, although illustrated as having a uniform width, it should be understood that opening 25o can be wider in certain portions due to the anisotropy of etching relative to the multiple layers 26, 27, 28 of spacer insulating layer 25.

[0077] like Figure 8 As shown, sidewall spacers 25s are formed at opposite sidewalls in the opening 25o of the spacer insulating layer 25. For example, the sidewall spacers 25s can be formed to define a desired first gate length L to be formed in a subsequent step. G1 This is particularly true in embodiments where the width of the gate opening 25o is non-uniform, as described above. In some embodiments, the sidewall spacers 25s can be formed using a spacer insulator shrinkage process. The sidewall spacers 25s can also be dielectric or other insulating layers (e.g., silicon nitride or silicon oxide layers) and can separate the lateral extension of the first portion 33a of the buried field plate 33 to prevent contact with the gate 32.

[0078] Figure 9 The diagram illustrates the formation of a gate 32 in an opening 25o within a spacer insulator layer 25. The gate 32 extends through the spacer insulator layer 25 to contact an exposed portion of the barrier layer 22. The gate 32 can be formed directly on the sidewall spacers 25s at opposite sidewalls of the spacer insulator layer 25 within the opening 25o via a metallization process, such that no gap may be formed between the sidewall spacers 25s and the gate 32. A suitable gate material may depend on the composition of the barrier layer 22. However, in some embodiments, materials capable of forming Schottky contacts with nitride-based semiconductor materials can be used for the gate 32, such as Ni, Pt, and NiSi. x Cu, Pd, Cr, TaN, W and / or WSiN.

[0079] The gate 32 includes one or more extensions (illustrated as opposing sidelobe portions 32a, 32b) that extend laterally on a surface portion of the spacer insulating layer 25 outside the opening 25o to define a second gate length L. G2The sidelobe portions 32a and 32b may be integral with the gate 32. The lengths of the sidelobe portions 32a and 32b extending onto the spacer insulating layer 25 on opposite sides of the gate 32 can be controlled during the manufacturing process. In some embodiments, the sidelobe portion 32a may be longer than the sidelobe portion 32b (and thus, define the second gate length L). G2 The majority of the gate 32 (and vice versa). In other embodiments, the sidelobe portions 32a and 32b may extend laterally along the surface of the third spacer layer 28 for substantially the same length on opposite sides of the gate 32. The gate-drain capacitance (C) of the transistor device can be further controlled as described below. gd ) and / or gate-source capacitance (C gs These capacitances may be due to the portion of the spacer insulating layer 25 sandwiched between the sidelobe portions 32a, 32b and the semiconductor layer structure 24.

[0080] like Figure 9 As shown, the gate 32 is formed such that on opposite sides of the gate 32, the sidelobe portions 32a and 32b are separated from the surface 24s of the semiconductor layer structure 24s (and thus the conductive channel defined at the heterojunction between the barrier layer 22 and the channel layer 20) by a substantially uniform distance or spacing S3. In the embodiments described herein, the buried field plate 33 having a stepped shape can be configured to increase the flatness of the third spacer layer 28, with the sidelobe portions 32a and 32b of the gate 32 extending on the third spacer layer 28 such that the spacer insulator layer 25 includes substantially coplanar surfaces on opposite sides of the gate 32, wherein the first and second portions 33a and 33b of the field plate 33 are constrained below the substantially coplanar surfaces.

[0081] In particular, due to Figure 3 The groove 26r in the first spacer layer 26 formed in the burial site plate 33, the upper surface of the first portion 33a of the burial site plate 33 can be substantially coplanar with the upper surface of the second spacer layer 27 on which the third spacer layer 28 is formed. Thus, when in Figure 6When the third spacer layer 28 is formed on the field plate 33 and the second spacer layer 27, the surface of the portion P of the spacer insulator layer 25 forming the gate opening 25o can be substantially planar, such that the side lobe portions 32a and 32b formed thereon on the opposite side of the gate 32 can be formed on substantially coplanar surfaces and uniformly spaced apart from the surface 24s of the semiconductor layer structure 24 by a distance S3. In contrast, the portion of the third spacer layer 28 formed on the second stepped portion 33b outside the recess 26r of the field plate 33 can have a non-uniform thickness (shown by the distance S4). The stepped or graded structure of the buried field plate 33 increases the distance between the non-uniform thickness S4 of the third spacer layer 28 and the portion P forming the gate 32, such that the side lobes or wings 32a and 32b are spaced apart from the surface 24s by a uniform distance S3. In some embodiments, the gate 32 may be formed with side lobes or wings 32a and 32b, which extend substantially symmetrically on opposite sides of the gate 32.

[0082] exist Figure 10 In this configuration, a fourth spacer layer 29 is formed on the gate 32 and the third spacer layer 28. The fourth spacer layer 29 may extend conformally along the side lobes 32a, 32b and the upper surface of the gate 32 and along the surface of the third spacer layer 28. The fourth spacer layer 29 may also be a dielectric or other insulating layer (e.g., a silicon nitride or silicon oxide layer) and may be formed by a method similar to or different from that of the first, second, and / or third spacer layers 26, 27, 28. In some embodiments, the fourth spacer layer 29 may be a passivation layer formed at a lower temperature than the first, second, and / or third spacer layers 26, 27, 28, because higher temperatures may not be feasible once the gate metallization is deposited.

[0083] exist Figure 11 In this process, a hole or opening 29o is formed in the fourth spacer layer 29 to expose a portion of the field plate 33. For example, the opening 29o can be optically defined and opened using a mask that exposes a portion of the fourth spacer layer 29 covering the field plate 33. Figure 11 As shown, opening 29o extends through spacer layers 29, 28 to expose the surface of the second portion 33b of the burial site plate 33. Opening 29o may additionally or alternatively expose the surface of the first portion 33a of the burial site plate 33.

[0084] Figure 12The illustration shows an additional or second field plate 34 forming a contact buried field plate 33 in an opening 29°. The second field plate 34 is a conductive structure extending through spacer layers 29, 28 to contact the first and / or second portions 33a, 33b of the buried field plate. The second field plate 34 may also have a stepped or graded structure, wherein the first portion 34a is closer to the surface 24s of the semiconductor layer structure 24 than the second portion 34b. The step difference between the surfaces of the first and second portions 34a and 34b of the second field plate 34 may be the same as or different from the step difference between the surfaces of the first and second portions 33a and 33b of the buried field plate 33. The lateral extension of the first portion 34a of the second field plate 34 toward the source or drain (S / D) can be controlled to further reduce peak values ​​or otherwise redistribute the electric field without substantially reducing the breakdown voltage above the threshold. Although not illustrated, source and drain electrodes can be formed on barrier layer 22 (e.g., by etching openings into spacer insulator layer 25 to expose the underlying barrier layer 22 and depositing ohmic contacts thereon) to achieve Figure 1 Device 100.

[0085] Figures 13-15 This is a schematic cross-section of a unit cell of a transistor structure including a buried field plate with various stepped or hierarchical structures, according to a further embodiment of the present invention. In particular, Figures 13-15 Examples of HEMT 100', 100" and 100"' including stepped or tiered landfill slab structures 33', 33" and 33"' are illustrated respectively. Some elements or layers of HEMT 100', 100" and 100"' may be similar to Figure 1 Those components or layers of HEMT 100, and their repeated descriptions are omitted.

[0086] For example, Figure 13 The diagram illustrates a structure consisting of corresponding layers, rather than as shown below. Figure 1 The buried field plate 33' is defined by first and second stepped portions 33a' and 33b' of a single continuous layer. The stepped portions 33a' and 33b' of the field plate 33' are positioned at different distances or spacings S1 and S2 from the surface 24s of the semiconductor layer structure (and thus the conductive channel 40 below), respectively. The respective upper surfaces of the first portion of the field plate 33a' and the second spacer layer 27 may be substantially coplanar. In some embodiments, the stepped portions 33a' and 33b' may include discontinuities between them.

[0087] In the embodiments described herein, the first portion 33a of the buried field plate 33 extends laterally by a length L toward the gate 32. fs Furthermore, the side lobe portion 32a of the gate 32 extends laterally towards the buried field plate 33, with a gate length L. G2 Part of it. Figures 1 to 13In some embodiments, a lateral spacing or interval is maintained between the first portion 33a of the buried field plate 33 and the sidelobe portion 32a of the gate 32, such that the laterally extending sidelobe portion 32a of the gate 32 does not overlap with the field plate 33. That is, the first portion 33a of the field plate 33 is constrained outside the edge or boundary of the sidelobe portion 32a and does not extend between the sidelobe portion 32a and the surface 24s of the semiconductor layer structure 24, such that the first portion 33a of the buried field plate 33 and the sidelobe portion 32a of the gate 32 are non-overlapping in a direction perpendicular to the surface 24s (also referred to herein as vertical overlap). However, embodiments of the invention are not limited to any particular length of the first portion 33a of the buried field plate 33; in some embodiments, the first portion 33a of the buried field plate 33 may overlap with the laterally extending sidelobe portions 32a, 32b.

[0088] Figure 14 This is a schematic cross-section of a unit cell of a transistor structure including a buried field plate 33”, wherein a first portion 33a” of the buried field plate 33” extends laterally toward the gate 32 beyond the edge of the side lobe portion 32a. The first portion 33a” of the buried field plate 33” overlaps perpendicularly with the side lobe portion 32a of the gate 32 and may further extend a distance from the edges of the side lobe portions 32a to the sidewall spacers 25s. As in other embodiments described herein, electrical isolation between the first portions 33a” of the field plate 33” overlapping with the side lobe portion 32a of the gate 32 is provided by portions of the spacer insulating layer 25 therebetween, particularly by the third spacer layer 28. Moreover, one of the sidewall spacers 25s provides electrical isolation between the laterally extended portion 33a” of the buried field plate 33” and the gate 32.

[0089] exist Figure 14 In the example, the first portion 33a” extends laterally along the entire portion of surface 24s between gate 32 and field plate 33” and contacts sidewall spacer 25s. However, the amount of overlap between the first portion 33a” of the buried field plate 33” and the sidelobe portion 32a of gate 32 and the length L of the first portion 33a” extending over the gate-drain region can be varied. fs .

[0090] Figure 15This is a schematic cross-section of a unit cell of a transistor structure including a buried field plate 33”', wherein the first portion 33a”' of the buried field plate 33”' also extends laterally toward the gate 32 and beyond the edge of the side lobe portion 32a, but along the entire portion between the gate 32 and the field plate 33”' less than the surface 24s. That is, the first portion 33a”' of the buried field plate 33”' overlaps perpendicularly with the side lobe portion 32a of the gate 32, but does not contact the sidewall spacers 25s. In this way, the first portion 33a”' of the field plate 33 can be laterally separated from the sidewalls of the gate 32 by the thickness of the sidewall spacers 25s or more. Figure 15 In this structure, the first and second step portions 33a”' and 33b”' are defined by corresponding layers rather than a single continuous layer. The first and second step portions 33a”' and 33b”' may overlap vertically. The corresponding upper surfaces of the first portion 33a”' of the field plate 33”' and the second spacer layer 27 may be substantially coplanar. The first portion 33a”' of the field plate 33”' extends between one of the substantially coplanar surfaces of the third spacer layer 28 and surface 24s. Electrical isolation between the first portions 33a”' of the field plate 33”' that overlap with the sidelobe portion 32a of the gate 32 is provided by portions of the third spacer layer 28 therebetween.

[0091] According to embodiments of the invention, by forming a spacer insulator layer 25 with varying thicknesses S1, S2, and S3 that separates the field plate step portions 33a, 33b and the gate sidelobe portion 32a from the surface 24s of the semiconductor layer structure 24, the capacitance between the gate 32 and the source or drain electrode 30 can be reduced (e.g., relative to a planar field plate separated from the surface 24s by a spacer insulator layer of uniform thickness). According to the embodiments described herein, the capacitance can be further reduced and / or adjusted by avoiding and / or controlling the vertical overlap between the field plate portion 33a and the gate sidelobe portion 32a.

[0092] In some embodiments, the stepped construction of the buried field plate can help reduce the peak electric field near the drain. In particular, by forming a buried field plate 33 with stepped structures 33a, 33b, and by forming a spacer insulating layer 25 with a large thickness S2 between the second portion 33b of the buried field plate 33 and the surface 24s of the semiconductor layer structure 24 (therefore, closer to the conductive channel 40 defined at the heterojunction between the barrier layer 22 and the channel layer 20), the peak electric field near the drain can be reduced, which can also reduce the charge trapping effect.

[0093] Therefore, embodiments of the present invention typically relate to transistor structures in which a buried field plate is separated from a barrier layer by a varying distance or spacing. In some embodiments, the field plate and semiconductor layer structure may be separated by one or more thinner spacer layers, while one or more thicker spacer layers may separate the lateral extensions of the field plate and the gate. In another embodiment, the spacer insulator layer may have a variable thickness, with a relatively thin thickness between the field plate and the semiconductor layer structure and a relatively thick thickness between the lateral extensions of the field plate and the gate. In some embodiments, the field plate may be provided in a recess within the spacer layer to reduce the distance or spacing between the field plate and the semiconductor layer structure.

[0094] Although embodiments of the invention have been described herein with reference to specific HEMT structures, the invention should not be construed as limited to such structures and can be applied to forming gate electrodes in many different transistor structures, such as pHEMTs (including GaAs / AlGaAs pHEMTs) and / or GaN MESFETs.

[0095] Furthermore, the additional layer can be incorporated into the transistor device while still benefiting from the teachings of this invention. Such an additional layer can include a GaN cap layer, as described, for example, in Smith's U.S. Patent No. 6,548,333. In some embodiments, a layer such as SiN can be deposited. x Alternatively, a relatively high-quality insulating layer such as AlN can be used to create the MISHEMT and / or passivation surface. Additional layers may also include composite hierarchical transition layers or multiple layers. Furthermore, the aforementioned barrier layer 22 and / or channel layer 20 may comprise multiple layers. Therefore, embodiments of the present invention should not be construed as limiting these layers to a single layer, but may include, for example, barrier layers having combinations of GaN, AlGaN, and / or AlN layers.

[0096] The invention has been described with reference to the accompanying drawings, in which embodiments of the invention are illustrated. However, the invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions is exaggerated for clarity. Similar numbering refers to similar elements.

[0097] It should be understood that when a component, such as a layer, region, or substrate, is referred to as being "on" or "extending to" another component, it can be directly on or directly extended to the other component, or intermediate components may exist. In contrast, when a component is referred to as being "directly on" or "directly extending to" another component, no intermediate components exist. It should also be understood that when a component is referred to as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, or intermediate components may exist. In contrast, when a component is referred to as being "directly connected" or "directly coupled" to another component, no intermediate components exist.

[0098] It should also be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of the invention, and similarly, a second element may be referred to as a first element.

[0099] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, relative terms are intended to encompass different orientations of the device. For example, if a device in a figure is flipped, an element described as being “below” the other element will be oriented “above” the other element. Thus, the exemplary term “below” can encompass both “below” and “above” orientations, depending on the specific orientation of the figure. Similarly, if a device in a figure is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the exemplary term “below” or “under” can encompass both “above” and “below” orientations.

[0100] The terminology used in the description of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in the description of the invention and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It should also be further understood that the terms “comprising” and / or “including”, when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0101] This document describes embodiments of the invention with reference to cross-sectional illustrations as schematic representations of ideal embodiments (and intermediate structures). Therefore, variations in shape as illustrated can be expected, for example, due to fabrication techniques and / or tolerances. Consequently, embodiments of the invention should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape, for example, due to fabrication processes. For instance, an injection region illustrated as a rectangle will typically have circular or curved features at its edges and / or a gradient of injection concentration, rather than a binary change from an injection to a non-injection region. Similarly, a buried region formed by injection may result in some injection in the region between the buried region and the surface through which the injection occurs. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, nor are they intended to limit the scope of the invention.

[0102] Unless otherwise specified, all terms used in the embodiments of the disclosed invention, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains, and are not necessarily limited to the specific definitions known at the time of the description of the invention. Therefore, these terms may include equivalents created after this time. It should be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as they have in the context of this specification and related art, and should not be interpreted in an idealized or overly formal sense unless otherwise expressly defined herein. All publications, patent applications, patents, and other references mentioned herein are incorporated herein by reference in their entirety.

[0103] Typical embodiments of the invention have been disclosed in the accompanying drawings and description, and although specific terms have been used, they are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A transistor, comprising: Semiconductor layer structure; The source electrode and drain electrode on the semiconductor layer structure; A gate electrode on the surface of the semiconductor layer structure between the source electrode and the drain electrode; and A field plate includes a first portion adjacent to the gate and a second portion connected to the first portion and adjacent to the source electrode or drain electrode, wherein the second portion is further away from the surface of the semiconductor layer structure than the first portion and closer to the surface of the semiconductor layer structure than an extension of the gate, wherein the extension of the gate extends laterally along the surface of the spacer insulator layer toward the first portion of the field plate, and wherein the first portion and the second portion of the field plate are below the surface of the spacer insulator layer.

2. The transistor according to claim 1, in, The spacer insulator layer includes a plurality of spacer layers stacked on the surface of the semiconductor layer structure to define a first thickness, a second thickness, and a third thickness that respectively separate a first portion of the field plate, a second portion of the field plate, and an extension of the gate from the surface of the semiconductor layer structure.

3. The transistor of claim 2, wherein the plurality of spacer layers define substantially coplanar surfaces on opposite sides of the gate, wherein an extension portion of the gate extends laterally toward a first portion of the field plate along one of the substantially coplanar surfaces.

4. The transistor of claim 3, wherein the plurality of spacer layers comprises: A first spacer layer includes grooves in its surface; The second spacer layer includes a first portion in the groove and a second portion on the surface of the first spacer layer outside the groove, wherein the first portion and the second portion of the second spacer layer are respectively located between the first portion and the second portion of the field plate and the surface of the semiconductor layer structure. and A third spacer layer includes substantially coplanar surfaces on the second spacer layer, wherein the field plate is located between the third spacer layer and the second spacer layer.

5. The transistor according to claim 3 or 4, wherein, The extension of the gate includes a side lobe portion that extends laterally directly along the substantially coplanar surfaces on the opposite side of the gate.

6. The transistor of claim 5, further comprising: Sidewall spacers separate the gate from one or more of the plurality of spacer layers on its opposite side, wherein a first portion of the field plate extends laterally toward the gate and is separated from the gate by one of the sidewall spacers.

7. The transistor according to any one of claims 2 to 4, wherein, The field plate is a first field plate, and the transistor further includes: The second field plate is on the surface of the spacer insulating layer and extends through a portion of it to contact the first field plate.

8. The transistor according to any one of claims 1 to 4, wherein, The first portion of the field plate and the extension portion of the gate extend laterally toward each other and are non-overlapping in a direction perpendicular to the surface of the semiconductor layer structure.

9. A transistor, comprising: Semiconductor layer structure; The source electrode and drain electrode on the semiconductor layer structure; A gate electrode on the surface of the semiconductor layer structure between the source electrode and the drain electrode; A first field plate having a stepped structure between the gate and the source or drain electrode, wherein the first field plate is in a spacer insulating layer and is closer to the surface of the semiconductor layer structure than the lateral extension of the gate, and wherein the lateral extension of the gate does not overlap with the first field plate. as well as A second field plate having a stepped structure on the surface of the spacer insulator layer, wherein the second field plate extends through a portion of the spacer insulator layer to contact the first field plate.

10. The transistor according to claim 9, wherein, The first field plate includes a first portion adjacent to the gate and a second portion adjacent to the source electrode or drain electrode, wherein the second portion is further away from the surface of the semiconductor layer structure than the first portion.

11. The transistor according to claim 10, in, The spacer insulator layer includes a plurality of spacer layers stacked on the surface of the semiconductor layer structure to define a first thickness, a second thickness, and a third thickness that respectively separate a first portion of the first field plate, a second portion of the first field plate, and a lateral extension of the gate from the surface of the semiconductor layer structure.

12. The transistor of claim 11, wherein, The plurality of spacer layers define substantially coplanar surfaces on opposite sides of the gate, and wherein the lateral extension of the gate includes a side lobe portion that extends laterally directly along the substantially coplanar surfaces on opposite sides of the gate.

13. The transistor of claim 12, wherein the plurality of spacer layers comprises: A first spacer layer includes grooves in its surface; The second spacer layer includes a first portion in the groove and a second portion on the surface of the first spacer layer outside the groove, wherein the first portion and the second portion of the second spacer layer are respectively located between the first portion and the second portion of the first field plate and the surface of the semiconductor layer structure. and A third spacer layer includes substantially coplanar surfaces on the second spacer layer, wherein the first field plate is located between the third spacer layer and the second spacer layer.

14. A transistor, comprising: The channel layer and the barrier layer define the heterostructure between them; The source electrode and drain electrode on the barrier layer; A gate electrode is located on the barrier layer and includes sidelobe portions that extend laterally from opposite sides of the gate electrode toward the source electrode and the drain electrode, respectively. A field plate on the barrier layer between the gate electrode and the drain electrode, the field plate having a stepped structure; and A spacer insulator layer includes a plurality of spacer layers with the field plate between the plurality of spacer layers, wherein the spacer layers are stacked on the barrier layer on opposite sides of the gate and separate sidelobe portions of the gate from the barrier layer, wherein the sidelobe portions of the gate extend laterally along the surface of the spacer insulator layer, and wherein the field plate is below the surface of the spacer insulator layer.

15. The transistor of claim 14, wherein, One of the side lobes of the gate overlaps the field plate in a direction perpendicular to the surface of the barrier layer.

16. The transistor of claim 14, wherein, The plurality of spacer layers define substantially coplanar surfaces on opposite sides of the gate, wherein the sidelobe portions of the gate extend laterally directly on the substantially coplanar surfaces.

17. The transistor according to claim 14 or 16, wherein, The spacer layer has a substantially uniform thickness on the opposite side of the gate.

18. The transistor according to claim 14 or 16, wherein, The field plate includes a first portion adjacent to the gate and a second portion adjacent to the drain electrode, wherein the second portion is further away from the surface of the barrier layer than the first portion.

19. The transistor of claim 18, wherein, The first portion of the field plate and one of the side lobes of the gate extend laterally toward each other and are non-overlapping in a direction perpendicular to the surface of the barrier layer.

20. The transistor of claim 18, further comprising: Sidewall spacers separate the gate from the plurality of spacer layers on its opposite side, wherein a first portion of the field plate extends laterally toward the gate and is separated from the gate by one of the sidewall spacers.

21. A method for manufacturing a transistor, the method comprising: Forming a channel layer and a barrier layer, which confine a heterostructure in between; A source electrode, a drain electrode, and a gate electrode are formed on the barrier layer, wherein the gate electrode includes a side lobe portion that extends laterally from opposite sides of the gate electrode toward the source electrode and the drain electrode, respectively. and A spacer insulator layer and a field plate are formed on the barrier layer. The field plate has a stepped structure, and the spacer insulator layer includes a plurality of spacer layers with the field plate between the plurality of spacer layers. The spacer layers are stacked on the barrier layer on opposite sides of the gate and separate the sidelobe portion of the gate from the barrier layer. The sidelobe portion of the gate extends laterally along the surface of the spacer insulator layer, and the field plate is below the surface of the spacer insulator layer.

22. The method of claim 21, wherein the plurality of spacer layers define substantially coplanar surfaces, and the sidelobe portions of the gate extend laterally directly on the substantially coplanar surfaces.

23. The method according to claim 21 or 22, wherein, The field plate includes a first portion adjacent to the gate and a second portion adjacent to the source electrode or drain electrode, wherein the second portion is further away from the surface of the barrier layer than the first portion.

24. The method of claim 23, wherein forming the spacer insulating layer and the field plate comprises: A first spacer layer is formed, the first spacer layer including grooves in its surface; A second spacer layer is formed, the second spacer layer comprising a first portion in the groove and a second portion on the surface of the first spacer layer outside the groove; The first portion and the second portion of the field plate are respectively formed on the first portion and the second portion of the second spacer layer; and A third spacer layer is formed on the second spacer layer and on the first and second portions of the field plate.

25. The method of claim 24, wherein the field plate is a first field plate, and the method further comprises: An opening is formed extending through the third spacer layer to expose at least one of the first or second portions of the first field plate; and A second field plate is formed on the third spacer layer and the second field plate extends into the opening to contact the first field plate.

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