Double-adjacent error correction code based on (23,12) Golay code for data storage correction

Abstract

The present invention discloses a double-adjacent error correction code based on (23,12) Golay code for data storage correction, including a coding unit and a decoding unit; the characteristics are: the coding unit encodes the data to be stored, calculates the check bit, and the check bit and the data bit are combined into a codeword as the output of the coding unit; the decoding unit decodes the received codeword, calculates the syndrome, calculates the data position where the soft error occurs according to the syndrome, and corrects it. The double-adjacent error correction code proposed by the present invention is optimized based on the (23,12) Golay code, optimizes the parity check matrix under the premise of ensuring that single-bit and double-adjacent bit errors can be corrected, reduces the column weight of the parity check matrix, optimizes the encoding and decoding algorithm, optimizes the encoding and decoding process, and reduces the area of ​​the coding unit and the decoding unit. At the same time, the data bit and the check bit are interleaved and stored, the data error position calculation process is optimized, the decoding unit area is reduced, the ECC module area is reduced, and the power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of data storage and communication, and in particular to a double-adjacent error correction code based on a (23, 12) Golay code for data storage correction. Background Art

[0002] With the continuous development of integrated circuits, the application of electronic products is ubiquitous, and the proportion of memory in chips is increasing. SRAM, as the on-chip storage of SoC (System on Chip), is the memory closest to the central processing unit CPU and has the fastest access speed. The correctness of the data stored in SRAM static memory is related to the correctness of the system function.

[0003] There is a lot of radiation in space, such as cosmic rays and solar radiation. Under high-energy particle radiation, the memory devices of integrated circuits are easily disturbed and cause random flipping of storage bits. This phenomenon of random flipping of storage bits caused by external influences only affects the correctness of data storage and does not damage electronic devices. It is called soft error. The existence of soft errors affects the data reliability of the memory and the functional correctness of the SoC. Other measures are needed to enhance the reliability of the memory.

[0004] Initially, the method of strengthening memory reliability was mainly used in the aerospace field. With the continuous development of integrated technology and the pursuit of low power consumption of chips, the process size has been continuously reduced, resulting in a decrease in circuit node voltage and node charge, which reduces the noise margin of the circuit and makes the circuit system more and more sensitive to radiation. Some radiation particles pass through the atmosphere to reach the ground, and with nuclear explosions, there are also high-energy radiation particles in the low-altitude area. In a radiation environment, the memory is easily bombarded by radiation particles and single event upsets (SEUs) and multiple cell upsets (MCUs) occur. The reduction in memory size increases the probability of data upsets. The reliability of memory in the civilian field has attracted more and more attention.

[0005] In order to reduce the probability of soft errors in memory, reinforcement is carried out at multiple levels at home and abroad, including process level, circuit level, and system level. Error correction codes (ECC) are a common system-level reinforcement method, and ECC is commonly used in industrial and civil fields to strengthen storage reliability.

[0006] ECC error correction code adds a small amount of redundant check bits and establishes the relationship between data and check bits according to a certain algorithm. When data is accidentally flipped, the flipped bits are detected and corrected according to the corresponding relationship between data and check bits, thereby enhancing the reliability of memory. ECC error correction code contains a variety of different encoding algorithms. Different encoding algorithms have different relationships between data bits and check bits, different error correction capabilities, and different encoding and decoding complexities. Researching different ECC error correction code algorithms and optimizing different ECC algorithms according to different application scenarios has become a focus.

[0007] Golay code is a typical ECC error correction code. Due to its perfect algebraic structure, Golay code has been widely studied. However, the encoding and decoding of double-adjacent error correction codes based on extended Golay codes are complex, and the circuit area and power consumption of the encoding unit and decoding unit are large. Therefore, it is necessary to optimize the ECC encoding and decoding process and reduce the circuit area and power consumption of the ECC module. Summary of the invention

[0008] The purpose of the present invention is: to address the above shortcomings, the present invention optimizes the algorithm based on Golay code, and provides a double adjacent error correction code based on (23,12) Golay code for data storage correction, which can correct single-bit and double adjacent bit errors, optimize the encoding and decoding process, reduce circuit area, and reduce circuit power consumption.

[0009] The technical solution of the present invention is:

[0010] A double-adjacent error correction code based on (23,12) Golay code for data storage correction includes a coding unit and a decoding unit; the coding unit encodes the data to be stored, calculates a check bit, and the check bit and the data bit are combined into a code word as the output of the coding unit; the decoding unit decodes the received code word, calculates a syndrome, calculates the data position where a soft error occurs according to the syndrome, and corrects it.

[0011] Preferably, the encoding process of the encoding unit includes calculating check bits and splicing codewords; each check bit is calculated from different data bits, the encoding unit inputs data with a bit width of 12, calculates to obtain 11 check bits, and the codeword consisting of data and check bits has a bit width of 23.

[0012] Preferably, the algorithm for calculating the check bit is based on the improved (23,12) Golay code double adjacent error correction parity check matrix, checki represents the i-th check bit, datai represents the i-th data bit, the first check bit check1 is generated by data1, data2, data4, data5, data6, data10, data12 data XOR calculation, check2 is generated by data2, data3, data5, data6, data7, data11 data XOR calculation, check3 is generated by data1, data3, data4, data6, data7, data8 data XOR calculation, check4 is generated by data2, data4, data5, data7, data8, data9 data XOR calculation, check5 is generated by data3, data5, data6, data8, data9, data10, data12 data XOR calculation Generated, check6 is generated by data4, data6, data7, data9, data10, and data11 data XOR calculation, check7 is generated by data1, data5, data7, data8, data10, and data11 data XOR calculation, check8 is generated by data1, data2, data6, data8, data9, data11, and data12 data XOR calculation, check9 is generated by data1, data2, data3, data7, data9, data10, and data12 data XOR calculation, check10 is generated by data2, data3, data4, data8, data10, data11, and data12 data XOR calculation, check11 is generated by data1, data3, data4, data5, data9, data11, and data12 data XOR calculation.

[0013] Preferably, the spliced ​​codeword is formed by interleaving a check bit and a data bit, and the interleaving combination order is {data1, check1, data2, check2, data3, check3, data4, check4, data5, check5, data6, check6, data7, check7, data8, check8, data9, check9, data10, check10, data11, check11, data12}.

[0014] Preferably, the decoding process of the decoding unit includes codeword splitting, recalculating check bits, calculating syndromes, calculating soft error data positions, and correcting data.

[0015] Preferably, the codeword splitting is to split the codeword received by the decoding unit to obtain 12 bits of data and 11 bits of check bits; the obtained data bits are represented by data_code, and the check bits are represented by check_code.

[0016] Preferably, the recalculated check bit is based on the improved (23,12) Golay code double adjacent error correction algorithm, and the algorithm is represented by a parity check matrix: check_newi is used to represent the recalculated i-th check bit, data_codei represents the i-th data bit obtained by splitting the codeword, the first check bit check_new1 is generated by data_code1, data_code2, data_code4, data_code5, data_code6, data_code10, and data_code12 data XOR calculation, check_new2 is generated by data_code2, data_code3, data_code5, data_code6, data_code7, and data_code11 data XOR calculation, check_new3 is generated by data_code1, data_code3, data_code4, data_code6, data_code7, and data_code8 data XOR calculation, check_new4 is generated by data_code2, data_code4, data_code5, data_code7, data_code8, and data_code9 data XOR calculation, eck_new5 is generated by XOR calculation of data_code3, data_code5, data_code6, data_code8, data_code9, data_code10, and data_code12; check_new6 is generated by XOR calculation of data_code4, data_code6, data_code7, data_code9, data_code10, and data_code11; check_new7 is generated by XOR calculation of data_code1, data_code5, data_code7, data_code8, data_code10, and data_code11; check_new8 is generated by XOR calculation of data_code1, data_code2, data_code6, data_code8, data_code9, data_code11, and data_code12; check_new9 is generated by XOR calculation of data_code1, data_code2, data_code3, data_code7, data_code9, data_code10, and data_code12.check_new10 is generated by XOR calculation of data_code2, data_code3, data_code4, data_code8, data_code10, data_code11, and data_code12. check_new11 is generated by XOR calculation of data_code1, data_code3, data_code4, data_code5, data_code9, data_code11, and data_code12. ,

[0017] Preferably, the calculated syndrome is obtained by XOR calculation of the check bit check_code split from the codeword and the recalculated check bit check_new, and the calculated syndrome is denoted by syn.

[0018] Preferably, the calculation of the soft error data position is based on the improved (23,12) Golay code double adjacent error correction algorithm, and flip_bitsi is used to indicate whether a soft error occurs in the i-th data. If flip_bitsi is "1", it indicates that a soft error occurs in the i-th data; if flip_bitsi is "0", it indicates that no soft error occurs in the i-th data; flip_bits1 is generated by the AND calculation of syn3, syn7, syn8, syn9, and syn11 syndromes; flip_bits2 is generated by the AND calculation of syn4, syn8, syn9, and syn10 syndromes; flip_bits3 is generated by the AND calculation of syn5, syn9, syn10, syn11, and syn1 syndromes; flip_bits4 is generated by the AND calculation of syn1, syn6, syn10, and syn11 syndromes; flip_bits5 is generated by the AND calculation of syn1 , syn2, syn7, and syn11 syndromes are generated by the AND calculation of syn1, syn2, syn3, and syn8 syndromes, flip_bits7 is generated by the AND calculation of syn2, syn3, syn4, and syn9 syndromes, flip_bits8 is generated by the AND calculation of syn3, syn4, syn5, and syn10 syndromes, flip_bits9 is generated by the AND calculation of syn4, syn5, syn6, and syn11 syndromes, flip_bits10 is generated by the AND calculation of syn1, syn5, syn6, and syn7 syndromes, flip_bits11 is generated by the AND calculation of syn2, syn6, syn7, and syn8 syndromes, and flip_bits12 is generated by the AND calculation of syn1, syn5, syn8, syn9, and syn10 syndromes.

[0019] Preferably, the correction data is the corrected data data_correct obtained by XORing the data data_code in the codeword with the data soft error position flip_bits.

[0020] The advantages of the present invention are:

[0021] The double-adjacent error correction code proposed in the present invention is optimized based on the (23,12) Golay code. Under the premise of ensuring that single-bit and double-adjacent bit errors can be corrected, the parity check matrix is ​​optimized, the column weight of the parity check matrix is ​​reduced, the encoding and decoding algorithm is optimized, the encoding and decoding process is optimized, and the area of ​​the encoding unit and the decoding unit is reduced. At the same time, the data bits and the check bits are interleaved and stored, the data error position calculation process is optimized, the decoding unit area is reduced, the ECC module area is reduced, and the power consumption is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0023] Figure 1 The parity check matrix of the double-adjacent error correction code optimized based on the (23,12) Golay code of the present invention;

[0024] Figure 2 A syndrome corresponding to a single-bit error of the interleaved codeword of the present invention;

[0025] Figure 3 The present invention simplifies the syndrome of the data error;

[0026] Figure 4 The invention is based on the syndrome corresponding to the (23,12) Golay code double adjacent error correction code data error. DETAILED DESCRIPTION

[0027] The present invention discloses a double-adjacent error correction code based on (23,12) Golay code for data storage correction, comprising a coding unit and a decoding unit; the coding unit encodes the data to be stored, calculates a check bit, and the check bit and the data bit are combined into a code word as the output of the coding unit; the decoding unit decodes the received code word, calculates a syndrome, calculates the data position where a soft error occurs according to the syndrome, and corrects it.

[0028] The encoding process of the encoding unit includes calculating the check bit and splicing the codeword; each check bit is calculated and generated by different data bits, the encoding unit inputs data with a width of 12, calculates the check bit to be 11 bits, and the codeword consisting of the data and the check bit has a width of 23. The decoding process of the decoding unit includes codeword splitting, recalculating the check bit, calculating the syndrome, calculating the soft error data position, and correcting the data.

[0029] like Figure 1As shown in FIG. 1 , the parity check matrix of the double-adjacent error correction code optimized based on the (23,12) Golay code in this embodiment, and the parity check matrix contains the ECC algorithm. The i-th row vector of the parity check matrix shows the relationship between the i-th check bit and the required data bit, and the j-th column vector of the parity check matrix shows the relationship between the j-th code element and the participating check bit. With the upper left as the low bit, the 12th column represents the relationship between the first bit of data and the check bit. This column shows the position of the check bit in which the first data bit participates. The position of "1" in this column indicates that the data participates in the generation of the corresponding check bit.

[0030] Figure 2 The parity check matrix H represents the syndrome corresponding to the single-bit error of the interleaved codeword. In addition to representing the relationship between the data bit and the parity check bit, it also has a deeper mathematical meaning: the column vector represents the syndrome of the single-bit data error flip. The new parity bit is XORed with the old parity bit in the codeword to calculate the syndrome, which is the deviation value of the new and old parity check bits generated before and after the data bit flips.

[0031] Figure 3 (a) is a simplified version of the syndrome when the first bit of data is wrong. The syndrome corresponding to the error mode in which the first bit of data is flipped is shown in the first column of the figure, and the syndrome corresponding to the error mode in which the first bit of data and the first check bit are flipped at the same time is shown in the second column of the figure. The syndromes in the two error modes are different only in the first bit, and the remaining ten bits are the same. Therefore, the two error modes in which the first bit of data is modified cover the two situations of the first bit of the syndrome. Therefore, whether the first bit of data is modified can be determined only by judging the last ten bits of the syndrome. The syndromes covering these two error modes are shown in the third column of the figure, where the question mark bit indicates that the bit is not of concern.

[0032] Figure 3 (b) represents the simplification of the syndrome when the second bit of data is wrong. The syndrome corresponding to the single-bit error mode where only the data is flipped is shown in the first column of the figure. The syndrome corresponding to the double-adjacent error mode where the second bit of data and the first check bit adjacent to the left are flipped at the same time is shown in the second column of the figure. The syndrome corresponding to the double-adjacent error mode where the second bit of data and the second check bit adjacent to the right of the data are flipped at the same time is shown in the third column of the figure. The syndrome corresponding to the triple-adjacent error mode where the second bit of data and the three adjacent bits to the left and right are flipped at the same time is shown in the fourth column of the figure. The four syndromes corresponding to these four error modes are different in only the first two bits, and the rest of the bits are the same; and the four syndromes corresponding to these four error modes cover all four combinations of the first two bits. Therefore, whether the second bit of data is modified can be determined by only judging the last 9 bits of the syndrome, as shown in the fifth column of the figure, where the question mark bit is a don't care bit and does not need to be involved in the judgment.

[0033] The corrections corresponding to the four error modes of the third data bit, the fourth data bit, the fifth data bit, the sixth data bit, the seventh data bit, the eighth data bit, the ninth data bit, and the tenth data bit are similar to the four error modes of the second data bit. These four error modes have only two different syndromes, and the other nine syndromes are the same. Moreover, these four error modes cover all situations of these two syndromes. Therefore, the four syndromes of the four errors can be combined into a syndrome containing only nine bits. The syndromes after the specific data is simplified are as follows: Figure 4 shown.

[0034] In summary, the present invention provides a double-adjacent error correction code based on the (23, 12) Golay code. Under the premise of ensuring the error correction capability of single bits and double-adjacent bits, the algorithm is optimized, the parity check matrix is ​​optimized, the encoding and decoding process is simplified, and the check bits and data bits are interleaved and stored, thereby simplifying the syndrome of each data error and optimizing the decoding process. Compared with traditional Golay codes, the present invention consumes less area and power consumption.

[0035] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any modifications made according to the spirit of the main technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A double-adjacent error correction code system based on (23,12) Golay code for data storage correction, comprising an encoding unit and a decoding unit; characterized in that: The encoding unit encodes the data to be stored, calculates the check bit, and combines the check bit with the data bit into a code word as the output of the encoding unit; the decoding unit decodes the received code word, calculates the syndrome, calculates the data position where the soft error occurs according to the syndrome, and corrects it; The encoding process of the encoding unit includes calculating the check bit and splicing the codeword; each check bit is calculated and generated by different data bits, the encoding unit inputs data with a width of 12, calculates the check bit to be 11 bits, and the codeword composed of the data and the check bit has a width of 23 bits; The algorithm for calculating the check bit is based on the improved (23,12) Golay code double adjacent error correction parity check matrix. Checki represents the i-th check bit, datai represents the i-th data bit, the first check bit check1 is generated by the XOR calculation of data1, data2, data4, data5, data6, data10, and data12, check2 is generated by the XOR calculation of data2, data3, data5, data6, data7, and data11, check3 is generated by the XOR calculation of data1, data3, data4, data6, data7, and data8, check4 is generated by the XOR calculation of data2, data4, data5, data7, data8, and data9, and check5 is generated by the XOR calculation of data3, data5, data6, data8, data9, data10, and data12 , check6 is generated by data4, data6, data7, data9, data10, and data11 XOR calculation, check7 is generated by data1, data5, data7, data8, data10, and data11 XOR calculation, check8 is generated by data1, data2, data6, data8, data9, data11, and data12 XOR calculation, check9 is generated by data1, data2, data3, data7, data9, data10, and data12 XOR calculation, check10 is generated by data2, data3, data4, data8, data10, data11, and data12 XOR calculation, check11 is generated by data1, data3, data4, data5, data9, data11, and data12 XOR calculation; The decoding process of the decoding unit includes codeword splitting, recalculating check bits, calculating syndromes, calculating soft error data positions, and correcting data; The codeword splitting is to split the codeword received by the decoding unit to obtain 12 bits of data and 11 bits of check bits; the obtained data bits are represented by data_code, and the check bits are represented by check_code; The recalculated check bits are based on an improved (23,12) Golay code double adjacent error correction algorithm, and the algorithm is represented by a parity check matrix: check_newi represents the recalculated i-th check bit, data_codei represents the i-th data bit obtained by codeword splitting, the first check bit check_new1 is generated by data_code1, data_code2, data_code4, data_code5, data_code6, data_code10, and data_code12 data XOR calculation, check_new2 is generated by data_code2, data_code3, data_code5, data_code6, data_code7, and data_code11 data XOR calculation, check_new3 is generated by data_code1, data_code3, data_code4, data_code6, data_code7, and data_code8 data XOR calculation, check_new4 is generated by data_code2, data_code4, data_code5, data_code7, data_code8, and data_code9 data XOR calculation, and check_new5 is generated by data_code2, data_code4, data_code5, data_code7, data_code8, and data_code9 data XOR calculation. k_new5 is generated by XOR calculation of data_code3, data_code5, data_code6, data_code8, data_code9, data_code10, and data_code12. check_new6 is generated by XOR calculation of data_code4, data_code6, data_code7, data_code9, data_code10, and data_code11. check_new7 is generated by XOR calculation of data_code1, data_code5, data_code7, data_code8, data_code10, and data_code11. check_new8 is generated by XOR calculation of data_code1, data_code2, data_code6, data_code8, data_code9, data_code11, and data_code12. check_new9 is generated by XOR calculation of data_code1, data_code2, data_code3, data_code7, data_code9, data_code10, and data_code12.check_new10 is generated by XOR calculation of data_code2, data_code3, data_code4, data_code8, data_code10, data_code11, and data_code12; check_new11 is generated by XOR calculation of data_code1, data_code3, data_code4, data_code5, data_code9, data_code11, and data_code12; The calculated syndrome is obtained by XOR calculation of the check bit check_code split from the codeword and the recalculated check bit check_new, and the calculated syndrome is represented by syn; The calculation of the soft error data position is based on the improved (23,12) Golay code double adjacent error correction algorithm, and flip_bitsi is used to indicate whether a soft error occurs in the i-th data. If flip_bitsi is "1", it indicates that a soft error occurs in the i-th data. If flip_bitsi is "0", it indicates that no soft error occurs in the i-th data. flip_bits1 is generated by the AND calculation of syn3, syn7, syn8, syn9, and syn11 syndromes, flip_bits2 is generated by the AND calculation of syn4, syn8, syn9, and syn10 syndromes, flip_bits3 is generated by the AND calculation of syn5, syn9, syn10, syn11, and syn1 syndromes, flip_bits4 is generated by the AND calculation of syn1, syn6, syn10, and syn11 syndromes, and flip_bits5 is generated by the AND calculation of syn1, syn7, syn8, syn9, and syn11 syndromes. The yn2, syn7, and syn11 syndromes are generated by the AND calculation, flip_bits6 is generated by the AND calculation of syn1, syn2, syn3, and syn8 syndromes, flip_bits7 is generated by the AND calculation of syn2, syn3, syn4, and syn9 syndromes, flip_bits8 is generated by the AND calculation of syn3, syn4, syn5, and syn10 syndromes, flip_bits9 is generated by the AND calculation of syn4, syn5, syn6, and syn11 syndromes, flip_bits10 is generated by the AND calculation of syn1, syn5, syn6, and syn7 syndromes, flip_bits11 is generated by the AND calculation of syn2, syn6, syn7, and syn8 syndromes, and flip_bits12 is generated by the AND calculation of syn1, syn5, syn8, syn9, and syn10 syndromes.

2. The dual-adjacent error correction code system according to claim 1, characterized in that: The spliced ​​codeword is formed by interleaving the check bits and the data bits, and the interleaving combination order is {data1, check1, data2, check2, data3, check3, data4, check4, data5, check5, data6, check6, data7, check7, data8, check8, data9, check9, data10, check10, data11, check11, data12}.

3. The dual-adjacent error correction code system according to claim 1, characterized in that: The correction data is the corrected data data_correct obtained by XORing the data data_code in the code word with the data soft error position flip_bits.

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