A memory device, a memory system, and a programming operation method

Abstract

This invention discloses a memory device, a memory system, and a programming operation method. The memory device includes: a memory array having multiple memory blocks, each memory block being arranged to have multiple memory sub-blocks; each memory sub-block containing at least one memory cell; and control circuitry coupled to the memory array, the control circuitry being configured to determine a verification loop count for programming a memory cell in a first memory sub-block of the first memory block to a target programmed data state during a non-last programming pass when performing multiple programming passes on a first memory block of the multiple memory blocks; and when programming memory cells in other memory sub-blocks of the first memory block to the target programmed data state using the same programming and verification conditions as for the first memory sub-block, at least no verification operation corresponding to the last time in the verification loop count is performed during the non-last programming pass of memory cells in the other memory sub-blocks.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a memory device, memory system, and programming operation method. Background Technology

[0002] Non-volatile memory (NDRAM) is widely used in electronic devices across various fields. Flash memory is one of the most widely used NDRAMs that can be electrically erased and reprogrammed. Flash memory can include both NOR and NAND architectures. Various operations, such as reading, programming, and erasing, are achieved by changing the threshold voltage of each memory cell in the flash memory to the required level. Flash memory operations can be performed at the block level, the page level, and the cell level. Programming multi-state flash memory is achieved by identifying multiple different allowable threshold voltage ranges. Currently, programming the memory cells of multi-state flash memory often involves multiple passes of programming and verification operations, resulting in a long programming time. Summary of the Invention

[0003] In view of this, the main objective of the present invention is to provide a memory device, a memory system, and a programming operation method to solve the related technical problems.

[0004] On one hand, the present invention provides a memory device comprising: a memory array having a plurality of memory blocks, wherein each of the memory blocks is arranged to include a plurality of memory sub-blocks; each memory sub-block includes at least one memory cell; and control circuitry coupled to the memory array; wherein,

[0005] The control circuit is configured to: determine a verification loop count for performing a verification operation on the storage cells in the first sub-block of the first storage block to the target programming data state during a non-last programming pass when performing multiple programming passes on the first storage block of the plurality of storage blocks;

[0006] When the storage cells in other storage sub-blocks of the first storage block are programmed to the target programming data state using the same programming and verification conditions as those used for the first storage sub-block, at least no verification operation corresponding to the last time in the verification loop count is performed in the non-last pass programming of the storage cells in the other storage sub-blocks.

[0007] Wherein, the first storage block is any one of the plurality of storage blocks; the first storage sub-block is any one of the first storage blocks; and the other storage sub-blocks are storage sub-blocks in the first storage block other than the first storage sub-block.

[0008] In one aspect, the present invention also provides a method for programming a memory device, the memory device comprising a memory array having a plurality of memory blocks, wherein each of the memory blocks is arranged to include a plurality of memory sub-blocks; each memory sub-block includes at least one memory cell;

[0009] The programming operation method includes:

[0010] The verification loop count is determined when performing verification operations on the first storage sub-block of the first storage block during non-last programming passes while performing multiple programming passes on the first storage block of the plurality of storage blocks;

[0011] When the storage cells in other storage sub-blocks of the first storage block are programmed to the target programming data state using the same programming and verification conditions as those used for the first storage sub-block, at least no verification operation corresponding to the last time in the verification loop count is performed in the non-last pass programming of the storage cells in the other storage sub-blocks.

[0012] Wherein, the first storage block is any one of the plurality of storage blocks; the first storage sub-block is any one of the first storage blocks; and the other storage sub-blocks are storage sub-blocks in the first storage block other than the first storage sub-block.

[0013] On one hand, embodiments of the present invention also provide a memory system comprising a memory device, the memory device comprising: a memory array having a plurality of memory blocks, wherein each of the memory blocks is arranged to include a plurality of memory sub-blocks; each memory sub-block includes at least one memory cell; and control circuitry coupled to the memory array; wherein the control circuitry is configured to: determine a verification loop count for performing a verification operation on a memory cell in a first memory sub-block of the first memory block to a target programming data state during a non-last programming pass when performing multiple programming passes on a first memory block of the plurality of memory blocks;

[0014] When the storage cells in other storage sub-blocks of the first storage block are programmed to the target programming data state using the same programming and verification conditions as those used for the first storage sub-block, at least no verification operation corresponding to the last time in the verification loop count is performed in the non-last pass programming of the storage cells in the other storage sub-blocks.

[0015] Wherein, the first storage block is any one of the plurality of storage blocks; the first storage sub-block is any one of the first storage blocks; and the other storage sub-blocks are storage sub-blocks in the first storage block other than the first storage sub-block.

[0016] as well as,

[0017] A controller coupled to the memory device, the controller being configured to control the memory device.

[0018] This invention provides a memory device, a memory system, and a programming operation method. The memory device includes: a memory array having a plurality of memory blocks, wherein each memory block is arranged to include a plurality of memory sub-blocks; each memory sub-block includes at least one memory cell; and a control circuit coupled to the memory array, the control circuit being configured to determine a verification loop count during a non-last programming pass of a memory cell in a first memory sub-block of the first memory block being programmed to a target programming data state while performing multiple programming passes on a first memory block of the plurality of memory blocks; and when memory cells in other memory sub-blocks of the first memory block are programmed to the target programming data state using the same programming and verification conditions as those used on the first memory sub-block, at least no verification operation corresponding to the last time in the verification loop count is performed during the non-last programming pass of the memory cells in the other memory sub-blocks; wherein the first memory block is any one of the plurality of memory blocks; the first memory sub-block is any one of the first memory blocks; and the other memory sub-blocks are memory sub-blocks other than the first memory sub-block. The memory device and programming method provided in this invention, when performing multiple programming passes on a memory block, determines the number of verification operations required to program a memory cell in a memory sub-block of the memory block to a target programming data state during non-last programming passes. Then, when performing the same multiple programming passes on other memory sub-blocks of the memory block using the same programming and verification conditions, the number of verification operations for some memory cells in other memory sub-blocks is reduced during non-last programming passes based on the determined number of verification operations. In this way, while ensuring read window margin, the programming time required can be reduced, thereby improving the programming (write) speed of the memory device. Attached Figure Description

[0019] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals can describe similar components in different views. The same numbers with different letter suffixes can represent different instances of similar components. The accompanying drawings generally illustrate the various embodiments discussed in this document by way of example, not limitation.

[0020] Figure 1 This is a top view of a NAND string according to an embodiment of the present invention;

[0021] Figure 2 This is an equivalent circuit diagram of a NAND string according to an embodiment of the present invention;

[0022] Figure 3This is a schematic diagram of the array structure of the storage unit provided in an embodiment of the present invention;

[0023] Figure 4 A perspective view of a portion of an exemplary embodiment of a single-block three-dimensional memory array provided in an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of the structure of a memory device having read / write circuitry for parallel reading and programming of memory cells according to an embodiment of the present invention;

[0025] Figures 6A to 6D Threshold voltage distribution of the memory cell provided in the embodiments of the present invention;

[0026] Figure 7 A schematic diagram of the stepping pulse structure of the ISPP method provided in this embodiment of the invention;

[0027] Figure 8 A schematic diagram of the verification voltage pulse provided in an embodiment of the present invention;

[0028] Figure 9 This is a schematic diagram of the structure of a memory device provided in an embodiment of the present invention;

[0029] Figure 10 This is a schematic diagram illustrating the execution of programming and verification operations when employing a predictive FBC verification strategy, as provided in an embodiment of the present invention.

[0030] Figure 11 This is a schematic diagram illustrating the verification information required for programming each programming data state of the storage unit coupled to word line WL10 in String0 after adopting the programming method provided in this embodiment of the invention.

[0031] Figure 12 This is a schematic diagram illustrating the verification information required for programming each programming data state of the storage units coupled to the word line WL10 in String1, String2, and String3 using the programming method provided in this embodiment of the invention.

[0032] Figure 13 This is a schematic flowchart of a method for programming a memory device according to an embodiment of the present invention;

[0033] Figure 14 A schematic diagram of a memory system provided in an embodiment of the present invention;

[0034] Figure 15(A) is a schematic diagram of an exemplary memory card with a memory system according to some aspects of the present invention;

[0035] Figure 15(B) is a schematic diagram of an exemplary solid-state drive (SSD) with a memory system according to some aspects of the present invention. Detailed Implementation

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the embodiments provided herein are merely illustrative of the invention and are not intended to limit the invention. Furthermore, the embodiments provided below are partial embodiments for implementing the present invention, and not all embodiments for implementing the present invention. Unless otherwise specified, the technical solutions described in the embodiments of the present invention can be implemented in any combination.

[0037] It should be noted that, in the embodiments provided by this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a method or apparatus that comprises a list of elements includes not only the elements expressly stated, but also other elements not expressly listed, or elements inherent to implementing the method or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other related elements in the method or apparatus that includes that element, such as steps in the method or units in the apparatus, for example, a unit may be a portion of circuitry, a portion of a processor, a portion of a program or software, etc.

[0038] Furthermore, although the concept of the present invention will be described with reference to NAND flash memory, it should be understood that embodiments of the present invention are not limited to this configuration. For example, the concept of the present invention can also be applied to electrically erasable and programmable ROM (EEPROM), NOR flash memory, phase-change RAM (PRAM), magnetic RAM (MPAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc., without departing from the concept of the present invention.

[0039] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0040] Figure 1 A top view of a NAND string provided in an embodiment of the present invention; Figure 2 for Figure 1 The diagram shows the equivalent circuit of a NAND string. In a NAND flash memory system, multiple transistors are arranged in series and sandwiched between two select gates (source gate and drain gate). The series-connected transistors and the two select gates are called a NAND string. Figure 1 and Figure 2The NAND string shown includes a top select gate (SGD) on the drain side, a bottom select gate (SGS) on the source side, and a top dummy transistor (SGDT), four transistors 101-104, and a bottom preset transistor (SGST) sandwiched between them. The top select gate (SGD) connects the NAND string to a bit line via a bit line contact; it is controlled by applying an appropriate voltage to the top select gate line (SGDL). The bottom select gate (SGS) connects the NAND string to the source line; it is controlled by applying an appropriate voltage to the bottom select gate line (SGSL). Each of the top dummy transistor SGDT, the four transistors 101-104, and the bottom preset transistor SGST includes a control gate and a floating gate. For example, the top dummy transistor SGDT includes a control gate CGDT and a floating gate FGDT; transistor 101 includes a control gate 101CG1 and a floating gate 101FG1; transistor 102 includes a control gate 102CG1 and a floating gate 102FG1; transistor 103 includes a control gate 103CG1 and a floating gate 103FG1; transistor 104 includes a control gate 104CG1 and a floating gate 104FG1; and the bottom dummy transistor SGST includes a control gate CGST and a floating gate FGST. The control gate CGST is connected to the bottom dummy word line BDWL; control gates 101CG1-104CG1 are connected to word lines WL0-WL3 respectively; and the control gate CGDT is connected to the top dummy word line TSWL.

[0041] It should be noted that, Figure 1 and Figure 2 This is merely an example illustrating four memory cells (transistors 101-104) used for read / write operations and two dummy memory cells (top dummy transistor SGDT and bottom dummy transistor SGST) used for read / write testing in a NAND string. In practical applications, a NAND string can contain 8, 16, 32, 64, 128 memory cells, etc., meaning the number of memory cells or dummy memory cells in a NAND string does not limit the scope of this invention. Furthermore, a typical structure of a flash memory system using a NAND structure includes multiple NAND strings. Each NAND string is connected to the source line via a bottom select gate (SGS) controlled by a bottom select gate line (SGSL), and connected to the corresponding bit line via a top select gate (SGD) controlled by a top select gate line (SGDL). Each bit line and the corresponding NAND string (single or multiple) connected to that bit line via bit line contacts form a column in an array of memory cells. Bit lines are shared by multiple NAND strings. Typically, bit lines extend at the top of the NAND string in a direction perpendicular to the word lines and are connected to one or more sense amplifiers. It should be understood that this invention utilizes only... Figure 1 and Figure 2The example illustrates the NAND string structure. In practical applications, the charge trapping layer is not necessarily a floating gate; it could also be a charge trapping nitride layer, a non-conductive dielectric material, etc.

[0042] In practical applications, the memory array in a memory device is transmitted via... Figure 1 and Figure 2 The NAND strings shown are arranged in a reasonable manner to form a memory array containing multiple storage blocks. An example structure is as follows: Figure 3 As shown. The memory array 300 is divided into BLOCK1-BLOCK. T A memory array with multiple memory blocks, where T is a positive integer. Each memory block contains a set of NAND strings, which are transmitted via bit lines BL0-BL1. M-1 and a set of common word lines WL0-WL N-1 Access, where M and N are both integers greater than 1. One end of the NAND string is connected to the corresponding bit line via the top select gate SGD (controlled by the top select gate line SGDL), and the other end is connected to the source line via the bottom select gate SGS (controlled by the bottom select gate line SGSL). Each memory block is divided into multiple pages. In some embodiments, the memory block is a conventional erase unit, and the page is a conventional programming unit. In other embodiments, other units of erase and programming may also be used. In an example, Figure 3 The physical structure of the memory cells in the illustrated memory array does not limit the scope of the invention.

[0043] In this invention, Figure 3 The memory array shown can be arranged in a 3DQLC structure. It should be noted that other structural arrangements do not limit the scope of the present invention.

[0044] For the structure of each storage block, such as Figure 4 The diagram shows a perspective view of a portion of an exemplary embodiment of a three-dimensional memory array with a single memory block provided by an embodiment of the present invention. (See reference...) Figure 4 The storage block 400 comprises multiple layers stacked on a substrate (not shown) and parallel to the surface of the substrate. Figure 4The diagram shows four word lines (WL) on four layers, which may be designated WL0 to WL3. The memory block 400 also has multiple vias perpendicular to the word lines. The intersection of a word line and a via forms a memory cell; therefore, a via can also be referred to as a string of memory cells. Those skilled in the art should understand that the number of word lines and the number of string of memory cells in the memory block 400 are not limited to specific values. For example, the memory block 400 may include 64 word lines, with 64 word lines intersecting with a string of memory cells to form 64 memory cells along the string. Furthermore, the number of string of memory cells in the memory block 400 may be on the order of hundreds of thousands, millions, or even larger, with a single word line including millions of memory cells formed by its intersection with, for example, millions of string of memory cells. The storage units in storage block 400 can be single-level or multi-level storage units. A single-level storage unit can be a single-level cell (SLC) capable of storing 1 bit; a multi-level storage unit can be a multi-level cell (MLC) capable of storing 2 bits, a three-level cell (TLC) capable of storing 3 bits, a four-level cell (QLC) capable of storing 4 bits, or a five-level cell (PLC) capable of storing 5 bits. For example... Figure 4 As shown, memory block 400 also includes bit lines (BL), bit line selectors (BLS, also known as top select gate line SGDL), source lines (SL), and source select lines (SLS, also known as bottom select gate line SGSL). These circuit lines, together with word lines (WL), enable addressing of any memory cell in memory block 400.

[0045] In some embodiments, the storage block 400 can be logically divided into multiple storage sub-blocks, wherein multiple storage cells coupled to a word line in a storage sub-block can be referred to as a storage cell page or storage page. In some embodiments, programming of the storage block can be performed on a per-storage-page basis.

[0046] based on Figure 3 The memory array shown, Figure 5 This illustrates the embodiment of the invention based on... Figure 3 The diagram shows a memory system 50 with read / write circuitry for parallel reading and / or programming of pages (or other units) of the memory array.

[0047] The memory system 50 includes a memory device 501 and a controller 502. The memory device 501 includes a memory array 300 (two-dimensional or three-dimensional), control circuitry 5011, read / write circuitry 5012A and 5012B, row decoders 5013A and 5013B, and column decoders 5014A and 5014B. In some embodiments, the various control circuits access the memory array 300 in a symmetrical manner on opposite sides of the memory array 300, thereby halving the density of access circuitry on each side. The read / write circuitry 5012A and 5012B include multiple sensing blocks SB for parallel reading or programming of pages in the memory array 300. The memory array 300 can be addressed via word lines through row decoders 5013A and 5013B and via bit lines through column decoders 5014A and 5014B. In some embodiments, the memory array 300, control circuitry 5011, read / write circuits 5012A and 5012B, row decoders 5013A and 5013B, and column decoders 5014A and 5014B can be fabricated on a chip, wherein... Figure 5 The dashed box in the middle can also represent a chip. External signals and data are transmitted between the host and controller 502 via signal line 503, and between the controller 502 and the chip via signal line 504. Control circuitry 5011 is configured to cooperate with read / write circuits 5012A and 5012B to perform memory operations on memory array 300. Control circuitry 5011 includes a state machine, an on-chip address decoder, and a power control module. The state machine is configured to provide chip-level control for memory operations; the on-chip address decoder is configured to provide an address interface between the address used by the controller of the host or memory system and the hardware address used by row decoders 5013A and 5013B and column decoders 5014A and 5014B. The power control module is configured to control the power and voltage supplied to the word lines and bit lines during each memory operation.

[0048] The memory arrays in the memory systems discussed above can be erased, programmed, and read. Since memory cells in a memory system can be arranged as single-level cells or multi-level cells, and multi-level cells can be further divided into multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), etc., for a memory page, at the end of a successful programming process (with verification), the threshold voltage of the programmed memory cell should be within one or more distributions. In practical applications, different types of memory cells have different data states, specifically... Figures 6A to 6D The threshold voltage distribution curves of memory cells are shown for single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC) respectively.

[0049] like Figure 6AAs shown, in an SLC, there are two threshold voltage distributions: E and P. Threshold voltage distribution E corresponds to the erase data state, and threshold voltage distribution P corresponds to the program data state. The threshold voltage of threshold voltage distribution E corresponding to the erase data state is lower than the threshold voltage of threshold voltage distribution P corresponding to the program data state. Therefore, memory cells with a threshold voltage in threshold voltage distribution E are in the erase data state; memory cells with a threshold voltage in threshold voltage distribution P are in the program data state. In some embodiments, an SLC-type memory cell stores one bit of data; specifically, an erased memory cell stores data 1, and a programmable memory cell stores data 0.

[0050] like Figure 6B As shown, in MLC, there are four threshold voltage distributions: E, P1, P2, and P3, with the threshold voltages increasing sequentially. Similarly, threshold voltage distribution E corresponds to the erased data state; threshold voltage distributions P1, P2, and P3 correspond to the programmed data state. In some embodiments, MLC-type memory cells store two bits of data. Specifically, erased memory cells store data 11, memory cells programmed to the P1 data state store data 10, memory cells programmed to the P2 data state store data 10, and memory cells programmed to the P3 data state store data 00.

[0051] like Figure 6C As shown, in a TLC, there are eight threshold voltage distributions: E, S1, S2, S3, S4, S5, S6, and S7, with the threshold voltages increasing sequentially. Similarly, threshold voltage distribution E corresponds to the erased data state; threshold voltage distributions S1, S2, S3, S4, S5, S6, and S7 correspond to the programmed data states. In some embodiments, TLC-type memory cells store three bits of data. Specifically, erased memory cells can store data 111, memory cells programmed to the S1 data state store data 110, memory cells programmed to the S2 data state store data 101, memory cells programmed to the S3 data state store data 100, memory cells programmed to the S4 data state store data 011, memory cells programmed to the S5 data state store data 010, memory cells programmed to the S6 data state store data 001, and memory cells programmed to the S7 data state store data 000.

[0052] like Figure 6DAs shown, in QLC, there are 16 threshold voltage distributions: E, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15, with the threshold voltages increasing sequentially. Similarly, threshold voltage distribution E corresponds to the erase data state; threshold voltage distributions L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15 correspond to the programming data states. For data state N, this data state N has a higher threshold voltage than data state N-1 and a lower threshold voltage than data state N+1. In some embodiments, a QLC-type memory cell stores four bits of data. Specifically, an erased memory cell can store the data 1111, and memory cells programmed to L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15 data states can sequentially store the data 1110, 1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, and 0000.

[0053] It should be noted that, regardless of the type of memory cell mentioned above, each threshold voltage distribution (data state) corresponds to a predetermined value of a set of data bits stored in the memory cell. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the memory cell depends on the data encoding scheme adopted by the memory cell, such as using Gray code encoding scheme.

[0054] In practical applications, for flash memory devices with multiple data states, such as NAND flash memory devices, to reduce coupling and interference between word lines when programming memory cells, multiple programming passes can be used in some embodiments to achieve a tighter threshold voltage distribution when programming memory pages or blocks. In some embodiments, the multiple programming passes can include two-pass programming, three-pass programming, etc., where two-pass programming can include a first coarse programming pass and a fine programming pass; three-pass programming can include a first coarse programming pass, a second coarse programming pass, and a fine programming pass. Here, the last programming pass in the multiple programming passes is fine programming; the first coarse programming pass and the second coarse programming pass are collectively referred to as coarse programming, or both can be referred to as non-last programming passes. In some embodiments, both non-last programming passes and fine programming passes can be incremental step pulse programming (ISPP). This ISPP scheme can gradually increase the word line bias voltage based on a step voltage while programming the memory cells in the selected memory page several times, where the incremental step pulse V... pgm For reference Figure 7To balance programming speed with a wide read window margin (RWM), in some embodiments, during non-final programming passes (each coarse programming stage), a programming voltage pulse with a large set step size (e.g., 0.5 volts (V)) is applied to selected word lines (word lines selected to be coupled with memory cells to be programmed) to quickly program the memory cells coupled to the selected word lines to an intermediate data state. In the fine programming stage, which follows each coarse programming stage, a programming voltage pulse with a smaller set step size (e.g., 0.2V) is applied to the selected word lines to accurately program the memory cells coupled to the selected word lines to the final data state. That is, in some embodiments, in each of the multiple programming passes, the programming voltage / pulse applied during the programming operation increases according to different set step sizes, the specific set step size of which can be set by the designer according to the actual programming situation. The intermediate data states refer to one or more data states before the programmed storage unit reaches its final data state. For example, when programming a TLC type storage unit, if the final data state of a certain storage unit is S3, then its intermediate data states can be at least one of S1 and S2; or other verifiable data states. The final data state is the data state that the user expects the programmed storage unit to be programmed into. For example, in the aforementioned programming of a TLC type storage unit, the final data state is S3.

[0055] It should be understood that during the programming of memory cells, in order to determine whether the programmed memory cell has been programmed to the target data state, a verification operation is added between the application of two programming voltage pulses (the process of applying programming voltage pulses is also called the programming operation) to determine whether the programmed memory cell has been programmed to the target data state. That is, the programming operation and the verification operation are performed alternately. The verification operation can be one or a group of verification voltage pulses, such as... Figure 8 As shown, Figure 8 In the diagram, 1001 and 1003 represent the step programming pulses V. pgm 1002 represents the verification voltage pulse. Based on the foregoing description, the multi-pass programming can include at least one coarse programming pass and one fine programming pass, with each pass including at least one programming operation and at least one verification operation.

[0056] However, research has found that the multi-pass programming method, which alternates between programming and verification operations, results in more verification operations, which slows down the programming process. In other words, in order to improve the reliability of programming, verification operations are performed after each programming operation. This leads to some unnecessary verification operations that increase the programming time (tPROG) and slow down the programming speed.

[0057] To solve the above technical problems, such as Figure 9 As shown, an embodiment of the present invention provides a memory device 501, comprising: a memory array 300 having a plurality of memory blocks, wherein each memory block is arranged to include a plurality of memory sub-blocks; each memory sub-block includes at least one memory cell; and a control circuit 5011 coupled to the memory array; wherein,

[0058] The control circuit 5011 is configured to: determine a verification loop count for performing a verification operation on the storage cells in the first sub-block of the first storage block to the target programming data state during a non-last programming pass when performing multiple programming passes on the first storage block of the plurality of storage blocks;

[0059] When the storage cells in other storage sub-blocks of the first storage block are programmed to the target programming data state using the same programming and verification conditions as those used for the first storage sub-block, at least no verification operation corresponding to the last time in the verification loop count is performed in the non-last pass programming of the storage cells in the other storage sub-blocks.

[0060] Wherein, the first storage block is any one of the plurality of storage blocks; the first storage sub-block is any one of the first storage blocks; and the other storage sub-blocks are storage sub-blocks in the first storage block other than the first storage sub-block.

[0061] It should be noted that the aforementioned appendix Figures 1 to 5 The described memory device is merely illustrative of the relationships between memory cell strings, memory blocks, memory sub-blocks, and word lines in a memory device, and is not intended to limit the invention. In other words, the memory device described in this embodiment may be an appendix. Figures 1 to 5 The structure described can also be other implementations of the structure.

[0062] Here, based on the foregoing description, the memory cells in each sub-block of the memory device are coupled to multiple word lines; memory cells in adjacent sub-blocks are coupled to each other via word lines. Based on this, the programming operation can be applying a programming voltage (or, referred to as a programming pulse) to a selected word line among the multiple word lines; the verification operation can be applying a verification voltage to the selected word line. In other embodiments, any one of the multiple programming passes may include at least one programming loop, and in some programming loops of the at least one programming loop, the verification voltage and the programming voltage / pulse are alternately applied to the selected word line; that is, typically one programming loop includes one programming operation and one verification operation. Based on the embodiments of the present invention, some verification operations can be skipped; therefore, only in some programming loops are the verification voltage and the programming voltage / pulse alternately applied to the selected word line.

[0063] It should be understood that the term "multiple programming passes" here can refer to two, three, four, or so on. The term "non-last programming pass" can refer to any rough programming pass performed before fine programming; that is, the non-last programming pass can refer to any rough programming pass within at least one rough programming pass.

[0064] Based on this, when the aforementioned multi-pass programming is two-pass programming, namely including one coarse programming and one fine programming, the non-last pass programming is the coarse programming. In this case, the verification loop count for determining whether to program the storage cells in the first storage sub-block to the target programming data state and perform verification operations during the non-last pass programming is the same as the verification loop count for determining whether to program the storage cells in the first storage sub-block to the target programming data state and perform verification operations during the coarse programming. When the aforementioned multi-pass programming includes multiple coarse programming passes, the non-last programming pass can be any one of the multiple coarse programming passes. In this case, the verification loop count for determining whether to program the storage cells in the first storage sub-block to the target programming data state and perform verification operations during the non-last pass programming can refer to the verification loop count for determining whether to program the storage cells in the first storage sub-block to the target programming data state and perform verification operations during a certain coarse programming pass among the multiple coarse programming passes.

[0065] It is understood that when the multi-pass programming includes multiple coarse programming passes, for each coarse programming pass, the verification loop count corresponding to the verification operation performed on the storage cell in the first storage sub-block to program the target programming data state can be determined.

[0066] For example, assuming the multi-pass programming includes two coarse-pass programming and one fine-pass programming, then the non-last pass programming can be either of the two coarse-pass programming. For instance, if the two coarse-pass programming are defined as the first coarse-pass programming and the second coarse-pass programming, the non-last pass programming can be either the first coarse-pass programming or the second coarse-pass programming. In this case, the verification cycle count for programming the storage cells in the first storage sub-block to the target programming data state during the first coarse-pass programming can be determined only; the verification cycle count for programming the storage cells in the first storage sub-block to the target programming data state during the first coarse-pass programming and the second coarse-pass programming can also be determined only; and the verification cycle count for programming the storage cells in the first storage sub-block to the target programming data state during the second coarse-pass programming can also be determined only. It should be understood that the verification loop count of the determined verification operation is only valuable when the non-last pass of programming performed on other storage sub-blocks corresponds to the non-last pass of programming performed on the storage cells in the first storage sub-block. For example, suppose the multi-pass programming performed on the first storage sub-block is a three-pass programming, and the determined verification loop count is the verification operation when the second coarse programming is performed on the first storage sub-block. Then, the multi-pass programming performed on the storage cells in other storage sub-blocks with the same three-pass programming can only refer to the determined verification loop count of the verification operation when the second coarse programming is performed on the first storage sub-block during the second coarse programming. This is to at least reduce the last verification operation in the verification loop count, thereby saving programming time.

[0067] It should also be noted that the terms "first" and "second" in the description of the first storage block, first storage sub-block, target programming data state, first storage unit, first loop count, and verification loop count in this technical solution are for ease of description only and are not intended to limit the present invention. Similarly, the second storage unit described below can also be understood in this way.

[0068] Based on the preceding description of storage unit types, the target programming data state described here may include one or more.

[0069] In some embodiments, when the target programming data state includes one, it is only necessary to determine the verification cycle count required to perform the verification operation to program the storage cells in the first storage sub-block to the target programming data state.

[0070] In practical applications, the target programming data state can also be any verifiable programming data state in coarse programming. For example, the target programming data state can be any programming data state in the aforementioned SLC, MLC, TLC, and QLC except for the erase data state.

[0071] In some embodiments, when the target programming data states include multiple states, the control circuit is further configured to: determine the verification cycle count corresponding to the verification operation performed when the storage cells in the first storage sub-block are programmed to each of the target programming data states during the non-last pass programming.

[0072] It should be noted that, at this time, the target programming data state can also be any of the multiple verifiable programming data states in the coarse programming. For example, the target data programming state can include multiple programming data states in the aforementioned MLC, TLC, and QLC, excluding the erase data state. In this case, during the non-final programming operation, the verification cycle count corresponding to the verification operation required to program the memory cells in the first storage sub-block to each programming data state can be determined separately.

[0073] For example, when the target data programming state includes two states, such as L1 and L2 in the aforementioned QLC, during the non-final programming pass, it is necessary to determine the verification loop count 1 corresponding to the verification operation required to program the storage cells in the first storage sub-block to L1; it is also necessary to determine the verification loop count 2 corresponding to the verification operation required to program the storage cells in the first storage sub-block to L2. It should be understood that the storage cells in the first storage sub-block programmed to L1 are different from the storage cells in the storage sub-block programmed to L2. Which cells need to be programmed to L1 and which need to be programmed to L2 are determined according to the aforementioned host instructions.

[0074] After programming the first storage sub-block, when programming other storage sub-blocks within the same first storage block using the same programming and verification conditions as the first storage sub-block, the storage cells in these other storage sub-blocks are programmed to the target programming data state. During the non-last pass programming of the storage cells in these other storage sub-blocks, at least the verification operation corresponding to the last time in the verification cycle count is not performed. That is, the storage cells in these other storage sub-blocks can be programmed using the same programming and verification conditions as the first storage sub-block. Furthermore, when programming the storage cells in these other storage sub-blocks to the target programming data state, during the non-last pass programming of these storage cells, at least the verification operation corresponding to the last time in the verification cycle count is not performed. In other words, when programming with the same programming and verification conditions as the first storage sub-block, during the corresponding non-last programming period, the verification operation required to program the storage cells in these other storage sub-blocks to the target programming data state can at least omit the last time in the aforementioned verification cycle count.

[0075] For example, if the target programming data state contains one instance and the determined verification loop count is 5, then under the same programming and verification conditions, programming storage cells in other storage sub-blocks to the target programming data state only requires performing the first 4 verification operations, omitting the last verification operation, thus saving programming time. If the target programming data state contains two instances, such as L1 and L2, and the determined verification loop count 1 is 6 and the determined verification loop count 2 is 7, then under the same programming and verification conditions, programming storage cells in any sub-block of other storage sub-blocks to L1 only requires performing the first 5 verification operations, omitting the last verification operation; similarly, programming storage cells in any sub-block of other storage sub-blocks to L2 only requires performing the first 6 verification operations, omitting the last verification operation.

[0076] Based on the foregoing description, the above technical solution can be understood as follows: When performing multiple programming passes on a memory block in a memory device, firstly, determine the verification loop count that needs to be performed when programming the memory cells in a memory sub-block to the target programming data state during a non-last programming pass on a memory sub-block; then, when programming the memory cells in other memory sub-blocks of the memory block to the same target programming data state using the same programming and verification conditions, the non-last programming pass on the memory cells in other memory sub-blocks can at least skip the verification operation corresponding to the last one in the verification loop count. That is, when programming the memory cells in other memory sub-blocks to the same target programming data state using the same programming and verification conditions, the non-last programming pass on the memory cells in other memory sub-blocks can at least skip the last programming operation to save tPROG. As for the guarantee of RWM, it can be considered in the final fine programming. It should be understood that the situation described here, where multiple programming passes performed on the first sub-block, is the same as multiple programming passes performed on other sub-blocks within the same memory block. In other words, if multiple programming passes performed on the first sub-block is two programming passes, then multiple programming passes performed on other sub-blocks within the same memory block are also two programming passes. That is, the so-called identical programming / programming conditions can refer to performing the same multiple programming passes on memory cells in any sub-block of a memory block, including cases where the initial programming voltage / pulse, step size, verification voltage, verification operation, etc., vary relatively little. It should be noted that in some descriptions, the memory sub-block is also described as a string. For example, suppose a memory block of a memory device has 6 memory sub-blocks, which means it contains 6 strings, namely String0, String1, String2, String3, String4, and String5.

[0077] Those skilled in the art should know that when programming a memory cell in a memory sub-block to a certain target programming data state, some memory cells may have their threshold voltage fall within the threshold voltage distribution corresponding to the target programming data state after one programming operation and one verification operation; other memory cells may require multiple programming and verification operations. Therefore, the verification cycle count mentioned here can refer to the number of verification operations required to be performed on the memory cell in the first memory sub-block that is last programmed to the target programming data state.

[0078] In some embodiments, after determining the verification loop count for performing verification operations on each target programming data state by programming the storage cells in the first storage sub-block, in some embodiments, the control circuit is further configured to: configure the number of verification operations that the storage cells in the other storage sub-blocks need to perform in the non-last pass of programming according to the determined verification loop count corresponding to each target data programming state.

[0079] In some embodiments, and in other embodiments, the control circuitry includes an external interface through which the number of verification operations to be performed on the storage cells in the other storage sub-blocks during the non-last pass programming is configured.

[0080] It should be noted that the external interface mentioned above may refer to the aforementioned Figure 5 Signal lines 504 and 503 are used to receive from the host the number of verification operations required by the user for other storage sub-blocks in the non-last programming. This number of verification operations can be obtained based on the aforementioned determined verification cycle count.

[0081] In some embodiments, when the verification strategy in the multi-pass programming employs predictive failure bit count (FBC) verification, the predictive FBC verification means that during the programming process of a certain storage block, when a preset proportion of storage cells in the certain storage block have been programmed to the target programming data state, the remaining storage cells in the certain storage block that have not been programmed to the target programming data state only need to undergo one more programming operation without performing a verification operation; the control circuit is further configured to: when performing multi-pass programming on the first storage block, determine the programming cycle count for programming the storage cells in the first storage sub-block to the target programming data state during the non-last programming pass;

[0082] When the storage cells in other storage sub-blocks of the first storage block are programmed to the target programming data state using the same programming and verification conditions as those used for the first storage sub-block, at least no programming operation corresponding to the last time in the programming cycle count is performed in the non-last pass programming of the storage cells in the other storage sub-blocks.

[0083] In some embodiments, the specific process of the predictive FBC verification strategy may include: when performing multiple programming passes on a certain storage sub-block, regardless of whether it is the coarse programming stage or the fine programming stage, after several alternating programming and verification operations, a certain proportion of the storage cells in the storage sub-block have been programmed to the target programming data state, leaving only a portion of storage cells that have not been programmed to the target programming data state, but whose intermediate data state is close to the target programming data state. At this point, only one more programming operation needs to be performed on this portion of storage cells, which will inevitably program this portion of storage cells to the target programming data state. Therefore, at this time, no further verification operation is needed. It should be noted that the preset proportion can be designed according to the actual memory device; for example, the preset proportion can be 90%, etc.

[0084] For example, such as Figure 10 As shown, in a coarse programming operation performed on a memory cell coupled to word line WL10 in a memory sub-block of a QLC type NAND flash memory device, the verification strategy adopts predictive FBC verification. In this coarse programming, after 5 alternating programming and verification operations, a certain proportion (e.g., 90%) of the memory cells coupled to word line WL10 have been programmed to the target programming data state. Only 10% of the memory cells have not been programmed to the target programming data state, but the intermediate programming data state of these 10% of memory cells is close to the target programming data state. At this point, only one programming operation needs to be performed on these 10% of memory cells, that is, the 6th programming operation, which will definitely program these 10% of memory cells to the target programming data state. This is predictable, so no further verification operation is needed.

[0085] As described above, when using predictive FBC verification, one verification operation has already been omitted. Furthermore, when using the memory device provided in this embodiment of the invention, and employing predictive FBC verification as the verification strategy in multi-pass programming, within the same memory block, it is only necessary to determine the verification loop count for programming the memory cells in one sub-block to the target programming data state. When programming memory cells in other memory sub-blocks, the last verification in the verification loop count can be omitted, that is, programming time is further reduced.

[0086] The study also found that when predictive FBC verification is used as the verification strategy in multi-pass programming, during the non-last pass of multi-pass programming, if the verification passes, that is, when the memory cell coupled to a word line is programmed to a certain programming data state, most of the memory cells have been programmed to that programming data state, and only a small portion of memory cells remain unprogrammed. At this time, whether the last programming operation is performed on this small portion of memory cells or not, the threshold voltage distribution of these memory cells coupled to the word line is very similar. Therefore, in this case, when performing multi-pass programming on the first memory block, the programming cycle count for programming the memory cells in the first memory sub-block to the target programming data state during the non-last pass of programming can also be determined. Subsequently, when the memory cells in other memory sub-blocks in the first memory block are programmed to the target programming data state using the same programming and verification conditions as the first memory sub-block, at least the programming operation corresponding to the last programming cycle count is not performed in the non-last pass of programming of the memory cells in the other memory sub-blocks.

[0087] In other words, when the verification strategy in multi-pass programming adopts predictive FBC verification, in the same storage block, it is only necessary to determine the programming cycle count of the programming operations required to program the storage cell in one sub-block to the target programming data state. When programming the storage cell in other storage sub-blocks, the last programming operation in the programming cycle count can be omitted.

[0088] Based on the foregoing description, when programming a memory block, during non-final programming passes, and when performing multiple programming passes on a memory block, based on the verification cycle count and programming cycle count of a certain memory sub-block, at least one verification operation can be skipped when programming other memory sub-blocks within that memory block. When using a predictive FBC verification scheme, one programming operation can also be skipped. This significantly saves tPROG. For RBM, this can be guaranteed during the fine programming phase. This not only speeds up programming but also ensures a wider RBM, guaranteeing programming reliability.

[0089] For example, consider a memory block in a memory device. This block has four sub-blocks (Strings), named String0, String1, String2, and String3. Each sub-block contains 128 word lines. The block contains four pages, and the storage units are of type QLC (Quick Logic Cell). For each QLC storage unit, a multi-pass programming approach is used, including coarse and fine programming phases. In the coarse programming phase, the verification strategy used is a predictive FCB (Fulfilled Common Block) verification strategy. In this case, such as... Figure 11As shown, this illustrates the verification information required for each programming data state of the storage unit in String0 coupled to word line WL10 during the coarse programming stage. After adopting the programming method provided in this embodiment, the verification information required for programming each programming data state of the storage unit in String0 coupled to word line WL10 is determined. Then, the verification information required for programming each programming data state of the storage units in String1, String2, and String3 coupled to word line WL10 can be obtained as follows: Figure 12 As shown. In Figure 12 In this context, X represents a validation operation that can be skipped (not performed). This approach saves programming time.

[0090] This invention provides a memory device that, when performing multiple programming passes on a memory block, determines the number of verification operations required to program a memory cell in a sub-block of the memory block to a target programming data state during non-last programming passes. Then, when performing the same multiple programming passes on other sub-blocks of the memory block using the same programming and verification conditions, the number of verification operations for some memory cells in other sub-blocks is reduced during non-last programming passes based on the determined number of verification operations. In this way, while ensuring read window margin, the programming time required can be reduced, thereby improving the programming (write) speed of the memory device.

[0091] The same inventive concept as described above, such as Figure 13 As shown, this embodiment of the invention also provides a method for programming a memory device 501, the memory device 501 including a memory array having a plurality of memory blocks, wherein each of the memory blocks is arranged to include a memory array comprising a plurality of memory sub-blocks; each memory sub-block includes at least one memory cell; and control circuitry coupled to the memory array; the method includes:

[0092] S131: Determine the verification loop count for performing verification operations during non-last programming passes when multiple programming passes are performed on the first storage block of the plurality of storage blocks, and programming the storage cells in the first sub-block of the first storage block to the target programming data state during the non-last programming pass;

[0093] S132: When programming the storage cells in other storage sub-blocks of the first storage block to the target programming data state using the same programming and verification conditions as for the first storage sub-block, at least no verification operation corresponding to the last time in the verification loop count is performed in the non-last pass programming of the storage cells in the other storage sub-blocks.

[0094] Wherein, the first storage block is any one of the plurality of storage blocks; the first storage sub-block is any one of the first storage blocks; and the other storage sub-blocks are storage sub-blocks in the first storage block other than the first storage sub-block.

[0095] It should be noted that the execution entity of the method can refer to the control circuit. Based on this, S131 means: when the control circuit performs multiple programming passes on the first memory block, it determines the verification loop count for programming the memory cells in the first memory sub-block to the target programming data state and performing verification operations during non-last programming passes. S132 means: when the control circuit programs the memory cells in other memory sub-blocks of the first memory block to the target programming data state using the same programming and verification conditions as for the first memory sub-block, at least during the non-last programming passes of the memory cells in the other memory sub-blocks, the verification operation corresponding to the last time in the verification loop count is not performed.

[0096] In some embodiments, the target programming data state includes one or more.

[0097] In some embodiments, when the target programming data states include multiple states, the programming operation method further includes: determining the verification cycle count corresponding to the verification operation performed when the storage cells in the first storage sub-block are programmed to each of the target programming data states during the non-last pass programming.

[0098] In some embodiments, the programming verification method further includes:

[0099] Configure the number of verification operations that the storage units in the other storage sub-blocks need to perform in the non-last pass of programming according to the verification loop count corresponding to each target data programming state.

[0100] In some embodiments, when the verification strategy in the multiple programming passes is Predicted Failure Bit Count (FBC) verification, the FBC verification means that during the programming process of a certain memory block, when a preset proportion of memory cells in the certain memory block have been programmed to the target programming data state, the remaining memory cells in the certain memory block that have not been programmed to the target programming data state only need to undergo one more programming operation without performing a verification operation; the programming operation method further includes:

[0101] When performing multiple programming passes on the first storage block, determine the programming cycle count for programming the storage cells in the first storage sub-block to the target programming data state during the non-last programming pass;

[0102] When the storage cells in other storage sub-blocks of the first storage block are programmed to the target programming data state using the same programming and verification conditions as those used for the first storage sub-block, at least no programming operation corresponding to the last time in the programming cycle count is performed in the non-last pass programming of the storage cells in the other storage sub-blocks.

[0103] In some embodiments, the memory cells in each memory subblock are coupled to multiple word lines; the memory cells of adjacent memory subblocks are coupled to each other via word lines; the programming operation is to apply a programming voltage / pulse to a selected word line among the multiple word lines; the verification operation is to apply a verification voltage to the selected word line; in the partial programming loop of the multi-pass programming, the verification voltage and the programming voltage / pulse are alternately applied to the selected word line.

[0104] In some embodiments, in each of the multiple programming passes, the programming voltage / pulse applied in the programming operation increases according to different set step sizes.

[0105] In some embodiments, the memory array is a three-dimensional NAND memory array.

[0106] It should be noted that this method and the aforementioned memory device belong to the same inventive concept. The terms appearing in this method have been explained in detail in the aforementioned memory device, and they also apply here, so they will not be repeated here.

[0107] Based on the same inventive concept as described above, such as Figure 14 As shown, this embodiment of the invention also provides a memory system 50, including a memory device 501. The memory device 501 includes: a memory array having a plurality of memory blocks, wherein each memory block is arranged to include a plurality of memory sub-blocks; each memory sub-block includes at least one memory cell; and control circuitry coupled to the memory array; wherein the control circuitry is configured to: determine a verification loop count for performing a verification operation on a memory cell in a first memory sub-block of the first memory block to a target programming data state during a non-last programming pass when performing multiple programming passes on a first memory block of the plurality of memory blocks; when programming memory cells in other memory sub-blocks of the first memory block to the target programming data state using the same programming and verification conditions as for the first memory sub-block, at least no verification operation corresponding to the last time in the verification loop count is performed during the non-last programming pass of memory cells in the other memory sub-blocks; wherein the first memory block is any one of the plurality of memory blocks; the first memory sub-block is any one of the first memory blocks; and the other memory sub-blocks are memory sub-blocks of the first memory block other than the first memory sub-block.

[0108] as well as,

[0109] A controller 502 is coupled to the memory device and is configured to control the memory device.

[0110] It should be noted that the memory system 50 can be related to the aforementioned Figure 5 The host communication is described. The host and / or the memory system 50 can be included in various products, such as Internet of Things (IoT) devices, like refrigerators or other devices, sensors, motors, mobile communication devices, automobiles, autonomous vehicles, etc., to support the product's processing, communication, or control. In one embodiment, the memory system 50 can be a discrete memory or memory component of the host device. In other embodiments, the memory system 50 can also be part of an integrated circuit, such as a system-on-a-chip (SOC). In this case, the memory system 50 is stacked or otherwise assembled with one or more components of the host. In other embodiments, the aforementioned memory system can be implemented and packaged in products such as memory cards, drives, etc., as shown in Figures 15(A) and 15(B), where Figure 15(A) shows a schematic diagram of an exemplary memory card with a memory system according to some aspects of the present invention; Figure 15(B) shows a schematic diagram of an exemplary solid-state drive (SSD) with a memory system according to some aspects of the present invention. In one example shown in Figure 15(A), the memory system controller 502 and a single memory device 501 can be integrated into a memory card 150. The memory card 150 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 150 may also include a connector for connecting the memory card 150 to a host computer (e.g., Figure 5 A memory card connector 1501 is coupled to a host (e.g., in a memory controller). In another example shown in FIG15(B), a memory controller 502 and multiple memory devices 501 may be integrated into an SSD 151. The SSD 151 may also include a connector for coupling the SSD 151 to a host (e.g., in a memory controller). Figure 5 The SSD connector 1511 is coupled to the host in the memory card 150. In some embodiments, the storage capacity and / or operating speed of the SSD 151 is greater than that of the memory card 150.

[0111] In some embodiments, the host may include a processor and host RAM, wherein the host RAM may include DRAM, SDRAM, or any other suitable volatile or non-volatile memory device. The memory system 50 may be provided with one or more communication interfaces for communicating with one or more components of the host. The one or more components of the host may be a Serial Advanced Technology Attachment (SATA) interface, a High-Speed ​​Peripheral Component Interconnect (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Memory (UFS) interface, or eMMC. TM Interfaces, etc. The host may also include electronic components, a memory card reader, or one or more other electronic components external to the memory system 50.

[0112] In some embodiments, the controller 502 may receive instructions from the host to communicate with the memory device 501, such as the controller 502 transferring data to one or more memory cells, planes, sub-blocks, blocks, or pages in the memory device 501 by executing write or erase instructions; or the controller 502 transferring data to the host by executing read instructions. In hardware, the controller 502 may include one or more controller units, circuits, or components configured to control access across the memory device 501 and provide a translation layer between the host and the memory system 50. The controller 502 may also include one or more input / output (I / O) circuits, lines, or interfaces to transfer data to or from the memory device 501. The controller 502 may also include a memory management unit and an array control unit.

[0113] The memory management unit may include circuit hardware or firmware, such as multiple components or integrated circuits associated with various memory management functions. Taking NAND memory as an example, it represents memory system operation or management functions. Those skilled in the art will understand that other forms of non-volatile memory may have similar memory operation or management functions. Specifically, the management functions of NAND memory may include wear leveling, such as garbage collection or recycling, error detection or correction, block retirement, or one or more other memory management functions. The memory management unit may process instructions from the host into commands recognizable by the memory system 50, for example, parsing or formatting instructions received from the host into commands related to the operation of the memory device 501; or the memory management unit may also generate device commands for the array control unit or one or more other components of the memory system 50, such as commands to implement various memory management functions.

[0114] The memory management unit may be configured to include a set of management tables for maintaining various information associated with one or more components of the memory system 50, such as various information associated with the memory array coupled to the controller 502, or one or more memory cells. For example, the management tables may include information such as block age, block erase count, error history, or one or more error counts for one or more blocks of memory cells coupled to the controller 502. Error counts may include operation error counts, read bit error counts, etc. In some embodiments, bit errors are considered uncorrectable bit errors if the detected error count exceeds a certain threshold. In some embodiments, the management tables may maintain counts of correctable or uncorrectable bit errors. The management tables may also include one or more L2P tables containing one or more L2P pointers that associate logical addresses with physical addresses at the memory device 501. In some embodiments, the management tables may include unencrypted L2P tables and / or encrypted L2P tables. Unencrypted L2P tables may include L2P pointers indicating unencrypted logical addresses and unencrypted physical addresses; encrypted L2P tables may contain encrypted L2P pointers indicating encrypted physical addresses and unencrypted logical addresses. In practical applications, the management table can be displayed at the memory management unit, that is, the management table can be stored in the RAM of the controller 502. In other embodiments, the management table can also be stored in the memory device 501. In use, the memory management unit can read part or all of the cached management table from the RAM of the controller 502; it can also read the management table from the memory device 501.

[0115] The array control unit may include circuitry or components configured to control the following related memory operations: writing data to one or more memory cells coupled to the memory system 50 of the controller 502, reading data from the one or more memory cells, or erasing the one or more memory cells. The array control unit may receive commands sent by the host or host commands generated internally by the memory management unit; these host commands may be related to wear leveling, error detection, or correction.

[0116] The array control unit may also include an error correction code (ECC) component, which may contain an ECC engine or other circuitry for detecting or correcting errors associated with writing or reading data from one or more memory cells coupled to the memory system 50 of the controller 502. The controller 502 is configured to effectively detect and recover from various operational or data storage-related error events, such as bit errors, operational errors, etc., while maintaining the integrity of data transferred between the host and the memory system 50, or maintaining the integrity of stored data, for example, by using redundant RAID storage. Failed memory resources, such as memory cells, memory arrays, pages, blocks, etc., may be removed or decommissioned to prevent future errors.

[0117] In the aforementioned memory system, in some embodiments, when the target programming data states include multiple states, the control circuit is further configured to: determine the verification cycle count corresponding to the verification operation performed when the memory cells in the first memory sub-block are programmed to each of the target programming data states during the non-last pass programming.

[0118] In some embodiments, the control circuit is further configured to configure the number of verification operations that the storage cells in the other storage sub-blocks need to perform in the non-last pass of programming, according to the determined verification cycle count corresponding to each target data programming state.

[0119] In some embodiments, when the verification strategy in the multiple programming passes is Predicted Failure Bit Count (FBC) verification, the FBC verification means that during the programming process of a certain memory block, when a preset proportion of memory cells in the certain memory block have been programmed to the target programming data state, only one programming operation needs to be performed on the remaining memory cells in the certain memory block that have not been programmed to the target programming data state, without performing a verification operation again; the control circuit is further configured to:

[0120] When performing multiple programming passes on the first storage block, determine the programming cycle count for programming the storage cells in the first storage sub-block to the target programming data state during the non-last programming pass;

[0121] When the storage cells in other storage sub-blocks of the first storage block are programmed to the target programming data state using the same programming and verification conditions as those used for the first storage sub-block, at least no programming operation corresponding to the last time in the programming cycle count is performed in the non-last pass programming of the storage cells in the other storage sub-blocks.

[0122] In some embodiments, the memory cells in each memory subblock are coupled to multiple word lines; the memory cells of adjacent memory subblocks are coupled to each other via word lines; the programming operation is to apply a programming voltage / pulse to a selected word line among the multiple word lines; the verification operation is to apply a verification voltage to the selected word line; in the partial programming loop of the multi-pass programming, the verification voltage and the programming voltage / pulse are alternately applied to the memory cells of the selected word line.

[0123] In some embodiments, in each of the multiple programming passes, the programming voltage / pulse applied in the programming operation increases according to different set step sizes.

[0124] In some embodiments, the memory array is a three-dimensional NAND memory array; the memory system is a three-dimensional NAND memory system.

[0125] It should be noted that the memory system includes the aforementioned memory device, and therefore, the two have the same technical features. The terms appearing in the memory system have been explained in detail in the aforementioned memory device, and are equally applicable here, and will not be repeated here.

[0126] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as those that may be used by one of ordinary skill in the art upon reading the above description. It should be understood that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be combined together to simplify the invention. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the disclosure may lie in fewer than all features of a particular disclosed embodiment. Therefore, the appended claims are thus incorporated into the detailed description, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or substitutions. The scope of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A memory device, characterized in that, It comprises: a memory array having multiple memory blocks, wherein each memory block is arranged to include multiple memory sub-blocks; each memory sub-block includes at least one memory cell; and control circuitry coupled to the memory array; wherein, The control circuit is configured to: when performing multiple programming passes on the first storage block among the plurality of storage blocks, during non-last programming passes, perform programming operations and verification operations on the storage cells in the first storage sub-block of the first storage block to program to the target programming data state, and count the number of verification operations required to successfully complete programming to the target programming data state, which is recorded as the verification loop count; When the storage cells in other storage sub-blocks of the first storage block are successfully programmed to the target programming data state using the same programming and verification conditions as those used for the first storage sub-block, at least no verification operation corresponding to the last time in the verification loop count is performed in the non-last pass programming of the storage cells in the other storage sub-blocks. Wherein, the first storage block is any one of the plurality of storage blocks; the first storage sub-block is any one of the first storage blocks; and the other storage sub-blocks are storage sub-blocks in the first storage block other than the first storage sub-block.

2. The memory device according to claim 1, characterized in that, The target programming data state includes one or more.

3. The memory device according to claim 2, characterized in that, When there are multiple target programming data states, the control circuit is further configured to: count the verification loop count corresponding to the verification operation performed when the storage cells in the first storage sub-block are successfully programmed to each of the target programming data states during the non-last programming pass.

4. The memory device according to claim 3, characterized in that, The control circuit is also configured to: configure the number of verification operations that the storage units in the other storage sub-blocks need to perform in the non-last pass of programming according to the statistical verification loop count corresponding to each target data programming state.

5. The memory device according to claim 1, characterized in that, When the verification strategy in the multi-pass programming is Predicted Failure Bit Count (FBC) verification, the FBC verification means that during the programming process of a certain memory block, when a preset proportion of memory cells in the memory block have been programmed to the target programming data state, the remaining memory cells in the memory block that have not been programmed to the target programming data state only need to undergo one more programming operation without performing a verification operation; the control circuit is also configured to: When performing multiple programming passes on the first storage block, the number of programming operations required to successfully program the storage cells in the first storage sub-block to the target programming data state during the non-last programming pass is counted and recorded as the programming loop count; When the storage cells in other storage sub-blocks of the first storage block are successfully programmed to the target programming data state using the same programming and verification conditions as those used for the first storage sub-block, at least no programming operation corresponding to the last time in the programming cycle count is performed in the non-last pass programming of the storage cells in the other storage sub-blocks.

6. The memory device according to any one of claims 1 to 5, characterized in that, The memory array is a three-dimensional NAND memory array.

7. A method for programming a memory device, characterized in that, The memory device includes a memory array having multiple memory blocks, wherein each memory block is arranged to include multiple memory sub-blocks; each memory sub-block includes at least one memory cell; the programming operation method includes: When performing multiple programming passes on the first storage block among the plurality of storage blocks, during non-last programming passes, operation verification and verification parameters are performed on the storage cells in the first storage sub-block of the first storage block to program to the target programming data state, and the number of verification operations required to successfully complete programming to the target programming data state is counted and recorded as the verification loop count. When the storage cells in other storage sub-blocks of the first storage block are successfully programmed to the target programming data state using the same programming and verification conditions as those used for the first storage sub-block, at least no verification operation corresponding to the last time in the verification loop count is performed in the non-last pass programming of the storage cells in the other storage sub-blocks. Wherein, the first storage block is any one of the plurality of storage blocks; the first storage sub-block is any one of the first storage blocks; and the other storage sub-blocks are storage sub-blocks in the first storage block other than the first storage sub-block.

8. The programming operation method according to claim 7, characterized in that, The target programming data state includes one or more.

9. The programming operation method according to claim 8, characterized in that, When there are multiple target programming data states, the programming operation method further includes: determining the verification loop count corresponding to the verification operation performed when the storage cell in the first storage sub-block is successfully programmed to each of the target programming data states during the non-last programming pass.

10. The programming operation method according to claim 9, characterized in that, The programming verification method further includes: Configure the number of verification operations that the storage units in the other storage sub-blocks need to perform in the non-last pass of programming according to the verification loop count corresponding to each target data programming state.

11. The programming operation method according to claim 7, characterized in that, When the verification strategy in the multi-pass programming is Predicted Failure Bit Count (FBC) verification, the FBC verification means that during the programming process of a certain memory block, when a preset proportion of memory cells in the memory block have been programmed to the target programming data state, the remaining memory cells in the memory block that have not been programmed to the target programming data state only need to undergo one more programming operation without performing a verification operation; the programming operation method further includes: When performing multiple programming passes on the first storage block, the number of programming operations required to successfully program the storage cells in the first storage sub-block to the target programming data state during the non-last programming pass is counted and recorded as the programming loop count; When the storage cells in other storage sub-blocks of the first storage block are successfully programmed to the target programming data state using the same programming and verification conditions as those used for the first storage sub-block, at least no programming operation corresponding to the last time in the programming cycle count is performed in the non-last pass programming of the storage cells in the other storage sub-blocks.

12. A memory system, characterized in that, A memory device includes: a memory array having a plurality of memory blocks, wherein each memory block is arranged to include a plurality of memory sub-blocks; each memory sub-block includes at least one memory cell; and control circuitry coupled to the memory array; wherein the control circuitry is configured to: when performing multiple programming passes on a first memory block of the plurality of memory blocks, during non-final programming passes, perform programming and verification operations on memory cells in a first memory sub-block of the first memory block to program to a target programming data state, and count the number of verification operations required to successfully program to the target programming data state, denoted as a verification loop count; when memory cells in other memory sub-blocks of the first memory block are successfully programmed to the target programming data state using the same programming and verification conditions as those for the first memory sub-block, during the non-final programming passes of memory cells in the other memory sub-blocks, at least no verification operation corresponding to the last time in the verification loop count is performed; wherein the first memory block is any one of the plurality of memory blocks; the first memory sub-block is any one of the first memory blocks; and the other memory sub-blocks are memory sub-blocks of the first memory block other than the first memory sub-block; as well as, A memory controller is coupled to the memory device and is configured to control the memory device.

13. The memory system according to claim 12, characterized in that, When the target programming data state includes multiple states, the control circuit is further configured to: count the verification loop count corresponding to the verification operation performed when the storage cells in the first storage sub-block are successfully programmed to each of the non-last programming passes.

14. The memory system according to claim 13, characterized in that, The control circuit is also configured to: configure the number of verification operations that the storage units in the other storage sub-blocks need to perform in the non-last pass of programming according to the statistical verification loop count corresponding to each target data programming state.

15. The memory system according to claim 14, characterized in that, When the verification strategy in the multi-pass programming is Predicted Failure Bit Count (FBC) verification, the FBC verification means that during the programming process of a certain memory block, when a preset proportion of memory cells in the memory block have been programmed to the target programming data state, the remaining memory cells in the memory block that have not been programmed to the target programming data state only need to undergo one more programming operation without performing a verification operation; the control circuit is also configured to: When performing multiple programming passes on the first storage block, the programming cycle count is counted for each programming operation performed during the non-last programming pass when the storage cells in the first storage sub-block are successfully programmed to the target programming data state. When the storage cells in other storage sub-blocks of the first storage block are successfully programmed to the target programming data state using the same programming and verification conditions as those used for the first storage sub-block, at least no programming operation corresponding to the last time in the programming cycle count is performed in the non-last pass programming of the storage cells in the other storage sub-blocks.

16. The memory system according to any one of claims 12 to 15, characterized in that, The memory array is a three-dimensional NAND memory array; the memory system is a three-dimensional NAND memory system.

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