Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device includes forming a first dielectric layer over a substrate; forming a metal layer in the first dielectric layer; forming an etch stop layer on a surface of the first dielectric layer and the metal layer; removing portions of the metal layer and the etch stop layer to form a recess in the metal layer; and forming a tungsten plug in the recess. The recess is separated from a bottom surface of the etch stop layer.

Description

Technical Field

[0001] The embodiments disclosed herein relate to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Integrated circuits (ICs) are typically designed to form circuits by incorporating active components, such as transistors, resistors, and capacitors, connected by conductive traces, such as metal wires and polysilicon wires. The active components in ICs are formed using a lithography process, which involves the use of photoresist, a photomask, a specialized light source, and various etchants. Increasingly dense ICs offer numerous advantages in terms of speed, functionality, and cost, but also make design and manufacturing increasingly challenging. Summary of the Invention

[0003] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device includes forming a first dielectric layer over a substrate; forming a metal layer in the first dielectric layer; forming an etch stop layer on the surfaces of the first dielectric layer and the metal layer; removing several portions of the metal layer and the etch stop layer to form a groove in the metal layer, the groove being separated from the bottom surface of the etch stop layer; and forming a tungsten plug in the groove.

[0004] According to another aspect of this disclosure, a method for manufacturing a semiconductor device includes forming a first dielectric layer over a substrate; forming a cobalt plug in the first dielectric layer; forming a nitride-based etch stop layer on the first dielectric layer and the cobalt plug; forming a second dielectric layer over the nitride-based etch stop layer; forming an opening in the second dielectric layer and the nitride-based etch stop layer to expose the upper surface of the cobalt plug; performing an etching operation using a fluorine-containing gas to (1) remove one or more layers of cobalt oxide formed on or below the upper surface of the cobalt plug, and (2) remove several portions of the cobalt plug located below the one or more layers of oxide to extend the opening into the cobalt plug; after extending the opening into the cobalt plug to a desired distance, performing a defluorination process to remove the fluorine-containing gas; forming a groove in the cobalt plug at the bottom of the opening, wherein the groove is separated from the nitride-based etch stop layer; and forming a tungsten plug in the groove and the opening.

[0005] According to another embodiment of this disclosure, a semiconductor device includes a first dielectric layer disposed above a semiconductor device structure and including a metal layer; an etch stop layer disposed above the first dielectric layer; a second dielectric layer disposed above the etch stop layer; a groove in the metal layer and separated from the etch stop layer; and a tungsten plug. Openings are defined in the second dielectric layer, the etch stop layer, and the metal layer, and the tungsten plug is disposed in the openings and the groove, the width of the groove being greater than the width of the opening. Attached Figure Description

[0006] The following detailed description, read in conjunction with the accompanying drawings, will provide the best understanding of the features disclosed herein. It should be emphasized that, in accordance with industry standard practice, many features are not drawn to scale. In fact, the dimensions of each feature can be increased or decreased as needed to clarify the discussion.

[0007] Figure 1A It is a plan view (top view) illustrating one of the multiple stages of a continuous manufacturing process for semiconductor devices;

[0008] Figure 1B It is a drawing along Figure 1A A cross-sectional view taken by line X1-X1;

[0009] Figure 1C and Figure 1D This is an enlarged view illustrating the gate structure;

[0010] Figure 1E A perspective view showing one of the stages in a continuous manufacturing process for a semiconductor device;

[0011] Figure 2A , Figure 2B , Figure 2C , Figure 2D ,and Figure 2E It is a cross-sectional view illustrating multiple stages of the continuous manufacturing process of semiconductor devices;

[0012] Figure 3A , Figure 3B , Figure 3C , Figure 3D ,and Figure 3E It illustrates multiple stages of the continuous manufacturing operation of a semiconductor device in accordance with this disclosure;

[0013] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H ,and Figure 4I It illustrates multiple stages of the continuous manufacturing operation of a semiconductor device in accordance with this disclosure;

[0014] Figure 4J It is drawn in Figures 4A to 4I The structure obtained after processing.

[0015] [Symbol Explanation]

[0016] 5: Fin-like structure

[0017] 10: Metal gate structure

[0018] 12: Gate dielectric layer

[0019] 14: Work Function Adjustment Layer

[0020] 16: Metallic Materials

[0021] 20: Cover with insulation layer

[0022] 30: Sidewall gap wall

[0023] 40: Interlayer dielectric layer

[0024] 45: First interlayer dielectric layer

[0025] 50: Source / Drain Region

[0026] 60: First etch stop layer

[0027] 65: Second interlayer dielectric layer

[0028] 67: Contact hole (opening)

[0029] 68: First contact pad layer, contact pad layer

[0030] 70: Lower contact, source / drain contact

[0031] 75: Second etch stop layer

[0032] 80: Third interlayer dielectric layer

[0033] 82: Contact hole (opening)

[0034] 100:Substrate

[0035] 110: Fin-like structure

[0036] 115: Passage Area

[0037] 120: Insulation layer

[0038] 130: Metal gate structure

[0039] 140: Covering isolation layer

[0040] 150: Sidewall

[0041] 160: Source / Drain Region

[0042] 170: Interlayer dielectric layer

[0043] 302: First Interlayer Dielectric (ILD) Layer

[0044] 303: Metal layer, cobalt metal layer

[0045] 304: Etching Stop Layer

[0046] 306: Second interlayer dielectric (ILD) layer, interlayer dielectric layer

[0047] 307: Adhesive layer

[0048] 311: Opening

[0049] 313: Groove, cobalt groove

[0050] 315: Tungsten plug

[0051] 321: Buffer layer

[0052] 401: Cobalt oxide (Co3O4) layer

[0053] 413: Groove

[0054] 415: Tungsten plug

[0055] 423: Defluorinating agent

[0056] H1: Distance

[0057] H2: Distance

[0058] H3: Distance

[0059] H4: Height, Distance

[0060] H5: Distance

[0061] W1: Width

[0062] W2: Width

[0063] W3: Width

[0064] W4: Width

[0065] X1-X1: Line Detailed Implementation

[0066] The following disclosure provides numerous different embodiments or examples to implement different features of the provided object. Specific examples of components, values, operations, materials, arrangements, or the like are described below to simplify this disclosure. These are, of course, merely examples and not intended to be limiting. For example, in the description, a process forming a first feature over a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in several instances in this disclosure. This repetition is for the purpose of brevity and clarity and does not inherently define the relationship between the various embodiments and / or configurations discussed.

[0067] Furthermore, spatial relational terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar terms may be used herein to concisely describe the relationship between one element or feature as illustrated in the accompanying drawings and another element (or other elements or features). These spatial relational terms, in addition to the directions depicted in the figures, are intended to encompass different orientations of the elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or other directions), and the spatial relational descriptive terms used herein may be interpreted accordingly. Additionally, the term “made of” may mean “comprising” or “consisting of.” In this disclosure, unless otherwise stated, the term “one of A, B, and C” means “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A and B and C), and not an element in A, an element in B, and an element in C.

[0068] Gradually, the increasingly dense integration of integrated circuits with ever-smaller physical dimensions has correspondingly made it challenging to design and manufacture many forms of integrated circuits using existing methods. Integrated circuit manufacturing processes are generally considered to include front-end (FEOL), mid-end (MEOL) (also known as mid-end process (MOL)), and back-end (BEOL) processes. The front-end process is the first part of integrated circuit manufacturing, in which individual active components are patterned on a semiconductor wafer. The mid-end process occurs after the front-end process and includes gate contact formation, source / drain contact formation, and local interconnect formation processes. The back-end process is the final part of integrated circuit manufacturing, in which individual components (transistors, capacitors, resistors, etc.) are interconnected with dielectric windows and conductive traces, such as metal lines.

[0069] In the manufacturing process, conductive patterns are formed in openings within an insulating layer to connect electronic structures beneath the insulating layer. These conductive patterns can be contacts, dielectric windows, or plugs. Due to stress on the conductive patterns, they may be damaged during or after one or more planarization operations, such as chemical mechanical polishing (CMP). In other cases, all or part of the conductive pattern is removed from the openings during or after the planarization operation.

[0070] This disclosure relates to an improved semiconductor device manufacturing process that includes a process for reducing stress between an insulating layer and a conductive pattern, thereby reducing damage to the conductive pattern and improving device performance. According to this disclosure, this process reduces the device's resistance and improves the current switching time in the device, resulting in faster switching times.

[0071] Figure 1A and Figure 1BIt is a stage in the continuous manufacturing process of semiconductor devices. Figure 1A This is a drawing of a plan (top) view. Figure 1B It is a drawing along Figure 1A The cross-sectional view intercepted by line X1-X1.

[0072] Figure 1A and Figure 1B This shows the structure of the semiconductor device after the metal gate structure 10 is formed. Figure 1A and Figure 1B In the fin structure 5, a metal gate structure 10 is formed above a portion of the fin structure, and a covering insulating layer 20 is disposed above the metal gate structure 10. In some embodiments, the thickness of the metal gate structure 10 is 15 nm to 50 nm. In some embodiments, the thickness of the covering insulating layer 20 is about 10 nm to about 30 nm, while in other embodiments, the thickness of the covering insulating layer 20 is about 15 nm to about 20 nm. Sidewall spacers 30 are provided on the sidewalls of the metal gate structure 10 and the covering insulating layer 20. In some embodiments, the film thickness of the sidewall spacers 30 at the bottom of the sidewall spacers 30 is about 3 nm to about 15 nm, while in other embodiments it is about 4 nm to about 8 nm. The combination of the metal gate structure 10, the covering insulating layer 20, and the sidewall spacers 30 can be collectively referred to as a gate structure. Furthermore, source / drain regions 50 are formed near the gate structure, and the gaps between the gate structures are filled with an interlayer dielectric (ILD) layer 40.

[0073] Figure 1C This is an enlarged view of the gate structure. The metal gate structure 10 comprises one or more layers of metal material 16, such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, or other conductive materials. The gate dielectric layer 12 disposed between the channel region of the fin structure 5 and the metal gate comprises one or more layers of metal oxide, such as a high-dielectric-constant metal oxide. Examples of metal oxides used for high-dielectric-constant dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and / or mixtures thereof.

[0074] In some embodiments, one or more work function adjustment layers 14 (MG) are situated between the gate dielectric layer 12 and the metal material 16. The work function adjustment layer 14 is composed of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For n-channel field-effect transistors, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer; for p-channel field-effect transistors, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer.

[0075] The overlay insulating layer 20 comprises one or more layers of insulating material, such as silicon nitride-based materials comprising SiN, SiCN, and SiOCN. The sidewall spacers 30 are composed of a material different from that of the overlay insulating layer 20 and comprise one or more layers of insulating material, such as silicon nitride-based materials comprising SiN, SiON, SiCN, and SiOCN. The interlayer dielectric layer 40 comprises one or more layers of insulating material, such as silicon oxide-based materials, such as silicon dioxide (SiO2) and SiON.

[0076] In some implementations, no gate covering insulating layer is formed, such as Figure 1D As shown.

[0077] The materials of the sidewall spacer 30, the covering insulating layer 20, and the interlayer dielectric layer 40 are different from each other so that each of these layers can be selectively etched. In one embodiment, the sidewall spacer 30 is composed of SiOCN, SiCN, or SiON, the covering insulating layer 20 is composed of SiN, and the interlayer dielectric layer 40 is composed of SiO2.

[0078] In this embodiment, a fin field-effect transistor (Fin FET) manufactured by a gate replacement process is used.

[0079] Figure 1E An example perspective view showing a fin field-effect transistor structure.

[0080] First, a fin-like structure 110 is fabricated on top of the substrate 100. The fin-like structure 110 includes a bottom region and an upper region as a channel region 115. The substrate 100 has, for example, approximately 1 × 10⁻⁶ fins. 15 cm -3 To approximately 1×10 18 cm -3 The impurity concentration is p-type silicon substrate. In other embodiments, substrate 100 has an impurity concentration of approximately 1 × 10⁻⁶. 15 cm -3 To approximately 1×1018 cm -3 The substrate 100 may contain an n-type silicon substrate with a low impurity concentration. Alternatively, the substrate 100 may contain a semiconductor of another element, such as germanium; a compound semiconductor, including group IV-IV compound semiconductors, such as SiC and SiGe; a group III-V compound semiconductor, such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In one embodiment, the substrate 100 is a silicon layer of an SOI (silicon-on-insulator) substrate.

[0081] After the fin structure 110 is formed, an insulating layer 120 is formed on top of the fin structure 110. The insulating layer 120 comprises one or more layers of insulating material formed by LPCVD (low-pressure chemical vapor deposition), plasma chemical vapor deposition, or flowable chemical vapor deposition, such as silicon oxide, silicon oxynitride, or silicon nitride. The insulating layer 120 may be formed from one or more layers of spin-on glass (SOG), SiO, SiON, SiOCN, and / or fluorine-doped silicon glass (FSG).

[0082] After forming an insulating layer 120 over the fin structure 110, a planarization operation is performed to remove a portion of the insulating layer 120. The planarization operation may include chemical mechanical polishing (CMP) and / or an etching process. Next, the insulating layer 120 is further removed (recessed) to expose the upper region of the fin structure 110.

[0083] A dummy gate structure is formed over the exposed fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer made of polysilicon. Sidewall spacers containing one or more layers of insulating material are also formed on the sidewalls of the dummy gate electrode layer. After forming the dummy gate structure, the fin structure 110 not covered by the dummy gate structure is recessed below the upper surface of the insulating layer 120. Then, a source / drain region 160 is formed over the recessed fin structure 110 using an epitaxial growth method. The source / drain region 160 may contain strain material to apply stress to the channel region 115.

[0084] Next, an interlayer dielectric (ILD) layer 170 is formed over the dummy gate structure and the source / drain regions. After planarization, the dummy gate structure is removed to form a gate gap. Then, a metal gate structure 130, including a metal gate electrode and a gate dielectric layer, such as a high-dielectric-constant dielectric layer, is formed in the gate gap. Furthermore, a cover isolation layer 140 is formed over the metal gate structure 130 to obtain... Figure 1E The finned field-effect transistor structure is shown. Figure 1EIn the diagram, a portion of the metal gate structure 130, the covering isolation layer 140, the sidewall 150, and the interlayer dielectric layer 170 are cut open to reveal the underlying structure.

[0085] Figure 1E The metal gate structure 130, the covering isolation layer 140, the sidewall 150, the source / drain region 160, and the interlayer dielectric layer 170 respectively substantially correspond to Figures 1A to 1D The structure comprises a metal gate structure 10, a covering insulating layer 20, sidewall spacers 30, a source / drain region 50, and an interlayer dielectric (ILD) layer 40. In some embodiments, one or more additional interlayer dielectric layers are formed above the interlayer dielectric layer 40 to form a first interlayer dielectric layer 45.

[0086] Figures 2A to 2E This shows the stages of the sequential manufacturing process corresponding to this semiconductor device structure. Figures 2A to 2E The image shows four fin-like structures 5, but the number of fin-like structures 5 is not limited to four, and can be one, two, three, or five or more.

[0087] After forming the metal gate structure, a first etch stop layer 60 is formed above the first interlayer dielectric layer 45 (or interlayer dielectric layer 40), and a second interlayer dielectric layer 65 is formed above the first etch stop layer 60, as follows. Figure 2A As shown. An etch stop layer and an interlayer dielectric layer are formed using suitable thin film formation methods, such as chemical vapor deposition, physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0088] Contact holes (openings) 67 for lower contacts 70 are formed in the first interlayer dielectric layer 45 and the second interlayer dielectric layer 65 by using one or more photolithography and etching operations, such as Figure 2B As shown.

[0089] Next, a first contact pad layer 68 is conformally formed in the contact hole 67 and on the upper surface of the second interlayer dielectric layer 65, and a conductive material is formed above the first contact pad layer 68. The contact pad layer 68 and the conductive material layer are formed by a suitable thin film formation method, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or electroplating. Subsequently, a planarization operation is performed, such as an etch-back operation or a chemical mechanical polishing (CMP) operation, to form the source / drain contact 70, as shown below. Figure 2C As shown.

[0090] Subsequently, a second etch stop layer 75 and a third interlayer dielectric layer 80 are formed, as follows: Figure 2DAs shown. In some embodiments, during the deposition process, the third interlayer dielectric layer 80 is doped with Ge and / or Sn by in-situ doping. In other embodiments, after the formation of the third interlayer dielectric layer 80, an ion implantation operation is performed to introduce Ge and / or Sn into the third interlayer dielectric layer 80. In other embodiments, the implantation operation is performed at a stage after the fabrication operation.

[0091] like Figure 2E As shown, contact holes (openings) 82 with upper contacts are formed in the third interlayer dielectric layer 80 and the second etch stop layer 75 by using one or more photolithography and etching operations.

[0092] Figure 3A , Figure 3B , Figure 3C , Figure 3D ,and Figure 3E This illustrates multiple stages of the continuous manufacturing operation of a semiconductor device according to this disclosure. It should be understood that... Figures 3A to 3E Additional operations are provided before, during, and after the current operation. For additional implementations of this method, some of the operations described below may be replaced or deleted. The order of operations / processes may be interchanged, or two or more operations may be performed simultaneously. Regarding... Figures 1A to 2E The materials, configurations, dimensions, and / or processes described may be used in the following embodiments, and their detailed descriptions may be omitted.

[0093] like Figure 3A As shown, a first interlayer dielectric (ILD) layer 302 is formed above a lower layer structure (not shown) on a semiconductor substrate (not shown). (For example, corresponding to...) Figure 2E The first interlayer dielectric layer 45 and the second interlayer dielectric layer 65 are present in the structure. In some embodiments, the underlying structure includes one or more fin-like structures formed above the semiconductor substrate. In some embodiments, the first interlayer dielectric (ILD) layer 302 is an insulating layer, such as silicon oxynitride or silicon oxide. The first interlayer dielectric (ILD) layer 302 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes including low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD).

[0094] In some embodiments, a metal layer 303 is formed in the first interlayer dielectric (ILD) layer 302 (e.g., corresponding to...). Figure 2E (Contact 70). In some embodiments, the metal layer 303 comprises cobalt. In some embodiments, one or more adhesive layers 307 are conformally formed in the openings of the first interlayer dielectric (ILD) layer 302 prior to the formation of the metal layer 303. In some embodiments, the adhesive layer 307 comprises titanium, titanium nitride, tantalum, and / or tantalum nitride.

[0095] After forming the metal layer 303, an etch stop layer 304 is formed over the first interlayer dielectric (ILD) layer 302 (e.g., corresponding to Figure 2E the second etch stop layer 75 in ). A second interlayer dielectric (ILD) layer 306 is formed over the etch stop layer 304 (e.g., corresponding to Figure 2E the third interlayer dielectric layer 80 in ). The etch stop layer 304 and the second interlayer dielectric (ILD) layer 306 are formed by a suitable thin film formation method, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments, the etch stop layer 304 comprises a nitride-based insulating material. In some embodiments, the nitride-based insulating material is a nitride or oxynitride of silicon, germanium, or silicon germanium (SiGe). In some embodiments, the nitride-based insulating material comprises silicon nitride and silicon oxynitride. For silicon oxynitride, in some embodiments of Si x O y N z , wherein y<z), the amount of nitrogen is greater than the amount of oxygen.

[0096] By using one or more lithography and dry etching operations, an opening (via window) 311 is formed in the second interlayer dielectric (ILD) layer 306 and the etch stop layer 304. The opening 311 exposes the upper surface of the metal layer 303. In some embodiments, an oxide layer (e.g., cobalt oxide) is formed on the exposed surface of the metal layer 303.

[0097] Please refer to Figure 3B , a wet etching operation is performed to substantially isotropically remove a portion of the metal layer 303 below the opening 311, thereby forming a recess 313 (e.g., a cobalt recess) in the metal layer 303. Due to the isotropic nature of the wet etching operation, the formed recess 313 extends laterally and in a vertically downward direction. The recess 313 extends laterally below the etch stop layer 304 and exposes a portion of the bottom surface of the etch stop layer 304 with respect to the opening 311. In some embodiments, an aqueous sulfuric acid solution is used as the wet etchant. In some embodiments, when an oxide layer is formed on the upper surface of the metal layer 303, the wet etching operation also removes the oxide layer.

[0098] As Figure 3C shown, in some embodiments, a conductive material such as tungsten is deposited in the opening 311 and the recess 313 to form a tungsten plug 315. The tungsten plug 315 occupies (fills) the opening 311 and the recess 313. The tungsten material forms "bulges" on the upper surface of the second interlayer dielectric (ILD) layer 306. The tungsten plug 315 is formed by a suitable thin film formation method, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments, the tungsten is deposited as a selective deposition, growing from the cobalt recess 313.

[0099] After the tungsten plug 315 is formed, germanium (Ge) is implanted into the second interlayer dielectric (ILD) layer 306. Germanium occupies the gap between the sidewalls forming the opening 311 and the outer surface of the tungsten plug 315. Therefore, the gap is reduced, and displacement of the tungsten plug 315 within the opening 311 is reduced. The groove 313 also restricts movement of the tungsten plug 315. For example, if the gap is not filled, further operations (e.g., polishing operations) could cause displacement of the tungsten plug 315 within the opening 311. The germanium (Ge) ions filling the gap restrict displacement, thereby reducing damage to the tungsten plug 315. In some embodiments, the germanium concentration is from about 1 atomic% to about 20 atomic%, and in other embodiments, the germanium concentration is from about 5 atomic% to about 10 atomic%. In some other embodiments, other materials such as tin are implanted.

[0100] In some embodiments, one or more adhesion layers 307 (and / or barrier layers) are formed on the upper surface of the second interlayer dielectric (ILD) layer 306 and on the tungsten plug 315, such as Figure 3D As shown. A buffer layer 321 is applied over the adhesive layer 307. In some embodiments, the buffer layer 321 comprises tungsten. In some embodiments, the adhesive layer 307 improves the adhesion of the buffer layer 321 to the interlayer dielectric layer 306. In some embodiments, the combination of the buffer layer 321 and / or the adhesive layer 307 and the buffer layer 321 helps to reduce stress during subsequent chemical mechanical polishing operations, thus reducing damage to the tungsten plug 315 due to the different chemical mechanical polishing stresses of the tungsten plug 315 and the interlayer dielectric layer 306 (silicon oxide).

[0101] The buffer layer 321 reduces the stress induced on the surface of the inter-layer dielectric (ILD) layer 306 during subsequent polishing operations. The buffer layer 321 also reduces the contact stress between the inter-layer dielectric layer 306 and the tungsten plug 315, thereby limiting damage to the tungsten plug 315. Figure 3E This diagram illustrates the structure obtained after chemical mechanical polishing (CMP) to remove the buffer layer 321, the adhesive layer 307, and part of the second interlayer dielectric layer 306.

[0102] Please refer to Figure 3EThe distance H1 represents the vertical distance between the upper surface of the second interlayer dielectric (ILD) layer 306 and the upper surface of the metal layer 303; the distance H2 represents the height of the groove 313 from the upper surface of the metal layer 303 to the lowest point in the groove 313; the width W1 represents the width of the opening 311; and the width W2 represents the width of the groove 313 at its widest point. In some embodiments, the distance H1 is about 200 nm to about 500 nm, the distance H2 is about 5 nm to about 15 nm, the width W1 is about 10 nm to about 20 nm, and the width W2 is about 15 nm to about 25 nm. In some embodiments, the aspect ratio of distance H1 / width W1 is about 12 to about 100. In some embodiments, the aspect ratio of distance H2 / width W2 is about 0.2 to about 2. Tungsten plugs with dimensions smaller than the above lower limits (e.g., distance H1 less than 200 nm, or distance H2 less than 5 nm, etc.) will have a relatively weak structure and are easily damaged during operations such as chemical mechanical polishing (CMP). Tungsten plugs with dimensions greater than the above upper limits (e.g., distance from H1 greater than 500 nm, distance from H2 greater than 15 nm, etc.) will be deeper and wider, and will occupy more space in the substrate.

[0103] Figures 4A to 4I This illustrates multiple stages of the continuous manufacturing operation of a semiconductor device according to this disclosure. It should be understood that... Figures 4A to 4I Additional operations are provided before, during, and after the current operation. For additional implementations of this method, some of the operations described below can be replaced or deleted. The order of operations / processes can be interchanged, or two or more operations can be performed simultaneously. Regarding... Figures 1A to 2E The materials, configurations, dimensions, and / or processes described may be used in the following embodiments, and their detailed descriptions may be omitted.

[0104] like Figure 4A As shown, a first interlayer dielectric (ILD) layer 302 is formed over a lower layer structure (not shown) on a semiconductor substrate (not shown). In some embodiments, the lower layer structure includes one or more fin-like structures formed over the semiconductor substrate. In some embodiments, the first interlayer dielectric (ILD) layer 302 is an insulating layer, such as silicon oxynitride or silicon oxide. The first interlayer dielectric (ILD) layer 302 is formed by chemical vapor deposition (CVD), including low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD); physical vapor deposition (PVD); atomic layer deposition (ALD); or other suitable processes.

[0105] In some embodiments, a metal layer 303 is formed in a first interlayer dielectric (ILD) layer 302. In some embodiments, the metal layer 303 comprises cobalt. In some embodiments, prior to forming the metal layer 303, one or more adhesive layers 307 are conformally formed in openings in the first interlayer dielectric (ILD) layer 302. In some embodiments, the adhesive layer 307 comprises titanium, titanium nitride, tantalum, and / or tantalum nitride.

[0106] After forming the metal layer 303, an etch stop layer 304 is formed over the first interlayer dielectric (ILD) layer 302. A second interlayer dielectric (ILD) layer 306 is formed over the etch stop layer 304. The etch stop layer 304 and the second interlayer dielectric (ILD) layer 306 are formed by a suitable thin film formation method, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments, the etch stop layer 304 comprises a nitride-based insulating material. In some embodiments, the nitride-based insulating material is a nitride or oxynitride of silicon, germanium, or silicon germanium (SiGe). In some embodiments, the nitride-based insulating material comprises silicon nitride and silicon oxynitride. For silicon oxynitride, in some embodiments (Si x O y N z , where y<z), the amount of nitrogen is greater than the amount of oxygen.

[0107] Openings (vias) 311 are formed in the second interlayer dielectric (ILD) layer 306 and the etch stop layer 304 by using one or more lithography and dry etching operations. The openings 311 expose the upper surface of the metal layer 303.

[0108] As Figure 4B illustrated, the surface of the cobalt metal layer 303 oxidizes after being exposed to the environment for a certain period of time (about 30 minutes), and one or more cobalt oxide (Co3O4) layers 401 are formed on the surface of the metal layer 303 (or, in other words, at the bottom of the opening 311). It is desirable to extend the opening 311 further into the metal layer 303 to provide improved support for a plug formed in the opening 311. To deepen the opening 311, the metal layer 303 is further etched. The one or more cobalt oxide (Co3O4) layers 401 limit further etching of the metal layer 303.

[0109] As Figure 4CAs shown, a thermal dry etching process is performed in which one or more layers of cobalt oxide (Co3O4) 401 are exposed to an etchant to remove the one or more layers of cobalt oxide (Co3O4) 401 substantially anisotropically. After removing the one or more layers of cobalt oxide (Co3O4) 401, the thermal dry etching process continues to remove a portion of the metal layer 303, thereby making the opening 311 "deeper". In some embodiments, nitrogen trifluoride (NF3) gas (or other fluorine-containing gas) is used as the etchant. The reaction between cobalt oxide (Co3O4) and nitrogen trifluoride gas releases cobalt difluoride (CoF2) gas.

[0110] Etch the metal layer 303 from the etch stop layer 304 to the desired distance (e.g., Figure 4J After reaching height H4), the etching operation is stopped by removing the etchant from opening 311. For example... Figure 4D As shown, the defluorination process is performed by introducing defluorinating agent 423 to remove fluorine from opening 311. In some embodiments, argon (Ar) or hydrogen (H2) plasma is used for defluorination. In some other embodiments, oxygen (O2) plasma is used.

[0111] like Figure 4E As shown, a wet etching operation is performed to substantially isotropically remove cobalt from the metal layer 303. Using the wet etching operation, the metal layer 303 is etched laterally and in a vertically downward direction, thereby creating an opening wider than 311 (e.g., width W4 is greater than width W3, as shown). Figure 4J The groove 413 (shown) is perpendicularly separated from the etch stop layer 304 because the hot dry etching process also removes part of the metal layer 303. For the purposes of this discussion, "separated" refers to the distance or gap between the etch stop layer 304 and the groove 413, so that the groove 413 does not contact the etch stop layer 304. Instead, the groove 313 (shown) Figure 3B Contact etching stop layer 304.

[0112] like Figure 4F As shown, in some embodiments, a conductive material, such as tungsten, is deposited in the opening 311 and the groove 413 to form a tungsten plug 415. The tungsten plug 415 occupies (fills) the opening 311 and the groove 413. The tungsten material forms a "bump" on the upper surface of the second interlayer dielectric (ILD) layer 306. The tungsten plug 415 is formed by a suitable thin film formation method, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments, the tungsten deposition is selective, growing from the cobalt groove 313.

[0113] Please refer to Figure 4GAfter the tungsten plug 415 is formed, germanium (Ge) is used for implantation. Germanium occupies the gap between the sidewall of the opening 311 and the outer surface of the tungsten plug 415. Therefore, the gap is "filled," reducing displacement of the tungsten plug 415 within the opening 311. A deeper groove 413 further restricts the movement of the tungsten plug 415. For example, if the gap were not filled, further operations (e.g., grinding) could cause displacement of the tungsten plug 415 within the opening 311. The germanium (Ge) filling the gap restricts displacement, thereby reducing damage to the tungsten plug 415.

[0114] In some embodiments, one or more adhesion layers 307 (and / or barrier layers) are formed on the upper surface of the second interlayer dielectric (ILD) layer 306 and on the tungsten plug 415, such as Figure 4H As shown in the diagram, a buffer layer 321 is applied over the adhesive layer 307. In some embodiments, the buffer layer 321 is composed of tungsten, and the adhesive layer 307 comprises titanium and titanium nitride.

[0115] The buffer layer 321 reduces stress induced on the surface of the inter-second dielectric (ILD) layer 306 during subsequent cleaning operations. The buffer layer 321 also reduces contact stress between the inter-second dielectric (ILD) layer 306 and the tungsten plug 415, thereby limiting damage to the tungsten plug 415.

[0116] Chemical mechanical polishing (CMP) is performed to remove the buffer layer 321, adhesive layer 307, tungsten plug 415, and part of the inter-second dielectric (ILD) layer 306, such as Figure 4I As shown.

[0117] After grinding the tungsten plug 415 and the second interlayer dielectric (ILD) layer 306, a second implantation operation is performed to implant germanium (Ge) into the gap between the sidewall of the opening 311 and the outer surface of the tungsten plug 415. Because the groove 413 is deeper than the groove 313, the first germanium implantation may not be sufficient to fill the gap. The second implantation operation fills the gap not filled by the first implantation operation, thus further securing the tungsten plug 415. In some embodiments, the depth (height H4) of the groove 413 may be smaller (e.g., about 1 to about 2 nm), and the second implantation operation is omitted. In some embodiments, in such... Figure 4G In the first implantation operation, germanium is implanted from the upper surface of the interlayer dielectric layer 306 into approximately 20% to 40% of its thickness. After one or more chemical mechanical polishing operations as described above, the thickness of the interlayer dielectric layer 306 is reduced by approximately 20% to approximately 40%, which means that the germanium implantation region of the interlayer dielectric layer 306 is substantially removed. By using the second implantation operation, germanium ions can be re-implanted into approximately 15% to approximately 35% of the remaining thickness of the interlayer dielectric layer.

[0118] Figure 4J This illustrates the structure obtained after the above processing steps. Please refer to... Figure 4J The distance H3 represents the vertical distance between the upper surface of the second interlayer dielectric (ILD) layer 306 and the upper surface of the metal layer 303; the distance H4 represents the distance of the groove 413 from the upper surface of the metal layer 303; the distance H5 represents the height of the groove 413 at its highest point; the width W3 represents the width of the opening 311; and the width W4 represents the width of the groove 413 at its widest point. In some embodiments, the distance H3 is approximately 200 nm to approximately 500 nm, the distance H5 is approximately 3 nm to approximately 10 nm, the width W3 is approximately 10 nm to approximately 20 nm, and the width W4 is approximately 15 nm to approximately 25 nm. The distance H4 is a value greater than 0. In some embodiments, the distance H4 is approximately 1 nm to approximately 10 nm. However, the value of the distance H4 may be varied depending on the application and design requirements. In some embodiments, the aspect ratio of distance H3 / width W3 is approximately 12 to approximately 100. In some embodiments, the aspect ratio of distance H5 / width W4 is approximately 0.2 to approximately 2. Tungsten plugs with dimensions smaller than the lower limits mentioned above (e.g., less than 200 nm from H3, or less than 3 nm from H5, etc.) will be relatively fragile structures and easily damaged during operations such as chemical mechanical polishing (CMP). Tungsten plugs with dimensions larger than the upper limits mentioned above (e.g., greater than 500 nm from H3, greater than 10 nm from H5, etc.) will be deeper and wider, and will occupy more space in the substrate.

[0119] According to embodiments disclosed herein, this processing method reduces the fluorine content in the cobalt layer during etching operations to obtain grooves of desired dimensions (e.g., depth and width) in the cobalt layer. Tungsten plugs formed in the grooves exhibit reduced resistance and improved switching speed.

[0120] It should be understood that not all advantages have necessarily been discussed here, all implementation methods or examples do not require particular advantages, and other implementation methods or examples may provide different advantages.

[0121] According to one embodiment of this disclosure, a method for manufacturing a semiconductor device includes forming a first dielectric layer over a substrate; forming a metal layer in the first dielectric layer; forming an etch stop layer on the surfaces of the first dielectric layer and the metal layer; removing portions of the metal layer and the etch stop layer to form a groove in the metal layer, the groove being separated from the bottom surface of the etch stop layer; and forming a tungsten plug in the groove. In some embodiments, the metal layer comprises cobalt, and a first portion of the metal layer at or near the surface of the metal layer comprises cobalt oxide. The method further includes performing an etching operation using a fluorine-containing gas to remove the first portion of the metal layer and a second portion of the metal layer located below the first portion to form a groove; and performing a defluorination process to remove the fluorine-containing gas after a groove of a desired distance has been formed in the metal layer. In some embodiments, the method further includes forming a second dielectric layer on the etch stop layer before etching; and removing portions of the second dielectric layer and the etch stop layer to form an opening. The groove is formed in the metal layer through the opening. In some embodiments, the method further includes performing a first ion implantation operation to implant an ion species into a second dielectric layer; and performing a planarization operation on the second dielectric layer and the tungsten plug. In some embodiments, the method further includes forming a buffer layer on the second dielectric layer before performing the planarization operation. In some embodiments, the method further includes performing a second ion implantation operation to implant an ion species into the second dielectric layer. In some embodiments, etching a first portion and a second portion to extend the opening into the metal layer. In some embodiments, a plasma of argon (Ar), hydrogen (H2), or oxygen (O2) is used for the defluorination process. In some embodiments, removing a portion of the metal layer includes performing a first etching operation to remove a first portion of the metal layer at or near the surface of the metal layer; removing a second portion of the metal layer below the first portion to extend the opening into the metal layer; and forming a groove in the metal layer. In some embodiments, the metal layer contains cobalt, and the first portion of the metal layer at or near the surface of the metal layer contains cobalt oxide. In some embodiments, performing the first etching operation involves treating the cobalt oxide with a fluorine-containing gas. This method also includes performing a defluorination process after the opening has extended into the metal layer to the desired distance to remove the fluorine-containing gas from the opening.

[0122] According to another aspect of this disclosure, a method for manufacturing a semiconductor device includes forming a first dielectric layer over a substrate; forming a cobalt plug in the first dielectric layer; forming a nitride-based etch stop layer on the first dielectric layer and the cobalt plug; forming a second dielectric layer over the nitride-based etch stop layer; forming an opening in the second dielectric layer and the nitride-based etch stop layer to expose the upper surface of the cobalt plug; performing an etching operation using a fluorine-containing gas to (1) remove one or more layers of cobalt oxide formed on or below the upper surface of the cobalt plug, and (2) remove portions of the cobalt plug located below the one or more layers of oxide to extend the opening into the cobalt plug; performing a defluorination process to remove the fluorine-containing gas after the opening has extended into the cobalt plug to the required distance; forming a groove in the cobalt plug at the bottom of the opening, wherein the groove is separated from the nitride-based etch stop layer; and forming a tungsten plug in the groove and the opening. In some embodiments, the method further includes performing a first implantation operation to implant germanium ions into a second dielectric layer, the germanium ions occupying a gap between the sidewall of an opening in the second dielectric layer and the outer surface of a tungsten plug; and performing a planarization operation to remove a portion of the tungsten plug and the second dielectric layer. In some embodiments, the method further includes performing a second ion implantation operation after the planarization operation to implant germanium ions into the second dielectric layer. In some embodiments, the etching operation further includes removing a portion of the cobalt plug located beneath one or more oxide layers to extend the opening into the cobalt plug. In some embodiments, forming a groove in the cobalt plug includes forming a groove having a width greater than the width of the opening. In some embodiments, the method further includes performing a defluorination process to remove fluorine-containing gases after the opening has extended into the cobalt plug.

[0123] According to another embodiment of this disclosure, a semiconductor device includes a first dielectric layer disposed above a semiconductor device structure and including a metal layer; an etch stop layer disposed above the first dielectric layer; a second dielectric layer disposed above the etch stop layer; a groove in the metal layer and separated from the etch stop layer; and a tungsten plug. Openings are defined in the second dielectric layer, the etch stop layer, and the metal layer. The tungsten plug is disposed in the openings and the groove, and the width of the groove is greater than the width of the opening. In some embodiments, the distance between the groove and the etch stop layer is 1 nm to 10 nm. In some embodiments, the second dielectric layer includes germanium. In some embodiments, the width of the opening is 10 nm to 20 nm, and the width of the groove is 15 nm to 25 nm. In some embodiments, the height of the groove is 3 nm to 10 nm. In some embodiments, the distance between the upper surface of the second dielectric layer and the upper surface of the metal layer is 200 nm to 500 nm. In some embodiments, the aspect ratio of the width of the groove to the height of the groove is 0.2 to 2, and the aspect ratio of the distance from the upper surface of the second dielectric layer to the upper surface of the metal layer to the width of the opening is 12 to 100.

[0124] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can easily use this disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that this equivalent architecture does not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

Claims

1. A method of manufacturing a semiconductor element, characterized by, The method includes: A first dielectric layer is formed on top of a substrate; A metal layer is formed in the first dielectric layer; An etch stop layer is formed on one surface of the first dielectric layer and the metal layer; Remove multiple portions of the metal layer and the etch stop layer to form a groove in the metal layer, the groove being separated from a bottom surface of the etch stop layer; and A tungsten plug is formed in the groove, wherein: The metal layer contains cobalt, and a plurality of first portions of the metal layer at or near a surface of the metal layer contain a cobalt oxide. The method also includes using a fluorine-containing gas to perform an etching operation to remove the plurality of first portions of the metal layer and to remove a plurality of second portions of the metal layer located beneath the plurality of first portions, thereby forming the groove.

2. The method according to claim 1, characterized in that, The method also includes: After the groove of the required distance is formed in the metal layer, a defluorination process is performed to remove the fluorine-containing gas.

3. The method according to claim 2, characterized in that, The method also includes: Before etching, a second dielectric layer is formed on the etch stop layer; and Multiple portions of the second dielectric layer and the etch stop layer are removed to form an opening, through which the groove is formed in the metal layer.

4. The method according to claim 3, characterized in that, The method also includes: Perform a first ion implantation operation to implant an ion species into the second dielectric layer; and A planarization operation is performed on the second dielectric layer and the tungsten plug.

5. The method according to claim 4, characterized in that, The method also includes: Before performing the planarization operation, a buffer layer is formed on the second dielectric layer.

6. The method according to claim 4, characterized in that, The method also includes: A second ion implantation operation is performed to implant the ion species into the second dielectric layer.

7. The method according to claim 3, characterized in that, Etching the plurality of first portions and the plurality of second portions causes the opening to extend into the metal layer.

8. The method according to claim 2, characterized in that, The defluorination process is performed using plasma containing argon, hydrogen, or oxygen.

9. A method for manufacturing a semiconductor device, characterized in that, The method includes: A first dielectric layer is formed on top of a substrate; A cobalt plug is formed in the first dielectric layer; A nitride-based etch stop layer is formed on the first dielectric layer and the cobalt plug; A second dielectric layer is formed above the nitride-based etch stop layer; An opening is formed in the second dielectric layer and the nitride-based etch stop layer to expose an upper surface of the cobalt plug; An etching operation is performed using a fluorine-containing gas to remove one or more layers of cobalt oxide formed on or below the upper surface of the cobalt plug, and to remove multiple portions of the cobalt plug below the one or more layers of oxide, so as to extend the opening into the cobalt plug. After extending the opening in the cobalt plug to the required distance, a defluorination process is performed to remove the fluorine-containing gas. A groove is formed in the cobalt plug at one bottom of the opening, wherein the groove is separated from the nitride-based etch stop layer; and A tungsten plug is formed in the groove and the opening.

10. The method according to claim 9, characterized in that, The method also includes: A first implantation operation is performed to implant a plurality of germanium ions into the second dielectric layer, the plurality of germanium ions occupying a plurality of gaps between a plurality of sidewalls of the opening in the second dielectric layer and an outer surface of the tungsten plug; as well as A planarization operation is performed to remove the tungsten plug and multiple portions of the second dielectric layer.

11. The method according to claim 10, characterized in that, The method also includes: After the planarization operation, a second implantation operation is performed to implant germanium ions into the second dielectric layer.

12. The method according to claim 9, characterized in that, The etching operation also includes removing multiple portions of the cobalt plug located beneath the one or more layers of oxide to extend the opening into the cobalt plug.

13. The method according to claim 11, characterized in that, Forming the groove in the cobalt plug includes forming the groove having a width greater than that of the opening.

14. A semiconductor element, characterized in that, The semiconductor device includes: A first dielectric layer is disposed above a semiconductor device structure; A metal layer is located within the first dielectric layer; An etch stop layer is disposed above the first dielectric layer; A second dielectric layer is disposed above the etch stop layer; A groove is located in the metal layer, and the groove is separated from the etch stop layer; as well as A tungsten plug, wherein an opening is defined in the second dielectric layer, the etch stop layer, and the metal layer, the tungsten plug is disposed in the opening and the groove, the width of the groove being greater than the width of the opening, wherein a gap is formed between the sidewall of the opening and the outer surface of the tungsten plug, and the gap is filled with germanium.

15. The semiconductor element according to claim 14, characterized in that, The distance between the groove and the etch stop layer is 1 nm to 10 nm.

16. The semiconductor element according to claim 14, characterized in that, The second dielectric layer contains germanium.

17. The semiconductor element according to claim 14, characterized in that, The width of the opening is 10 nm to 20 nm, and the width of the groove is 15 nm to 25 nm.

18. The semiconductor element according to claim 14, characterized in that, The height of the groove is 3nm to 10nm.

19. The semiconductor element according to claim 14, characterized in that, The distance between an upper surface of the second dielectric layer and an upper surface of the metal layer is 200 nm to 500 nm.

20. The semiconductor element according to claim 14, characterized in that, The aspect ratio of the height of the groove to the width of the groove is 0.2 to 2, and the aspect ratio of the distance from the upper surface of the second dielectric layer to the upper surface of the metal layer to the width of the opening is 12 to 100.

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