Fin-type field-effect transistor devices and methods

Abstract

This disclosure relates to fin field-effect transistor devices and methods. A method of forming a semiconductor device includes: forming a gate structure over a fin protruding above a substrate, the gate structure being surrounded by a first ILD layer; forming a trench adjacent to the fin in the first ILD layer; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing sidewalls of the first dummy material; lining the sidewalls of the opening with a second dummy material; after lining, forming a conductive material in the opening; after forming the conductive material, removing the first dummy material and the second dummy material from the trench and the opening, respectively; and after removal, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.

Description

Technical Field

[0001] This disclosure relates generally to the semiconductor field, and more particularly to fin field-effect transistor devices and methods. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the repeated reduction in the minimum feature size, which allows more components to be integrated into a given area.

[0003] FinFET devices are becoming increasingly common in integrated circuits. FinFET devices have a three-dimensional structure comprising semiconductor fins protruding from a substrate. A gate structure, configured to control the flow of charge carriers within the conductive channels of the FinFET device, surrounds the semiconductor fins. For example, in a tri-gate FinFET device, the gate structure surrounds three sides of the semiconductor fin, thereby forming conductive channels on the three sides of the semiconductor fin. Summary of the Invention

[0004] One aspect of this disclosure provides a method for forming a semiconductor device, the method comprising: forming a gate structure over a first fin, wherein the first fin protrudes above a substrate and the gate structure is surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the first fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming a first opening in the first ILD layer and the second ILD layer, wherein the first opening exposes a sidewall of the first dummy material; lining the sidewall of the first opening with a second dummy material; after lining the sidewall of the first opening, forming a conductive material in the first opening; after forming the conductive material, removing the first dummy material from the trench and removing the second dummy material from the first opening; and after the removal, sealing the first opening and the trench by forming a dielectric layer over the second ILD layer.

[0005] Another aspect of this disclosure provides a method for forming a semiconductor device, the method comprising: forming a gate structure over a first fin and over a second fin adjacent to the first fin, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer and between the first fin and the second fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and over the first dummy material; forming a first opening and a second opening in the first ILD layer and the second ILD layer, the first opening exposing the first dummy material and the second opening exposing an underlying source / drain region; lining the sidewalls of the first opening and the sidewalls of the second opening with a second dummy material; after lining, forming a conductive material in the first opening and the second opening; after forming the conductive material, removing the first dummy material from the trench and removing the second dummy material from the first opening and the second opening; and after the removal, forming a dielectric layer over the second ILD layer to seal the trench, the first opening, and the second opening.

[0006] Another aspect of this disclosure provides a semiconductor device comprising: a fin protruding above a substrate; a gate structure situated above the fin; an interlayer dielectric (ILD) layer situated above the fin and surrounding the gate structure; a via extending through the ILD layer and electrically coupled to an underlying source / drain region; and an air gap surrounding the via, wherein the via is separated from the ILD layer by the air gap. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 This is a perspective view of a FinFET according to some embodiments.

[0009] Figure 2-7 , Figure 8A , Figure 8B , Figures 9A-9D , Figure 10A-10D , Figure 11A-11D , Figure 12A-12D , Figures 13A-13D , Figures 14A-14D , Figures 15A-15D and Figures 16A-16D Various views of a FinFET device at various manufacturing stages according to one embodiment are shown.

[0010] Figure 17 A top view of a FinFET device according to one embodiment is shown.

[0011] Figure 18 A top view of a FinFET device according to another embodiment is shown.

[0012] Figure 19 A top view of a FinFET device according to yet another embodiment is shown.

[0013] Figure 20 A flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments is shown. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In addition, spatially related terms (e.g., "below," "under," "down," "above," "upper," etc.) may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly. Throughout the discussion herein, unless otherwise specified, the same or similar reference numerals in different figures refer to the same or similar elements formed using the same or similar (one or more) materials and by the same or similar forming methods. Furthermore, figures with the same reference numerals but different letters (e.g., Figures 9A-9D The image shows different views of the same semiconductor device at the same manufacturing stage.

[0016] Embodiments of this disclosure are discussed in the context of forming semiconductor devices, and more specifically, in the context of forming air moats (e.g., air gaps) around vias and / or forming air gaps in the dielectric layer of a FinFET device. The principles of this disclosure can also be applied to other types of devices, such as planar devices.

[0017] According to one embodiment of this disclosure, a gate structure is formed on the fin, and an interlayer dielectric (ILD) layer is formed around the gate structure. An air gap is formed in the ILD layer around the source / drain contacts, and / or adjacent to the fin in the ILD layer. The air gap helps to reduce the parasitic capacitance of the formed device, thereby improving device performance.

[0018] Figure 1 An example of a FinFET 30 is shown in the perspective view. The FinFET 30 includes a substrate 50 and a fin 64 that protrudes above the substrate 50. An isolation region 62 is formed on the opposite side of the fin 64, and the fin 64 protrudes above the isolation region 62. A gate dielectric 66 runs along the sidewalls of the fin 64 and over the top surface of the fin 64, and a gate electrode 68 is located on the gate dielectric 66. A source / drain region 80 is within the fin 64 and is located on the opposite side of the gate dielectric 66 and the gate electrode 68. Figure 1 The reference cross sections used in the following figures are further illustrated. Cross section BB extends along the longitudinal axis of the gate electrode 68 of the FinFET 30. Cross section AA is perpendicular to cross section BB and along the longitudinal axis of fin 64 in the direction of current flow, for example, between the source / drain regions 80. Cross section CC is parallel to cross section BB and crosses the source / drain region 80. Cross section DD is parallel to cross section AA and is located outside fin 64 (e.g., between two adjacent fins 64). For clarity, these reference cross sections are referenced in subsequent figures.

[0019] Figure 2-7 , Figure 8A , Figure 8B , Figures 9A-9D , Figure 10A-10D , Figure 11A-11D , Figure 12A-12D , Figures 13A-13D , Figures 14A-14D , Figures 15A-15D and Figures 16A-16D Various views (e.g., cross-sectional view, top view) of the FinFET device 100 according to an embodiment at various manufacturing stages are shown. The FinFET device 100 is similar to Figure 1 The FinFET 30 in this example differs in that it has multiple fins and multiple gate structures. Figure 2-5 A cross-sectional view of the FinFET device 100 along section BB is shown. Figure 6 , Figure 7 and Figure 8A A cross-sectional view of the FinFET device 100 along section AA is shown. Figure 8B A plan view of the FinFET device 100 is shown. For Figures 9A-9D , Figure 10A-10D , Figure 11A-11D , Figure 12A-12D , Figures 13A-13D , Figures 14A-14D , Figures 15A-15D and Figures 16A-16D With the letter A (e.g.) Figure 9A B (e.g.) Figure 9B ), C (e.g.) Figure 9C ) and D (e.g.) Figure 9D The figure shows cross-sectional views of the FinFET device 100 along sections DD, AA, BB, and CC, respectively.

[0020] Figure 2 A cross-sectional view of substrate 50 is shown. Substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0021] refer to Figure 3 Using techniques such as photolithography and etching to... Figure 2 The substrate 50 shown is patterned. For example, a mask layer, such as a pad oxide layer 52 and an overlying pad nitride layer 56, is formed on the substrate 50. The pad oxide layer 52 may be a thin film comprising silicon oxide, for example, formed using a thermal oxidation process. The pad oxide layer 52 may serve as an adhesion layer between the substrate 50 and the overlying pad nitride layer 56, and may also serve as an etch stop layer for etching the pad nitride layer 56. In some embodiments, the pad nitride layer 56 is formed of silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof, and may be formed using, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0022] Photolithography can be used to pattern the mask layer. Typically, photolithography utilizes a photoresist material (not shown), which is deposited, irradiated (exposed), and developed to remove a portion of the photoresist. The remaining photoresist protects the underlying material (e.g., the mask layer in this example) from subsequent processing steps (e.g., etching). In this example, as... Figure 3 As shown, a photoresist material is used to pattern the pad oxide layer 52 and the pad nitride layer 56 to form a patterned mask 58.

[0023] The patterned mask 58 is then used to pattern the exposed portion of the substrate 50 to form trenches 61, thereby... Figure 3 Semiconductor fins 64 are defined between adjacent trenches 61. In some embodiments, the semiconductor fins 64 are formed by etching trenches in the substrate 50 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching may be anisotropic. In some embodiments, the trenches 61 may be stripes (viewed from top) that are parallel to each other and closely spaced from one another. In some embodiments, the trenches 61 may be continuous and surround the semiconductor fins 64. The semiconductor fins 64 may also be referred to as fins 64 hereinafter.

[0024] The fin 64 can be patterned using any suitable method. For example, the fin 64 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing patterns to be created with, for example, smaller pitches than that achievable using a single direct photolithography process in other ways. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin.

[0025] Figure 4An insulating material is formed between adjacent semiconductor fins 64 to form an isolation region 62. The insulating material can be an oxide, such as silicon oxide, nitrides, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to transform it into another material (e.g., oxide)), or a combination thereof. Other insulating materials and / or other formation processes can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. A planarization process, such as chemical mechanical polishing (CMP), can remove any excess insulating material and form a coplanar (not shown) top surface of the isolation region 62 and the top surface of the semiconductor fin 64. The patterned mask 58 (see also...) can also be removed by the planarization process. Figure 3 ).

[0026] In some embodiments, the isolation region 62 includes a liner, such as a liner oxide (not shown), at the interface between the isolation region 62 and the substrate 50 / semiconductor fin 64. In some embodiments, the liner oxide is formed to reduce crystal defects at the interface between the substrate 50 and the isolation region 62. Similarly, the liner oxide can also be used to reduce crystal defects at the interface between the semiconductor fin 64 and the isolation region 62. The liner oxide (e.g., silicon oxide) can be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 50, but other suitable methods can also be used to form the liner oxide.

[0027] Next, the isolation region 62 is recessed to form a shallow trench isolation (STI) region 62. Recessing the isolation region 62 causes the upper portion of the semiconductor fin 64 to protrude from between adjacent STI regions 62. The top surface of the STI region 62 can have a flat surface (as shown), a convex surface, a concave surface (such as a dish), or a combination thereof. The top surface of the STI region 62 can be formed as flat, raised, and / or recessed by appropriate etching. An acceptable etching process (e.g., an etching process selective for the material of the isolation region 62) can be used to recess the isolation region 62. For example, dry etching or wet etching using dilute hydrofluoric acid (dHF) can be performed to recess the isolation region 62.

[0028] Figures 2 to 4 An embodiment of forming fin 64 is shown, but fins can be formed in a variety of different processes. For example, the top of substrate 50 can be replaced with a suitable material, such as an epitaxial material suitable for the intended type of semiconductor device to be formed (e.g., n-type or p-type). The substrate 50 with the epitaxial material on top is then patterned to form the semiconductor fin 64 containing the epitaxial material.

[0029] As another example, a dielectric layer can be formed above the top surface of the substrate; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed so that the homoepitaxial structures protrude from the dielectric layer to form fins.

[0030] In yet another example, a dielectric layer can be formed above the top surface of the substrate; trenches can be etched through the dielectric layer; a heteroepitaxial structure can be epitaxially grown in the trenches using a material different from the substrate; and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form a fin.

[0031] In embodiments where one or more epitaxial materials or structures (e.g., heteroepitaxial or homoepitaxial structures) are grown, the grown material or structure may be doped in situ during growth, which avoids prior and subsequent implantation, but in-situ and implantation doping can be used together. Furthermore, it may be advantageous for the material epitaxially grown in the NMOS region to differ from the material in the PMOS region. In various embodiments, fin 64 may comprise silicon germanium (Si... x Ge 1-x (where x can be between 0 and 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0032] Figure 5 A dummy gate structure 75 is shown formed on a semiconductor fin 64. In some embodiments, the dummy gate structure 75 includes a gate dielectric 66 and a gate electrode 68. A mask 70 may be formed on the dummy gate structure 75. To form the dummy gate structure 75, a dielectric layer is formed on the semiconductor fin 64. The dielectric layer may be, for example, silicon oxide, silicon nitride, or a multilayer thereof, and the dielectric layer may be deposited or thermally grown.

[0033] A gate layer is formed on top of a dielectric layer, and a mask layer is formed on top of the gate layer. The gate layer can be deposited on top of the dielectric layer and then planarized, for example, by CMP. The mask layer can be deposited on top of the gate layer. The gate layer can be formed of, for example, polysilicon, but other materials can also be used. The mask layer can be formed of, for example, silicon nitride.

[0034] After forming layers (e.g., dielectric layer, gate layer, and mask layer), the mask layer can be patterned using acceptable photolithography and etching techniques to form mask 70. The pattern of mask 70 can then be transferred to the gate layer and dielectric layer using acceptable etching techniques to form gate electrode 68 and gate dielectric layer 66, respectively. Gate electrode 68 and gate dielectric layer 66 cover the corresponding channel regions of semiconductor fin 64. The longitudinal direction of gate electrode 68 can also be substantially perpendicular to the longitudinal direction of the corresponding semiconductor fin 64.

[0035] exist Figure 5 In the example, the gate dielectric 66 is shown formed over the fin 64 (e.g., over the top surface and sidewalls of the fin 64) and over the STI region 62. In other embodiments, the gate dielectric 66 may be formed by thermal oxidation of the material of the fin 64, thus the gate dielectric 66 may be formed over the fin 64 but not over the STI region 62. These and other variations are fully intended to be included within the scope of this disclosure.

[0036] Next, as Figure 6 As shown, a lightly doped drain (LDD) region 65 is formed in fin 64. The LDD region 65 can be formed by an implantation process. The implantation process can implant n-type or p-type impurities into fin 64 to form the LDD region 65. In some embodiments, the LDD region 65 is adjacent to the channel region of the FinFET device 100. Some portions of the LDD region 65 may extend below the gate 68 and into the channel region of the FinFET device 100. Figure 6 A non-limiting example of LDD region 65 is shown. Other configurations, shapes, and formation methods of LDD region 65 are also possible and are fully intended to be included within the scope of this disclosure. For example, LDD region 65 may be formed after the gate spacer 87 is formed.

[0037] Still referencing Figure 6 After forming the LDD region 65, a gate spacer 87 is formed on the gate structure. Figure 6 In the example, a gate spacer 87 is formed on the opposite sidewall of the gate electrode 68 and the opposite sidewall of the gate dielectric 66. The gate spacer 87 may be formed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or combinations thereof, and may be formed using, for example, thermal oxidation, CVD, or other suitable deposition processes.

[0038] like Figure 6The shape and formation method of the gate spacer 87 shown are merely non-limiting examples, and other shapes and formation methods are possible. For example, the gate spacer 87 may include a first gate spacer (not shown) and a second gate spacer (not shown). The first gate spacer may be formed on opposite sidewalls of the dummy gate structure 75. The second gate spacer may be formed on the first gate spacer, with the first gate spacer disposed between the respective gate structure and the respective second gate spacer. The first gate spacer may have an L-shape in a cross-sectional view. As another example, the epitaxial source / drain region 80 (see [link to documentation]) may be formed. Figure 7 Afterwards, gate spacers 87 are formed. In some embodiments, in Figure 7 Prior to the epitaxial process of the illustrated epitaxial source / drain region 80, a dummy gate spacer is formed on a first gate spacer (not shown), and after the formation of the epitaxial source / drain region 80, the dummy gate spacer is removed and replaced with a second gate spacer. All such embodiments are intended to be included within the scope of this disclosure.

[0039] Next, as Figure 7 As shown, a source / drain region 80 is formed. The source / drain region 80 is formed by etching the fins 64 to form recesses and epitaxially growing material in the recesses using suitable methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or combinations thereof.

[0040] like Figure 7 As shown, the epitaxial source / drain region 80 may have a surface that protrudes from the corresponding surface of the fin 64 (e.g., protrudes above the non-recessed portion of the fin 64) and may have a facet. The source / drain regions 80 of adjacent fins 64 may merge to form a continuous epitaxial source / drain region 80. In some embodiments, the source / drain regions 80 of adjacent fins 64 do not merge but remain separate source / drain regions 80. In some example embodiments where the resulting FinFET is an n-type FinFET, the source / drain region 80 includes silicon carbide (SiC), silicon phosphide (SiP), phosphorus-doped silicon carbide (SiCP), etc. In alternative exemplary embodiments where the resulting FinFET is a p-type FinFET, the source / drain region 80 includes SiGe and p-type impurities such as boron or indium.

[0041] The epitaxial source / drain region 80 can be formed by implanting dopants, followed by an annealing process. This implantation process may include forming and patterning a mask, such as a photoresist, to cover the areas in the FinFET to be protected from the implantation process. The source / drain region 80 may have a diameter of approximately 1E19 cm⁻¹.-3 Approximately 1E21cm -3 The range of impurity (e.g., dopant) concentrations. In some embodiments, the epitaxial source / drain regions may be doped in situ during growth.

[0042] In some embodiments, after the source / drain region 80 is formed, a contact etch stop layer (CESL) (not shown) is formed over the source / drain region 80, the dummy gate structure 75, and the gate spacer 87. The CESL acts as an etch stop layer in subsequent etch processes and may comprise suitable materials such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, and may be formed by suitable formation methods such as CVD, PVD, or combinations thereof.

[0043] Next, a first interlayer dielectric (ILD) 90 is formed over the fin 64 around the dummy gate structure 75. In some embodiments, the first ILD 90 is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or undoped silicate glass (USG), and can be deposited by any suitable method such as CVD, PECVD, or FCVD. A planarization process (e.g., CMP) can be performed to remove the mask 70 and remove portions of the CESL disposed over the gate electrode 68, such that after the planarization process, the top surface of the first ILD 90 is flush with the top surface of the gate electrode 68.

[0044] Next, in Figure 8A In this process, a post-gate process (sometimes referred to as a replacement gate process) is performed to replace gate electrode 68 and gate dielectric 66 with an effective gate (also referred to as a replacement gate or metal gate) and (one or more) effective gate dielectric materials, respectively. Therefore, in the post-gate process, gate electrode 68 and gate dielectric 66 can be referred to as a dummy gate electrode and a dummy gate dielectric, respectively. In some embodiments, the effective gate is a metal gate.

[0045] refer to Figure 8A The dummy gate structure 75 is replaced with a replacement gate structure 97. According to some embodiments, to form the replacement gate structure 97, the gate electrode 68 and the gate dielectric 66 directly beneath it are removed in one or more etching steps, thereby forming recesses (not shown) between the gate spacers 87. Each recess exposes a channel region of a corresponding fin 64. During dummy gate removal, the gate dielectric 66 can be used as an etch stop layer when etching the gate electrode 68. The gate dielectric 66 can then be removed after the gate electrode 68 has been removed.

[0046] Next, a gate dielectric layer 94, a barrier layer 96, a work function layer 98, and a gate electrode 86 are formed in the recess for replacing the gate structure 97. The gate dielectric layer 94 is conformally deposited in the recess, for example, on the top surface and sidewalls of the fin 64, on the sidewalls of the gate spacer 87, and on the top surface of the first ILD 90 (not shown). According to some embodiments, the gate dielectric layer 94 comprises silicon oxide, silicon nitride, or a multilayer thereof. In other embodiments, the gate dielectric layer 94 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 94 may have a k-value (e.g., dielectric constant) greater than about 7.0, and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. Methods for forming the gate dielectric layer 94 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc.

[0047] Next, a barrier layer 96 is conformally formed over the gate dielectric layer 94. The barrier layer 96 may include a conductive material (e.g., titanium nitride), but other materials (e.g., tantalum nitride, titanium, tantalum, etc.) may be used alternatively. The barrier layer 96 may be formed using a CVD process (e.g., PECVD). However, other alternative processes such as sputtering, metal-organic chemical vapor deposition (MOCVD), or ALD may also be used.

[0048] Next, in some embodiments, a work function layer 98 (e.g., a p-type work function layer or an n-type work function layer) may be formed in a recess above the barrier layer 96 and is formed prior to the formation of the gate 86. Exemplary p-type work function metals that may be included in the gate structure of a p-type device include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals that may be included in the gate structure of an n-type device include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function value is associated with the material composition of the work function layer, and therefore, the material of the work function layer is selected to adjust its work function value in order to achieve a target threshold voltage Vt in the device to be formed. One or more work function layers may be deposited by CVD, physical vapor deposition (PVD), and / or other suitable processes.

[0049] Next, a seed layer (not shown) is conformally formed on the work function layer 98. The seed layer may include copper, titanium, tantalum, titanium nitride, tantalum nitride, or combinations thereof, and may be deposited by ALD, sputtering, PVD, or the like. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. For example, the seed layer may include a titanium layer and a copper layer above the titanium layer.

[0050] Next, a gate electrode 86 is deposited on the seed layer, and the remaining portion of the recess is filled. The gate electrode 86 can be made of a metal-containing material (e.g., Cu, Al, W, etc.), a combination thereof, or multiple layers thereof, and can be formed by, for example, electroplating, electroless plating, or other suitable methods. After forming the gate electrode 86, a planarization process (e.g., CMP) can be performed to remove excess portions of the gate dielectric layer 94, the barrier layer 96, the work function layer 98, the seed layer, and the gate electrode 86 located above the top surface of the first ILD 90. The remaining portions of the gate dielectric layer 94, the barrier layer 96, the work function layer 98, the seed layer, and the gate electrode 86 thus form the replacement gate structure 97 (also referred to as the metal gate structure) of the resulting FinFET device 100. Figure 8A As shown, due to the planarization process, the metal gate structure 97, the gate spacer 87, and the first ILD 90 have coplanar upper surfaces.

[0051] Figure 8B It shows Figure 8A A plan view of the FinFET device 100. Note that, for simplicity... Figure 8B Not all features of the FinFET device 100 are shown. Specifically, Figure 8B Four fins 64 (e.g., 64A, 64B, 64C, and 64D) and four metal gate structures 97 (e.g., 97A, 97B, 97C, and 97D) located above the fins 64 are shown when viewed from above (e.g., in a top view). Figure 8B Exemplary locations of openings 104, 110, and 112, which are formed in subsequent processing, are further shown by dashed lines. Furthermore, Figure 1 Sections AA, BB, CC, and DD are also present in the data. Figure 8B As shown in the image. Figure 8B The number of fins 64 and the number of metal gate structures 97 shown in (and other figures) are for illustrative purposes and are not limiting; other numbers are also possible and are fully intended to be included within the scope of this disclosure.

[0052] Next, in Figures 9A-9DIn this process, an etch stop layer 101 is formed over the first ILD 90, and a hard mask layer 103 is formed over the etch stop layer 101. The etch stop layer 101 can be formed of a material other than, for example, silicon nitride and silicon oxide to provide etch selectivity. For example, the etch stop layer 101 can be formed from carbon-based nitrides (e.g., silicon carbonitride, silicon carbonitride oxide) or metal nitrides (e.g., boron nitride, aluminum nitride) using suitable formation methods such as CVD, PECDV, and ALD. The hard mask layer 103 can be formed from a suitable material such as silicon nitride, for example, using CVD, PECVD, etc. Note that, for simplicity, in Figures 9A-9D In the following figures, LDD region 65 is not shown, and details of the metal gate structure 97 (e.g., individual layers) are not shown.

[0053] Next, an opening 104 is formed in the hard mask layer 103. The opening 104 can be formed using photolithography and etching techniques. Due to the etch selectivity between the hard mask layer 103 and the etch stop layer 101, the etching process forming the opening 104 etches through the hard mask layer 103 and stops at (e.g., exposing) the etch stop layer 101. Figure 8B and Figures 9A-9D As shown, opening 104 is formed between and spaced apart from adjacent fins (e.g., 64C and 64B). In the example shown, the longitudinal axis of opening 104 (along the direction of section DD) is parallel to the longitudinal axis of fin 64, and... Figure 8B In the top view, opening 104 overlaps with three metal gate structures 97B, 97C, and 97D. Note that, as will be readily understood by those skilled in the art, Figure 8B and Figures 9A-9D The number, location, shape, and size of the openings 104 shown are merely non-limiting examples. Other variations and modifications are possible and are fully intended to be included within the scope of this disclosure. For example, Figure 17-19 An additional example of opening 104 is shown, the details of which are discussed below.

[0054] Next, in Figure 10A-10D An optional redeposition layer 102 is conformally formed over the hard mask layer 103 and the opening 104. In the illustrated embodiment, the redeposition layer 102 is formed of the same material as the hard mask layer 103 (e.g., SiN). The redeposition layer 102 can be formed by CVD, ALD, etc. For example, the thickness of the redeposition layer 102 can be between about 5 angstroms and about 10 angstroms. The redeposition layer 102 can be formed to reduce the size of the opening 104, which is used for subsequent metal gate dicing processes to dice some of the metal gate structures 97. Furthermore, the redeposition layer 102 can reduce damage to the fins 64 during the etching process of the metal gate dicing process. In some embodiments, the redeposition layer 102 is omitted.

[0055] Next, in Figure 11A-11D In this process, multiple etching processes are performed to remove the portion of the first ILD 90 located directly below the opening 104, the portion of the metal gate structure 97 located directly below the opening 104, and the portion of the corresponding gate spacer 87 located directly below the opening 104. In other words, the opening 104 extends through the etch stop layer 101 and the first ILD 90, exposing the STI region 62. The portion of the opening 104 below the hard mask layer 103 can also be referred to as the trench 104. Figure 11C As shown, opening 104 will intersect each metal gate structure 97 (e.g., see...). Figure 8B The 97B, 97C, and 97D gates are separated (e.g., diced) into two separate metal gate structures. This can be called a diced metal gate process. Figure 11A In the example, multiple etching processes can over-etch at the location where the removed metal gate structure 97 once existed, thus forming a recess 106 extending into the STI region 62.

[0056] In some embodiments, the multiple etching processes include a first dry etching process, a wet etching process, and a second dry etching process performed sequentially. A first dry etching process (e.g., a plasma process) is performed to penetrate (e.g., remove) the redeposited layer 102, and this first dry etching process can be performed using an etching gas containing CH3F, Ar, He, O2, combinations thereof, etc. Next, a wet etching process is performed using, for example, a mixture of hydrochloric acid (HCl) and deionized water (DIW). The wet etching process can be performed to clean (e.g., remove) residues and / or byproducts from the first dry etching process. Next, a second dry etching process (e.g., a plasma process) is performed to remove the remaining layer / structure below the opening 104, and this second dry etching process can be performed using an etching gas containing Cl2, SiCl4, CH4, CF4, BCl3, Ar, O2, combinations thereof, etc.

[0057] Next, in Figure 12A-12D In this process, a first dummy material 105 (also referred to as a sacrificial material) is formed to fill the opening 104. In some embodiments, the first dummy material 105 is formed of materials that are subsequently etched in an etching process for removing the first dummy material 105 (see [link to etching process]). Figures 15A-15DThe first dummy material 105 provides etch selectivity with materials of other layers / structures (e.g., first ILD 90, etch stop layer 101, STI region 62, fin 64, source / drain region 80, metal gate structure 97, subsequently formed liner layer 111, and contacts 113). The first dummy material 105 can be a suitable semiconductor material (e.g., Si or Ge) or a suitable metal oxide material (e.g., Al2O3, Ga2O3, TiO2, In2O3, ZnO). Suitable formation methods, such as PVD, CVD, ALD, etc., can be performed to form the first dummy material 105.

[0058] After the first dummy material 105 is formed, a planarization process (e.g., CMP) is performed to remove excess portions of the first dummy material 105 disposed outside the opening 104. The planarization process may also remove the hard mask layer 103. Figure 12A , 12C As shown in Figure 12D, after the planarization process, the etch stop layer 101 is exposed, and the first dummy material 105 and the etch stop layer 101 have coplanar (e.g., flush) upper surfaces.

[0059] Next, in Figures 13A-13D In this process, a second ILD 107 is formed over the etch stop layer 101 and the first dummy material 105. The second ILD 107 can be formed from the same material as the first ILD 90 using the same or similar formation methods, so details will not be repeated. Next, openings 110 and 112 extending through the second ILD 107, the etch stop layer 101, and the first ILD 90 are formed using, for example, photolithography and etching techniques. Those skilled in the art will readily understand that the number, location, and size of the openings 110 / 112 shown are for illustrative purposes only and are not limiting.

[0060] like Figure 8B As shown in the top view, opening 110 is formed along the longitudinal axis of opening 104, and at least some portions of opening 110 overlap with opening 104. Therefore, opening 110 exposes the sidewalls of the first dummy material 105, as... Figure 13A As shown. In Figure 13A In the example, opening 110A exposes the sidewall of the first ILD 90 on the left and the sidewall of the first dummy material 105 on the right, and opening 110B exposes the sidewall of the first dummy material 105 on both the left and right sides. Opening 110 may further extend into the STI region 62. Figure 8B and 13DAs shown, opening 112 is formed on the source / drain region 80 and may extend into the source / drain region 80. In some embodiments, openings 110 and 112 are formed using the same photomask in the same processing steps, for example, in the same photolithography and etching steps.

[0061] Next, a second dummy material 109 (also referred to as a sacrificial material) is conformally formed over the second ILD 107 and along the sidewalls and bottom of the openings 110 / 112. In the illustrated embodiment, the second dummy material 109 is formed of the same material as the first dummy material 105. In some embodiments, the first dummy material 105 and the second dummy material 109 are formed of different materials, but have substantially the same etching rate (e.g., within 10% of each other) for the subsequent etching process used to remove the first dummy material 105 and the second dummy material 109. Next, an anisotropic etching process is performed to remove a portion of the second dummy material 109 disposed at the bottom of the openings 110 / 112, such that the second dummy material 109 lining the sidewalls of the openings 110 / 112 but not covering the bottom of the openings 110 / 112.

[0062] like Figure 13A As shown, the second dummy material 109 in the opening 110 (e.g., 100A, 100B) contacts and extends along the sidewalls of the first dummy material 105. In the subsequent etching process that removes the first dummy material 105 and the second dummy material 109 (see...),... Figure 15A In the process, the etchant removes the second dummy material 109 in opening 110, and then continues to remove the first dummy material 105 in opening 104. In other words, the etchant can contact the first dummy material 105 through opening 110. Details are discussed below.

[0063] Next, in Figures 14A-14DIn the process, an inner liner 111 is conventionally formed in the openings 110 / 112, for example, on the source / drain region 80 at the bottom of the opening 112, on the STI region at the bottom of the opening 110, and on the second dummy material 109 along the sidewalls of the openings 110 / 112. Although not shown, the inner liner 111 may also be formed on the upper surface of the second dummy material 109 extending along the upper surface of the second ILD 107. Next, a conductive material 113 is formed on the inner liner 111 to fill the openings 110 / 112. Next, a planarization process (e.g., CMP) is performed to remove portions of the second dummy material 109, portions of the inner liner 111, and portions of the conductive material 113 from the upper surface of the second ILD 107. After the planarization process, the upper surface of the second ILD 107 is exposed, the remaining portion of the conductive material 113 forms the contact 113 (also referred to as the contact plug), and the inner liner 111 surrounds the contact 113.

[0064] In some embodiments, the inner liner 111 is formed from a suitable conductive material such as SiN, SiO2, AlN, Al2O3, SiC, SiCN, or SiCON using a suitable formation method such as PVD, CVD, or ALD. In some embodiments, the inner liner 111 separates the conductive material 113 from the second dummy material 109 and thus prevents the second dummy material 109 from being consumed by the conductive material 113 (e.g., by chemical reaction). The conductive material 113 can be, for example, Co, W, Cu, Al, Au, combinations thereof, etc., and can be formed using CVD, PVD, ALD, electroplating, etc. Note that in this discussion, unless otherwise specified, conductive material refers to electrically conductive material, and conductive feature (e.g., conductive wire) refers to conductive feature.

[0065] exist Figures 14A-14D In the opening 112 above the source / drain region 80, a contact 113 is electrically coupled to the source / drain region 80 and may be referred to as a source / drain contact. The contact 113 formed in the opening 110 is electrically isolated (e.g., not electrically connected to a functional circuit) and may be referred to as a dummy contact.

[0066] Next, in Figures 15A-15DIn this process, the first dummy material 105 and the second dummy material 109 are removed, and an air gap 108 is formed at the location where the first dummy material 105 and the second dummy material 109 were previously located. In some embodiments, a suitable etching process (e.g., a selective etching process) is performed using an etchant that is selective (e.g., has a higher etching rate) for one or more of the first dummy material 105 and the second dummy material 109, such as dry etching, wet etching, reactive ion etching, etc., to remove the first dummy material 105 and the second dummy material 109 without significantly damaging other layers or structures. For example, a dry etching process can be performed using oxygen-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBR3), or iodine-containing gas.

[0067] like Figures 15A-15D As shown, the air gap 108 includes a portion of the groove 104 (see Figure 104). Figure 11A This includes some portions of openings 110 / 112. When viewed from above (e.g., in a top view), each contact 113 is surrounded by an air gap 108. Therefore, the air gap 108 around each contact 113 can also be referred to as an air trench. Note that although the first dummy material 105 in the trench 104 is covered by the second ILD 107, as discussed earlier, the etchant of the etching process can contact (and remove) the first dummy material 105 through the air gap 108 corresponding to the opening 110.

[0068] Next, in Figures 16A-16D In this process, a dielectric layer 115 is formed on the second ILD 107 to seal the air gap 108. The dielectric layer 115 can be a low-k dielectric material, such as SiCON, SiCO, SiC, etc., and can be formed by CVD, PECVD, ALD, etc. Some portions of the dielectric layer 115 can protrude into the air gap 108, thereby sealing the air gap 108. In other words, the air gap 108 is sealed to form a closed cavity.

[0069] In advanced processing nodes, parasitic capacitance increases significantly as feature sizes shrink and transistor integration density increases, thereby degrading device performance. This disclosure reduces the parasitic capacitance of the formed device and improves device performance by forming an air gap 108 in the device to reduce the dielectric constant (e.g., average dielectric constant) of the first ILD 90 and the second ILD 107. The disclosed method can be easily integrated into existing manufacturing processes. Achieving improved device performance requires little or no additional cost.

[0070] As will be readily understood by those skilled in the art, additional processes can be performed to complete the fabrication of the FinFET device 100. For example, an interconnect structure is formed on dielectric layer 115, the interconnect structure including multiple dielectric layers and conductive features (e.g., vias, conductive lines) formed in the multiple dielectric layers. The interconnect structure electrically connects underlying electrical components to form a functional circuit. Details are not discussed here.

[0071] Figure 17-19 Additional example FinFET devices (e.g., 100A, 100B, and 100C) in various embodiments are shown. FinFET devices 100A, 100B, and 100C are similar to FinFET device 100, but the number, location, shape, and / or size of the trenches 104 are different. Figure 8B The FinFET device 100 is different.

[0072] exist Figure 17 In the FinFET device 100A, two trenches 104A and 104B are formed along the longitudinal direction of fin 64. Note that trenches 104A and 104B do not overlap with the metal gate structure 97D, therefore, the metal gate structure 97D is not cut by the metal gate cutting process.

[0073] exist Figure 18 In the FinFET device 100B, two trenches 104A and 104B are formed. Trench 104A has a first portion (e.g., a left portion) and a second portion (e.g., a right portion), the first portion being narrower than the second portion in the direction of cross section BB. Trench 104A overlaps with metal gate structures 97A, 97B, and 97C. Trench 104B is spaced apart from trench 104A and has the same width as the second portion of trench 104A in the direction of cross section BB. Neither trench 104A nor 104B overlaps with metal gate structure 97D.

[0074] exist Figure 19 In the FinFET device 100C, two trenches 104A and 104B are formed. Trench 104A is narrower than trench 104B in the direction of cross section BB. Trench 104A overlaps with metal gate structures 97B and 97C. Trench 104B is disposed on the opposite side of metal gate structure 97D to trench 104A.

[0075] The embodiments can achieve advantages. For example, this disclosure reduces the parasitic capacitance of the formed device and improves device performance by forming an air gap 108 in the device. The disclosed method can be easily integrated into existing manufacturing processes. Achieving improved device performance requires little or no additional cost.

[0076] Figure 20A flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments is shown. It should be understood that... Figure 20 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 20 The various steps are shown.

[0077] refer to Figure 20 In block 1010, a gate structure is formed on a first fin, wherein the first fin protrudes above the substrate, and the gate structure is surrounded by a first interlayer dielectric (ILD) layer. In block 1020, a trench adjacent to the first fin is formed in the first ILD layer. In block 1030, the trench is filled with a first dummy material. In block 1040, a second ILD layer is formed on the first ILD layer and the first dummy material. In block 1050, a first opening is formed in the first ILD layer and the second ILD layer, wherein the first opening exposes the sidewalls of the first dummy material. In block 1060, the sidewalls of the first opening are lined with a second dummy material. In block 1070, after lining the sidewalls of the first opening, a conductive material is formed in the first opening. In block 1080, after forming the conductive material, the first dummy material is removed from the trench, and the second dummy material is removed from the first opening. In block 1090, after removal, the first opening and the trench are sealed by forming a dielectric layer on the second ILD layer.

[0078] In one embodiment, a method of forming a semiconductor device includes: forming a gate structure over a first fin, wherein the first fin protrudes above a substrate and the gate structure is surrounded by a first interlayer dielectric (ILD) layer; forming a trench adjacent to the first fin in the first ILD layer; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming a first opening in the first ILD layer and the second ILD layer, wherein the first opening exposes a sidewall of the first dummy material; lining the sidewall of the first opening with a second dummy material; after lining the sidewall of the first opening, forming a conductive material in the first opening; after forming the conductive material, removing the first dummy material from the trench and removing the second dummy material from the first opening; and after the removal, sealing the first opening and the trench by forming a dielectric layer over the second ILD layer. In one embodiment, the first dummy material and the second dummy material are formed of the same material. In one embodiment, the first dummy material and the second dummy material are removed in the same etching process using an etchant selective for the first dummy material and the second dummy material. In one embodiment, forming the dielectric layer includes forming the dielectric layer using a low-k dielectric material. In one embodiment, the method further includes, after lining the sidewalls of the first opening and before forming the conductive material, conformally forming an inner liner layer in the first opening on the second dummy material, wherein the conductive material in the first opening is surrounded by the inner liner layer. In one embodiment, forming the trench includes: forming an etch stop layer over the first ILD layer; forming a hard mask layer over the etch stop layer; forming an opening in the hard mask layer, wherein the opening exposes the etch stop layer; conformally forming a redeposition layer over the hard mask layer and in the opening, wherein the redeposition layer and the hard mask layer are formed of the same material; and performing a plurality of etching processes to remove a portion of the first ILD layer located below the opening in the hard mask layer. In one embodiment, performing the plurality of etching processes includes: performing a first dry etching process to remove the redeposited layer; performing a wet etching process after the first dry etching process to remove residues from the first dry etching process; and performing a second dry etching process after the wet etching process, wherein the second dry etching process removes a portion of the hard mask layer, a portion of the etch stop layer, and a portion of the first ILD layer. In one embodiment, a portion of the gate structure is located below an opening in the hard mask layer, wherein the second dry etching process removes that portion of the gate structure.In one embodiment, the gate structure is formed on a second fin parallel to the first fin, wherein the trench is formed between and spaced apart from the first and second fins. In one embodiment, the method further includes: forming a second opening in the first and second ILD layers, wherein the second opening exposes an underlying source / drain region; lining the sidewalls of the second opening with a second dummy material; forming the conductive material in the second opening after lining the sidewalls of the second opening; removing the second dummy material from the second opening after forming the conductive material; and sealing the second opening by forming a dielectric layer over the second ILD layer after removing the second dummy material from the second opening. In one embodiment, the first and second openings are formed in the same processing step. In one embodiment, the method further includes: forming a conductive liner layer in the first and second openings before forming the conductive material, wherein the conductive material is surrounded by the conductive liner layer after forming the conductive material.

[0079] In one embodiment, a method of forming a semiconductor device includes: forming a gate structure over a first fin and over a second fin adjacent to the first fin, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer and between the first fin and the second fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and over the first dummy material; forming a first opening and a second opening in the first ILD layer and the second ILD layer, the first opening exposing the first dummy material and the second opening exposing an underlying source / drain region; lining the sidewalls of the first opening and the sidewalls of the second opening with a second dummy material; after lining, forming a conductive material in the first opening and the second opening; after forming the conductive material, removing the first dummy material from the trench and removing the second dummy material from the first opening and the second opening; and after the removal, forming a dielectric layer over the second ILD layer to seal the trench, the first opening, and the second opening. In one embodiment, the first opening is formed between the first fin and the second fin, wherein, in a top view, the first opening overlaps with the trench. In one embodiment, the first dummy material and the second dummy material are formed of the same material. In one embodiment, the first dummy material and the second dummy material are removed by the same etching process. In one embodiment, the first bottom of the first opening and the second bottom of the second opening do not contain the second dummy material, wherein the method further includes, after the liner and before the formation of the conductive material, forming a conductive liner layer in the first opening and the second opening, wherein the conductive material is surrounded by the conductive liner layer.

[0080] In one embodiment, a semiconductor device includes: a fin protruding above a substrate; a gate structure situated above the fin; an interlayer dielectric (ILD) layer situated above the fin and surrounding the gate structure; a via extending through the ILD layer and electrically coupled to an underlying source / drain region; and an air gap surrounding the via, wherein the via is separated from the ILD layer by the air gap. In one embodiment, the semiconductor device further includes a conductive liner layer surrounding the via and situated below a bottom surface of the via facing the source / drain region. In one embodiment, in a top view, the air gap surrounds the via and is disposed on a first side of the gate structure overlapping at least a portion of the source / drain region.

[0081] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0082] Example 1. A method of forming a semiconductor device, the method comprising:

[0083] A gate structure is formed on a first fin, wherein the first fin protrudes above the substrate, and the gate structure is surrounded by a first interlayer dielectric (ILD) layer.

[0084] A trench adjacent to the first fin is formed in the first ILD layer;

[0085] Fill the trench with the first dummy material;

[0086] A second ILD layer is formed on top of the first ILD layer and the first dummy material;

[0087] A first opening is formed in the first ILD layer and the second ILD layer, wherein the first opening exposes the sidewall of the first dummy material;

[0088] The sidewall of the first opening is lined with a second dummy material;

[0089] After lining the sidewall of the first opening, a conductive material is formed in the first opening;

[0090] After forming the conductive material, the first dummy material is removed from the trench and the second dummy material is removed from the first opening; and

[0091] After the removal, the first opening and the trench are sealed by forming a dielectric layer on top of the second ILD layer.

[0092] Example 2. The method according to Example 1, wherein the first dummy material and the second dummy material are formed of the same material.

[0093] Example 3. The method according to Example 2, wherein the first dummy material and the second dummy material are removed in the same etching process using an etchant that is selective for the first dummy material and the second dummy material.

[0094] Example 4. The method according to Example 1, wherein forming the dielectric layer includes forming the dielectric layer using a low-k dielectric material.

[0095] Example 5. The method according to Example 1 further includes, after lining the sidewall of the first opening and before forming the conductive material:

[0096] An inner liner is conformally formed on the second dummy material in the first opening, wherein the conductive material in the first opening is surrounded by the inner liner.

[0097] Example 6. The method according to Example 1, wherein forming the trench includes:

[0098] An etch stop layer is formed on top of the first ILD layer;

[0099] A hard mask layer is formed on top of the etch stop layer;

[0100] An opening is formed in the hard mask layer, wherein the opening exposes the etch stop layer;

[0101] A redeposition layer is conformally formed on top of the hard mask layer and within the opening, wherein the redeposition layer and the hard mask layer are formed of the same material; and

[0102] Multiple etching processes are performed to remove a portion of the first ILD layer that is located below an opening in the hard mask layer.

[0103] Example 7. The method according to Example 6, wherein performing the plurality of etching processes includes:

[0104] Perform a first dry etching process to remove the re-deposited layer;

[0105] Following the first dry etching process, a wet etching process is performed to remove residues from the first dry etching process; and

[0106] After the wet etching process, a second dry etching process is performed, wherein the second dry etching process removes a portion of the hard mask layer, a portion of the etch stop layer, and a portion of the first ILD layer.

[0107] Example 8. The method according to Example 7, wherein a portion of the gate structure is located below an opening in the hard mask layer, wherein the second dry etching process removes this portion of the gate structure.

[0108] Example 9. The method according to Example 1, wherein the gate structure is formed on a second fin parallel to the first fin, wherein the trench is formed between and spaced apart from the first fin and the second fin.

[0109] Example 10. The method described in Example 1 further includes:

[0110] A second opening is formed in the first ILD layer and the second ILD layer, wherein the second opening exposes the underlying source / drain region;

[0111] The sidewall of the second opening is lined with the second dummy material;

[0112] The conductive material is formed in the second opening after the sidewall of the second opening is lined with it.

[0113] After the conductive material is formed, the second dummy material is removed from the second opening; and

[0114] After removing the second dummy material from the second opening, the second opening is sealed by forming the dielectric layer on top of the second ILD layer.

[0115] Example 11. The method according to Example 10, wherein the first opening and the second opening are formed in the same processing step.

[0116] Example 12. The method according to Example 10 further includes: forming a conductive inner liner in the first opening and the second opening before forming the conductive material, wherein the conductive material is surrounded by the conductive inner liner after the conductive material is formed.

[0117] Example 13. A method of forming a semiconductor device, the method comprising:

[0118] A gate structure is formed on a first fin and on a second fin adjacent to the first fin, the gate structure being surrounded by a first interlayer dielectric (ILD) layer;

[0119] A groove is formed in the first ILD layer and between the first fin and the second fin;

[0120] Fill the trench with the first dummy material;

[0121] A second ILD layer is formed on top of the first ILD layer and on top of the first dummy material;

[0122] A first opening and a second opening are formed in the first ILD layer and the second ILD layer, the first opening exposing the first dummy material and the second opening exposing the underlying source / drain region;

[0123] The sidewalls of the first opening and the second opening are lined with a second dummy material.

[0124] After the liner, a conductive material is formed in the first opening and the second opening;

[0125] After forming the conductive material, the first dummy material is removed from the trench and the second dummy material is removed from the first opening and the second opening; and

[0126] After the removal, a dielectric layer is formed on top of the second ILD layer to seal the trench, the first opening, and the second opening.

[0127] Example 14. The method according to Example 13, wherein the first opening is formed between the first fin and the second fin, wherein, in a top view, the first opening overlaps with the groove.

[0128] Example 15. The method according to Example 13, wherein the first dummy material and the second dummy material are formed of the same material.

[0129] Example 16. The method according to Example 15, wherein the first dummy material and the second dummy material are removed by the same etching process.

[0130] Example 17. The method according to Example 13, wherein the first bottom of the first opening and the second bottom of the second opening are without the second dummy material, wherein the method further comprises, after the liner and before the formation of the conductive material:

[0131] A conductive liner is formed in the first opening and the second opening, wherein the conductive material is surrounded by the conductive liner.

[0132] Example 18. A semiconductor device comprising:

[0133] The fins protrude above the substrate;

[0134] A gate structure is located on the fin;

[0135] An interlayer dielectric (ILD) layer is located above the fin and surrounds the gate structure;

[0136] Vias extend through the ILD layer and are electrically coupled to the underlying source / drain regions; and

[0137] An air gap surrounds the via, wherein the via is separated from the ILD layer by the air gap.

[0138] Example 19. The semiconductor device according to Example 18 further includes a conductive inner liner layer surrounding the via and located beneath the bottom surface of the via facing the source / drain region.

[0139] Example 20. The semiconductor device according to Example 18, wherein, in a top view, the air gap surrounds the via, and the air gap is disposed on a first side of the gate structure that overlaps with at least a portion of the source / drain region.

Claims

1. A method for forming a semiconductor device, the method comprising: A gate structure is formed on a first fin, wherein the first fin protrudes above the substrate, and the gate structure is surrounded by a first interlayer dielectric (ILD) layer. A trench adjacent to the first fin is formed in the first interlayer dielectric (ILD) layer; Fill the trench with the first dummy material; A second interlayer dielectric ILD layer is formed on top of the first interlayer dielectric ILD layer and the first dummy material; A first opening is formed in the first interlayer dielectric ILD layer and the second interlayer dielectric ILD layer, wherein the first opening exposes the sidewall of the first dummy material; The sidewall of the first opening is lined with a second dummy material; After lining the sidewall of the first opening, a conductive material is formed in the first opening; After forming the conductive material, the first dummy material is removed from the trench and the second dummy material is removed from the first opening; and After the removal, the first opening and the trench are sealed by forming a dielectric layer on top of the second interlayer dielectric (ILD) layer.

2. The method according to claim 1, wherein, The first dummy material and the second dummy material are formed of the same material.

3. The method according to claim 2, wherein, The first dummy material and the second dummy material are removed in the same etching process using an etchant that is selective for the first dummy material and the second dummy material.

4. The method according to claim 1, wherein, Forming the dielectric layer includes forming the dielectric layer using a low-k dielectric material.

5. The method of claim 1, further comprising, after lining the sidewall of the first opening and before forming the conductive material: An inner liner is conformally formed on the second dummy material in the first opening, wherein the conductive material in the first opening is surrounded by the inner liner.

6. The method according to claim 1, wherein, Forming the trench includes: An etch stop layer is formed on top of the first interlayer dielectric (ILD) layer; A hard mask layer is formed on top of the etch stop layer; An opening is formed in the hard mask layer, wherein the opening exposes the etch stop layer; A redeposition layer is conformally formed on top of the hard mask layer and within the opening, wherein the redeposition layer and the hard mask layer are formed of the same material; and Multiple etching processes are performed to remove a portion of the first interlayer dielectric (ILD) layer that is located below an opening in the hard mask layer.

7. The method according to claim 6, wherein, Performing the plurality of etching processes includes: Perform a first dry etching process to remove the re-deposited layer; Following the first dry etching process, a wet etching process is performed to remove residues from the first dry etching process; and After the wet etching process, a second dry etching process is performed, wherein the second dry etching process removes a portion of the hard mask layer, a portion of the etch stop layer, and a portion of the first interlayer dielectric (ILD) layer.

8. The method according to claim 7, wherein, A portion of the gate structure is located below an opening in the hard mask layer, wherein the second dry etching process removes this portion of the gate structure.

9. The method according to claim 1, wherein, The gate structure is formed on a second fin parallel to the first fin, wherein the trench is formed between the first fin and the second fin and spaced apart from the first fin and the second fin.

10. The method according to claim 1, further comprising: A second opening is formed in the first interlayer dielectric ILD layer and the second interlayer dielectric ILD layer, wherein the second opening exposes the underlying source / drain region; The sidewall of the second opening is lined with the second dummy material; The conductive material is formed in the second opening after the sidewall of the second opening is lined with it. After the conductive material is formed, the second dummy material is removed from the second opening; and After the second dummy material is removed from the second opening, the second opening is sealed by forming the dielectric layer on top of the second interlayer dielectric (ILD) layer.

11. The method according to claim 10, wherein, The first opening and the second opening are formed in the same processing step.

12. The method of claim 10, further comprising: Before the conductive material is formed, a conductive inner liner is formed in the first opening and the second opening, wherein the conductive material is surrounded by the conductive inner liner after the conductive material is formed.

13. A method of forming a semiconductor device, the method comprising: A gate structure is formed on a first fin and on a second fin adjacent to the first fin, the gate structure being surrounded by a first interlayer dielectric (ILD) layer. A trench is formed in the first interlayer dielectric (ILD) layer and between the first fin and the second fin; Fill the trench with the first dummy material; A second interlayer dielectric ILD layer is formed on top of the first interlayer dielectric ILD layer and on top of the first dummy material; A first opening and a second opening are formed in the first interlayer dielectric ILD layer and the second interlayer dielectric ILD layer, the first opening exposing the first dummy material and the second opening exposing the underlying source / drain region; The sidewalls of the first opening and the second opening are lined with a second dummy material. After the liner, a conductive material is formed in the first opening and the second opening; After the conductive material is formed, the first dummy material is removed from the trench and the second dummy material is removed from the first opening and the second opening; as well as After the removal, a dielectric layer is formed on the second interlayer dielectric (ILD) layer to seal the trench, the first opening, and the second opening.

14. The method according to claim 13, wherein, The first opening is formed between the first fin and the second fin, wherein, in a top view, the first opening overlaps with the groove.

15. The method according to claim 13, wherein, The first dummy material and the second dummy material are formed of the same material.

16. The method according to claim 15, wherein, The first dummy material and the second dummy material are removed by the same etching process.

17. The method according to claim 13, wherein, The first bottom of the first opening and the second bottom of the second opening do not contain the second dummy material, wherein the method further includes, after the liner and before the formation of the conductive material: A conductive liner is formed in the first opening and the second opening, wherein the conductive material is surrounded by the conductive liner.

18. A semiconductor device, comprising: The first and second fins protrude above the substrate; A shallow trench isolation region is located on the substrate and between the first fin and the second fin; A gate structure is located above the shallow trench isolation region; An interlayer dielectric (ILD) layer is located above the shallow trench isolation region and surrounds the gate structure; The first and second vias extend through the interlayer dielectric (ILD) layer and are electrically coupled to the underlying source / drain regions. as well as An air gap extends laterally around the first and second through holes and between the first and second through holes along the length of the first and second fins.

19. The semiconductor device of claim 18, further comprising a conductive liner layer surrounding the first via and the second via and located beneath the bottom surfaces of the first via and the second via facing the source / drain regions.

20. The semiconductor device according to claim 18, wherein, In the top view, the air gap surrounds the first via and the second via, and the air gap is disposed on the first side of the gate structure that overlaps with at least a portion of the source / drain region.

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